QorIQ Communications Platforms T Series QorIQ T2080 and T2081 communication processors Overview safe partitioning of control and data plane The four e6500 dual-threaded cores share a The 28 nm QorIQ T2080 and T2081 applications within the device. low-latency backside 2 MB L2 cache, allowing communications processors bring the * Enterprise equipment: Modular Ethernet efficient sharing of code and data. Each architectural innovations of the T series switches, services cards, UTM equipment, flagship T4240, such as the 1.8 GHz enterprise storage, data center dual-threaded e6500 core, into an eight virtual core mid-range platform at reduced power and price points. The T2080 processor is primarily intended to succeed our successful P3041 and P2041 mid-range series of quad-core devices as a control plane or integrated control and data plane processor. It provides an excellent boosting the performance of media and networking algorithms, offering native inline broadband access, metro Ethernet, optical programming and using less power than a networking separate DSP. * Wireless infrastructure: Mobile backhaul, NICs, channel cards, control cards in LTE, Virtualization WCDMA, GSM, WiMAX The T2080 and T2081 processors include support for hardware-assisted virtualization. * Aerospace and defense: ruggedized or highly secure routers, avionics networking, capability, cache size, SerDes bandwidth and instrumentation panels, military SBCs budget. It also provides a value engineering opportunity for P4080 customers, as T2080 provides equivalent performance at much lower price and power. technology-based SIMD engine, dramatically * Service provider: Core and edge routers, migration path, as it offers 2x or better in core Ethernet connectivity within a similar power e6500 core implements the Freescale AltiVec The e6500 core offers an extra core privilege level (hypervisor) and hardware offload of logical to real address translation. In addition, * Industrial computing: SBCs, factory the T2080 and T2081 include platform-level automation, test and measurement enhancements such as SR-IOV and I/O virtualization with DMA memory protection e6500 Core through IOMMUs and configurable "storage The T2080 and T2081 processors are profiles," which provide isolation of I/O buffers The T2081 is a smaller package version of based on the 64-bit e6500 core, built on between guest environments. Virtualization the T2080, which is pin compatible with Power Architecture technology, and run software for the T2080 and T2081 processors the quad-core T1042. This provides T1042 up to 1.8 GHz. The e6500 core also offers includes kernel virtualization model (KVM), customers an easy upgrade to higher higher aggregate instructions per clock at Linux(R) containers and the Freescale performance if processing requirements lower power with an innovative "fused core" hypervisor. increase. It also enables customers to reuse approach to threading. The e6500's fully a single board for two different product resourced dual threads provide 1.7 times the performance levels. performance of a single thread. QorIQ T2080 Communications Processor QorIQ T2080 Communications Processor T1 T2 T1 Power Architecture(R) e6500 32 KB D-Cache 32 KB I-Cache 32 KB D-Cache virtual core device achieves up to 1.8 GHz T2 Power Architecture e6500 32 KB I-Cache 32 KB D-Cache 32 KB I-Cache 2 MB Banked L2 PAMU 4x I2C SPI, GPIO 2x USB 2.0 + PHY Pattern Match RMan Engine 2.1 Buffer Mgr. HiGig 2x DMA DCB 1GbE 1GbE 1GbE 1GbE 8-Lane 10 GHz SerDes Core Complex (CPU, L2, L3 Cache) Basic Peripherals and Interconnect PAMU Real-Time Debug Parse, Classify, Distribute PCle 2x DUART DCE 1.0 Security 5.2 Queue (XOR Mgr. CRC) sRIO Power Management Peripheral Access Management Unit PAMU PCle IFC SD/MMC 32/64-bit DDR3/3L Memory Controller 512 KB Platform Cache PreFetch CoreNet Coherency Fabric Security Monitor PCle Advanced virtualization technology facilitates T1 PCle unpredictable control plane code branches. 32 KB D-Cache 1/10 GbE pipeline for better latency response to 32 KB I-Cache Security Fuse Processor 1/10 GbE even while maintaining a short seven-stage T2 Power Architecture e6500 Accelerators and Memory Control SATA 2.0 plane applications. The highly efficient eight T1 SATA 2.0 applications or mixed control and data T2 Power Architecture e6500 sRIO targeted at mid-range control plane 1/10 GbE The T2080 and T2081 processors are 1/10 GbE Target Markets and Applications (R) Watchpoint Cross Trigger Perf. Monitor Trace Aurora 8-Lane 8 GHz SerDes Networking Elements Data Path Acceleration Architecture (DPAA) The T2080 and T2081 processors integrate the QorIQ DPAA, an innovative multicore infrastructure for scheduling work to cores (physical and virtual), hardware accelerators and network interfaces. The FMAN, a primary element of the DPAA, parses headers from incoming packets and classifies and selects data buffers with optional policing and congestion management. The FMAN passes its work to the QMAN, which assigns it to cores or accelerators with a multi-level scheduling hierarchy, while maintaining packet ordering. The BMAN manages allocation and de-allocation of packet buffers. The T2080 and T2081's implementation of DPAA offers accelerators for cryptography, deep packet inspection and compression/decompression. T2080 vs. T2081 Differences T2080 T2081 SerDes 16 8 PCIe 2x Gen3 + 2x Gen2 1x Gen3 + 3x Gen2 SRIO 2 + RMan No SATA 2 No Aurora Yes No 10 Gb/s MACs Up to four, with XFI, XAUI, HiGig Up to 2x XFI 1 Gb/s MACs Up to eight Up to seven Package 25 x 25mm, 896 pins, 0.8 mm pitch 23 x 23mm, 780 pins, 0.8 mm pitch, pin compatible with T1042 T2080 and T2081 Features List Four dual-threaded e6500 cores built on Power Architecture(R) technology * * * * * CoreNet platform cache * 512 KB shared platform cache with prefetch engine Hierarchical interconnect fabric * CoreNet fabric supporting coherent and non-coherent transactions with prioritization and bandwidth allocation amongst CoreNet endpoints Software and Tool Support Memory controller * 64-bit DDR3/3L SDRAM up to 2133 MT/s * 72-bit width including ECC Freescale and our partner network deliver a wide range of tools, run-time software, reference solutions and services to accelerate DPAA incorporating acceleration for the following functions * Packet parsing, classification and distribution to 24 Gb/s (FMAN) * Queue management for scheduling, packet sequencing and congestion management of up to 224 queues (QMAN) * Hardware buffer management for buffer allocation and de-allocation with 64 buffer pools (BMAN) * Cryptography acceleration to 10 Gb/s (SEC) * Decompression/compression acceleration at up to 17.5 Gb/s (DCE) * DPAA chip-to-chip interconnect via RapidIO(R) message manager (RMAN) (T2080 only) * Pattern matching acceleration to 10 Gb/s (PME) SerDes * 16 lanes at up to 10 GHz (8 on T2081) Ethernet interfaces * Quality of service: Egress traffic shaping and priority flow control for data center bridging in converged data center applications * 8 MACs (7 on T2081), multiplexed over the following options: Up to four 10 Gb/s MACs supporting XFI/KR, XAUI and HiGig (two on T2081 supporting XFI/KR only) Up to eight 1 Gb/s MACs (5 on T2080) supporting SGMII Up to two 2.5 Gb/s SGMII Up to two RGMII High-speed peripheral interfaces * * * * Two PCI Express 3.0 controllers (one on T2081) Two PCI Express 2.0 controllers (three on T2081) Endpoint SR-IOV Two Serial RapidIO 2.1 controllers/ports running at up to 5 GHz with Type 11 messaging and Type 9 data streaming support (T2080 only) Additional peripheral interfaces * * * * * * * Two serial ATA (SATA 2.0) controllers (T2080 only) Two High-Speed USB 2.0 controllers with integrated PHYs Enhanced secure digital host controller (SD/MMC/eMMC) Enhanced serial peripheral interface Four I2C controllers Four UARTS Integrated flash controller supporting NAND and NOR flash memory DMA * Dual eight channel Support for hardware virtualization and partitioning enforcement * * * * * * * QorIQ trust architecture * Secure boot, secure debug, tamper detection (T2080 only), volatile key storage, alternate image and key revocation your designs. * QorIQ T2080 reference design board (T2080RDB) * CodeWarrior Development Studio for Power Architecture * Freescale Linux SDK * VortiQa Application Software VortiQa Application Identification Software (AIS) Enterprise Software for Networking VortiQa open network switch software VortiQa open network director software * Professional Services & Support Commercial Services Linux SDK Support Package Reference Design Software (RDS) Support Package * Third Party Software and Tools Enea, Green Hills, Mentor Graphics and Wind River Up to 1.8 GHz, 6.0 DMIPS/MHz per core Shares a 2 MB L2 cache Three levels of instructions: User, supervisor, hypervisor Hybrid 32-bit mode to support legacy software and transition to a 64-bit architecture Advanced power saving modes include state retention power gating Extra privileged level for hypervisor support Logical to real address translation Virtual core aware MMU/TLB vMPIC (virtualized interrupt controller)/virtual core capable PPC cores vDMA (user level DMA engine) PAMU v2 (I/O MMU supporting paging) DPAA (Ethernet MAC virtualization, accelerator virtualization) For more information, please visit freescale.com/QorIQ Freescale, the Freescale logo, AltiVec, CodeWarrior and QorIQ are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm Off. CoreNet is a trademark of Freescale Semiconductor, Inc. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. All other product or service names are the property of their respective owners. (c) 2014 Freescale Semiconductor, Inc. Document Number: T2080FS REV 1