S6
NC
Dual-In-Line
S3
S5
V+
EN
V–
S14
A2
S15
S1
A3
S12
S10
1
2
3
4
5
6
7
8
28
27
26
25
24
S16
23
22
21
Top View
S8
9S2
20
S9
A0
A1
10
S7
19
NC
S13
11
NC
12
S11
18
17
GND
13 16
14 15
D
S4
Decoders/Drivers A0
A2
S1b
V+
S5b
S1a
A1
NC
Db
NC
V–
Dual-In-Line
S2a
S7a
S6a
S8a
S4b
S7b
EN
Da
S3b
S8b
S5a
S2b
GND
S3a
NC
S4a
S6b
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
Top View
920
10 19
11
12
18
17
13 16
14 15
Decoders/Drivers
DG506A_MIL DG507A_MIL
DG506A_MIL/507A_MIL
Vishay Siliconix
Document Number: 70066
S-00405—Rev. D, 21-Feb-00 www.vishay.com
1
Single 16-Ch/Differential 8-Ch CMOS Analog Multiplexers
(Obsolete for non-hermetic. Use DG406/407 as pin-for-pin replacements.)
FEATURES BENEFITS APPLICATIONS
DLow On-Resistance: 240
DTTL and CMOS Logic Compatible
DLow Power: 30 mW
DBreak-Before-Make Switching
D44-V Power Supply Rating
DTransition Time: 600 ns
DEasily Interfaced
DLow Power Consumption
DLow System Crosstalk
DWide Analog Signal Range
DCommunication Systems
DATE
DData Acquisition Systems
DAudio Signal Routing and Multiplexing
DMedical Instrumentation
DESCRIPTION
A channel in the on state conducts current equally well in both
directions. In the off state each channel blocks voltages up to
the power supply rails, normally 30 V peak-to-peak. An enable
(EN) function allows for device selection when several
multiplexers are used. All control inputs, address (AX) and
enable (EN) are TTL or CMOS compatible over the full
specified operating temperature range.
The DG506A_MIL/507A_MIL are fabricated in the
Vishay Siliconix PLUS-40 process, which includes improved
ESD protection for ruggedness. An epitaxial layer prevents
latch up.
The DG506A_MIL/507A_MIL are available in hermetic
packages. For plastic packages, use the DG406/407 as
pin-for-pin replacements.
For wideband/video multiplexing, the DG536 is
recommended.
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
DG506A_MIL/507A_MIL
Vishay Siliconix
www.vishay.com
2Document Number: 70066
S-00405—Rev. D, 21-Feb-00
TRUTH TABLES AND ORDERING INFORMATION
TRUTH TABLE Ċ DG506A_MIL
A3A2A1A0EN On Switch
X X X X 0 None
0 0 0 0 1 1
0 0 0 1 1 2
0 0 1 0 1 3
0 0 1 1 1 4
0 1 0 0 1 5
0 1 0 1 1 6
0 1 1 0 1 7
0 1 1 1 1 8
1 0 0 0 1 9
1 0 0 1 1 10
10101 11
1 0 1 1 1 12
1 1 0 0 1 13
1 1 0 1 1 14
1 1 1 0 1 15
1 1 1 1 1 16
ORDERING INFORMATION Ċ DG506A_MIL
Temp Range Package Part Number
DG506AAK
_
28-Pin CerDIP DG506AAK/883
–55 to 125_C28-Pin Sidebraze JM38510/19001BXC
LCC-28* DG506AAZ/883
*Block Diagram and Pin Configuration not shown.
TRUTH TABLE Ċ DG507A_MIL
A2A1A0EN On Switch
X X X 0 None
0 0 0 1 1
0 0 1 1 2
0 1 0 1 3
0 1 1 1 4
1 0 0 1 5
1 0 1 1 6
1 1 0 1 7
1 1 1 1 8
Logic “0” = VAL v 0.8 V
Logic “1” = VAH w 2.4 V
X = Don’t Care
ORDERING INFORMATION Ċ DG507A_MIL
Temp Range Package Part Number
DG507AAK
_
28-Pin CerDIP DG507AAK/883
–55 to 125_C28-Pin Sidebraze JM38510/19003BXC
28-Pin LCC DG507AAZ/883
ABSOLUTE MAXIMUM RATINGS
Voltage Referenced to V–
V+ 44 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GND 25 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Inputsa, VS, VD(V–) –2 V to (V+) +2 V or. . . . . . . . . . . . . . . . . . . . . . . .
20 mA, whichever occurs first
Current (Any Terminal, Except S or D) 30 mA. . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous Current, S or D 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak Current, S or D
(Pulsed at 1 ms, 10% Duty Cycle Max) 40 mA. . . . . . . . . . . . . . . . . . . . . . . . .
Storage Temperature (CerDIP) –65 to 150_C. . . . . . . . . . . . . . . . . . . .
(Plastic DIP) –65 to 125_C. . . . . . . . . . . . . . . .
Power Dissipation (Package)b
28-Pin CerDIP and Sidebraze 1200 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28-Pin PLCCNO TAG 1200 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LCC-20,28c1000 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Notes:
a. Signals on SX, DX or INX exceeding V+ or V– will be clamped by internal
diodes. Limit forward diode current to maximum current ratings.
b. All leads soldered or welded to PC board.
c. Derate 14 mW/_C above 75_C.
DG506A_MIL/507A_MIL
Vishay Siliconix
Document Number: 70066
S-00405—Rev. D, 21-Feb-00 www.vishay.com
3
SPECIFICATIONSa
Test Conditions
Unless Otherwise Specified A Suffix
–55 to 125_C
Parameter Symbol V+ = 15 V, V– = –15 V
VIN = 2.4 V, 0.8 VfTempbMindTypcMaxdUnit
Analog Switch
Analog Signal RangeeVANALOG Full –15 15 V
Drain-Source
On-Resistance rDS(on) VD = "10 V, IS = –200 ARoom
Full 240 400
500
rDS(on) MatchinggrDS(on) –10 V < VS < 10 V Room 6 %
Source Off
Leakage Current IS(off) VS = "10 V, VD = #10 V
VEN = 0 V Room
Full –1
–50 1
50
Drain Off VD= #10 V
"
DG506A_MIL Room
Full –10
–300 10
300
Drain Off
Leakage Current ID(off) VS = "10 V
VEN = 0 V DG507A_MIL Room
Full –5
–200 5
200 nA
Drain On
"
DG506A_MIL Room
Full –10
–300 10
300
Drain On
Leakage Current ID(on) VS = VD = "10 V DG507A_MIL Room
Full –5
–200 5
200
Digital Control
Logic Input Current VA = 2.4 V Room
Full –10
–30
Logic Input Current
Input Voltage High IAH VA = 15 V Room
Full 10
30 A
Logic Input Current
Input Voltage Low IAL VEN = 0 V, 2.4 V, VA = 0 V Room
Full –10
–30
Dynamic Characteristics
Transition Time tTRANS See Figure 2 Room 0.6 1.0
Break-Before-Make Time tOPEN See Figure 4 Room 0.2
Enable Turn-On Time tON(EN) Room 1 1.5 s
Enable Turn-Off Time tOFF(EN) See Figure 3 Room 0.4 1.0
Charge Injection Q Room 6 pC
Off IsolationhOIRR VEN = 0 V, RL = 1 k , CL = 15 pF
VS = 7 VRMS, f = 500 kHz Room 68 dB
Source Off Capacitance CS(off) VEN = 0 V, VS = 0 V, f = 140 kHz Room 6
VEN = 0 V DG506A_MIL Room 45 pF
Drain Off Capacitance CD(off) VD = 0 V
f = 140 kHz DG507A_MIL Room 23
Power Supplies
Positive Supply Current I+ Room 1.3 2.4
Negative Supply Current I–VEN = 0 V, VA = 0 V Room –1.5 –0.7 mA
Notes:
a. Refer to PROCESS OPTION FLOWCHART.
b. Room = 25_C, Full = as determined by the operating temperature suffix.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
e. Guaranteed by design, not subject to production test.
f. VIN = input voltage to perform proper function.
g. rDS(on) +ǒrDS(on)MAX –rDS(on)MIN
rDS(on)AVE Ǔ
h. Off isolation +20 log VD
VS,V
S+input to off switch, VD+output due to VS.
DG506A_MIL/507A_MIL
Vishay Siliconix
www.vishay.com
4Document Number: 70066
S-00405—Rev. D, 21-Feb-00
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
rDS(on) vs. VD and Power Supply Input Switching Threshold vs.
V+ and V– Supply Voltages
Supply Current vs. Switching Frequency Crosstalk vs. Frequency
Charge Injection vs. Analog Voltage rDS(on) vs. VD and Temperature
rDS(on)
– Drain-Source On-Resistance (
(V)
T
V
Q (pC)
rDS(on)
– Drain-Source On-Resistance ((dB)
TALK
X
VD – Drain Voltage (V) V+, V– Positive and Negative Supplies (V)
VD – Drain Voltage (V)VS – Source Voltage (V)
f – Frequency (Hz) f – Frequency (Hz)
I+, I– (mA)
15–15
2.5
2.0
1.5
1.0
0.5
0
400
16
–15–10 –50 510
14
12
10
8
6
4
2
0
350
300
250
200
150
100
50
0–10 –50 51015
125_C
600
–20 –10 0 10 20
500
400
300
200
100
V+ = 15 V
V– = –15 V
V+ = 15 V
V– = –15 V
0
6
4
2
0
–2
–4
–6
V+ = 15 V
V– = –15 V
100 k
10 k 1 M
0
–20
–40
–60
–80
–100
–120
1 k 1 M 10 M10 k 100 k
CerDIP
Plastic
V+ = 15 V
V– = –15 V
ref. 0.0 dBm
”10
"5 V
"7.5 V
"10 V
"15 V
"20 V
”5”15 ”20
I–
I+
25_C
–55_C
)W
)W
DG506A_MIL/507A_MIL
Vishay Siliconix
Document Number: 70066
S-00405—Rev. D, 21-Feb-00 www.vishay.com
5
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
Off Isolation vs. Frequency Switching Time vs. Temperature
IS(off) vs. Analog Voltage ID(on), ID(off) vs. Analog Voltage
Switching Time vs. Positive Supply Voltage Leakages vs. Temperature
(pA)
ID
(pA)
IS
Leakage Current
(ns)t TRANS
, t OPEN
(ns)t TRANS
, t OPEN
OIRR (dB)
f – Frequency (Hz) Temperature (_C)
V+ – Positive Supply (V) Temperature (_C)
VS – Source Voltage (V) VD – Drain Voltage (V)
0
–20
–40
–60
–80
–100
–120 1 k 1 M 10 M10 k 100 k
CerDIP
Plastic
V+ = 15 V
V– = –15 V
ref. 0 dBm
ID(off)
ID(on)
V+ = 15 V
V– = –15 V
TA = 25_C
20
0
–20
–40
–60
–80 –15 –10 –50 5 1015
1000
–55
800
600
400
200 –35 –15 5 25 45 65 105 125
85
tRANS
tOPEN
1100
10 12 14 16 18 20 22
1000
900
800
700
600
500
400
300
200
V+ = 15 V
V– = –15 V
VD = "14 V
ID(on), ID(off)
IS(off)
100 nA
10 nA
1 nA
100 pA
10 pA
1 pA
0.1 pA–55 –35 –15 5 25 45 65 85 105 125
tRANS
tOPEN
V+ = 15 V
V– = –15 V
900
700
500
300
15
10
5
–5
–15 –15 –10 –50 5 1015
–10
0
V+ = 15 V
V– = –15 V
VS = –VD
TA = 25_C
IS(off)
DG506A_MIL/507A_MIL
Vishay Siliconix
www.vishay.com
6Document Number: 70066
S-00405—Rev. D, 21-Feb-00
SCHEMATIC DIAGRAM (TYPICAL CHANNEL)
FIGURE 1.
V+
EN
V–
V+
V–
V+
AX
V+
V+
V–
V–
A0
GND
Decode/
Drive
S1
Sn
D
V+
V–
–
+V–
V+
–
+
–
+
TEST CIRCUITS
FIGURE 2. Transition Time
Logic
Input
Switch
Output
VS8
VO
tTRANS
tr <20 ns
tf <20 ns
S8 ONS1 ON tTRANS
0 V
VS1
50%
90%
90%
3 V
0 V
DG506A_MIL
S1b
S8b
A2
Db
A1
*
A0
* = S1a – S8a, S2b – S7b, Da
50 1 M
VO
+2.4 V
+15 V
–15 V
EN V+
V–GND 35 pF
S1
S2 – S15
S16
A2
A1
A0
50 1 M
VO
A3
#10 V
"10 V
+2.4 V
+15 V
–15 V
EN V+
V–GND D
35 pF
DG507A_MIL #10 V
"10 V
DG506A_MIL/507A_MIL
Vishay Siliconix
Document Number: 70066
S-00405—Rev. D, 21-Feb-00 www.vishay.com
7
TEST CIRCUITS
FIGURE 3. Enable Switching Time
VO
10%
tr <20 ns
tf <20 ns
VO
Logic
Input
tON(EN)
90%
Switch
Output
50%
tOFF(EN)
3 V
0 V
0 V
A1
50
A0
S1
VO
A2–5 V
+15 V
–15 V 1 k
EN
S2 – S16
V+
V–GND D
35 pF
A3
VO
S1b
A2
S1a – S8a
S2b – S8b
A1
Da and Db
A0
50 1 k
+15 V
–15 V
EN
V+
V–GND 35 pF
DG506A_MIL
DG507A_MIL
–5 V
FIGURE 4. Break-Before-Make Interval
50%
80%
Logic
Input
Switch
Output
VO
VS
tOPEN
tr <20 ns
tf <20 ns
0 V
3 V
0 V
50
A0
All S and Da
1 k
A3
D,Db
A1
A2
+2.4 V
+15 V
–15 V
EN V+
V–
VO
GND
+5 V
35 pF
DG506A_MIL
DG507A_MIL
DG506A_MIL/507A_MIL
Vishay Siliconix
www.vishay.com
8Document Number: 70066
S-00405—Rev. D, 21-Feb-00
APPLICATION HINTSa
V+
Positive Supply
Voltage
(V)
V–
Negative Supply
Voltage
(V)
VIN
Logic Input Voltage
VINH(min)/VINL(max)
(V)
VS or VD
Analog Voltage
Range
(V)
15b
12
10
8c
–15
–12
–10
–8
2.4/0.8
2.4/0.8
2.2/0.6
2.0/0.5
–15 to 15
–12 to 12
–10 to 10
–8 to 8
Notes:
a. Application Hints are for DESIGN AID ONLY, not guaranteed and not subject to production testing.
b. Electrical Parameter Chart based on V+ = 15 V, V– = –15 V.
c. Operation below "8 V is not recommended due to shift in VINL(MAX).
Overvoltage Protection
A very convenient form of overvoltage protection consists of
adding two small signal diodes (1N4148, 1N914 type) in series
with the supply pins (see Figure 5). This arrangement
effectively blocks the flow of reverse currents. It also floats the
supply pin above or below the normal V+ or V– value. In this
case the overvoltage signal actually becomes the power
supply of the IC. From the point of view of the chip, nothing has
changed, as long as the dif ference between VS and the V– rail
doesn’t exceed +44 V. The addition of these diodes will reduce
the analog signal range to 1 V below V+ and 1 V above V–, but
it preserves the low channel resistance and low leakage
characteristics.
1N4148
DG506A_MIL
–V
+V
1N4148
Internal
Junction
Internal
Junction
FIGURE 5. Overvoltage Protection Using Blocking
Diodes
V+ v Vg vV–
SX
Vg
+V
–VDG507A_MIL
FIGURE 6. A 32-Channel Data Acquisition System
A0A1A2A3
Channel 1
Channel 2
Channel 16
DG506A_MIL
#1
EN
A0A1A2A3
Channel 17
Channel 18
Channel 32
DG506A_MIL
#2
EN
D
DG419
AS/H A/D Data
Bus
Controller
D
