FEBRUARY 2001
DSC-2989/09
1
©2000 Integrated Device Technology, Inc.
Features
◆◆
◆◆
◆High-speed (equal access and cycle times)
– Military: 25/35/45/55/70/85ns (max.)
◆◆
◆◆
◆Low power consumption
◆◆
◆◆
◆Battery backup operation — 2V data retention
(L version only)
◆◆
◆◆
◆Available in high-density industry standard 22-pin, 300 mil
ceramic DIP
◆◆
◆◆
◆Produced with advanced CMOS technology
◆◆
◆◆
◆Inputs/outputs TTL-compatible
◆◆
◆◆
◆Military product compliant to MIL-STD-883, Class B
Description
The IDT7188 is a 65,536-bit high-speed static RAM organized as
16K x 4. It is fabricated using IDT’s high-performance, high-reliability
technology — CMOS. This state-of-the-art technology, combined with
Functional Block Diagram
A
0
DECODER 65,536-BIT
MEMORY ARRAY
COLUMN I/O
2989 drw 01
INPUT
DATA
CONTROL
W
E
CS
GND
A
13
I/O
0
I/O
1
I/O
2
I/O
3
V
CC
,
innovative circuit design techniques, provides a cost effective approach
for memory intensive applications.
Access times as fast as 25ns are available. The IDT7188 offers a
reduced power standby mode, ISB1, which is activated when CS goes
HIGH. This capability significantly decreases power while enhancing
system reliability. The low-power version (L) version also offers a battery
backup data retention capability where the circuit typically consumes only
30µW operating from a 2V battery.
All inputs and outputs are TTL-compatible and operate from a single
5V supply. The IDT7188 is packaged in a 22-pin, 300 mil ceramic DIP
providing excellent board-level packing densities.
Military grade product is manufactured in compliance with the latest
revision of MIL-STD-883, Class B, making it ideally suited to military
temperature applications demanding the highest level of performance
and reliability.
CMOS Static RAM
64K (16K x 4-Bit) IDT7188S
IDT7188L
2
IDT7188S/L
CMOS Static RAM 64K (16K x 4-Bit) Military Temperature Range
Absolute Maximum Ratings(1)
Recommended DC Operating
Conditions
Recommended Operating
Temperature and Supply Voltage
Pin Configuration
Capacitance
(TA = +25°C, f = 1.0MHz, VCC = 0V)
Pin Descriptions
Truth Table(1)
NOTE:
1 . H = VIH, L = VIL, X = don't care.
DIP
Top View
2989 drw 02
5
6
7
8
9
10
11
1
2
3
4
22
21
20
19
18
17
D22-1
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
V
CC
A
13
A
11
A
10
I/O
3
16
15
G
ND
I/O
2
I/O
1
I/O
0
CS
14
A
12
WE
A
8
A
9
13
12
,
Name Description
A
0
- A
13
Address Inputs
CS Chi p Se le c t
WE Write Enable
I/O
0
- I/O
3
Data Inp ut/ Outp ut
V
CC
Power
GND Ground
2989 tbl 01
Mode CS WE I/O Power
Standby H X High-Z Standby
Read L H D
OUT
Active
Write L L D
IN
Active
2989 tbl 02
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
Symbol Rating Value Unit
V
TERM
Te rm inal Vo ltag e with Re s p e ct to GND -0. 5 to + 7.0 V
T
A
Operating Temperature -55 to +125
o
C
T
BIAS
Temperature Under Bias -65 to +135
o
C
T
STG
Storage Temperature -65 to +150
o
C
P
T
Po we r Dis s ip ati o n 1. 0 W
I
OUT
DC Outp ut Current 50 mA
2989 tbl 03
NOTE:
1. This parameter is determined by device characterization, but is not production
tested.
Symbol Parameter
(1)
Conditions Max. Unit
C
IN
Inp ut Cap ac itanc e V
IN
= 0V 6 pF
C
I/O
I/O Cap acitance V
OUT
= 0V 6 pF
2989 tbl 04
NOTE:
1. VIL (min.) = –3.0V for pulse width less than 20ns,once per cycle.
Symbol Parameter Min. Typ. Max. Unit
V
CC
Supply Vo ltage 4.5 5.0 5.5 V
GNDGround 000V
V
IH
Inp ut High Vo ltag e 2. 2
____
6.0 V
V
IL
Inp ut Low Vo ltag e -0.5
(1)
____
0.8 V
2989 tbl 05
Grade Temperature GND Vcc
Military -55
O
C to +125
O
C0V 5V ± 10%
2989 tbl 06
6.42
IDT7188S/L
CMOS Static RAM 64K (16K x 4-Bit) Military Temperature Range
3
DC Electrical Characteristics
(VCC = 5.0V ± 10%)
DC Electrical Characteristics(1)
(VCC = 5V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V)
Symbol Parameter Test Conditions
IDT7188S IDT7188L
UnitMin. Max. Min. Max.
|I
LI
| Input Leakage Current V
CC
= Max., V
IN
=
GND to V
CC
____
10
____
5µA
|I
LO
| Output Leakage Current V
CC
= Max., CS = V
IH
, V
OUT
= GND to V
CC
____
10
____
5µA
V
OL
Outp ut Low Vo ltag e I
OL
= 10mA, V
CC
= Min.
____
0.5
____
0.5 V
I
OL
= 8mA, V
CC
= Min.
____
0.4
____
0.4
V
OH
Output High Voltage I
OH
= -4mA, V
CC
= Min. 2.4
____
2.4
____
V
2989 tbl 07
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX address and data inputs are cycling at the maximum frequency of read cycles of 1/tRC. f = 0 means no input lines change.
Symbol Parameter Power 7188S25
7188L25 7188S35
7188L35 7188S45
7188L45 7188S55
7188L55 7188S70
7188L70 7188S85
7188L85 Unit
I
CC1
Operating Power
Supply Current
CS = V
IL
, Outp uts Op e n
V
CC
= Max., f
=
0
(2)
S 105 105 105 105 105 105 mA
L808080808080
I
CC2
Dynamic Operating Current
CS = V
IL
, Outp uts Op e n
V
CC
= Max. , f = f
MAX
(2)
S 155 140 140 140 140 140 mA
L 120 115 110 110 110 105
I
SB
Stand by Power Supply
Curre nt (TTL Le ve l)
CS > V
IH
, Outp uts Op e n
V
CC
= Max. , f = f
MAX
(2)
S605050505050
mA
L404035353535
I
SB1
Full S tand by Po wer
Sup p ly Curre nt (CMOS Le ve l)
CS > V
HC
, V
CC
= Max., V
IN
> V
HC
or V
IN
< V
LC
, f = 0
(2)
S202020202020
mA
L 1.5 1.5 1.5 1.5 1.5 1.5
2989 tbl 08
4
IDT7188S/L
CMOS Static RAM 64K (16K x 4-Bit) Military Temperature Range
Data Retention Characteristics
(L Version Only) (VHC = VCC - 0.2V)
Low VCC Data Retention Waveform
AC Test Conditions
Figure 1. AC Test Load Figure 2. AC Test Load
(for tHZ, tLZ, tWZ, tOHZ and tOW)
*Includes scope and jig capacitances
2989 drw 03
D
A
T
A
RETENTION
MODE
4.5V 4.5V
V
DR
≥2V
V
IH
V
IH
t
R
t
CDR
V
CC
CS V
DR
,
2989 drw 04
480Ω
30pF*
255Ω
D
ATA
OUT
5V
,
2989drw 05
480Ω
5pF*
255Ω
D
ATA
OUT
5V
,
NOTES:
1. TA = +25°C.
2. tRC = Read Cycle Time.
3. This parameter is guaranteed by device characterization but is not production tested.
Typ.
(1)
V
CC
@ Max.
V
CC
@
Symbol Parameter Test
Condition Min. 2.0V 3.0V 2.0V 3.0V Unit
V
DR
V
CC
fo r Data Rete nti on
____
2.0
____ ____ ____ ____
V
I
CCDR
Data Rete ntion Current
____
10 15 600 900 µA
t
CDR
(3)
Chi p Des elect to Data Retention Tim e CS > V
HC
V
IN
> V
HC
or
< V
LC
0
____ ____ ____ ____
ns
t
R
(3)
Op eration Re co ve ry Time t
RC
(2)
____ ____ ____ ____
ns
I
I
LI
I
(3)
Input L e ak ag e Cur re nt
____ ____ ____
22µA
29 89 t bl 09
Inp ut Pul s e Le v e ls
Inp ut Ris e / Fall Time s
Inp ut Ti ming Re fe re nc e Le v e ls
Outp ut Re fe re nc e Le ve ls
AC Test Load
GND to 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
29 89 t b l 10
6.42
IDT7188S/L
CMOS Static RAM 64K (16K x 4-Bit) Military Temperature Range
5
Timing Waveform of Read Cycle No. 2(1,3)
NOTES:
1. WE is HIGH for Read cycle.
2. CS is LOW for Read cycle.
3. Address valid prior to or coincident with CS transition LOW.
4. Transition is measured ±200mV from steady state voltage.
5. All Read cycle timings are referenced from the last valid address to the first transitioning address.
Timing Waveform of Read Cycle No. 1(1,2)
AC Electrical Characteristics (VCC = 5.0V ± 10%)
DDRESS
DATAOUT
2989 drw 06
tRC
tAA
tOH
PREVIOUS DATA VALID DATA VALID
(5)
DATA
OUT
CS
I
CC
I
SB
V
CC
SUPPLY
CURRENT
2989 drw 07
t
ACS
(4)
t
LZ (4)
t
HZ
t
PD
t
PU
(5)
t
RC
DATA VALID
HIGH IMPEDANCE
,
NOTE:
1. This parameter is guaranteed by device characterization but is not production tested.
Symbol Parameter
7188S25
7188L25 7188S35
7188L35 7188S45
7188L45 7188S55
7188L55 7188S70
7188L70 7188S85
7188L85
Unit
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Read C ycl e
t
RC
Re ad Cyc le Time 25
____
35 —45 —55
____
70
____
85
____
ns
t
AA
Address Access Time
____
25
____
35
____
45
____
55
____
70
____
85 ns
t
ACS
Chip Se lect Acce ss Time
____
25
____
35
____
45
____
55
____
70
____
85 ns
t
OH
Output Hold from Address Change 5
____
5
____
5
____
5
____
5
____
5
____
ns
t
LZ
(1) Outp ut Se lec t to Output in Lo w-Z 5
____
5
____
5
____
5
____
5
____
5
____
ns
t
HZ
(1) Chip Deselect to Output in H igh-Z
____
10
____
14
____
14
____
20
____
25
____
30 ns
t
PU
(1) Chip Select to Powe r Up Time 0
____
0
____
0
____
0
____
0
____
0
____
ns
t
PD
(1) C hip Deselect to Power Down Time
____
25
____
35
____
45
____
55
____
70
____
85 ns
298 9 tbl 11
6
IDT7188S/L
CMOS Static RAM 64K (16K x 4-Bit) Military Temperature Range
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,3)
NOTES:
1. WE or CS must be HIGH during all address transitions.
2. A write occurs during the overlap (tWP) of a LOW CS and a LOW WE.
3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
4 . During this period, I/O pins are in the output state so that the input signals should not be applied.
5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high-impedance state.
6. Transition is measured ±200mV from steady state.
AC Electrical Characteristics (VCC = 5.0V ± 10%)
CS
1
,CS
2
DATA
IN
DDRESS
WE
DATA
OUT
2989 drw 08
t
AW
t
WR
t
DW
t
WC
t
WP
t
DH
t
WZ
t
OW
(4)
t
AS
(6)
(4)
(6)
DATA VALID
NOTE:
1. This parameter is guaranteed by device characterization.
Symbol Parameter
7188S25
7188L25 7188S35
7188L35 7188S45
7188L45 7188S55
7188L55 7188S70
7188L70 7188S85
7188L85
Unit
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Write C ycle
t
WC
Write Cycle Time 20
____
30
____
40
____
50
____
60
____
75
____
ns
t
CW
Chip Select to End-o f-Write 20
____
25
____
35
____
50
____
60
____
75
____
ns
t
AW
Address Valid to End-of-Write 20
____
25
____
35
____
50
____
60
____
75
____
ns
t
AS
Address Se t-up Time 0
____
0
____
0
____
0
____
0
____
0
____
ns
t
WP
Write Pulse Width 20
____
25
____
35
____
50
____
60
____
75
____
ns
t
WR
Wri te Re c o v ery Ti me 0
____
0
____
0
____
0
____
0
____
0
____
ns
t
DW
Data Valid to End-of-Write 13
____
15
____
20
____
25
____
30
____
35
____
ns
t
DH
Data Hold Time 0
____
0
____
0
____
0
____
0
____
0
____
ns
t
WZ
(1)
Write Enab le to Outp ut in High-Z
____
7
____
10
____
15
____
25
____
30
____
40 ns
t
OW
(1)
Outp ut A ctiv e fro m E nd -o f-Write 5
____
5
____
5
____
5
____
5
____
5
____
ns
2989 tbl 12
6.42
IDT7188S/L
CMOS Static RAM 64K (16K x 4-Bit) Military Temperature Range
7
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,2,3,5)
Ordering Information
NOTES:
1. WE or CS must be HIGH during all address transitions.
2. A write occurs during the overlap (tWP) of a LOW CS and a LOW WE.
3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
4 . During this period, I/O pins are in the output state so that the input signals should not be applied.
5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high-impedance state.
6. Transition is measured ±200mV from steady state.
CS
DATA
IN
A
DDRESS
WE
t
t
WR
2989 drw 09
t
AW
t
DW
t
WC
t
CW
t
DH
t
AS
DATA VALID
,
X
Power
XX
Speed
X
Package
X
Process/
Temperature
Range
BMilitary (-55°C to +125°C)
Compliant to MIL-STD-883, Class B
D 300 mil Ceramic DIP (D22-1)
25
35
45
55
70
85
S
LStandard Power
Low Power
7188
Speed in nanoseconds
2989 drw 10
Device
Type
,
I
DT
8
IDT7188S/L
CMOS Static RAM 64K (16K x 4-Bit) Military Temperature Range
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Datasheet Document History
11/xx/99 Updated to new format
Pg. 2, 3, 4 Removed commercial temperature data
Pg. 8 Added Datasheet Document History
08/09/00 Not recommended for new designs
02/01/01 Removed "Not recommended for new designs"
CORPORATE HEADQUARTERS for SALES: for Tech Support:
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San Jose, CA 95138 408-284-8200 800-345-7015
fax: 408-284-2775
www.idt.com