THCV226_Rev.1.20_E THCV226 V-by-One(R) HS High-speed Video Data Receiver General Description Features THCV226 is designed to support video data transmission between the host and display. This chip can receive 32bit video data and 3bit control data via four differential pairs of V-by-One(R) HS lanes. This chip in TQFP package supports the video data transmission up to 1080p/10b/120Hz. The maximum serial data rate is 3.4Gbps/lane. Normal / High-speed LVDS output selectable 1.8V single power supply Color depth selectable: 8/10 bits per colors Crossing / Distribution mode selectable Monitoring signal function 1.8V LVCMOS I/O interface Package: 128pin 0.4mm-pitch TQFP (16mm x 16mm) Wide frequency range AC coupling for CML inputs CDR requires no external frequency reference Supports Spread Spectrum Clocking tolerance with up to 30kHz/0.5%(center spread) V-by-One(R) HS standard compliant PLL requires no external components Power down / Output enable mode Block Diagram VDD HTPDN LOCKN BETOUT DGLOCK Copyright(c)2019 THine Electronics, Inc. ..... ..... RLE0p/n RLCLK0p/n Color Depth Normal Speed LVDS Mode High-Speed LVDS Mode 8bit 1.2 to 2.7Gbps 1.2 to 2.36Gbps 10bit 1.6 to 3.4Gbps 1.6 to 3.14Gbps ..... ..... RLA1p/n RLE1p/n RLCLK1p/n ..... ..... RLA2p/n Clock Frequency of LVDS Output RLE2p/n RLCLK2p/n ..... RLA3p/n ..... LVDS Serializer LVDS Serializer LVDS Serializer LVDS Serializer Controls Data Transmission Rate of CML Input RLA0p/n RLE3p/n RLCLK3p/n Color Depth Normal Speed LVDS Mode High-Speed LVDS Mode 8bit 40 to 90MHz 80 to 157MHz 10bit 40 to 85MHz 80 to 157MHz PLL Cross Switch Deskew & Formatter CML Deserializer CDR Rx3p Rx3n Deskew & Formatter Rx2p Rx2n CML Deserializer Rx1p Rx1n CML Deserializer Rx0p Rx0n CML Deserializer (1.8V) Color Depth Transmission Mode Setting Power Down Output Enable Monitoring Signal Setting 1/27 THine Electronics, Inc. Security E THCV226_Rev.1.20_E PIN Configuration LVDD GND CVDD RLE0p RLE0n RLD0p RLD0n GND LVDD RLCLK0p RLCLK0n RLC0p RLC0n GND LVDD RLB0p RLB0n RLA0p RLA0n GND LVDD CVDD GND COL OPF MODE0 MODE1 MODE2 Reserved3 Reserved4 Reserved5 GND 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 Reserved6 Reserved7 OE IOVDD DGLOCK HTPDN LOCKN CVDD GND VVDD Rx0n Rx0p GND Rx1n Rx1p VVDD GND Rx2n Rx2p GND Rx3n Rx3p VVDD GND CVDD BET_SEL0 BET_SEL1 MON_EN BET_EN BET_LAT BETOUT GND 97 64 98 63 99 62 100 61 101 60 102 59 103 58 104 57 105 56 106 55 THCV226 107 108 54 53 TQFP 128pin 109 110 52 51 111 50 112 49 113 48 114 47 115 46 116 45 117 44 118 43 119 42 120 41 121 40 122 39 123 38 124 37 125 36 126 35 127 34 128 33 RLA1n RLA1p RLB1n RLB1p RLC1n RLC1p LVDD GND RLCLK1n RLCLK1p RLD1n RLD1p LPVDD GND RLE1n RLE1p RLA2n RLA2p LPVDD GND RLB2n RLB2p RLC2n RLC2p LVDD GND RLCLK2n RLCLK2p RLD2n RLD2p RLE2n RLE2p 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 LVDD GND CVDD RLA3n RLA3p RLB3n RLB3p GND LVDD RLC3n RLC3p RLCLK3n RLCLK3p GND LVDD RLD3n RLD3p RLE3n RLE3p GND LVDD PVDD CVDD PDN Reserved2 Reserved1 Reserved0 MAP RS PRBS IOVDD GND Copyright(c)2019 THine Electronics, Inc. 2/27 THine Electronics, Inc. Security E THCV226_Rev.1.20_E PIN Description PIN Name Rx0n , Rx0p Rx1n , Rx1p Rx2n , Rx2p Rx3n , Rx3p RLA0n , RLA0p RLB0n , RLB0p RLC0n , RLC0p RLCLK0n , RLCLK0p RLD0n , RLD0p RLE0n , RLE0p RLA1n , RLA1p RLB1n , RLB1p RLC1n , RLC1p RLCLK1n , RLCLK1p RLD1n , RLD1p RLE1n , RLE1p RLA2n , RLA2p RLB2n , RLB2p RLC2n , RLC2p RLCLK2n , RLCLK2p RLD2n , RLD2p RLE2n , RLE2p RLA3n , RLA3p RLB3n , RLB3p RLC3n , RLC3p RLCLK3n , RLCLK3p RLD3n , RLD3p RLE3n , RLE3p DGLOCK PIN No 107, 108 110, 111 114, 115 117, 118 83, 82 81, 80 77, 76 75, 74 71, 70 69, 68 64, 63 62, 61 60, 59 56, 55 54, 53 50, 49 48, 47 44, 43 42, 41 38, 37 36, 35 34, 33 29, 28 27, 26 23, 22 21, 20 17, 16 15, 14 101 Type CI CI CI CI LO LO LO LO LO LO LO LO LO LO LO LO LO LO LO LO LO LO LO LO LO LO LO LO BI HTPDN 102 OD LOCKN 103 OD COL 88 I OPF 89 I MODE2,1,0 OE 92,91,90 99 I I BET_SEL1,0 123, 122 I Copyright(c)2019 THine Electronics, Inc. Description CML Data Input CML Data Input CML Data Input CML Data Input LVDS Data Output LVDS Data Output LVDS Data Output LVDS Data Output LVDS Data Output LVDS Data Output LVDS Data Output LVDS Data Output LVDS Data Output LVDS Data Output LVDS Data Output LVDS Data Output LVDS Data Output LVDS Data Output LVDS Data Output LVDS Data Output LVDS Data Output LVDS Data Output LVDS Data Output LVDS Data Output LVDS Data Output LVDS Data Output LVDS Data Output LVDS Data Output Connect all DGLOCK pins in multiple-chip configuration. Must be left OPEN for single-chip configuration Hot plug detect output Must be connected to Tx HTPDN with a 10K pull-up resistor Lock detect output Must be connected to Tx LOCKN with a 10K pull-up resistor Color depth select 1 : 10bit mode 0 : 8bit mode Output Pattern at CDR Fail Condition (LOCKN=1) 1 : LVDS output Low data 0 : LVDS output Hi-Z data Input / Output mode select LVDS Output Enable 1 : Normal Operation 0 : Output Disable Monitoring pin select 3/27 THine Electronics, Inc. Security E THCV226_Rev.1.20_E BET_EN 125 I BET_LAT 126 I MON_EN 124 I PRBS 3 I RS 4 I MAP 5 I PDN 9 I BETOUT Reserved 0,1,2,3,4,5 Field-BET enable 1 : Enable 0 : Normal operation Latch select input under Field BET operation 1 : Latched result output 0 : Reset latched result Monitoring mode enable 1 : Monitoring enable 0 : Monitoring disable Must be tied to GND or used for Monitoring Signal Function, refer to Table10. LVDS swing level select 1 : Normal swing (350mV) 0 : Reduced swing (200mV) LVDS output format select 1 : JEIDA format 0 : VESA format Power down 1 : Normal operation 0 : Power down operation Field BET result output Must be tied to GND 127 O 6, 7, 8, 93, 94, I 95 Reserved 6,7 97, 98 O Must be open CVDD 10, 30, 67, 86, PWR 1.8V power supply for Logic block 104, 121 VVDD 106, 112, 119 PWR 1.8V power supply for V-by-One(R) HS block LVDD 12, 18, 24, 32, PWR 1.8V power supply for LVDS block 40, 58, 65, 73, 79, 85 PVDD 11 PWR 1.8V power supply for PLL block LPVDD 46, 52 PWR 1.8V power supply for LVDS analog block IOVDD 2, 100, PWR 1.8V power supply for LVCMOS I/O buffer GND 1, 13, 19, 25, GND Ground 31, 39, 45, 51, 57, 66, 72, 78, 84, 87, 96, 105, 109, 113, 116, 120, 128 CI : CML Input buffer , LO : LVDS Output buffer , BI : LVCMOS Bi-directional buffer I : LVCMOS Input buffer , O : LVCMOS Output buffer , OD : Open Drain buffer PWR : 1.8V Power supply , GND : Ground Copyright(c)2019 THine Electronics, Inc. 4/27 THine Electronics, Inc. Security E THCV226_Rev.1.20_E Functional Description Functional Overview With V-by-One(R) HS's proprietary encoding scheme and CDR (Clock and Data Recovery) architecture, THCV226 enables the transmission of 8 or 10-bit video data, 2-bit synchronizing control data of HSYNC, VSYNC, and Data Enable(DE), by a pair cable with minimal external components. THCV226 automatically extracts the clock from the incoming data streams and converts the serial data into video data with DE being high or synchronizing control data with DE being low, recognizing which type of serial data is being sent by the transmitter. Also, THCV226 outputs the recovered data in the LVDS data format. THCV226 can operate for a wide range of a serial bit rate from 1.2Gbps to 3.4Gbps. It is unnecessary to use any external frequency reference, such as a crystal oscillator. Data Enable Requirement (DE) There are some requirements for DE signal as described in Figure1 and Figure2. If DE=Low and MODE0=0, control data of same cycle and particular assigned data bit `CTL' except the first and last pixel are transmitted. If DE=Low and MODE0=1, control data of same cycle and particular assigned data bit `CTL' except the first 2cycle and last 2pixel are transmitted. Otherwise video data is transmitted during DE=High. The length of DE being low and high must be at least 8 clock cycles long, as described in Figure17 and Table17. DE must be toggled as High -> Low -> High at regular interval. The length of particular DE cycle must be same at all lane. CTL Bit Transmission There is particular assigned data bit `CTL' which can be transmitted at blanking period except the first and the last pixel on DE=Low. Transmitter Data bit : R/G/B, CONT THCV226 1 R/G/B CONT CTL 0 VSYNC HSYNC Control bit : HSYNC, VSYNC Data bit : CTL* DE DE=1 , R/G/B, CONT DE=0 , CTL* except the 1st and the last pixel Other R/G/B, CONT=Invalid. DE=1 , HSYNC, VSYNC=Fixed DE=0 , HSYNC, VSYNC DE CTL* are particular assigned bits among R/G/B, CONT that can carry arbitrary data during DE=Low period. Figure 1. Conceptual Diagram of Basic Operation of Chipset Copyright(c)2019 THine Electronics, Inc. 5/27 THine Electronics, Inc. Security E THCV226_Rev.1.20_E LVDS Input of Source Device TLyzp/n DE=High Active period Data : Invalid DE=Low Blanking period Data : Particular assigned bit `CTL' is transmitted except the first and last pixel of Blanking period. 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 (LVDS In/put) TLCp/n D D D D D D D D D V H 3 2 1 0 V H 3 2 1 0 V H 3 2 1 0 V H 3 2 1 0 V H 3 2 1 0 V H 3 2 1 0 V H 3 2 1 0 V H 3 2 1 0 V H 3 2 E E E E E E E E E (LVDS In/put) TLCLKp/n (LVDS In/put) THCV226 LVDS Transmitter Output RLyzp/n 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 (LVDS Output) RLCp/n Hi (LVDS Output) V H 3 2 1 0 Hi V H 3 2 1 0 Lo V H 3 2 1 0 Lo V H 3 2 1 0 Lo V H 3 2 1 0 Lo V H 3 2 1 0 Lo V H 3 2 1 0 Hi V H 3 2 1 0 Hi V H 3 2 RLCLKp/n (LVDS Output) y=A,B,D,E z=0,1,2,3 Figure 2-1. Timing Diagram of Data and Synchronizing Signals (Normal LVDS mode) LVDS Input of Source Device TLyzp/n (LVDS In/put) TLCp/n (LVDS In/put) DE=High Active period Data : Invalid DE=Low Blanking period Data : Particular assigned bit `CTL' is transmitted except the first and last pixel of Blanking period. 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 D E V H 3 2 1 0 D E V H 3 2 1 H 3 2 1 0 D E V H 3 2 1 0 D E V H TLCLKp/n (LVDS In/put) THCV226 LVDS Transmitter Output RLyzp/n (LVDS Output) RLCp/n (LVDS Output) 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 Hi V H 3 2 1 0 Lo V H 3 2 1 0 Lo V H 3 2 1 0 Lo V H 3 2 1 0 Lo V H 3 2 1 0 Lo V H 3 2 1 0 Lo V H 3 2 1 0 Lo V H 3 2 1 0 Hi V H 3 2 RLCLKp/n (LVDS Output) y=A,B,D,E z=0,1,2,3 Figure 2-2. Timing Diagram of Data and Synchronizing Signals (HSLVDS mode) Copyright(c)2019 THine Electronics, Inc. 6/27 THine Electronics, Inc. Security E THCV226_Rev.1.20_E Color Depth Mode Function COL 1 0 Operation Mode 10-bit R/G/B data (4byte mode for V-by-One(R) HS Standard) 8-bit R/G/B data (3byte mode for V-by-One(R) HS Standard) Table 1. Color Depth Mode Select Transmission Mode Select MODE 2, 1, 0 111 110 101 100 011 010 001 000 COL 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Copyright(c)2019 THine Electronics, Inc. V-by-One HS LVDS Operation Mode 40 - 78.5MHz 80 - 157MHz HSLVDS / Distribution mode2 40 - 78.5MHz 80 - 157MHz 40 - 85MHz 40 - 85MHz Normal LVDS / Distribution mode2 40 - 90MHz 40 - 90MHz 40 - 78.5MHz 80 - 157MHz HSLVDS / Distribution mode1 40 - 78.5MHz 80 - 157MHz 40 - 85MHz 40 - 85MHz Normal LVDS / Distribution mode1 40 - 90MHz 40 - 90MHz 40 - 78.5MHz 80 - 157MHz HSLVDS / Crossing Mode 40 - 78.5MHz 80 - 157MHz 40 - 85MHz 40 - 85MHz Normal LVDS / Crossing mode 40 - 90MHz 40 - 90MHz 40 - 78.5MHz 80 - 157MHz HSLVDS mode 40 - 78.5MHz 80 - 157MHz 40 - 85MHz 40 - 85MHz Normal LVDS mode 40 - 90MHz 40 - 90MHz Table 2. Transmission Mode Select 7/27 THine Electronics, Inc. Security E THCV226_Rev.1.20_E HSLVDS / Distribution mode MODE2,1,0 = 111 Normal LVDS / Distribution mode MODE2,1,0 = 110 Rx0n/p RLy0n/p Rx0n/p RLy0n/p Rx1n/p RLy1n/p Rx1n/p RLy1n/p Rx2n/p RLy2n/p Rx2n/p RLy2n/p Rx3n/p RLy3n/p Rx3n/p RLy3n/p MODE2,1,0 = 101 MODE2,1,0 = 100 Rx0n/p RLy0n/p Rx0n/p RLy0n/p Rx1n/p RLy1n/p Rx1n/p RLy1n/p Rx2n/p RLy2n/p Rx2n/p RLy2n/p Rx3n/p RLy3n/p Rx3n/p RLy3n/p HSLVDS mode Normal LVDS mode MODE2,1,0 = 011 MODE2,1,0 = 010 Rx0n/p RLy0n/p Rx0n/p RLy0n/p Rx1n/p RLy1n/p Rx1n/p RLy1n/p Rx2n/p RLy2n/p Rx2n/p RLy2n/p Rx3n/p RLy3n/p Rx3n/p RLy3n/p MODE2,1,0 = 001 MODE2,1,0 = 000 Rx0n/p RLy0n/p Rx0n/p RLy0n/p Rx1n/p RLy1n/p Rx1n/p RLy1n/p Rx2n/p RLy2n/p Rx2n/p RLy2n/p Rx3n/p RLy3n/p Rx3n/p RLy3n/p y=A,B,C,CLK,D,E Figure 3. Transmission Mode Select Diagram Power Down Mode PDN 1 0 Operation Normal operation Power down operation Table 3. Power Down Mode Copyright(c)2019 THine Electronics, Inc. 8/27 THine Electronics, Inc. Security E THCV226_Rev.1.20_E Hot-plug and Lock Detect Function HTPDN and LOCKN are both open drain outputs from THCV226. Pull-up resistors must be placed at V-by-One(R) HS transmitter side. See Figure.4 and 5. If THCV226 is not active (power down mode (PDN=0) or powered off), HTPDN is open. Otherwise, HTPDN is pulled down by THCV226. HTPDN at V-by-One(R) HS transmitter side is High when THCV226 is not active or the receiver board is not connected. Then V-by-One(R) HS transmitter side enters into the power down mode. When HTPDN transits from High to Low, V-by-One(R) HS transmitter starts up and transmits training pattern for link training. LOCKN indicates whether THCV226 is in CDR state or not. If THCV226 is in the CDR unlock state, LOCKN is open. Otherwise (in the CDR lock state), it is pulled down by THCV226. V-by-One(R) HS transmitter side keeps transmitting training pattern until LOCKN transition to Low. After training is done, THCV226 sinks current, and LOCKN turns to Low. Then V-by-One(R) HS transmitter side starts transmitting normal video pattern. (Tx side) VDD PDN Transmitter HTPDN THCV226 HTPDN (Tx side) LOCKN Transmitter LOCKN HTPDN DGLOCK LOCKN Figure 4. HTPDN and LOCKN Scheme VDD PDN Transmitter HTPDN THCV226 HTPDN (Tx side) LOCKN Transmitter LOCKN HTPDN DGLOCK LOCKN Figure 5. Copyright(c)2019 THine Electronics, Inc. HTPDN and LOCKN Scheme without HTPDN Connection 9/27 THine Electronics, Inc. Security E THCV226_Rev.1.20_E Multiple-chip Configuration In order to reduce the number of cables needed for HTPDN and LOCKN in multiple-chip configuration, THCV226 is equipped with the DGLOCK pin. When all the DGLOCK pins are connected as in Figure 6 , the connected Rx chips can share the CDR lock status via DGLOCK, making all the Rx chips in the same operation status. (Tx side) VDD PDN Transmitter HTPDN (Tx side) LOCKN Transmitter THCV226 HTPDN (Rx side) LOCKN HTPDN DGLOCK LOCKN PDN Transmitter Transmitter HTPDN HTPDN LOCKN LOCKN THCV226 HTPDN DGLOCK LOCKN Figure 6. Usage of DGLOCK in Multiple-Rx Configuration Field BET Operation In order to help to debug high-speed serial links of CML lines, THCV226 has an operation mode acted as the bit error tester (Field BET). In the Field BET mode, the on-chip pattern generator on V-by-One(R) HS transmitter side is enabled and generates a test pattern. THCV217, which is an example of Tx device, has this function mode. In this mode, THCV217 internally generates the test pattern, encodes the data according to the 8b10b protocol, scrambles, and then serializes onto the CML high-speed lines. THCV226 receives the data stream and checks whether the sampled data has bit error. "Field BET" mode of THCV226 is activated by setting BET_EN=1. As for THCV226, when the internal test pattern check circuit is enabled, the pattern check result can be monitored at the BETOUT pin. The BETOUT pin goes Low whenever bit errors occur and stays High when there is no bit error. Please refer to Figure 7 and Figure 8. Table 5 shows possible combination of Tx and Rx for normal and Field BET operation. BETOUT L H Copyright(c)2019 THine Electronics, Inc. Result Bit error occurred No error Table 4. Field BET Result 10/27 THine Electronics, Inc. Security E THCV226_Rev.1.20_E THCV217 BET BET_EN 0 0 0 1 1 0 1 THCV226 BET_LAT BET_SEL1 0 1 0 0 1 0 0 1 0 1 1 0 1 1 1 BET_SEL0 0 1 0 1 Condition Operation Output Latch Select Normal Operation Forbidden Forbidden Forbidden Reset latched result Field BET Operation (Lane0) Latched result Reset latched result Field BET Operation (Lane1) Latched result Reset latched result Field BET Operation (Lane2) Latched result Reset latched result Field BET Operation (Lane3) Latched result Table 5. Field BET Operation THCV217 THCV226 TEST Pattern Generator TEST Pattern Checker BET = 1 BET_EN BETOUT Test Point for Field BET CLKIN Figure 7. Normal Operation BET_LAT Field BET Configuration Field BET Operation THCV219 (BET) Bit error Bit error Rxyn/p y=0,1,2,3 BET_LAT BETOUT Latched result Figure 8. Reset Latched result Relationship between Bit Error and BETOUT LVDS Reduced Swing Output Function RS pin controls LVDS output swing level. RS 0 1 Output Swing Level Reduced Swing Level ( 200mV typical ) Normal Swing Level ( 350mV typical ) Table 6. LVDS Output Level Select Copyright(c)2019 THine Electronics, Inc. 11/27 THine Electronics, Inc. Security E THCV226_Rev.1.20_E LVDS Output Enable Function By setting the OE and OPF pins, the following output enable function can be selected. In output disable condition, all the outputs take low fixed data or High-Z except for HTPDN, LOCKN and DGLOCK. LOCKN OE OPF LVDS Outputs Output Condition Low Fixed Data Output Enable Hi-Z Low Fixed Data Output Disable Hi-Z Status 1 0 1 0 1 0 1 0 1 H 0 1 L 0 Output Enable Normal Data Output Disable Low Fixed Data Hi-Z Table 7. LVDS Output Enable Function LVDS Data Mapping LVDS data (video data, control data, DE) are mapped as Figure 9. RLC[6] is special bit for DE (data enable). RLC[5:4] are for control data bits, and the other bits are for video data. Also there are special assigned bits, `CTL' transmitted under DE=0 condition. The number of LVDS channels depends on color depth mode, COL. RLD[6] is not available at COL=0, 8-bit color depth mode. Vdiff = 0 (RLCLKzp) - (RLCLKzn) tRCOP Data width 32 24 Previous cycle Current cycle Next cycle RLAzp/n RLAz[1] RLAz[0] RLAz[6] RLAz[5] RLAz[4] RLAz[3] RLAz[2] RLAz[1] RLAz[0] RLAz[6] RLAz[5] RLAz[4] RLAz[3] RLAz[2] RLAz[1] RLAz[0] RLBzp/n RLBz[1] RLBz[0] RLBz[6] RLBz[5] RLBz[4] RLBz[3] RLBz[2] RLBz[1] RLBz[0] RLBz[6] RLBz[5] RLBz[4] RLBz[3] RLBz[2] RLBz[1] RLBz[0] RLCzp/n RLCz[1] RLCz[0] RLCz[6] (DE) RLCz[5] (V) RLCz[4] (H) RLCz[3] RLCz[2] RLCz[1] RLCz[0] RLCz[6] (DE) RLCz[5] (V) RLCz[4] (H) RLCz[3] RLCz[2] RLCz[1] RLCz[0] RLDzp/n RLDz[1] RLDz[0] RLDz[6] RLDz[5] RLDz[4] RLDz[3] RLDz[2] RLDz[1] RLDz[0] RLDz[6] RLDz[5] RLDz[4] RLDz[3] RLDz[2] RLDz[1] RLDz[0] RLEzp/n RLEz[1] RLEz[0] RLEz[6] RLEz[5] RLEz[4] RLEz[3] RLEz[2] RLEz[1] RLEz[0] RLEz[6] RLEz[5] RLEz[4] RLEz[3] RLEz[2] RLEz[1] RLEz[0] z = 0,1,2,3 Data Enable Figure 9. Copyright(c)2019 THine Electronics, Inc. Control Data Bits LVDS Output Switching Timing Diagram 12/27 THine Electronics, Inc. Security E THCV226_Rev.1.20_E THCV226 Output RLAz[0] RLAz[1] RLAz[2] RLAz[3] RLAz[4] RLAz[5] RLAz[6] RLBz[0] RLBz[1] RLBz[2] RLBz[3] RLBz[4] RLBz[5] RLBz[6] RLCz[0] RLCz[1] RLCz[2] RLCz[3] RLCz[4] RLCz[5] RLCz[6] RLDz[0] RLDz[1] RLDz[2] RLDz[3] RLDz[4] RLDz[5] RLDz[6] RLEz[0] RLEz[1] RLEz[2] RLEz[3] RLEz[4] RLEz[5] RLEz[6] COL 0 (8bit) R[2] R[3] R[4] R[5] R[6] R[7] G[2] G[3] G[4] G[5] G[6] G[7] B[2]*2 B[3]*2 B[4]*2 B[5]*2 B[6]*2 B[7]*2 HSYNC VSYNC DE R[0] R[1] G[0] G[1] B[0]*2 B[1]*2 N/A*1 Channel Power Down Comment 1 (10bit) R[4] R[5] R[6] R[7] R[8] R[9] G[4] G[5] G[6] G[7] G[8] G[9] B[4]*2 B[5]*2 B[6]*2 B[7]*2 B[8]*2 B[9]*2 HSYNC VSYNC DE R[2] R[3] G[2] G[3] B[2]*2 B[3]*2 CONT[1]*2*3 R[0]*2 R[1]*2 G[0]*2 G[1]*2 B[0]*2 B[1]*2 CONT[2]*2*3 Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Control bit Control bit Data Enable*2 Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Table 8. LVDS Data Mapping Table for JEIDA Format (MAP=1) *1 N/A : Not available. THCV226 outputs RLDz[6]=0 *2 CTL bits, which are carried during DE=0 expect the 1st and the last pixel.(If MODE0=0) Which are carried during DE=0 except the 1st, 2nd and last 2pixel.(IF MODE0=1) *3 3D flags defined in the V-by-One(R) HS Standard are assigned to the following bits. V-by-One(R) HS Standard Packer/Unpacker D[24](3DLR) LVDS RLEz[6]. V-by-One(R) HS Standard Packer/Unpacker D[25](3DEN) LVDS RLDz[6]. ( z=0,1,2,3) Copyright(c)2019 THine Electronics, Inc. 13/27 THine Electronics, Inc. Security E THCV226_Rev.1.20_E THCV226 Output RLAz[0] RLAz[1] RLAz[2] RLAz[3] RLAz[4] RLAz[5] RLAz[6] RLBz[0] RLBz[1] RLBz[2] RLBz[3] RLBz[4] RLBz[5] RLBz[6] RLCz[0] RLCz[1] RLCz[2] RLCz[3] RLCz[4] RLCz[5] RLCz[6] RLDz[0] RLDz[1] RLDz[2] RLDz[3] RLDz[4] RLDz[5] RLDz[6] RLEz[0] RLEz[1] RLEz[2] RLEz[3] RLEz[4] RLEz[5] RLEz[6] COL 0 (8bit) R[0] R[1] R[2] R[3] R[4] R[5] G[0] G[1] G[2] G[3] G[4] G[5] B[0]*2 B[1]*2 B[2]*2 B[3]*2 B[4]*2 B[5]*2 HSYNC VSYNC DE R[6] R[7] G[6] G[7] B[6]*2 B[7]*2 N/A*1 Channel Power Down Comment 1 (10bit) R[0]*2 R[1]*2 R[2] R[3] R[4] R[5] G[0]*2 G[1]*2 G[2] G[3] G[4] G[5] B[0]*2 B[1]*2 B[2]*2 B[3]*2 B[4]*2 B[5]*2 HSYNC VSYNC DE R[6] R[7] G[6] G[7] B[6]*2 B[7]*2 CONT[1]*2*3 R[8] R[9] G[8] G[9] B[8]*2 B[9]*2 CONT[2]*2*3 Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Control bit Control bit Data Enable*2 Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Table 9. LVDS Data Mapping Table for VESA Format (MAP=0) *1 N/A : Not available. THCV226 outputs RLDz[6]=0 *2 CTL bits, which are carried during DE=0 expect the 1st and the last pixel.(If MODE0=0) Which are carried during DE=0 except the 1st, 2nd and last 2pixel.(IF MODE0=1) *3 3D flags defined in the V-by-One(R) HS Standard are assigned to the following bits. V-by-One(R) HS Standard Packer/Unpacker D[24](3DLR) LVDS RLEz[6]. V-by-One(R) HS Standard Packer/Unpacker D[25](3DEN) LVDS RLDz[6]. ( z=0,1,2,3) Copyright(c)2019 THine Electronics, Inc. 14/27 THine Electronics, Inc. Security E THCV226_Rev.1.20_E Monitoring Signal Function The recovered HSYNC, VSYNC, DE or CLK from V-by-One(R) HS signals can be monitored by "Monitoring Signal Function". The monitoring lane out of four high-speed data lane is selectable. This function is used for debugging purpose and set by five pins, MON_EN, BET_SEL1, BET_SEL0, BET_LAT and PRBS. The monitoring signal is outputted from BETOUT pin as 1.8V LVCMOS signal. All signals operate as normal mode except these setting pins and monitoring output pin when "Monitoring Signal Function" is enabled. See the table below. Function MON_EN 0 Pin Option Lane Selection BET_SEL1 BET_SEL0 BET_SEL1 BET_SEL0 0 0 0 1 1 0 1 1 1 Signal Selection BET_LAT PRBS BET_LAT 0 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 Table 10. Copyright(c)2019 THine Electronics, Inc. Monitoring Output BETOUT BETOUT DE HSYNC VSYNC CLK DE HSYNC VSYNC CLK DE HSYNC VSYNC CLK DE HSYNC VSYNC CLK Description Normal mode Monitoring Signal Mode to Check Lane0 Monitoring Signal Mode to Check Lane1 Monitoring Signal Mode to Check Lane2 Monitoring Signal Mode to Check Lane3 Monitoring Signal Function 15/27 THine Electronics, Inc. Security E THCV226_Rev.1.20_E Absolute Maximum Ratings Parameter Supply Voltage (VVDD,LVDD,LPVDD,PVDD,CVDD,IOVDD) CMOS Input Voltage CMOS Output Voltage Open Drain Output Voltage CML Receiver Input Voltage LVDS Transmitter Output Voltage Output Current Storage temperature Junction temperature Reflow Peak Temperature/Time Maximum Power Dissipation @+25deg Min Typ Max Unit -0.3 - 2.1 V -0.3 -0.3 -0.3 -0.3 -0.3 -50 -55 - - IOVDD+0.3 IOVDD+0.3 3.6 VVDD+0.3 LVDD+0.3 50 125 125 260/10 2.5 V V V V V mA C C C/sec W Min Typ Max Unit 1.62 1.80 1.98 V -40 - 85 C Table 11. Absolute Maximum Ratings Recommended Operating Conditions Symbol VDD Ta Parameter Supply Voltage (VVDD,LVDD,LPVDD,PVDD,CVDD,IOVDD) Operating Temperature Table 12. Recommended Operating Condition Electrical Specifications Symbol VIH VIL VOH VOL IOZH IOZL IIH IIL Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage ( IO Type : O ) *1 Low Level Output Voltage ( IO Type : O,OD ) *1 Low Level Output Voltage ( IO Type : BI ) *1 Output Leak Current High in Hi-Z State Output Leak Current Low in Hi-Z State High Level Input Leakage Current Low Level Input Leakage Current Condition - Min 0.65VDD -0.3 Typ - Max VDD+0.3 0.35VDD Unit V V IOH = -2mA VDD-0.2 - VDD V IOL = 2mA GND - 0.2 V IOL = 160uA GND - 0.2 V - -10 - 10 uA - -10 - 10 uA - -10 - 10 uA - -10 - 10 uA Table 13. Electrical Specifications *1 IO Type : O = BETOUT , Reserved6,7 OD = HTPDN, LOCKN BI = DGLOCK Copyright(c)2019 THine Electronics, Inc. 16/27 THine Electronics, Inc. Security E THCV226_Rev.1.20_E Symbol VRTH VRTL IRIH IRIL IRRIH IRRIL RRIN Parameter CML Differential Input High Threshold CML Differential Input Low Threshold CML Input High Leak Current CML Input Low Leak Current CML Input High Current CML Input Low Current CML Differential Input Resistance Condition Min Typ Max Unit - - - 50 mV - -50 - - mV -10 - 10 uA -10 - 10 uA -6 - 2 - mA mA 80 100 120 PDN=0, Rxzp/n=VDD PDN=0 Rxzp/n=GND Rxzp/n=VDD Rxzp/n=GND - Table 14. Electrical Specifications ( z=0,1,2,3 ) Symbol VROD ROD VROC ROC IROS Parameter LVDS Differential Mode Output Voltage LVDS Differential Mode Output Voltage Change in VROD between Complementary Output States LVDS Common Mode Output Voltage Change in VROD between Complementary Output States LVDS Output Short Circuit Current LVDS Output Tri-State Current IROZ Condition RL = 100 RS = 1 RL = 100 RS = 0 RL = 100 Min Typ Max Unit 250 350 450 mV 100 200 300 mV - - 35 mV RL = 100 1.125 1.25 1.375 V RL = 100 - - 35 mV - - 100 mA -20 - 20 uA Max 515 415 475 335 440 355 405 285 1 Unit RLyzp/n = GND RL = 100 PDN = 0 RLyzp/n =GND VDD Table 15. Electrical Specifications ( y=A,B,C,CLK,D,E / z=0,1,2,3 ) Supply Current Symbol Parameter Power Supply Current (Worst case pattern) 10bit mode IRCCW Power Supply Current (Gray scale pattern) 10bit mode IRCCS Power Down Supply Current Conditions MODE2,1,0=111 MODE2,1,0=001 MODE2,1,0=000 MODE2,1,0=100 MODE2,1,0=111 MODE2,1,0=001 MODE2,1,0=000 MODE2,1,0=100 PDN = 0 Min - Typ(*1) 450 360 420 295 370 300 345 245 - Table 16. Supply Current *1 : VDD=1.8V, Room temperature Copyright(c)2019 THine Electronics, Inc. 17/27 THine Electronics, Inc. Security E mA mA THCV226_Rev.1.20_E Switching Characteristics Symbol tRBIT tRISK tRIJT tRCOP tRLVT Parameter Condition Min Typ Max Unit Unit Interval (UI) COL = 0 370 tRCOP/30 833 ps COL = 1 294 tRCOP/40 625 ps CML Lane0/1/2/3 Input Inter COL = 0 -30 - 30 UI Pair Skew Margin COL = 1 -40 - 40 UI CML Lane0/1/2/3 Input Jitter COL = 0 - - 15 UI Margin COL = 1 - - 20 UI Clock Out Period - 6.37 - 25 ns - - 0.6 1.5 ns -0.20 tRCOP/7 -0.20 2tRCOP/7 -0.20 3tRCOP/7 -0.20 4tRCOP/7 -0.20 5tRCOP/7 -0.20 6tRCOP/7 -0.20 - 0.20 tRCOP/7 +0.20 2tRCOP/7 +0.20 3tRCOP/7 +0.20 4tRCOP/7 +0.20 5tRCOP/7 +0.20 6tRCOP/7 +0.20 ns 0.25 tRCOP/7 +0.25 2tRCOP/7 +0.25 3tRCOP/7 +0.25 4tRCOP/7 +0.25 5tRCOP/7 +0.25 6tRCOP/7 +0.25 ns 500 ps LVDS Differential Output Transition Time tROP1 LVDS Output Data Position0 HSLVDS tROP0 LVDS Output Data Position1 mode tROP6 LVDS Output Data Position2 tROP5 LVDS Output Data Position3 tROP4 LVDS Output Data Position4 tROP3 LVDS Output Data Position5 tROP2 LVDS Output Data Position6 tROP1 LVDS Output Data Position0 Normal LVDS tROP0 LVDS Output Data Position1 mode tROP6 LVDS Output Data Position2 tROP5 LVDS Output Data Position3 tROP4 LVDS Output Data Position4 tROP3 LVDS Output Data Position5 tROP2 LVDS Output Data Position6 tROSK tRDC (tRCOP= 6.37ns - 8.33ns) (tRCOP= Link0/1/2/3 LVDS Output Clock Skew 11.1ns -16.6ns) - -0.25 tRCOP/7 -0.25 2tRCOP/7 -0.25 3tRCOP/7 -0.25 4tRCOP/7 -0.25 5tRCOP/7 -0.25 6tRCOP/7 -0.25 - Input Data to Output Data MODE0 = 0 (17+27/30) Delay COL = 0 tRCOP+4.5 MODE0 = 1 (34+24/30) COL = 0 tRCOP+5.0 Copyright(c)2019 THine Electronics, Inc. 18/27 tRCOP/7 2tRCOP/7 3tRCOP/7 4tRCOP/7 5tRCOP/7 6tRCOP/7 tRCOP/7 2tRCOP/7 3tRCOP/7 4tRCOP/7 5tRCOP/7 6tRCOP/7 - - - ns ns ns ns ns ns ns ns ns ns ns ns (17+27/30) tRCOP+13.5 (34+24/30) tRCOP+15.5 THine Electronics, Inc. Security E ns THCV226_Rev.1.20_E MODE0 = 0 tRPD tRHPD0 tRHPD1 tRPLL0 tRPLL1 tRPLL2 tRLCK0 tRLCK1 tRDLH tRDLL tRDEH tRDEL Power On to PDN High Delay PDN High to HTPDN Low Delay PDN Low to HTPDN High Delay Training Pattern Input to LOCKN Low Delay PDN Low to LOCKN High Delay LOCKN Low to LVDS CLK Lock Time LOCKN Low to LVDS to LVDS Output Delay LOCKN High Output High-Z/Low Delay DGLOCK High to LOCKN Low DGLOCK Low to LOCKN High DE=1 Duration DE=0 Duration (17+7/40) COL = 1 tRCOP+4.5 MODE0 = 1 (33+14/40) COL = 1 tRCOP+5.0 - - (17+7/40) tRCOP+13.5 (33+14/40) tRCOP+15.5 - 0 - - ns - - - 1 us - - - 1 us - - - 10 ms - - - 10 us - - - 10 ms - - - 1 ms - - - 1 ms - 0 - - ns - 0 - - ns MODE0 = 0 8tRCOP - - ns MODE0 = 1 16tRCOP - - ns MODE0 = 0 8tRCOP - - ns MODE0 = 1 16tRCOP - - ns Table 17. Switching Characteristics Copyright(c)2019 THine Electronics, Inc. ns 19/27 THine Electronics, Inc. Security E THCV226_Rev.1.20_E AC Timing Diagram and Test Circuit (Tx side) (Tx side) 50 50 Txzp C=75 200nF Txzn C=75 200nF Rxzp Rxzn Zo=50 50 z=0,1,2,3 50 Vterm = 1.3V(typ) CML Transmitter CML Receiver (THCV226) Figure 10. CML Buffer Scheme Vdiff = (Rx0p) - (Rx0n) tRBIT (1UI) Vdiff = 0 -tRISK Vdiff = (Rx1p) - (Rx1n) Vdiff = 0 tRIJT +tRISK Vdiff = (Rx2p) - (Rx2n) Vdiff = 0 +tRISK Vdiff = (Rx3p) - (Rx3n) Vdiff = 0 Figure 11. CML Input Timing Diagram RLyzp RL=100 CL=5pF RLyzn 80% Vdiff = (RLyzp) - (RLyzn) y=A,B,C,CLK,D,E z=0,1,2,3 20% tRLVT Figure 12. Copyright(c)2019 THine Electronics, Inc. tRLVT LVDS Output Switching Timing Diagram and Test Circuit 20/27 THine Electronics, Inc. Security E THCV226_Rev.1.20_E tROP2 tROP3 tROP4 tROP5 tROP6 tROP0 tROP1 Vdiff = (RLyzp) - (RLyzn) RLyz5 RLyz4 RLyz3 RLyz2 RLyz1 RLyz0 RLyz6 RLyz5 RLyz4 RLyz3 RLyz2 RLyz1 RLyz0 Vdiff = (RLCLKzp) - (RLCLKzn) Vdiff = 0 y = A,B,C,D,E z = 0,1,2,3 tRCOP Figure 13. LVDS Output Switching Timing Diagram Vdiff = (RLCLKzp) - (RLCLKzn) Vdiff = 0 tROSK Vdiff = (RLCLKzp) - (RLCLKzn) z = 0,1,2,3 Figure 14. Vdiff = 0 LVDS Output Switching Timing Diagram Pixel 1st bit Vdiff = (Rxzp) - (Rxzn) Vdiff = 0 Vdiff = (RLCLKzp) - (RLCLKzn) tRDC z = 0,1,2,3 Previous cycle Current cycle Figure 15. V-by-One(R) HS Input to LVDS Output Latency Copyright(c)2019 THine Electronics, Inc. 21/27 THine Electronics, Inc. Security E THCV226_Rev.1.20_E VDD tRPD PDN tRHPD0 tRHPD1 HTPDN Training Pattern Rxzp/N Training Pattern Normal Pattern Normal Pattern Training Pattern tRPLL1 tRPLL0 LOCKN tRDLH tRDLL DGLOCK tRPLL2 RLCLKzp/n Hi-Z Invalid Clock Hi-Z Invalid Pattern OPF=0 tRLCK1 Invalid Clock Hi-Z Invalid Pattern Hi-Z Invalid Clock Hi-Z tRLCK0 RLyzp/n OPF=0 Valid Pattern Invalid Pattern Valid Pattern Hi-Z VDD tRPD PDN tRHPD0 tRHPD1 HTPDN Training Pattern Rxz/p/n Normal Pattern Training Pattern Normal Pattern Training Pattern tRPLL1 tRPLL0 LOCKN tRDLH tRDLL DGLOCK tRPLL2 RLCLKzp/n OPF=1 tRLCK1 Invalid Clock Invalid Clock Low Pattern Invalid Clock Invalid Pattern Low Pattern Invalid Pattern Hi-Z Invalid Clock Hi-Z Invalid Pattern tRLCK0 RLyzp/n OPF=1 y = A,B,C,D,E z = 0,1,2,3 Invalid Pattern Valid Pattern Figure 16. Valid Pattern THCV226 Lock/Unlock Sequence Vdiff = (RLCLKzp)-(RLCLKzn) DE DE DE DE DE DE Vdiff = (RLCzp)-(RLCzn) Z = 0,1,2,3 tRDEH tRDEL Figure 17. DE Period Requirement Copyright(c)2019 THine Electronics, Inc. 22/27 THine Electronics, Inc. Security E THCV226_Rev.1.20_E Note 1) LVDS Output Pin Connection In case that the LVDS Rx of destination device is equipped with pull-up resistors connected to higher than THCV226's VDD voltage, this can cause violation of absolute maximum ratings to THCV226. This phenomenon may be happened at power-on phase and Hi-Z state of the whole system including LVDS Rx device. One solution for this problem is power-down control for LVDS Rx device during no LVDS input or Hi-Z state period, if its pull-up resistors can be cut off at power-down state. Another solution is to set THCV226's OPF option pin to VDD. This setting provides low fixed data output mode at PDN=1, not Hi-Z state mode. HVDD(3.3V) LVDS Receiver LVDD(1.8V) LVDS Buffer ! 1.8V thin transistor 2) Cable Connection and Disconnection Do not connect and disconnect the LVDS and CML cables, when the power is supplied to the system. 3) GND Connection Connect the each GND of the PCB which Transmitter and Receiver. It is better for EMI reduction to place GND cables as close to LVDS and CML cables as possible. 4) Multi-drop Connect Multi-drop connect is not recommended. THCV226 LVDS Rx LVDS Rx Copyright(c)2019 THine Electronics, Inc. 23/27 THine Electronics, Inc. Security E THCV226_Rev.1.20_E 5) Multiple Counterpart Use Multiple counterpart use such as the following system is not recommended. If it is not avoidable, please check whether tRISK and tRIJT spec of THCV226 can be kept or not. Furthermore, please contact to mspsupport@thine.co.jp (for FAE mailing list) Tx0n/p CLKOUT DATA IC (R) V-by-One HS Tx ! Tx2n/p CLKOUT DATA Tx1n/p V-by-One(R) HS Tx THCV226 Tx3n/p 6) Multiple Device Connection HTPDN and LOCKN signals are supposed to be connected properly for their purpose like the following figure. HTPDN should be from just one THCV226 to multiple Tx devices because its purpose is only ignition of all Tx devices. LOCKN should be connected so as to indicate that CDR status of all Rx devices becomes ready to receive normal operation data. LOCKN of Tx side can be simply split to multiple Tx devices. THCV226's DGLOCK is appropriate for multiple Rx use. Also possible time difference of internal processing time (THCV226 tRDC) on multiple data stream must be accommodated and compensated by the following destination device connected to multiple THCV226s, which may have internal FIFO. Copyright(c)2019 THine Electronics, Inc. 24/27 THine Electronics, Inc. Security E THCV226_Rev.1.20_E Source Device THCV226 clkout.1 HTPDN HTPDN clkout.2 LOCKN LOCKN clkout.3 DGLOCK clkout.4 FIFO clkin Time diff. comes up THCV226 Destination Device clkout.1 HTPDN clkout.2 LOCKN clkout.3 DGLOCK clkout.4 FIFO Internal processing time tRDC clkin.1 Source Device 1 THCV226 HTPDN HTPDN clkout.2 LOCKN LOCKN clkout.3 DGLOCK clkout.4 Ex. synchronized Time diff. comes up Source Device 2 clkin.2 clkout.1 THCV226 FIFO Destination Device clkout.1 HTPDN HTPDN clkout.2 LOCKN LOCKN clkout.3 DGLOCK clkout.4 FIFO Internal processing time tRDC Copyright(c)2019 THine Electronics, Inc. 25/27 THine Electronics, Inc. Security E THCV226_Rev.1.20_E Package 97 65 64 128 33 16.00 14.00 98 1 32 16.00 14.00 0.40 +0.05 0.18 +0.05 0.08MAX 1.20 MAX 1.00 +0.05 0.05 0.15 0.25TYP 0 7 0.45 0.75 1.00TYP Unit : mm Detail of Lead End Figure 18. Copyright(c)2019 THine Electronics, Inc. 128-pin TQFP package physical dimension 26/27 THine Electronics, Inc. Security E THCV226_Rev.1.20_E Notices and Requests 1. The product specifications described in this material are subject to change without prior notice. 2. The circuit diagrams described in this material are examples of the application which may not always apply to the customer's design. THine Electronics, Inc. ("THine") is not responsible for possible errors and omissions in this material. Please note even if errors or omissions should be found in this material, THine may not be able to correct them immediately. 3. This material contains THine's copyright, know-how or other proprietary. Copying or disclosing to third parties the contents of this material without THine's prior permission is prohibited. 4. Note that even if infringement of any third party's industrial ownership should occur by using this product, THine will be exempted from the responsibility unless it directly relates to the production process or functions of the product. 5. Product Application 5.1 Application of this product is intended for and limited to the following applications: audio-video device, office automation device, communication device, consumer electronics, smartphone, feature phone, and amusement machine device. This product must not be used for applications that require extremely high-reliability/safety such as aerospace device, traffic device, transportation device, nuclear power control device, combustion chamber device, medical device related to critical care, or any kind of safety device. 5.2 This product is not intended to be used as an automotive part, unless the product is specified as a product conforming to the demands and specifications of IATF16949 ("the Specified Product") in this data sheet. THine accepts no liability whatsoever for any product other than the Specified Product for it not conforming to the aforementioned demands and specifications. 5.3 THine accepts liability for demands and specifications of the Specified Product only to the extent that the user and THine have been previously and explicitly agreed to each other. 6. Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain small probability, which is inevitable to a semi-conductor product. Therefore, you are encouraged to have sufficiently redundant or error preventive design applied to the use of the product so as not to have our product cause any social or public damage. 7. Please note that this product is not designed to be radiation-proof. 8. Testing and other quality control techniques are used to this product to the extent THine deems necessary to support warranty for performance of this product. Except where mandated by applicable law or deemed necessary by THine based on the user's request, testing of all functions and performance of the product is not necessarily performed. 9. Customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods under the Foreign Exchange and Foreign Trade Act. 10. The product or peripheral parts may be damaged by a surge in voltage over the absolute maximum ratings or malfunction, if pins of the product are shorted by such as foreign substance. The damages may cause a smoking and ignition. Therefore, you are encouraged to implement safety measures by adding protection devices, such as fuses. THine Electronics, Inc. sales@thine.co.jp https://www.thine.co.jp Copyright(c)2019 THine Electronics, Inc. 27/27 THine Electronics, Inc. Security E