2.7 V to 5.5 V, Serial-Input,
Voltage Output, Unbuffered 16-Bit DAC
AD5541A
Rev. A
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Fax: 781.461.3113 ©2010–2011 Analog Devices, Inc. All rights reserved.
FEATURES
16-bit resolution
11.8 nV/√Hz noise spectral density
1 μs settling time
1.1 nV-sec glitch energy
0.05 ppm/°C temperature drift
5 kV HBM ESD classification
0.375 mW power consumption at 3 V
2.7 V to 5.5 V single-supply operation
Hardware CS and LDAC functions
50 MHz SPI-/QSPI-/MICROWIRE-/DSP-compatible interface
Power-on reset clears DAC output to zero scale
Available in 3 mm × 3 mm, 8-/10-lead LFCSP and 10-lead
MSOP
APPLICATIONS
Automatic test equipment
Precision source-measure instruments
Data acquisition systems
Medical instrumentation
Aerospace instrumentation
Communications infrastructure equipment
Industrial control
FUNCTIONAL BLOCK DIAGRAMS
16-BIT DAC
16-BI T DAC LATCH
SERIAL I NPUT REGISTER
V
DD
V
LOGIC
DGND
DIN
REF
SCLK
CS
LDAC
VOUT
AGND
AD5541A
08516-001
CONTROL
LOGIC
Figure 1. AD5541A
16-BIT DAC
16-BI T DAC LATCH
SERIAL INPUT REGISITER
V
DD
GND
DIN
REF
S
CLK
CS
CLR
V
OUT
AD5541A-1
CONTROL
LOGIC
08516-002
Figure 2. AD5541A-1
GENERAL DESCRIPTION
The AD5541A is a single, 16-bit, serial input, unbuffered voltage
output digital-to-analog converter (DAC) that operates from a
single 2.7 V to 5.5 V supply.
The DAC output range extends from 0 V to VREF and is guaranteed
monotonic, providing ±1 LSB INL accuracy at 16 bits without
adjustment over the full specified temperature range of −40°C
to +125°C. The AD5541A is available in a 3 mm × 3 mm, 10-lead
LFCSP and 10-lead MSOP. The AD5541A-1 is available in a
3 mm × 3 mm, 8-lead LFCSP.
Offering unbuffered outputs, the AD5541A achieves a 1 µs set-
tling time with low power consumption and low offset errors.
Providing low noise performance of 11.8 nV/√Hz and low
glitch, the AD5541A is suitable for deployment across multiple
end systems.
The AD5541A uses a versatile 3-wire interface that is compatible
with 50 MHz SPI, QSPI™, MICROWIRE™, and DSP interface
standards.
Table 1. Related Devices
Part No. Description
AD5040/AD5060 2.7 V to 5.5 V 14-/16-bit buffed output DACs
AD5541/AD5542 2.7 V to 5.5 V 16-bit voltage output DACs
AD5781/AD5791 18-/20-bit voltage output DACs
AD5024/AD5064 4.5 V to 5.5 V, 12-/16-bit quad channel DACs
AD5061 Single, 16-bit nanoDAC, ±4 LSB INL, SOT-23
AD5542A 16-bit, bipolar, voltage output DAC
PRODUCT HIGHLIGHTS
1. 16-bit performance without adjustment.
2. 2.7 V to 5.5 V single operation.
3. Low 11.8 nV/√Hz noise spectral density.
4. Low 0.05 ppm/°C temperature drift.
5. 3 mm × 3 mm LFCSP and MSOP packaging.
AD5541A
Rev. A | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagrams............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Characteristics........................................................................ 4
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 9
Terminology .................................................................................... 13
Theory of Operation ...................................................................... 14
Digital-to-Analog Section ......................................................... 14
Serial Interface............................................................................ 14
Unipolar Output Operation...................................................... 15
Output Amplifier Selection....................................................... 15
Force Sense Amplifier Selection............................................... 16
Reference and Ground............................................................... 16
Power-On Reset.......................................................................... 16
Power Supply and Reference Bypassing.................................. 16
Applications Information.............................................................. 17
Microprocessor Interfacing....................................................... 17
AD5541A to ADSP-BF531 Interface ....................................... 17
AD5541A to SPORT Interface.................................................. 17
Layout Guidelines....................................................................... 17
Galvanically Isolated Interface ................................................. 17
Decoding Multiple DACs.......................................................... 18
Outline Dimensions....................................................................... 19
Ordering Guide .......................................................................... 20
REVISION HISTORY
3/11—Rev. 0 to Rev. A
Added 10-Lead LFCSP and 8-Lead LFCSP.....................Universal
Changes to Features, General Description, and Product
Highlights Sections and Table 1 ..................................................... 1
Added Figure 2; Renumbered Sequentially .................................. 1
Changes to Logic Inputs Parameter, Table 1................................. 3
Changes to Figure 3.......................................................................... 5
Changes to Table 5............................................................................ 6
Changes to Table 6............................................................................ 7
Added Figure 5 and Figure 6............................................................8
Added Table 7; Renumbered Sequentially .....................................8
Changes to Figure 15...................................................................... 10
Changed VREF to VREF – 1 LSB in Unipolar Output Operation
Section.............................................................................................. 15
Updated Outline Dimensions....................................................... 18
Changes to Ordering Guide.......................................................... 18
7/10—Revision 0: Initial Version
AD5541A
Rev. A | Page 3 of 20
SPECIFICATIONS
VDD = 2.7 V to 5.5 V, 2.5 V ≤ VREF ≤ VDD, AGND = DGND = 0 V, −40°C < TA < +125°C,1 unless otherwise noted.
Table 2.
Parameter Min Typ Max Unit Test Condition
STATIC PERFORMANCE
Resolution 16 Bits
Relative Accuracy (INL) ±0.5 ±1.0 LSB B grade
±0.5 ±2.0 LSB A grade
Differential Nonlinearity (DNL) ±0.5 ±1.0 LSB Guaranteed monotonic
Gain Error 0.5 ±2 LSB TA = 25°C
±3 LSB −40°C < TA < +85°C
±4 LSB −40°C < TA < +125°C
Gain Error Temperature Coefficient ±0.1 ppm/°C
Zero-Code Error 0.3 ±0.7 LSB TA = 25°C
±1.5 LSB −40°C < TA < +85°C
±3 LSB −40°C < TA < +125°C
Zero-Code Temperature Coefficient ±0.05 ppm/°C
DC Power Supply Rejection Ratio ±1 LSB ∆VDD ± 10%
OUTPUT CHARACTERISTICS2
Output Voltage Range 0 VREF − 1 LSB V Unipolar operation
DAC Output Impedance 6.25 kΩ Tolerance typically 20%
DAC REFERENCE INPUT3
Reference Input Range 2.0 VDD V
Reference Input Resistance 9 kΩ Unipolar operation
Reference Input Capacitance 26 pF Code 0x0000
26 pF Code 0xFFFF
LOGIC INPUTS
Input Current ±1 A
Input Low Voltage, VINL 0.4 V VLOGIC = 1.8 V to 5.5 V
0.8 V
VLOGIC = 2.7 V to 5.5 V
Input High Voltage, VINH 2.4 V
VLOGIC = 4.5 V to 5.5 V
1.8 V
VLOGIC = 2.7 V to 3.6 V
1.3 V
VLOGIC = 1.8 V to 2.7 V
Input Capacitance2 10 pF
Hysteresis Voltage2 0.15 V
POWER REQUIREMENTS
VDD 2.7 5.5 V All digital inputs at 0 V, VLOGIC, or VDD
IDD 125 150 µA VIH = VLOGIC or VDD and VIL = GND
VLOGIC 1.8 5.5 V
ILOGIC 15 24 µA All digital inputs at 0 V, VLOGIC, or VDD
Power Dissipation 0.625 0.825 mW
1 For 2.7 V ≤ VLOGIC ≤ 5.5 V: −40°C < TA < +125°C. For 1.8 V ≤ VLOGIC ≤ 2.7 V: −40°C < TA < +105°C.
2 Guaranteed by design, but not subject to production test.
3 Reference input resistance is code-dependent, minimum at 0x8555.
AD5541A
Rev. A | Page 4 of 20
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V, 2.5 V ≤ VREF ≤ VDD, AGND = DGND = 0 V, −40°C < TA < +125°C, unless otherwise noted.
Table 3.
Parameter Min Typ Max Unit Test Condition
Output Voltage Settling Time 1 s To ½ LSB of full scale, CL = 10 pF
Slew Rate 17 V/s CL = 10 pF, measured from 0% to 63%
Digital-to-Analog Glitch Impulse 1.1 nV-sec 1 LSB change around major carry
Reference −3 dB Bandwidth 2.2 MHz All 1s loaded
Reference Feedthrough 1 mV p-p All 0s loaded, VREF = 1 V p-p at 100 kHz
Digital Feedthrough 0.2 nV-sec
Signal-to-Noise Ratio 92 dB
Spurious Free Dynamic Range 80 dB Digitally generated sine wave at 1 kHz
Total Harmonic Distortion 74 dB DAC code = 0xFFFF, frequency 10 kHz,
VREF = 2.5 V ± 1 V p-p
Output Noise Spectral Density 11.8 nV/√Hz DAC code = 0x0000, frequency = 1 kHz
Output Noise 0.134 V p-p 0.1 Hz to 10 Hz
AD5541A
Rev. A | Page 5 of 20
TIMING CHARACTERISTICS
VDD = 5 V, 2.5 V ≤ VREF ≤ VDD, VINH = 90% of VLOGIC, VINL = 10% of VLOGIC, AGND = DGND = 0 V, −40°C < TA < +105°C, unless otherwise
noted.
Table 4.
Parameter1, 2
Limit at
1.8 ≤ VLOGIC ≤ 2.7 V
Limit at
2.7 V ≤ VLOGIC ≤ 5.5 V Unit Description
fSCLK 14 50 MHz max SCLK cycle frequency
t1 70 20 ns min SCLK cycle time
t2 35 10 ns min SCLK high time
t3 35 10 ns min SCLK low time
t4 5 5 ns min
CS low to SCLK high setup
t5 5 5 ns min
CS high to SCLK high setup
t6 5 5 ns min
SCLK high to CS low hold time
t7 10 5 ns min
SCLK high to CS high hold time
t8 35 10 ns min Data setup time
t9 5 4 ns min Data hold time (VINH = 90% of VDD, VINL = 10% of VDD)
t9 5 5 ns min Data hold time (VINH = 3 V, VINL = 0 V)
t10 20 20 ns min
LDAC pulse width
t11 10 10 ns min
CS high to LDAC low setup
t12 15 15 ns min
CS high time between active periods
1 Guaranteed by design and characterization. Not production tested.
2 All input signals are specified with tR = tF = 1 ns/V and timed from a voltage level of (VINL + VINH)/2.
SCLK
CS
DIN DB15
LDAC
t
6
t
4
t
12
t
8
t
9
t
2
t
3
t
1
t
7
t
5
t
11
t
10
08516-003
Figure 3. Timing Diagram
AD5541A
Rev. A | Page 6 of 20
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 5.
Parameter Rating
VDD to AGND −0.3 V to +6 V
VLOGIC to DGND −0.3 V to +6 V
Digital Input Voltage to DGND −0.3 V to VDD/VLOGIC +
0.3 V
VOUT to AGND −0.3 V to VDD + 0.3 V
AGND to DGND −0.3 V to +0.3 V
Input Current to Any Pin Except Supplies ±10 mA
Operating Temperature Range
Industrial (A, B Versions) −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature (TJ max) 150°C
Package Power Dissipation (TJ max − TA)/θJA
Thermal Impedance, θJA
LFCSP (CP-10-9) 50°C/W
LFCSP (CP-8-11) 62°C/W
MSOP (RM-10) 135°C/W
Lead Temperature, Soldering
Peak Temperature1 260°C
ESD2 5 kV
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
1 As per JEDEC Standard 20.
2 Human body model (HBM) classification.
AD5541A
Rev. A | Page 7 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
V
DD 1
V
OUT 2
A
GND
3
REF
4
CS
5
V
LOGIC
10
DGND
9
LDAC
8
DIN
7
SCLK
6
AD5541A
TOP VIEW
(Not to Scal e)
08516-031
Figure 4. AD5541A 10-Lead MSOP Pin Configuration
Table 6. AD5541A Pin Function Descriptions
Pin No. Mnemonic Description
1 VDD Analog Supply Voltage.
2 VOUT Analog Output Voltage from the DAC.
3 AGND Ground Reference Point for Analog Circuitry.
4 REF Voltage Reference Input for the DAC. Connect to an external 2.5 V reference. The reference can range from
2 V to VDD.
5 CS Logic Input Signal. The chip select signal is used to frame the serial data input.
6 SCLK
Clock Input. Data is clocked into the serial input register on the rising edge of SCLK. The duty cycle must be
between 40% and 60%.
7 DIN Serial Data Input. This device accepts 16-bit words. Data is clocked into the serial input register on the rising edge
of SCLK.
8 LDAC LDAC Input. When this input is taken low, the DAC register is simultaneously updated with the contents of the
serial register data.
9 DGND Digital Ground. Ground reference for digital circuitry.
10 VLOGIC Logic Power Supply.
AD5541A
Rev. A | Page 8 of 20
08516-004
NOTES
1. FOR INCREAS E D RELI ABIL I
T
Y OF THE SO L DE R
JOINTS AND M AX IMUM THERMAL CAPABIL ITY,
IT I S RECOMM E NDE D THAT T HE PAD BE SOLDERED
TO THE SUBS T RAT E , G ND.
3SCLK
4DIN
1REF
2CS
6V
OUT
5CLR
8GND
7V
DD
TOP VI EW
(No t to S c ale)
AD5541A-1
Figure 5. AD5541A-1 8-Lead LFCSP Pin Configuration
08516-005
1VDD
2VOUT
3AGND
4REF
5
10 VLOGIC
9DGND
8
7DIN
6SCLK
TOP VIEW
(No t to Scal e)
AD5541A
CS
LDAC
NOTES
1. F O R I NCRE ASE D RELI ABI L I
T
Y OF THE SOLDER
JOINT S AND M AX IMUM THERMAL CAPABILITY,
IT I S RE COMMENDED T HAT THE PAD BE SOLDERED
TO THE SUBSTRATE, GND.
Figure 6. AD5541A 10-Lead LFCSP Pin Configuration
Table 7. AD5541A-1 and AD5541A Pin Function Descriptions
Pin No.
8-Lead LFCSP 10-Lead LFCSP Mnemonic Description
1 4 REF
Voltage Reference Input for the DAC. Connect to an external 2.5 V reference. The
reference can range from 2 V to VDD.
2 5 CS Logic Input Signal. The chip select signal is used to frame the serial data input.
3 6 SCLK
Clock Input. Data is clocked into the serial input register on the rising edge of SCLK.
Duty cycle must be between 40% and 60%.
4 7 DIN
Serial Data Input. This device accepts 16-bit words. Data is clocked into the serial input
register on the rising edge of SCLK.
5 N/A1 CLR Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all
LDAC pulses are ignored. When CLR is activated, the serial input register and the DAC
register are cleared to zero scale.
6 2 VOUT Analog Output Voltage from the DAC.
N/A1 9 DGND Digital Ground. Ground reference for digital circuitry.
7 1 VDD Analog Supply Voltage.
8 N/A1 GND Ground Reference Point for Both Analog and Digital Circuitry.
N/A1 3 AGND Ground Reference Point for Analog Circuitry.
N/A1 10 VLOGIC Logic Power Supply.
N/A1 8 LDAC LDAC Input. When this input is taken low, the DAC register is simultaneously updated
with the contents of the serial input register.
EPAD
Exposed Pad. For increased reliability of the solder joints and maximum thermal
capability, it is recommended that the pad be soldered to the substrate, GND.
1 N/A means not applicable.
AD5541A
Rev. A | Page 9 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
0.50
0.25
0
–0.25
–0.50
–0.750 8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536
CODE
INTEG RAL NONLINEARI TY (LSB)
08516-006
V
DD
= 5V
V
REF
= 2. 5V
Figure 7. Integral Nonlinearity vs. Code
0.25
0
–0.25
–0.50
–0.75
–1.00
–60 –40 –20 0 20 40 60 80 100 120 140
TEM PE RAT URE ( ° C)
INT E GRAL NONLINEARI T Y (LS B)
08516-007
V
DD
= 5V
V
REF
= 2. 5V
Figure 8. Integral Nonlinearity vs. Temperature
0.50
0.25
0
–0.25
–0.50
–0.75 234567
SUPPLY VOLTAGE (V)
LINEARITY ERROR (L S B)
08516-008
DNL
INL
V
REF
= 2. 5V
T
A
= 25°C
Figure 9. Linearity Error vs. Supply Voltage
0.50
0.25
0
–0.25
–0.50 0 8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536
CODE
DIF FERENTIAL NONLINE ARI TY ( LSB)
08516-009
V
DD
= 5V
V
REF
= 2. 5V
Figure 10. Differential Nonlinearity vs. Code
0.75
0.50
0.25
0
–0.25
–0.50
–60 –40 –20 0 20 40 60 80 100 120 140
TEM PE RAT URE ( ° C)
DIFFE RENTIAL NONLI NEARITY ( LSB)
08516-010
V
DD
= 5V
V
REF
= 2. 5V
Figure 11. Differential Nonlinearity vs. Temperature
0.75
0.50
0.25
0
–0.25
–0.50 012345
REFE RENCE V O L T AG E (V)
LINEARITY ERROR (L S B)
08516-011
6
DNL
INL
V
DD
= 5V
T
A
= 25° C
Figure 12. Linearity Error vs. Reference Voltage
AD5541A
Rev. A | Page 10 of 20
3
2
1
0
–1
–2
–3
–100 –50 0 50 100 150
TEM PE RAT URE ( ° C)
GA IN E R ROR ( LS B )
08516-012
VDD = 5V
VREF = 2.5V
TA = 25°C
Figure 13. Gain Error vs. Temperature
160
0
20
40
60
80
100
120
140
–55 –5 45 95
TEMPERATURE (°C)
SUPPL Y CURRENT (µA)
08516-013
V
DD
= 5V
V
REF
= 2. 5V
T
A
= 25°C
Figure 14. Supply Current vs. Temperature
200
0
20
40
60
80
100
120
140
160
180
1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0
DIGITAL INPUT VOLTAGE (V)
SUPPL Y CURRENT ( µA)
08516-014
Figure 15. Supply Current vs. Digital Input Voltage
1.5
–1.5
–1.0
–0.5
0
0.5
1.0
–5–55 45 95
TEM PE RAT URE ( ° C)
ZERO - CO DE ERRO R (LSB)
V
DD
= 5V
V
REF
= 2. 5V
T
A
= 25°C
08516-015
Figure 16. Zero-Code Error vs. Temperature
08516-016
0
50
100
150
200
012345
SUPPLY CURRENT (µ A)
VOLTAG E ( V)
6
T
A
= 25°C
REFERENCE VO LT AGE
V
DD
= 5V
SUPPLY VOLTAGE
V
REF
= 2.5V
Figure 17. Supply Current vs. Reference Voltage or Supply Voltage
200
150
100
50
00 70,00060,00050,00040,00030,00020,00010,000 CO DE (Decimal )
REFE RENCE CURRE NT (µ A)
08516-017
V
DD
= 5V
V
REF
= 2. 5V
T
A
= 25° C
Figure 18. Reference Current vs. Code
AD5541A
Rev. A | Page 11 of 20
08516-018
V
REF
= 2. 5V
V
DD
= 5V
T
A
= 25°C
DIN (5V /DIV )
V
OUT
(50mV/DIV)
2µs/DIV
100
10
90
0%
Figure 19. Digital Feedthrough
VOLTAGE (V)
1.236
1.234
1.232
1.230
1.228
1.226
1.224
–0.5 0 0.5 1.0 1.5 2.0
5
0
–5
–10
–15
–20
–25
–30
TIME (ns)
V
OUT
CS
08516-032
Figure 20. Digital-to-Analog Glitch Impulse
0
8516-020
•••••••• •••• •••• •••• •••• •••• •••• •••• ••••
•••••••• •••• •••• •••• •••• •••• •••• •••• ••••
100
90
10
0%
CS (5V/DIV )
V
OUT
(0.5V/DIV)
V
REF
= 2. 5V
V
DD
= 5V
T
A
= 25°C
200pF
10pF
50pF 100pF
2µs/DIV
Figure 21. Large Signal Settling Time
•••••••• •••• •••• •••• •••• •••• •••• •••• ••••
•••••••• •••• •••• •••• •••• •••• •••• •••• ••••
100
90
10
0%
08516-021
V
OUT
(1V/DI V)
V
OUT
(50mV/DIV)
GAIN = –216
1LS B = 8.2m V
0.5µs/DIV
V
REF
= 2. 5V
V
DD
= 5V
T
A
= 25°C
Figure 22. Small Signal Settling Time
5
4
3
2
1
090 100 110 120
I
DD
SUPPLY (µA)
HITS
08516-038
+125°C
+25°C
–55°C
Figure 23. Analog Supply Current Histogram
6
5
4
3
2
1
015 16 17 18 19
I
LOGIC
AT RAILS (µA)
HITS
08516-039
+125°C
+25°C
–55°C
Figure 24. Digital Supply Current Histogram
AD5541A
Rev. A | Page 12 of 20
40
20
0
–20
–40
–60
–80
–1000 10,000 20,000 30,000 40,000 60,00050,000 70,000
FREQUENCY (Hz )
VOUT (dBm)
08516-036
10
5
0
–50 20406080100120
FREQUENCY ( Hz)
OUTPUT NOISE (µ V rms)
08516-033
Figure 25. 0.1 Hz to 10 Hz Output Noise Figure 28. Total Harmonic Distortion
40
35
30
25
20
15
10
5
0
600 700 800 900 1000 12001100 1300 1400
FREQUENCY (Hz )
NOI S E S PECTRAL DENSITY (n V rms/ Hz)
08516-034
10
0
–20
–10
–30
–40
–50
–601k 10k 100k 1M 10M 100M
FREQUENCY ( Hz)
V
OUT
/
V
REF
(dBm)
08516-037
Figure 26. Noise Spectral Density vs. Frequency,1 kHz Figure 29. Multiplying Bandwidth
14
12
10
8
6
4
2
0
9600 9700 9800 9900 10,000 10,20010,100 10,300 10,400
FREQUENCY ( Hz)
NOISE SPECTRAL DENSITY (nV rms/ Hz)
08516-035
Figure 27. Noise Spectral Density vs. Frequency, 10 kHz
AD5541A
Rev. A | Page 13 of 20
TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL)
For the DAC, relative accuracy or INL is a measure of the
maximum deviation, in LSBs, from a straight line passing
through the endpoints of the DAC transfer function. A typical
INL vs. code plot is shown in Figure 7.
Differential Nonlinearity (DNL)
DNL is the difference between the measured change and the
ideal 1 LSB change between any two adjacent codes. A specified
differential nonlinearity of ±1 LSB maximum ensures mono-
tonicity. A typical DNL vs. code plot is shown in Figure 10.
Gain Error
Gain error is the difference between the actual and ideal analog
output range, expressed as a percent of the full-scale range.
It is the deviation in slope of the DAC transfer characteristic
from ideal.
Gain Error Temperature Coefficient
Gain error temperature coefficient is a measure of the change
in gain error with changes in temperature. It is expressed in
ppm/°C.
Zero-Code Error
Zero-code error is a measure of the output error when zero
code is loaded to the DAC register.
Zero-Code Temperature Coefficient
This is a measure of the change in zero-code error with a
change in temperature. It is expressed in mV/°C.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-sec
and is measured when the digital input code is changed by
1 LSB at the major carry transition. A digital-to-analog glitch
impulse plot is shown in Figure 20.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but it is measured when the DAC output is not updated.
CS is held high while the SCLK and DIN signals are toggled. It
is specified in nV-sec and is measured with a full-scale code
change on the data bus, that is, from all 0s to all 1s and vice
versa. A typical digital feedthrough plot is shown in . Figure 19
Power Supply Rejection Ratio (PSRR)
PSRR indicates how the output of the DAC is affected by changes
in the power supply voltage. The power supply rejection ratio is
expressed in terms of percent change in output per percent
change in VDD for full-scale output of the DAC. VDD is varied by
±10%.
Reference Feedthrough
Reference feedthrough is a measure of the feedthrough from the
VREF input to the DAC output when the DAC is loaded with all
0s. A 100 kHz, 1 V p-p is applied to VREF. Reference feedthrough
is expressed in mV p-p.
AD5541A
Rev. A | Page 14 of 20
THEORY OF OPERATION
The AD5541A is a single, 16-bit, serial input, voltage output
DAC. It operates from a single supply ranging from 2.7 V to 5 V
and consumes typically 125 µA with a supply of 5 V. Data is written
to these devices in a 16-bit word format, via a 3- or 4-wire serial
interface. To ensure a known power-up state, this part is designed
with a power-on reset function. The output is reset to 0 V.
DIGITAL-TO-ANALOG SECTION
The DAC architecture consists of two matched DAC sections.
A simplified circuit diagram is shown in Figure 30. The DAC
architecture of the AD5541A is segmented. The four MSBs of
the 16-bit data-word are decoded to drive 15 switches, E1 to
E15. Each switch connects one of 15 matched resistors to either
AGND or VREF. The remaining 12 bits of the data-word drive
the S0 to S11 switches of a 12-bit voltage mode R-2R ladder
network.
2R . . . . .
S1 . . . . .
2R
S11
2R
E1
2R . . . . .
E2 . . . . .
2R 2R
S0
2R
E15
R R
V
REF
V
OUT
12-BI T R-2R LADDER FO UR MS Bs DE CODED
INTO 15 EQUAL SEGMENTS
08516-022
Figure 30. DAC Architecture
With this type of DAC configuration, the output impedance is
independent of code, whereas the input impedance seen by the
reference is heavily code dependent. The output voltage is
dependent on the reference voltage, as shown in the following
equation:
N
REF
OUT
DV
V2
×
=
where:
D is the decimal data-word loaded to the DAC register.
N is the resolution of the DAC.
For a reference of 2.5 V, the equation simplifies to the following:
536,65
5.2 D
VOUT
×
=
This gives a VOUT of 1.25 V with midscale loaded and 2.5 V with
full scale loaded to the DAC.
The LSB size is VREF/65,536.
SERIAL INTERFACE
The AD5541A is controlled by a versatile 3- or 4-wire serial
interface that operates at clock rates of up to 50 MHz and is
compatible with SPI, QSPI, MICROWIRE, and DSP interface
standards. The timing diagram is shown in Figure 3. The
AD5541A has a separate serial input register from the 16-bit
DAC register that allows preloading of a new data value into the
serial input register without disturbing the present DAC output
voltage.
Input data is framed by the chip select input, CS. After a high-
to-low transition on CS, data is shifted synchronously and
latched into the serial input register on the rising edge of the
serial clock, SCLK. After 16 data bits have been loaded into the
serial input register, a low-to-high transition on CS transfers the
contents of the shift register to the DAC register if LDAC is held
low. If LDAC is high at this point, a low-to-high transition on
CS transfers the contents into the serial input register only.
After a new value is fully loaded in the serial input register, it
can be asynchronously transferred to the DAC register by
strobing the LDAC pin. Data is loaded MSB first in 16-bit
words. Data can be loaded to the part only while CS is low.
AD5541A
Rev. A | Page 15 of 20
UNIPOLAR OUTPUT OPERATION
This DAC is capable of driving unbuffered loads of 60 kΩ.
Unbuffered operation results in low supply current, typically
300 A, and a low offset error. The AD5541A provides a
unipolar output swing ranging from 0 V to VREF − 1 LSB.
Figure 31 shows a typical unipolar output voltage circuit. The
code table for this mode of operation is shown in Table 8. The
example includes the ADR421 2.5 V reference and the AD8628
low offset and zero-drift reference buffer.
Table 8. Unipolar Code Table
DAC Latch Contents
MSB LSB Analog Output
1111 1111 1111 1111 VREF × (65,535/65,536)
1000 0000 0000 0000 VREF × (32,768/65,536) = ½ VREF
0000 0000 0000 0001 VREF × (1/65,536)
0000 0000 0000 0000 0 V
Assuming a perfect reference, the unipolar worst-case output
voltage can be calculated from the following equation:
()
INLVVV
D
VZSE
GE
REF
UNIOUT +++×=
−16
2
where:
VOUT−UNI is the unipolar mode worst-case output.
D is the code loaded to DAC.
VREF is the reference voltage applied to the part.
VGE is the gain error in volts.
VZSE is the zero-scale error in volts.
INL is the integral nonlinearity in volts.
OUTPUT AMPLIFIER SELECTION
For bipolar mode, a precision amplifier should be used and
supplied from a dual power supply. This provides the ±VREF
output. In a single-supply application, selection of a suitable
op amp may be more difficult because the output swing of the
amplifier does not usually include the negative rail, in this case,
AGND. This can result in some degradation of the specified
performance unless the application does not use codes near zero.
The selected op amp must have a very low offset voltage (the
DAC LSB is 38 V with a 2.5 V reference) to eliminate the need
for output offset trims. Input bias current should also be very
low because the bias current, multiplied by the DAC output
impedance (approximately 6 k), adds to the zero-code error.
Rail-to-rail input and output performance is required. For fast
settling, the slew rate of the op amp should not impede the
settling time of the DAC. Output impedance of the DAC is
constant and code independent, but to minimize gain errors,
the input impedance of the output amplifier should be as high
as possible. The amplifier should also have a 3 dB bandwidth of
1 MHz or greater. The amplifier adds another time constant to
the system, thus increasing the settling time of the output. A
higher 3 dB amplifier bandwidth results in a shorter effective
settling time of the combined DAC and amplifier.
08516-023
V
OUT
V
OUT
V
IN
REF
DGND AGND
V
DD
DIN
SCLK
CS
AD5541A
AD820/
OP196
AD8628
ADR421
+
0.1µF
0.1µF
0.1µF 10µF
UNIPOLAR
OUTPUT
EXTERNAL
OP AMP
5V
5V
SERIAL
INTERFACE
1µF
6
2
4
Figure 31. Unipolar Output
AD5541A
Rev. A | Page 16 of 20
FORCE SENSE AMPLIFIER SELECTION
Use single-supply, low noise amplifiers. A low output impedance at
high frequencies is preferred because the amplifiers must be
able to handle dynamic currents of up to ±20 mA.
REFERENCE AND GROUND
Because the input impedance is code dependent, drive the refer-
ence pin from a low impedance source. The AD5541A operates
with a voltage reference ranging from 2 V to VDD. References
below 2 V result in reduced accuracy. The full-scale output
voltage of the DAC is determined by the reference. Table 8
outlines the analog output voltage or particular digital codes.
If the application does not require separate force and sense
lines, tie the lines close to the package to minimize voltage
drops between the package leads and the internal die.
POWER-ON RESET
The AD5541A has a power-on reset function to ensure that the
output is at a known state on power-up. On power-up, the DAC
register contains all 0s until the data is loaded from the serial
register. However, the serial register is not cleared on power-up;
therefore, its contents are undefined. When loading data initially
to the DAC, 16 bits or more should be loaded to prevent erroneous
data appearing on the output. If more than 16 bits are loaded,
the last 16 are kept, and if less than 16 bits are loaded, bits remain
from the previous word. If the AD5541A must be interfaced
with data shorter than 16 bits, pad the data with 0s at the LSBs.
POWER SUPPLY AND REFERENCE BYPASSING
For accurate high resolution performance, it is recommended
that the reference and supply pins be bypassed with a 10 F
tantalum capacitor in parallel with a 0.1 F ceramic capacitor.
AD5541A
Rev. A | Page 17 of 20
APPLICATIONS INFORMATION
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5541A is via a serial bus
that uses standard protocol that is compatible with DSP proces-
sors and microcontrollers. The communications channel requires
a 3- or 4-wire interface consisting of a clock signal, a data signal,
and a synchronization signal. The AD5541A requires a 16-bit
data-word with data valid on the rising edge of SCLK.
AD5541A TO ADSP-BF531 INTERFACE
The SPI interface of the AD5541A is designed to be easily
connected to industry-standard DSPs and microcontrollers.
Figure 32 shows how the AD5541A can be connected to the
Analog Devices, Inc., Blackfin® DSP. The Blackfin has an
integrated SPI port that can be connected directly to the SPI
pins of the AD5541A.
0
8516-040
AD5541A
CS
SCLK
DIN
LDAC
SPISELx
SCK
MOSI
PF9
ADSP-BF531
Figure 32. AD5541A to ADSP-BF531 Interface
AD5541A TO SPORT INTERFACE
The Analog Devices ADSP-BF527 has one SPORT serial port.
Figure 33 shows how one SPORT interface can be used to
control the AD5541A.
0
8516-041
AD5541A
CS
SCLK
DIN
LDAC
SPORT_TFS
SPORT_TSCK
SPORT_DTO
GPIO0
ADSP-BF527
Figure 33. AD5541A to SPORT Interface
LAYOUT GUIDELINES
In any circuit where accuracy is important, careful consider-
ation of the power supply and ground return layout helps to
ensure the rated performance. Design the printed circuit board
(PCB) on which the AD5541A is mounted so that the analog
and digital sections are separated and confined to certain areas
of the board. If the AD5541A is in a system where multiple
devices require an analog ground-to-digital ground connection,
make the connection at one point only. Establish the star
ground point as close as possible to the device.
The AD5541A should have ample supply bypassing of 10 F
in parallel with 0.1 F on each supply located as close to the
package as possible, ideally right up against the device. The
10 F capacitors are the tantalum bead type. The 0.1 F capaci-
tor should have low effective series resistance (ESR) and low
effective series inductance (ESI), such as the common ceramic
types, which provide a low impedance path to ground at high
frequencies to handle transient currents due to internal logic
switching.
GALVANICALLY ISOLATED INTERFACE
In many process control applications, it is necessary to provide
an isolation barrier between the controller and the unit being
controlled to protect and isolate the controlling circuitry from
any hazardous common-mode voltages that may occur. iCoupler®
products from Analog Devices provide voltage isolation in excess
of 2.5 kV. The serial loading structure of the AD5541A makes
the part ideal for isolated interfaces because the number of
interface lines is kept to a minimum. Figure 34 shows a 4-channel
isolated interface to the AD5541A using an ADuM1400. For
further information, visit http://www.analog.com/icouplers.
ENCODE
SERIAL
CLOCK IN
CONTROLLER
ADuM1400
1
SERIAL
DATA OUT
SYNC O UT
LO AD DAC
OUT
DECODE TO
SCLK
TO
DIN
TO
CS
TO
LDAC
V
IA
V
OA
ENCODE DECODE
V
IB
V
OB
ENCODE DECODE
V
IC
V
OC
ENCODE DECODE
V
ID
V
OD
08516-042
1
ADDIT IONA L PINS O M ITTED FOR CLARITY.
Figure 34. Isolated Interface
AD5541A
Rev. A | Page 18 of 20
DECODING MULTIPLE DACS
The CS pin of the AD5541A can be used to select one of a
number of DACs. All devices receive the same serial clock and
serial data, but only one device receives the CS signal at any one
time. The DAC addressed is determined by the decoder. There is
some digital feedthrough from the digital input lines. Using a
burst clock minimizes the effects of digital feedthrough on the
analog signal channels. shows a typical circuit. Figure 35
AD5541A
CS
DIN
SCLK
V
OUT
AD5541A
CS
DIN
SCLK
V
OUT
AD5541A
CS
DIN
SCLK
V
OUT
AD5541A
CS
DIN
SCLK
V
OUT
V
DD
DGND
EN
CODED
ADDRESS
SCLK
DIN
ENABLE
DECODER
08516-030
Figure 35. Addressing Multiple DACs
AD5541A
Rev. A | Page 19 of 20
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-187-BA
091709-A
6°
0°
0.70
0.55
0.40
5
10
1
6
0.50 BSC
0.30
0.15
1.10 MAX
3.10
3.00
2.90
COPLANARITY
0.10
0.23
0.13
3.10
3.00
2.90
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
Figure 36. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
2.48
2.38
2.23
0.50
0.40
0.30
121009-A
TOP VIEW
10
1
6
5
0.30
0.25
0.20
BOTTOM VIEW
PIN 1 INDEX
AREA
SEATING
PLANE
0.80
0.75
0.70
1.74
1.64
1.49
0.20 REF
0.05 MAX
0.02 NOM
0.50 BSC
EXPOSED
PAD
3.10
3.00 SQ
2.90
PIN1
INDICATOR
(R0.15)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 37. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-10-9)
Dimensions shown in millimeters
AD5541A
Rev. A | Page 20 of 20
2.44
2.34
2.24
TOP VIEW
8
1
5
4
0.30
0.25
0.20
BOTTOM VIEW
PIN 1 INDEX
AREA
SEATING
PLANE
0.80
0.75
0.70
1.70
1.60
1.50
0.203 REF
0.05 MAX
0.02 NOM
0.50 BSC
EXPOSED
PAD
3.10
3.00 SQ
2.90
PIN1
INDICATOR
(R0.15)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.50
0.40
0.30
COMPLIANT
TO
JEDEC STANDARDS MO-229-WEED
01-24-2011-B
Figure 38. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-8-11)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 INL DNL
Power-On
Reset to Code Temperature Range Package Description
Package
Option
Branding
Code
AD5541ABRMZ ±1 LSB ±1 LSB Zero Scale −40°C to +125°C 10-Lead MSOP RM-10 DEQ
AD5541ABRMZ-REEL7 ±1 LSB ±1 LSB Zero Scale −40°C to +125°C 10-Lead MSOP RM-10 DEQ
AD5541AARMZ ±2 LSB ±1 LSB Zero Scale −40°C to +125°C 10-Lead MSOP RM-10 DER
AD5541AARMZ-REEL7 ±2 LSB ±1 LSB Zero Scale −40°C to +125°C 10-Lead MSOP RM-10 DER
AD5541AACPZ-REEL7 ±2 LSB ±1 LSB Zero Scale −40°C to +125°C 10-lead LFCSP_WD CP-10-9 DER
AD5541ABCPZ-REEL7 ±1 LSB ±1 LSB Zero Scale −40°C to +125°C 10-lead LFCSP_WD CP-10-9 DEQ
AD5541ABCPZ-500RL7 ±1 LSB ±1 LSB Zero Scale −40°C to +125°C 10-lead LFCSP_WD CP-10-9 DEQ
AD5541ABCPZ-1-RL7 ±1 LSB ±1 LSB Zero Scale −40°C to +125°C 8-lead LFCSP_WD CP-8-11 DFG
EVAL-AD5541ASDZ AD5541A Evaluation Board
1 Z = RoHS Compliant Part.
©2010–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08516-0-3/11(A)
