W964B6BBN80I - Winbond Electronics

W964B6BBN

1M WORD × 16 BIT LOW POWER PSEUDO SRAM

Publication Release Date: March 31, 2003

- 1 - Revision A1

Table of Contents-

1. GENERAL DESCRIPTION.................................................................................................................. 3

2. FEATURES ......................................................................................................................................... 3

3. PRODUCT OPTIONS ......................................................................................................................... 3

5. Ball DESCRIPTION............................................................................................................................. 4

6. BLOCK DIAGRAM .............................................................................................................................. 5

7. FUNCTION TRUTH TABLE ................................................................................................................ 6

8. ELECTRICAL CHARACTERISTICS ...................................................................................................7

Absolute Maximum Ratings .............................................................................................................. 7

Recommended Operation Conditions............................................................................................... 7

Capacitance ...................................................................................................................................... 8

DC Characteristics ............................................................................................................................ 8

AC Characteristics ............................................................................................................................ 9

Read Operation ..........................................................................................................................................9

Write Operation.........................................................................................................................................11

Power Down and Power Down Program Parameters ...............................................................................13

Other Timing Parameters .........................................................................................................................13

AC Test Conditions...................................................................................................................................13

9. TIMING WAVEFORMS ..................................................................................................................... 14

Read Timing #1 ( OE Control Access)............................................................................................ 14

Read Timing #2 ( CE1 Control Access) .......................................................................................... 15

Read Timing #2 ( CE1 Control Access) .......................................................................................... 16

Read Timing #3 (Address Access after OE Control Access) ........................................................ 17

Read Timing #4 (Address Access after CE1 Control Access)....................................................... 18

Write Timing #1 ( CE1 Control) ....................................................................................................... 19

Write Timing #2-1 ( WE Control, Single Write Operation) .............................................................. 20

Write Timing #2 ( WE Control, Continuous Write Operation) ......................................................... 21

Read/Write Timing #1-1 ( CE1 Control)........................................................................................... 22

Read/Write Timing #1-2 ( CE1 Control)........................................................................................... 23

W964B6BBN

- 2 -

Read ( OE Control) / Write ( WE Control) Timing #2-1 .................................................................. 24

Read ( OE Control) / Write ( WE Control) Timing #2-2 .................................................................. 25

Power Down Program Timing ......................................................................................................... 26

Power Down Entry and Exit Timing................................................................................................. 26

Power-up Timing #1 ........................................................................................................................ 26

Power-up Timing #2 ........................................................................................................................ 27

Standby Entry Timing after Read or Write ...................................................................................... 27

10. PACKAGE DIMENSION.................................................................................................................. 28

TFBGA 48 Balls (6 x 8 mm^2, pitch 0.75 mm)................................................................................ 28

11. ORDERING INFORMATION........................................................................................................... 29

12. VERSION HISTORY ....................................................................................................................... 30

W964B6BBN

1. GENERAL DESCRIPTION

W964B6BBN is a 16M bits CMOS pseudo static random access memory (Pseudo SRAM), organized

as 1M words x 16 bits. Using advanced single transistor DRAM architecture and 0.175 µm process

technology; W964B6BBN delivers fast access cycle time and low power consumption. It is suitable for

mobile device application such as Cellular Phone and PDA, which high-density buffer is needed and

power dissipation is most concerned

2. FEATURES

• Asynchronous SRAM interface

• Fast access cycle time:

− tRC = 70 nS (-70), 80 nS (-80)

• Low power consumption:

− IDDA1 = 20 mA Max.

− IDDS1 = 70 µA Max.

• Byte write control

• Wide operating conditions:

− VDD = +2.3V to +2.7V

• Temperature

− TA = 0°C to +70°C

− TA = -25°C to +85°C (Extended temperature)

− TA = -40°C to +85°C (Industrial temperature)

3. PRODUCT OPTIONS

PARAMETER W964B6BBN70 W964B6BBN80

tRC 70 nS Min. 80 nS Min.

IDDS1 70 µA Max. 70 µA Max.

IDDA1 20 mA 20 mA

VDD 2.3V to 2.7V 2.3V to 2.7V

Publication Release Date: March 31, 2003

- 3 - Revision A1

W964B6BBN

4. BALL CONFIGURATION

Top view

23 56

( FBGA48 , 6 x 8mm , pitch 0.75mm )

DQ9

DQ10

DQ15

DQ16

A18

DQ11

DQ12

DQ13

DQ14

A19

A17

A14

A12

A16

A15

A13

A10

CE1

DQ2

DQ4

DQ5

DQ6

A11

CE2

DQ1

DQ3

DQ7

DQ8

5. BALL DESCRIPTION

SYMBOL DESCRIPTION

A0 − A19 Address input

CE1 Chip Enable Input 1, Low: Enable

CE2 Chip Enable Input 2, High: Enable, Low: Enter Power Down mode

WE Write enable input

OE Output Enable input

LB Lower byte write control

UB Upper byte write control

I/O0 − I/O15 Data inputs/outputs

VDD Power supply

VSS Ground

NC No Connection

- 4 -

W964B6BBN

6. BLOCK DIAGRAM

ADDRESS

LATCH &

BUFFER

ROW

DECODER

MEMORY

CELL

ARRAY

33,554,432 bits

INPUT /

OUTPUT

BUFFER

INPUT DATA

LATCH &

CONTROL

SENSE /

SWITCH

COLUMN /

DECODER

ADDRESS

LATCH &

BUFFER

A18

DQ1

DQ8

DQ9

DQ16

CE2

TIMING

CONTROL

CE1

POWER

CONTROL

VDD

VSS

OUTPUT

DATA

CONTROL

Publication Release Date: March 31, 2003

- 5 - Revision A1

W964B6BBN

7. FUNCTION TRUTH TABLE

Mode Note CE2

CE1 WE OE LB UB A0-18 DQ1-8 DQ9-16 IDD Data

Retention

Standby

(Deselect) H X X X X X High-Z High-Z IDDS Yes

Output

Disable *1 H H X X *5 High-Z High-Z

No Read H H Valid High-Z High-Z

Read *2

H L

L *4 Valid Output

Valid

Output

Valid

Write (Upper Byte) H L Valid Invalid Input

Valid

Write (Lower Byte) L H Valid Input

Valid Invalid

Write (Word)

L H

L L Valid

Input

Valid

Input

Valid

IDDA Yes

Power Down *3 L X X X X X X High-Z High-Z IDDP No/Yes

Notes: L = VIL, H = VIH, X can be either VIL or VIH, High-Z = High impedance, KEY = Key Address.

*1: Output Disable mode should not be kept longer than 1 µS.

*2: Byte control at Read mode is not supported.

*3: Power Down mode can be entered from Standby state and all DQ pins are in High-Z state. IDDP current and data

retention depend on the selection of Power Down Program.

*4: Either or both LB and UB must be Low for Read operation.

*5: Can be either VIL or VIH but must be valid before Read or Write.

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W964B6BBN

8. ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

PARAMETER SYMBOL VALUE UNIT

Voltage of VDD Supply Relative to VSS VDD -0.5 to +3.6 V

Voltage at Any Pin Relative to VSS VIN, VOUT -0.5 to +3.6 V

Short Circuit Output Current IOUT ±50 mA

Storage Temperature TSTG -55 to +125 °C

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

Recommended Operation Conditions

(Reference to VSS)

PARAMETER NOTES SYMBOL MIN. MAX. UNIT

VDD 2.3 2.7 V

Supply Voltage VSS 0 0 V

High Level Input Voltage *1 VIH 2.0 VDD +0.3 V

Low Level Input Voltage *2 VIL -0.3 0.4 V

Ambient Temperature TA 0 70

°C

Ambient Temperature TA -25 85 °C

Ambient Temperature TA -40 85 °C

Notes:

*1: Maximum DC voltage on input and I/O pins are VDD +0.3V. During voltage transitions, inputs may positive overshoot to

VDD +1.0V for periods of up to 5 nS.

*2: Minimum DC voltage on input and I/O pins are -0.3V. During voltage transitions, inputs may negative overshoot to -

1.0V for periods of up to 5 nS.

WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All

the device’s electrical characteristics are warranted when operated within these ranges.

Always use semiconductor devices within the recommended operating conditions. Operation outside

these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the datasheet. Users considering application outside the listed conditions are advised to contact their

Winbond representative beforehand.

Publication Release Date: March 31, 2003

- 7 - Revision A1

W964B6BBN

Capacitance

Test conditions: TA = 25°C, f = 1.0 MHz

SYMBOL DESCRIPTION TEST SETUP TYP. MAX. UNIT

CIN1 Address Input Capacitance VIN = 0V - 5 pF

CIN2 Control Input Capacitance VIN = 0V - 5 pF

CIO Data Input/Output Capacitance VIO = 0V - 8 pF

DC Characteristics

(Under Recommended Operating Conditions unless otherwise noted) notes*1, *2, *3

PARAMETER SYM. TEST CONDITIONS MIN. MAX. UNIT

Input Leakage Current ILI VIN = VSS to VDD -1.0 +1.0

µA

Output Leakage Current ILO VOUT = VSS to VDD, Output Disable -1.0 +1.0 µA

Output High Voltage

Level VOH VDD = VDD, IOH = -0.5 mA 1.8 - V

Output Low Voltage Level VOL IOL = 1 mA - 0.4 V

(TTL) IDDS

VDD = VDD Max.,

VIN = VIH or VIL

CE1 = CE2 = VIH

- 3 mA

Standby

Current

(CMOS) IDDS1

VDD = VDD Max.,

VIN ≤ 0.2V or VIN ≥ VDD -0.2V,

CE1 = CE2 ≥ VDD -0.2V

- 70

µA

IDDA1 tRC / tWC =

Minimum - 20 mA

Active Current

IDDA2

VDD = VDD Max.,

VIN = VIH or VIL,

CE1= VIL and CE2 =

VIH, IOUT = 0 mA

tRC / tWC =

1 µS - 3 mA

Notes:

*1: All voltages are reference to VSS.

*2: DC Characteristics are measured after following POWER-UP timing.

*3: IOUT depends on the output load conditions.

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W964B6BBN

AC Characteristics

(Under Recommended Operating Conditions unless otherwise noted)

Read Operation

-70 -80

PARAMETER SYM.

Min. Max. Min. Max.

UNIT NOTES

Read Cycle Time tRC 70 - 80 - nS

Chip Enable Access Time tCE - 65 - 75 nS *1, *3

Output Enable Access Time tOE - 40 - 45 nS *1

Address Access Time tAA - 65 - 75 nS *1

Output Data Hold Time tOH 5 - 5 - nS *1

CE1 Low to Output Low-Z tCLZ 5 - 5 - nS *2

OE Low to Output Low-Z tOLZ 0 - 0 - nS *2

CE1 High to Output High-Z tCHZ - 20 - 25 nS *2

OE High to Output High-Z tOHZ - 20 - 25 nS *2

Address Setup Time to CE1 Low tASC -5 - -5 - nS *4

tASO 30 - 35 - nS *3, *5

Address Setup Time to OE Low tASO[ABS] 10 - 10 - nS *6

LB / UB Setup Time to CE1 Low tBSC -5 - -5 - nS

LB / UB Setup Time to OE Low tBSO 10 - 10 - nS

Address Invalid Time tAX - 5 - 5 nS

Address Hold Time from CE1 Low tCLAH 70 - 80 - nS

Address Hold Time from OE Low tOLAH 40 - 45 - nS *9

Address Hold Time from CE1 High tCHAH -5 - -5 - nS

Address Hold Time from OE High tOHAH -5 - -5 - nS

LB / UB Hold Time from CE1 High tCHBH -5 - -5 - nS

LB / UB Hold Time from OE High tOHBH -5 - -5 - nS

CE1 Low to OE Low Delay Time tCLOL 25 1000 30 1000 nS

*3, *5, *7, *8

OE Low to CE1 High Delay Time tOLCH 35 - 40 - nS *7

CE1 High Pulse Width tCP 12 - 15 - nS

tOP 25 1000 30 1000 nS *5, *7, *8

OE High Pulse Width tOP[ABS] 12 - 15 - ns *6

Publication Release Date: March 31, 2003

- 9 - Revision A1

W964B6BBN

Read Operation, Continued

Notes:

*1: The output load is 30 pF.

*2: The output load is 5 pF.

*3: The tCE is applicable if OE is brought to Low before CE1 goes Low and is also applicable if actual value of both or

either tASO or tCLOL is shorter than specified value.

*4: Applicable if OE is brought to Low before CE1 goes Low.

*5: The tASO, tCLOL(min.) and tOP(min.) are reference values when the access time is determined by tOE. If actual value of

each parameter is shorter than specified minimum value, tOE become longer by the amount of subtracting actual

value from specified minimum value.

For example, if actual tASO, tASO(actual), is shorter than specified minimum value, tASO(min), during OE control

access (ie., CE1 stays Low), the tOE become tOE(max.) + tASO(min.) - tASO(actual).

*6: The tASO[ABS] and tOP[ABS] is the absolute minimum value during OE control access.

*7: If actual value of either tCLOL or tOP is shorter than specified minimum value, both tOLAH and tOLCH become tRC(min.) -

tCLOL(actual) or tRC(min.) - tOP(actual).

*8: Maximum value is applicable if CE1 is kept at low.

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W964B6BBN

AC Characteristics, Continued

Write Operation

-70 -80

PARAMETER SYM.

Min. Max. Min. Max.

UNIT NOTES

Write Cycle Time tWC 70 - 80 - nS *1

Address Setup Time tAS 0 - 0 - nS *2

Address Hold Time tAH 35 - 40 - nS *2

CE1 Write Setup Time tCS 0 1000 0 1000 nS

CE1 Write Hold Time tCH 0 1000 0 1000 nS

WE Setup Time tWS 0 - 0 - nS

WE Hold Time tWH 0 - 0 - nS

LB and UB Setup Time tBS -5 - -5 - nS

LB and UB Hold Time tBH -5 - -5 - nS

OE Setup Time tOES 0 1000 0 1000 nS *3

tOEH 30 1000 35 1000 nS *3, *4

OE Hold Time tOEH[ABS] 12 - 15 - nS *5

OE High to CE1 Low Setup Time tOHCL -5 - -5 - nS *6

OE High to Address Hold Time tOHAH -5 - -5 - nS *7

CE1 Write Pulse Width tCW 45 - 50 - nS *1, *8

WE Write Pulse Width TWP 45 - 50 - nS *1, *8

CE1 Write Recovery Time tWRC 10 - 15 - nS *1, *9

WE Write Recovery Time tWR 10 1000 15 1000 nS *1, *3, *9

Data Setup Time tDS 15 - 20 - nS

Data Hold Time tDH 0 - 0 - nS

CE1 High Pulse Width tCP 12 - 15 - nS *9

Publication Release Date: March 31, 2003

- 11 - Revision A1

W964B6BBN

Write Operation, Continued

Notes:

*1: Minimum value must be equal or greater than the sum of actual tCW (or tWP) and tWRC (or tWR).

*2: New write address is valid from either CE1 or WE is brought to High.

*3: The tOEH is specified from end of tWC(min.). The tOEH(min.) is a reference value when the access time is determined

by tOE.

If actual value, tOEH(actual) is shorter than specified minimum value, tOE become longer by the amount of subtracting

actual value from specified minimum value.

*4: The tOEH(max.) is applicable if CE1 is kept at Low and both WE and OE are kept at High.

*5: The tOEH[ABS] is the absolute minimum value if write cycle is terminated by WE and CE1 stays Low.

*6: tOHCL(min.) must be satisfied if read operation is not performed prior to write operation.

In case OE is disabled after tOHCL(min.), WE Low must be asserted after tRC(min.) from CE1 Low. In other words,

read operation is initiated if tOHCL(min.) is not satisfied.

*7: Applicable if CE1 stays Low after read operation.

*8: tCW and tWP is applicable if write operation is initiated by CE1 and WE , respectively.

*9: tWRC and tWR is applicable if write operation is terminated by CE1 and WE , respectively.

The tWR(min.) can be ignored if CE1 is brought to High together or after WE is brought to High. In such case, the

tCP(min.) must be satisfied.

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W964B6BBN

AC Characteristics, Continued

Power Down and Power Down Program Parameters

-70 -80

PARAMETER SYM.

Min. Max. Min. Max.

UNIT NOTES

CE2 Low Setup Time for Power Down Entry tCSP 10 - 10 - nS

CE2 Low Hold Time after Power Down Entry tC2LP 70 - 80 - nS

CE1 High Setup Time following CE2 High after

Power Down Exit tCHS 10 - 10 - nS

Other Timing Parameters

-70 -80

PARAMETER SYM.

Min. Max. Min. Max.

UNIT NOTES

CE1 High to OE Invalid Time for Standby Entry tCHOX 10 - 10 - nS

CE1 High to WE Invalid Time for Standby Entry tCHWX 10 - 10 - nS *1

CE2 Low Hold Time after Power-up tC2LH 50 - 50 -

µS *2

CE2 High Hold Time after Power-up tC2HL 50 - 50 -

µS *3

CE1 High Hold Time following CE2 High after

Power-up tCHH 350 - 350 - µS *2

Input Transition Time tT 1 25 1 25 nS *4

Notes:

*1: Some data might be written into any address location if tCHWX(min.) is not satisfied.

*2: Must satisfy tCHH(min.) after tC2LH(min.).

*3: Requires Power Down mode entry and exit after tC2HL.

*4: The Input Transition Time (tT) at AC testing is 5ns as shown in below. If actual tT is longer than 5 nS, it may violate AC

specified of some timing parameters.

AC Test Conditions

SYMBOL DESCRIPTION TEST SETUP VALUE UNIT NOTE

VIH Input High Level VDD = 2.3V to 2.7V 2.0 V

VIL Input Low Level VDD = 2.3V to 2.7V 0.4 V

VREF Input Timing Measurement Level VDD = 2.3V to 2.7V 1.1 V

TT Input Transition Time Between VIL and VIH 5 nS

Publication Release Date: March 31, 2003

- 13 - Revision A1

W964B6BBN

9. TIMING WAVEFORMS

Read Timing #1 ( OE Control Access)

(Output)

ADDRESS

CE1

LB / UB

tRC tRC

tCE

tCLOL tOE

tASO

tBSO

tOLZ

tOHAH

tOP

tOHBH tBSO

tOHZ

tOH tOLZ tOH

tOHZ

tOHBH

tOE

tOLCH

tOHAHtASO

ADDRESS VALID ADDRESS VALID

VALID DATA OUTPUT VALID DATA OUTPUT

Note: CE2, PE and WE must be High for entire read cycle.

Either or both LB and UB must be Low when both CE1 and OE are Low.

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W964B6BBN

Timing Waveforms, Continued

Read Timing #2 ( CE1 Control Access)

(Output)

ADDRESS

CE1

LB / UB

tRC tRC

tCE

tOLZ

tCHAH

tCP

tCHBH tBSC

tCHZ

tOH tCLZ tOH

tCHZ

tCHBH

tCHAHtASC

ADDRESS VALID ADDRESS VALID

VALID DATA OUTPUT VALID DATA OUTPUT

tASC

tBSC

tCE

Note: CE2, PE and WE must be High for entire read cycle.

Either or both LB and UB must be Low when both CE1 and OE are Low.

Publication Release Date: March 31, 2003

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W964B6BBN

Timing Waveforms, Continued

Read Timing #2 ( CE1 Control Access)

(Output)

ADDRESS

CE1

LB / UB

tRC tRC

tCE

tOLZ

tCHAH

tCP

tCHBH tBSC

tCHZ

tOH tCLZ tOH

tCHZ

tCHBH

tCHAHtASC

ADDRESS VALID ADDRESS VALID

VALID DATA OUTPUT VALID DATA OUTPUT

tASC

tBSC

tCE

Note: CE2, PE and WE must be High for entire read cycle.

Either or both LB and UB must be Low when both CE1 and OE are Low.

- 16 -

W964B6BBN

Timing Waveforms, Continued

Read Timing #3 (Address Access after OE Control Access)

(Output)

CE1

LB / UB

tRC tRC

tOLZ tOH tOH

tOHBH

tOHAH

VALID DATA OUTPUT VALID DATA OUTPUT

tBSO

ADDRESS VALID ADDRESS VALID

tAX

tOHZ

tASO tOLAH

tOE

tAA

ADDRESS

Note: CE2, PE and WE must be High for entire read cycle.

Either or both LB and UB must be Low when both CE1 and OE are Low.

Publication Release Date: March 31, 2003

- 17 - Revision A1

W964B6BBN

Timing Waveforms, Continued

Read Timing #4 (Address Access after CE1 Control Access)

(Output)

CE1

LB / UB

tRC tRC

tCLZ tOH tOH

tCHBH

tCHAH

VALID DATA OUTPUT VALID DATA OUTPUT

tBSC

ADDRESS VALID ADDRESS VALID

tAX

tCHZ

tCLAH

tCE

tAA

ADDRESS

tASC

Note: CE2, PE and WE must be High for entire read cycle.

Either or both LB and UB must be Low when both CE1 and OE are Low.

- 18 -

W964B6BBN

Timing Waveforms, Continued

Write Timing #1 ( CE1 Control)

(Intput)

ADDRESS

LB / UB

ADDRESS VALID

VALID DATA INTPUT

tWS

tAS

tAS tAH

tWC

tBS

tOHCL

tWC

tWRC

tBH tBS

tDHtDS

CE1

tWH tWS

Note: CE2 and PE must be High for entire write cycle.

Publication Release Date: March 31, 2003

- 19 - Revision A1

W964B6BBN

Timing Waveforms, Continued

Write Timing #2-1 ( WE Control, Single Write Operation)

(Intput)

ADDRESS

LB / UB

ADDRESS VALID

VALID DATA INTPUT

tCS

tAS tAH

tWP

tBS

tOES

tWC

tDHtDS

CE1

tOHAH

tOHCL

tBH

tAS

tCP

tWR

tCH

tBH

tOHZ

Note: CE2 and PE must be High for entire write cycle.

- 20 -

W964B6BBN

Timing Waveforms, Continued

Write Timing #2 ( WE Control, Continuous Write Operation)

(Intput)

ADDRESS

LB / UB

ADDRESS VALID

VALID DATA INTPUT

tCS

tAS tAH

tWP

tBS

tOES

tWC

tDHtDS

CE1

tOHAH

tOHCL

tOHBH

tAS

tWR

tBH

tOHZ

tBS

Note: CE2 and PE must be High for entire write cycle.

Publication Release Date: March 31, 2003

- 21 - Revision A1

W964B6BBN

Timing Waveforms, Continued

Read/Write Timing #1-1 ( CE1 Control)

(Intput)

ADDRESS

LB / UB

ADDRESS VALID

VALID DATA INTPUT

tWS

tAS tAH

tCW

tBS

tOHCL

tWC

tDHtDS

CE1

tCHAH

tWH

tCHBH

tAS

tWRC

tBH

tCHZ

tBSO

tCP

tOH

tWH tWS

tOLZ

tCLOL

VALID DATA INTPUT

Note: Write address is valid from either CE1 or WE of last falling edge.

- 22 -

W964B6BBN

Timing Waveforms, Continued

Read/Write Timing #1-2 ( CE1 Control)

ADDRESS

LB / UB

tRC

tCLZ tOH

tCHAH

ADDRESS VALID

VALID DATA OUTPUT VALID DATA OUTPUT

tOEH

tOE

tAS

WRITE ADDRESS

tCHBH tBS

tWH tWS

tCP

tOHCL

tDH

tCHZ

CE1

tBH tBSC

tWRC tASC

tWRC(min)

tWH tWS

Note: The tOEH is specified from the time satisfied both tWRC and tWR(min).

Publication Release Date: March 31, 2003

- 23 - Revision A1

W964B6BBN

Timing Waveforms, Continued

Read ( OE Control) / Write ( WE Control) Timing #2-1

(Intput)

ADDRESS

LB / UB

WRITE ADDRESS

VALID DATA INTPUT

Low

tAS tAH

tWP

tBS

tOES

tWC

tDHtDS

CE1

tOHAH

tOHBH

tASO

tOHZ

tOH

tWR

tOLZ

tOEH

VALID DATA INTPUT

tOEHtBH

READ ADDRESS

Note: CE1 can be tied to Low for WE and OE controlled operation.

When

CE1 is tied to Low, output is exclusively controlled by OE .

- 24 -

W964B6BBN

Timing Waveforms, Continued

Read ( OE Control) / Write ( WE Control) Timing #2-2

ADDRESS

LB / UB

tRC

tOLZ tOH

tOHAH

ADDRESS VALID

VALID DATA OUTPUT VALID DATA OUTPUT

Low

tAS

WRITE ADDRESS

tBS

tOES

tDH

tOHZ

CE1

tBH tBSO

tASO

tWR tOEH

tOE

tOHBH

Note: CE1 can be tied to Low for WE and OE controlled operation.

When

CE1 is tied to Low, output is exclusively controlled by OE .

Publication Release Date: March 31, 2003

- 25 - Revision A1

W964B6BBN

Timing Waveforms, Continued

Power Down Program Timing

ADDRESS

(A20-16)

tEAS

CE1

tEPS

tEAH

tEP tEPH

KEY

Note: CE2 must be High for Power Down Program operation.

Any other inputs not specified above can be either High or Low.

Power Down Entry and Exit Timing

CE2

DQ High-Z

tC2LPtCSP

Power Down Entry Power Down Mode Power Down Exit

CE1

tCHS

tCHH (tCHHN)

Note: This Power Down mode can be also used for Power-up #2 below except that tCHHN can not be used at Power-up timing.

Power-up Timing #1

CE2

VDD VDD min

tC2LH

CE1

tCHS

tCHH

Note: The tC2LH specifies after VDD reaches specified minimum level.

Timing Waveforms, Continued

- 26 -

W964B6BBN

Power-up Timing #2

CE2

VDD VDD min

tC2HL

CE1

tC2LP

tCSP tCHH

tC2HL

tCHS

Note: The tC2HL specifies from CE2 low to High transition after VDD reaches specified minimum level.

CE1 must be brought to High prior to or together with CE2 Low to High transition.

Standby Entry Timing after Read or Write

CE1

Active (Read) Standby

tCHOX

Active (Write) Standby

tCHWX

Note: Both tCHOX and tCHWX define the earliest entry timing for Standby mode. If either of timing is not satisfied, it takes tRC(min)

period from either last address transition of A0, A1 and A2, or CE1 Low to High transition.

Publication Release Date: March 31, 2003

- 27 - Revision A1

W964B6BBN

10. PACKAGE DIMENSION

TFBGA 48 Balls (6 x 8 mm^2, pitch 0.75 mm)

- 28 -

W964B6BBN

11. ORDERING INFORMATION

PART NO. SPEED OPERATING

TEMPERATURE PACKAGE

W964B6BBN70 70 nS 0 to 70 TFBGA 48, 6 mm x 8 mm, BALL PITCH 0.75 mm

W964B6BBN70E 70 nS -25 to 85 TFBGA 48, 6 mm x 8 mm, BALL PITCH 0.75 mm

W964B6BBN70I 70 nS -40 to 85 TFBGA 48, 6 mm x 8 mm, BALL PITCH 0.75 mm

W964B6BBN80 80 nS 0 to 70 TFBGA 48, 6 mm x 8 mm, BALL PITCH 0.75 mm

W964B6BBN80E 80 nS -25 to 85 TFBGA 48, 6 mm x 8 mm, BALL PITCH 0.75 mm

W964B6BBN80I 80 nS -40 to 85 TFBGA 48, 6 mm x 8 mm, BALL PITCH 0.75 mm

Notes:

1. Winbond reserves the right to make changes to its products without prior notice.

2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in

applications where personal injury might occur as a consequence of product failure.

Publication Release Date: March 31, 2003

- 29 - Revision A1

W964B6BBN

- 30 -

12. VERSION HISTORY

VERSION DATE PAGE DESCRIPTION

A1 March 31, 2003 - Create new document

Headquarters

No. 4, Creation Rd. III,

Science-Based Industrial Park,

Hsinchu, Taiwan

TEL: 886-3-5770066

FAX: 886-3-5665577

http://www.winbond.com.tw/

Taipei Office

TEL: 886-2-8177-7168

FAX: 886-2-8751-3579

Winbond Electronics Corporation America

2727 North First Street, San Jose,

CA 95134, U.S.A.

TEL: 1-408-9436666

FAX: 1-408-5441798

Winbond Electronics (H.K.) Ltd.

No. 378 Kwun Tong Rd.,

Kowloon, Hong Kong

FAX: 852-27552064

Unit 9-15, 22F, Millennium City,

TEL: 852-27513100

Please note that all data and specifications are subject to change without notice.

All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.

Winbond Electronics (Shanghai) Ltd.

200336 China

FAX: 86-21-62365998

27F, 2299 Yan An W. Rd. Shanghai,

TEL: 86-21-62365999

Winbond Electronics Corporation Japan

Shinyokohama Kohoku-ku,

Yokohama, 222-0033

FAX: 81-45-4781800

7F Daini-ueno BLDG, 3-7-18

TEL: 81-45-4781881

9F, No.480, Rueiguang Rd.,

Neihu District, Taipei, 114,

Taiwan, R.O.C.