Preliminary W89C926 PENTIC+
PCMCIA ETHERNET NETWORK
TWISTED PAIR INTERFACE CONTROLLER
Publication Release Date: January 1996
- 1 - Revision A1
GENERAL DESCRIPTION
The W89C926 PENTIC+ is a CMOS device designed for easy implementation of PCMCIA R2.1
compatible CSMA/CD local area networks. The W89C926 combines a W89C902 Serial LAN
Coprocessor for Twisted-pair (SLCT) with a PCMCIA Bus Interface (PBI), thus integrating into
a single chip all the registers and logic necessary to connect the SLCT to buffer SRAMs, flash
memories (or an EEPROM), and the PCMCIA system bus.
The PCMCIA Bus Interface (PBI) is designed to provide a switchless setting architecture that allows
the card setting to be configured by software. It implements a full set of PCMCIA registers for
PCMCIA R2.1 compatibility and a set of configuration registers for switchless card setting. The card
can be configured quickly and easily by modifying the contents of the configuration registers. The
PENTIC+ can run with shared memory mode and NE2000TM I/O mode drivers on a 16-bit bus
interface. No extra effort is needed to ensure software compatibility.
The PENTIC+ provides a flexible flash memory (up to 128 KB)/EEPROM (up to 512 bytes)
architecture for PCMCIA nonvolatile storage and an ID/Configuration auto-load architecture for
power-on initialization. Vendors can store the Ethernet ID, configuration, and CIS in the flash
memory or EEPROM. The PENTIC+ will auto-load necessary information when power is switched on.
FEATURES
• Runs with NE2000 TM or shared memory drivers
• Supports up to 128 KB flash memory (8K/112K for attribute/common memory) or 512 bytes
EEPROM (for attribute memory only) for nonvolatile memory
• Uses one 16 KB SRAM or one 32 KB SRAM (if EEPROM is used) for 16 KB Ethernet ring buffer
• Auto-load algorithm provided for power-on initialization
• Supports necessary PCMCIA registers
• Configuration registers allow switchless card setting
• UTP/BNC auto media-switching function provided
•Drives necessary LEDs for network status display
• Single 5V power supply with low power consumption
• 100-pin thin package (TQFP) fits into PCMCIA Type II profile
Ethernet is a registered trademark of the Xerox Corporation.
NE2000TM is a trademark of Novell, Inc.
W89C926 PENTIC+
- 2 -
PIN CONFIGURATION
32
31
12345 6 78 9 1
01
11
21
31
41
51
61
71
81
92
02
12
22
9
2
32
42
52
62
72
83
0
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
5
1
5
2
5
3
5
4
5
5
5
6
5
7
5
8
5
9
6
0
6
1
6
2
6
3
6
4
6
5
6
6
6
7
6
8
6
9
7
0
7
1
7
2
7
3
7
4
7
5
7
6
7
7
7
8
7
9
8
0
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
.
H
D
1
0
H
D
2
V
C
C
H
D
9
G
N
D
H
D
1
H
D
0
H
A
0
H
D
8
H
A
1
/
R
E
G
H
A
2
/
I
N
P
A
C
K
D
G
N
D
H
A
3
D
V
C
C
/
W
A
I
T
H
A
4
H
A
5
H
A
6
R
E
S
E
T
H
A
1
2
H
A
1
5
H
A
7
/
I
R
E
Q
H
A
1
6
H
A
1
4
/
W
E
H
A
1
3
H
A
8
IOWR
HA9
IORD
HA11
OE
CE2
HA10
HD15
CE1
HD14
HD7
HD13
GND
HD6
HD12
HD5
HD11
HD4
HD3
T
H
I
N
R
X
I
+
R
X
I
-
G
N
DX
1X
2
/
G
D
L
N
K
/
A
C
T
L
E
D
M
S
A
1
5
C
D
+
C
D
-
R
X
+
T
X
+
T
X
-
R
X
-
T
X
O
+
T
X
O
-
A
G
N
D
M
S
A
1
6
M
S
D
3
M
S
D
4
M
S
D
5
M
S
D
6
M
S
D
7
E
E
C
S
,
/
F
C
S
/
R
C
S
M
S
A
1
0
/
M
S
R
D
M
S
A
1
1
A
V
C
C
VCC
MSA8
MSA13
MSWR
MSD0
MSA1
MSA3
MSA9
GND
MSD2
MSD1
MSA0
MSA2
MSA4
MSA5
MSA6
MSA7
MSA12
MSA14
IOS16
VCC
W89C926 PENTIC+
Publication Release Date: January 1996
- 3 - Revision A1
PIN DESCRIPTION
NAME NUMBER TYPE DESCRIPTION
PCMCIA Bus Interface
HA0-2
HA3, 4
HA5-7
HA8-10
HA11-13
HA14-16
9, 10, 12
15, 18
20-22
30, 32, 37
34, 23,29
28, 24, 25
I/TTL Host Address Bus:
Host address lines used to decode access to the card's
memory and I/O spaces.
HD0-2
HD3-5
HD6-8
HD9-11
HD12-15
8, 6, 2
50, 49, 47
44, 41, 7
4, 1, 48
46, 42, 40, 38
IO/3SH Host Data Bus:
Bidirectional host data bus.
IREQ
26 O/TTL Interrupt Request:
IREQ
is asserted by the PENTIC+ to request host
service. During auto-loading, which is caused by a H/W
reset,
IREQ
will assert low until auto-loading is
complete. This signaling is used as Rdy/-Bsy of
Memory Only Interface during initialization, according to
PCMCIA R2.1.
IORD
33 I/TTL I/O Read:
IORD
is asserted by the system to read data from the
card's I/O space. It has an internal 100K ohm pull-high
resistor.
IOWR
31 I/TTL I/O Write:
IOWR
is asserted by the system to write data to the
card's I/O space. It has an internal 100K ohm pull-high
resistor.
WE
27 I/TTL Write Enable:
The
WE
input is asserted by the system to strobe
memory write data into the card memory. It has an
internal 100K ohm pull-high resistor.
W89C926 PENTIC+
- 4 -
Pin Description, continued
NAME NUMBER TYPE DESCRIPTION
OE
35 I/TTL Output Enable:
The
OE
line is asserted by the system to obtain
memory read data from the card memory. It has an
internal 100K ohm pull-high resistor.
CE1,239, 36 I/TTL Card Enable:
CE1,2 are asserted by the system for data bus width
control as shown below. These pins have an internal
100K ohm pull-high resistor.
CE2 CE HD15-HD8 HD7-HD0
0
0
1
1
0
1
0
1
Valid
Valid
High-Z
High-Z
Valid
High-Z
Valid
High-Z
REG
11 I/TTL Register & I/O selection:
REG
is asserted by the system to access attribute
memory or I/O space. It remains high inactive for
common memory accesses. It has an internal 100K ohm
pull-high resistor.
IOIS
16
100 O/TTL 16-bit I/O access:
Asserted by the PENTIC+ to inform the system that
current operation is a 16-bit I/O access.
INPACK
13 O/TTL Input Acknowledge:
Asserted by the PENTIC+ when it has been selected
and can respond to an I/O read cycle.
17 O/TTL Wait State:
Asserted by the PENTIC+ to insert wait states into
current memory or I/O access cycles.
RESET 19 I/TTL Card Reset:
A RESET pulse will initiate the PENTIC+'s initialization
procedure, including auto-ID/configuration loading,
register initialization, and state machine initialization.
The pulse width should be at least 500 nS to be
recognized as a valid reset. This pin has an internal
100K ohm pull-up resistor.
W89C926 PENTIC+
Publication Release Date: January 1996
- 5 - Revision A1
Pin Description, continued
NAME NUMBER TYPE DESCRIPTION
Memory Support Interface
MSA0-7
MSA8-10
MSA11-13
MSA14-16
90-97
82, 81, 78
80, 98, 84
99, 69, 70
O/TTL Memory Support Address:
Latched address used to decode accesses to the on-
board memory.
MSD0-2
MSD3-7 89-87
71-75 IO/3SH
I/O/3SH
Memory Support Data Bus:
Bidirectional on-board memory data bus.
EEPROM Interface:
During the EEPROM auto-load or read/write sequence,
MSD0 is used as a serial data input/output from/to
EEPROM, MSD1 outputs EEPROM commands to
EEPROM, and MSD2 sends a clock with a period of 1.2
microseconds. This function is available only when
EECS/
FCS
is low during H/W reset.
RCS
77 O/TTL SRAM Chip Select:
RCS
is asserted by the PENTIC+ for SRAM chip
enable during buffer memory access.
EECS/
FCS
76 O/3SH
I/3SH
Nonvolatile Memory Chip Select:
EECS/
FCS
is asserted by the PENTIC+ for chip enable
during nonvolatile memory access. It is active low for
flash memory enable and active high for EEPROM chip
enable.
Nonvolatile Memory Detection:
During H/W reset, the PENTIC+ will determine the
existing nonvolatile memory type by sampling the
voltage level on this pin. If this pin is externally pulled
high with a 470K ohm resistor, the PENTIC+ will
determine that the memory is a flash memory; if the pin
is pulled low with a 470K ohm resistor, it will determine
that the memory is an EEPROM.
MSRD
79 O/TTL Memory Support Read:
MSRD
is asserted by the PENTIC+ to strobe read data
from the on-board memory. Both SRAM and flash
memory use
MSRD
as the read command strobe.
W89C926 PENTIC+
- 6 -
Pin Description, continued
NAME NUMBER TYPE DESCRIPTION
MSWR
86 O/TTL Memory Support Write:
MSWR
is asserted by the PENTIC+ to strobe write data
into the on-board memory. Both SRAM and flash
memory use
MSWR
as the write command strobe.
Network Interface
TXO+, - 60, 59 O/DIF Twisted Pair Transmit Outputs:
UTP differential output pair. A 1.21 KΩ precision resistor
should be shunted across these pins for signal pre-
equalization.
RXI+, - 58, 57 I/DIF Twisted Pair Receive Inputs:
These inputs are fed into a differential amplifier which
passes valid data to the LCE core. A 100Ω precision
resistor should be shunted across these pins for
impedance matching.
TX+, - 64, 63 O/DIF AUI Transmit Outputs:
Differential transmit outputs. These pins should be con-
nected to 270 ohm external pull-down resistors.
RX+, - 66, 65 I/DIF AUI Receive Inputs:
Differential receive input pair from AUI interface.
CD+, - 68, 67 I/DIF AUI Collision Inputs:
Differential collision input pair from AUI interface.
X1 55 I/XTAL Crystal Input:
Master 20 MHz clock input.
X2 54 O/XTAL Crystal Feedback Output:
This pin should be connected to the crystal when a
crystal is used and should be left unconnected when an
oscillator is used.
THIN 51 O/TTL Thin Cable Select:
This pin is high when the PENTIC+ is configured for thin
cable media. It can be used as a switch to DC-DC con-
verter for network media selection.
ACTLED
52 O/TTL Activity:
This output asserts low for approximately 50 mS
whenever the PENTIC+ transmits or receives data
without collisions. This output can also be controlled by
the power-down state machine; refer to the descriptions
of the COR and CFA registers for more details.
W89C926 PENTIC+
Publication Release Date: January 1996
- 7 - Revision A1
Pin Description, continued
NAME NUMBER TYPE DESCRIPTION
GDLNK
53 O/TTL GoodLink:
This output asserts low if the PENTIC+ is in TPI mode,
link checking is enabled, and the link integrity is good or
if link checking is disabled; otherwise, is not asserted.
This output can also be controlled by power down state
machine; refer to the description of the COR and CFA
registers for more details.
Power Pins
AVCC 61 Analog Power Supply Pins:
These pins supply +5V to the PENTIC+'s analog
circuitry for the network interface. Analog layout rules
and decoupling methods must be applied between this
pin and AGND.
AGND 62 Analog Ground Pins:
These pins are the ground to the analog circuitry.
VCC 3, 16, 45, 83 Digital Power Supply Pins:
These pins supply +5V to the PENTIC+'s digital
circuitry.
GND 5, 14, 43,
56, 85 Digital Ground Pins:
These pins are the ground to the digital circuitry.
Note: I: input pin; O: output pin; IO: bidirectional input/output pin; TTL: TTL level buffer stage; ODH: open drain buffer stage;
MOS: MOS level buffer stage; 3SH: Tri-state buffer stage; DIF: differential buffer stage, XTAL: crystal.
W89C926 PENTIC+
- 8 -
BLOCK DIAGRAM
HA0-16 HD0-15
PCMCIA slot
PCMCIA Bus Interface Logic and Drivers
Interrupt
Control
Flash
Memory
Control
Buffer
Memory
Control
Config.
Registers
& Control
Local Bus
Arbiter
ID
Registers
Local Bus
EEPROM
Control
W89C902
Core
W89C926 PENTIC+
Publication Release Date: January 1996
- 9 - Revision A1
SYSTEM DIAGRAM
W89C926
W89C92
optional
TP/IF
LEDs
OSC/XTAL
PCMCIA slot
MSD0-7
3
MSA0-16
HA0-16
15
HD0-15
EEPROM
93C56/66
(EECS/FCS
pull low)
FLASH
128KB X 1
(EECS/FCS
pull high)
SRAM
or 32KB X 1
16 KB X 1
(EECS/FCS
pull low)
Two combinations may be used for the hardware structure:
Combination 1: EECS/FCS pull high/128 KB X 1 flash memory/16 KB X 1 SRAM
Combination 2: EECS/FCS pull low/256 or 512B EEPROM/32 KB X 1 SRAM
FUNCTIONAL DESCRIPTION
ADDRESS MAPPING
EEPROM MAPPING
EEPROM ADDRESS HIGH BYTE LOW BYTE
00H -Word Count
01H CFB CFA
02H ID-1 ID-0
03H ID-3 ID-2
04H ID-5 ID-4
05H Check Sum Board Type (05H)
06H-08H - -
09H 57H 57H
0AH-nH CIS CIS
(n+1) H-FFH - -
Notes:
1. The fifth (05H) word is used for shared memory mode and the ninth (09H) word is used for NE2000 mode.
2. Word Count = nH (n should be set as a non zero value, a zero value will cause an unpredicted error).
W89C926 PENTIC+
- 10 -
ATTRIBUTE MEMORY MAPPING
EECS/FCS Pull High (Flash Memory)
ATTRIBUTE MEMORY
OFFSET (HA0-16)
TYPE CONTENTS
00000H
00F9EH Flash CIS
00FA0H Flash ID-0
00FA2H Flash ID-1
00FA4H Flash ID-2
00FA6H Flash ID-3
00FA8H Flash ID-4
00FAAH Flash ID-5
00FACH Flash Board Type (05H)
00FAEH Flash Check Sum
00FB0H Flash -
00FB2H Flash -
00FB4H Flash -
00FB6H Flash -
00FB8H Flash -
00FBAH Flash -
00FBCH Flash 57H
00FBEH Flash 57H
00FC0H Flash CFA
00FC2H Flash CFB
- - -
00FD0H Register COR
00FD2H Register CCSR
00FD4H Register -
00FD6H Register SCR
-Register Reserved (see note)
00FF0H Register CFA
00FF2H Register CFB
00FF4H Register SR
00FF6H
00FFEH Register Reserved
01000H
03FFEH Flash CIS
W89C926 PENTIC+
Publication Release Date: January 1996
- 11 - Revision A1
EECS/FCS Pull Low (EEPROM)
ATTRIBUTE MEMORY
OFFSET (HA0-16)
TYPE CONTENTS
00000H
003D6H Memory (SRAM) CIS
-Unsued -
00FD0H Register COR
00FD2H Register CCSR
00FD4H Register -
00FD6H Register SCR
-Register Reserved (see note)
00FF0H Register CFA
00FF2H Register CFB
00FF4H Register SR
00FF6H
00FFEH Register Reserved
01000H
03FFEH Unused -
Notes:
1.The reserved register space in the attribute space is left for future extension. Users should not place their application in this
area.
2. When EECS/FCS is pulled high, address 00FA0H to 00FFEH is used for Ethernet ID, configuration, and registers.
Vendors should not put CIS in this region.
3. When EECS/FCS is pulled low, Address 00000H to 003D6H is read-only. The PENTIC+ will ignore write accesses to this
area.
NE2000 Mode Mapping
I/O Mapping
SYSTEM I/O
OFFSET (HA0-4)
NAME OPERATION
00H
0FH LCE Core
Registers Register
Read/Write
10H
17H Remote DMA Port Remote DMA
Read/Write
18H
1FH Reset Port Software Reset
Notes:
1. The PENTIC+ decodes only HA0-4 for I/O access, so the IOBase address is left for the host adapter and the socket service
to determine.
2. To issue a S/W reset, simply issue an I/O read to the Reset Port. The PENTIC+ will assert a 600 nS internal reset pulse to
reset the core state machine. If the host tries to access the PENTIC+, WAIT will be asserted low until the reset is
completed.
W89C926 PENTIC+
- 12 -
Buffer Memory Mapping
NIC CORE
MEMORY MAP
NE2000 COMPATIBLE
0000H
001FH ID Registers
0020H
00FFH Aliased
0100H
3FFFH ID Registers
4000H
7FFFH Buffer SRAM
(16K × 8)
8000H
BFFFH Aliased
ID Registers
C000H
FFFFH Aliased Buffer SRAM
Nonvolatile Memory Mapping
F/
EE
= 1 (flash memory used)
SYSTEM
OFFSET (HA0-16)
MEMORY TYPE NAME
00000H
03FFFH Attribute/
Flash CIS/ID/PCMCIA Register
(8K × 8)
04000H
1FFFFH Common/
Flash (112K × 8)
F/
EE
= 0 (EEPROM used)
SYSTEM
OFFSET (HA0-16)
MEMORY TYPE NAME
00000H
003D6H Attribute/
(Note) CIS
(492 × 8)
Notes:
1. This attribute memory is an image from EEPROM. It is actually resident in upper half of the SRAM after power-on auto-
loading.
2. Refer to "Attribute Memory Mapping" for detailed locations.
3. The PENTIC+ decodes HA0-16 for memory access. The (common or attribute) MEMBase addresses are left for the host adapter
and the socket service to determine.
W89C926 PENTIC+
Publication Release Date: January 1996
- 13 - Revision A1
Shared Memory Mode Mapping
I/O Mapping
SYSTEM I/O
OFFSET (HA0-4)
NAME OPERATION
00H MMA I/O Write
01H Word/-Byte I/O Read
05H MMB I/O Write
08H
0FH ID Registers I/O Read
10H
1FH LCE Core
Registers Register
Read/Write
Notes:
1. The PENTIC+ decodes only HA0-4 for I/O access, so the IOBase address is left for the host adapter and the socket service
to determine.
2. MMA and MMB are used for shared memory mapping control. Since the PENTIC+ decodes only MSA = 0000H to 03FFFH
for shared memory that is, the shared memory base address for the PENTIC+ is 00000H, MMB and bit 0 to 5 of MMA should
be set to 0.
3. Since the PENTIC+ supports 16-bit mode only, the Word/-Byte will be read as 01H.
Buffer Memory Mapping
SYSTEM
OFFSET (HA0-16)
MEMORY TYPE SHARED MEMORY MODE
00000H
03FFFH Common/SRAM Buffer SRAM (16K × 8)
04000H
07FFFH Common/(Note) Unused
Notes:
1. This region is occupied by flash memory.
2. The PENTIC+ decodes HA0-16 for memory access. The (common or attribute) MEMBase addresses are left for the host adapter
and the socket service to determine.
Nonvolatile Memory Mapping
F/
EE
= 1 (flash memory used)
SYSTEM
OFFSET (HA0-16)
MEMORY TYPE NAME
00000H
03FFFH Attribute/
Flash CIS/ID/PCMCIA Register
(8K × 8)
04000H
1FFFFH Common/
Flash (112K × 8)
W89C926 PENTIC+
- 14 -
F/
EE
= 0 (EEPROM used)
SYSTEM
OFFSET (HA0-16)
MEMORY TYPE NAME
00000H
003D6H Attribute/
(Note) CIS
(492x 8)
Notes:
1. This attribute memory is an image from EEPROM. It is physically resident in upper half of the SRAM after power-on auto-
loading.
2. Refer to "Attribute Memory Mapping" for detailed locations.
3. The PENTIC+ decodes HA0-16 for memory access. The (common or attribute) MEMBase addresses are left for the host adapter
and the socket service to determine.
REGISTER FILE
The W89C926 PENTIC+ has four register sets: the core register set, the PCMCIA configuration
register set, the LAN configuration register set, and the special control register set. The core register
set is the same as that in the W89C90 and will not be discussed here. The other three register sets
are described below.
PCMCIA Configuration Register Set
The PENTIC+ provides three PCMCIA configuration registers needed to ensure compatibility with
various operating systems.
COR (Configuration Option Register)
Access Address: AMBase + 00FD0H
Access Type: Attribute Memory Read/Write
BIT SYMBOL DESCRIPTION
0-5 IDX0-5 Configuration Index
These six bits are used to indicate entry of the card configuration table
located in the CIS (Card Information Structure; refer to PCMCIA R2.1).
These bits are 0 at power-on.
6-Reserved, must be 1 (level mode interrupt) when read.
7SRESET S/W Reset
A software reset is issued when a 1 is written to this bit. This is the same
as a H/W reset except that this bit and the necessary information (CFA,
CFB, CIS, and Ethernet ID) are not cleared, and the auto-load procedure
is not performed. Returning a 0 to this bit will leave the PENTIC+ in a
post-reset state the same as that following a hardware reset. The value of
this bit at power-on is 0.
W89C926 PENTIC+
Publication Release Date: January 1996
- 15 - Revision A1
CCSR (Card Configuration and Status Register)
Access Address: AMBase + 00FD2H
Access Type: Attribute Memory Read/Write
BIT SYMBOL DESCRIPTION
0-Reserved, must be 0.
1Intr Interrupt Status
This bit indicates the internal status of an interrupt request. It remains high
until the condition that caused the interrupt request has been serviced.
This bit is 0 at power-on.
2-7 -Reserved, must be 0s.
SCR (Socket and Copy Register)
The SCR is used to enable the PENTIC+ to distinguish between similar cards installed in the same
system.
Access Address: AMBase + 00FD6H
Access Type: Attribute Memory Read/Write
BIT SYMBOL DESCRIPTION
0-3 SocNum Socket Number
Set these bits to indicate to the PENTIC+ that it is located in the n'th
socket. The first socket is numbered 0. This permits any cards designed to
do so to share a common set of IO ports while remaining uniquely
identifiable. These bits are 0 at power-on.
4-6 CopNum Copy Number
Set these bits to indicate to the PENTIC+ that it is the n'th copy of another
card installed in the system that is configured identically. The first identical
card should be assigned a value of 0 as its copy number. This permits any
cards designed to do so to share a common set of I/O ports while
remaining uniquely identifiable and consecutively ordered. These bits are
0s at power-on.
7-Reserved, must be 0.
LAN Configuration Register Set
These two registers are used for LAN configuration control.
CFA (Configuration Register A)
This register is used to select the PENTIC+'s operating mode and LED control.
Access Address: AMBase + 00FF0H
Access Type: Attribute Memory Read/Write
W89C926 PENTIC+
- 16 -
BIT SYMBOL DESCRIPTION
0M/-IO Share Memory/IO Mode Select
The PENTIC+ will operate in shared memory mode if this bit is high;
otherwise, it will be in I/O mode.
1-5 -Reserved, must be 0s.
6F/
EE
Flash or EEPROM Select.
This bit directly reflects the sampled value on pin EECS/
FCS
during a
H/W reset. This bit will be high or low if EECS/
FCS
is pulled high or low.
This bit is read-only.
7LED LED Disable.
Setting this bit high disables the LED indicators in order to save power.
CFB (Configuration Register B)
Access Address: AMBase + 00FF2H
Access Type: Attribute Memory Read/Write
BIT SYMBOL DESCRIPTION
0-1 PHY01 Physical Media Select
These two bits determine to which type of medium the PENTIC+ is
attached. The THIN pin will output low in 10BASE5 mode and high in
10BASE2 mode, according to PHY0,1. This can be used to control the
DC-DC converter for electrical isolation.
PHY1 Attached Medium Type
TPI (10BASE-T Compatible Squelch Level)
Thin Ethernet (10BASE2)
Thick Ethernet (10BASE5)
TPI (Reduced Squelch Level)
PHY0
0 0
0 1
1 0
1 1
The PENTIC+ also provides a UTP/BNC auto media-switching function.
The physical interface will jump from UTP to BNC when the PENTIC+ is
configured at UTP, the link checking is enabled, and the UTP path is
broken. It will jump back immediately if the UTP path has been
reconnected. When the physical interface is not configured at TPI or the
link checking is disabled, the auto media-switching function will be
disabled.
W89C926 PENTIC+
Publication Release Date: January 1996
- 17 - Revision A1
CFB (Configuration Register B), continued
BIT SYMBOL DESCRIPTION
2LNKEN Link Enable
Writing a "1" to this bit will disable the link pulse generation, auto media-
switching function, and link integrity check function. Writing a "0" to this bit
will enable these functions.
3LNKSTS Link Status
This bit indicates the present link status. It is high if the PENTIC+ is in TPI
mode, the link checking is enabled, and the link integrity is good or if the
link checking is disabled; otherwise, it is low.
4IO16CON IOIS16 Timing Control.
If this bit is set high, the IOIS16 signal will decode CE1,2; otherwise,
IOIS16 is decoded according to HA and REG (default).
5FWEN Flash Write Enable.
The default setting for the flash memory is write-protected. If FWEN = 1,
the PENTIC+ allows the flash to be written to. The write command and
chip select signal is prohibited if FWEN = 0.
6SRAMSEL SRAM Speed Select.
If SRAMSEL = 1, the SRAM-15 is selected. Otherwise, SRAM-70 is used.
The default is SRAM-70.
7-Reserved.
Special Control Register Set
These registers are used for special checking or EEPROM access control.
Signature Register (SR)
A signature register is used for identification so that the software driver can easily distinguish between
different chips. The content can be read out in toggled order as follows:
Access Address: AMBase + 00FF4H
Access Type: Attribute Memory Read
MSB
LSB
(2N)th time: 10001000 where N = 1, 2, ... (after H/W reset)
(2N-1)th time: 00000000
EEPROM Access Register (EEAR)
This register is located on page 3 and is used for EEPROM read/write access control. It is inhibited
when EECS/
FCS
is pulled high.
Access Address: IOBase + 02H
Access Type: I/O Read/Write
W89C926 PENTIC+
- 18 -
BIT SYMBOL DESCRIPTION
0-5 -Reserved. Must be 0s.
6EW/
ER
EEPROM Write/Read Select.
This bit selects the EEPROM read/write sequence. If EW/
ER
= 1, the
write sequence is selected. If EW/
ER
= 0, the read sequence is selected.
7EOS EEPROM Operation Select.
This bit enables the EEPROM read/write sequence. If EOS = 1, the
EEPROM read/write sequence will be started. EOS is reset if the
read/write sequence is finished or aborted.
EEPROM Address/Data Register (ADR)
This register is located on page 3 and is used for EEPROM address or data transfer during EEPROM
access.
Access Address: IOBase + 04H
Access Type: I/O Read/Write
POWER-ON INITIALIZATION AND AUTO-LOADING PROCESS
When powered on, the system should reset the card first, as required by the PCMCIA specifications.
The reset signal will trigger a number of internal operations: First, the PENTIC+ monitors the
EECS/
FCS
pin to determined where the configurations are stored. If this pin is pulled high, the
configurations are stored in the flash memory; if it is pulled low, they are stored in an EEPROM.
Then, within 10ms after the reset pulse is negated, the PENTIC+ will automatically load the
configurations, ID, and CIS data into the LAN configuration registers and the upper half of SRAM (if
an EEPROM is used). During this auto-load procedure the PENTIC+ will assert IREQ low for
Rdy/Bsy signaling, since the socket is configured at the memory-only interface during initialization.
Note that this auto-load operation occurs only after a hardware reset pulse. A software reset
(including setting COR.SRESET = 1) will not invoke this operation.
EECS/FCS Pulled High
If EECS/
FCS
is pulled high, this indicates that the configurations are stored in a flash memory.
Accordingly, after a power-on reset the PENTIC+ will automatically load the LAN configuration
registers from flash memory. The Ethernet IDs stored in the flash memory will be mapped into ID
registers automatically when they are read.
W89C926 PENTIC+
Publication Release Date: January 1996
- 19 - Revision A1
CE1,2
F/EE
FCS
MSRD
T > 20 mS
sampling
MSD0-7
MSAn
MSAn
FCS
MSRD
MSD0-7
flash address
T < 5 mS
IREQ
RESET
T > 500 nS
(Rdy/Bsy)
T > 150 nS T > 60 nS T > 60 nS
flash address
T > 150 nS
T > 150 S
µ
S
CE
AUTO
R
FR FOZ FR FOZ
EECS/FCS Pulled Low
If EECS/
FCS
is pulled low, this indicates that the configurations, Ethernet ID, and CIS are stored in
an EEPROM. In this case, after a power-on reset the PENTIC+ will load the configurations into the
LAN configuration registers and the Ethernet IDs and CIS into the higher half of SRAM memory (with
auto-mapping to ID registers and attribute memory space, respectively). Since the EEPROM used is
a 93C66, a serial EEPROM storage device, the access time is quite long and the system has to wait
for the loading sequence (refer to PCMCIA R2.1). Loading a word of EEPROM typically takes 34 µS.
The exact time for EEPROM loading depends on the length of CIS but must not exceed 10 mS.
W89C926 PENTIC+
- 20 -
RESET
CE1,2
F/EE
EECS, RCS
MSWR
T > 500 nS
T > 20 mS
T > 150 S
sampling
MSD0-7
MSAn
MSAn
EECS
MSD0-2
MSD0-7
RCS
MSWR
16 bit EEload
low byte high byte
even address odd address
T < 10 mS
IREQ
(Rdy/Bsy)
T > 100 nS T > 100 nS
T > 20 nS T > 20 nS
T > 0.5 S
T > 32 S
µ
µ
µ
EER
EEOZ
SW
SOZ
SW
SOZ
AUTO
CE
S
R
EEPROM Contents Load Back
When an EEPROM is used to store CIS, the PENTIC+ allows the contents of the EEPROM to be
modified by means of the following sequence:
write (EEAR, EOS = 1 EW/ER = 1)
write (ADR, address);
write (ADR, word_data);
wait ( );
repeat (
read(EEAR, EOS);
) until (EOS = 0);
/* The entire sequence should be consecutive or the process will be aborted. */
W89C926 PENTIC+
Publication Release Date: January 1996
- 21 - Revision A1
The ADR register located at page3 04H of the core controller is used as a temporary register for
EEPROM read/write. When the EEPROM load-back sequence specified above is performed, the
content of the specified address will be overwritten by the new data. Note that since the EEPROM is
word-aligned, each time the sequence is performed one word of data is modified. The address range
available is from 00H to ffH. To make sure that the EEPROM is written correctly, the programmer can
use the following read-check process to read a word from a specified address in the EEPROM.
write (EEAR, EOS = 1 EW/ER = 0);
write (ADR, address);
wait ( );
repeat (
read(EEAR, EOS);
) until (EOS = 0);
read(ADR); /* read word data */
/* The entire sequence should be consecutive or the process will be aborted. */
Note that data will be kept in the ADR until they are updated. That is, the data can be read out any
time afterwards unless new data have been written.
SRAM Physical Map
When an EEPROM is used for attribute memory storage, the 32K byte SRAM has two roles in the
PENTIC+ design: the first 16K bytes of SRAM serve as an Ethernet buffer ring, while the remainder is
used for temporary storage of Ethernet IDs and CIS storage (if EECS/
FCS
is pulled low). The
detailed physical mapping of the SRAM memory is shown in the table below. When a flash memory is
used, only a 16K byte SRAM is needed to serve as the Ethernet ring buffer.
SRAM Physical
Address
EECS/
FCS
pull low EECS/
FCS
pull high
0000H-
3FFFH Ethernet
Buffer Ethernet
Buffer
4000H ID0
4001H ID1
4002H ID2
4003H ID3
4004H ID4
4005H ID5
4006H Board Type (05H)
4007H Checksum
4008H-
400DH -Unused
400EH 57H
400FH 57H
4010H-
41FBH CIS
41FCH-
7FFFH -
W89C926 PENTIC+
- 22 -
Note that if EECS/
FCS
is pulled low, the CIS is stored in the SRAM starting at address 4010H. The
length of the CIS depends on the word count specified in the first byte of EEPROM. During a power-
on reset, the PENTIC+ will load the exact word count specified in the EEPROM rather than read in all
bytes in the EEPROM.
The PENTIC+ will automatically translate the address from the host if the host tries to read CIS. It will
translate the attribute memory address by assuming that the first CIS byte is stored at 00H of attribute
memory, the second CIS byte is stored at 02H, and so forth. Users should assign CIS accordingly, or
else the CIS may be lost.
Also note that for auto-load information write protection, the PENTIC+ will ignore any write operation
above 4000H of SRAM. If it is necessary to change the settings, users should do so by writing the
flash memory or EEPROM.
Minimal System Design
A low-cost, dedicated LAN card can be designed using the PENTIC+ chip, a 32K x 8 SRAM, a serial
EEPROM (93C66/93CS66), and a pig tail for the network interface MAU, along with certain other
peripheral components. The following is a sample CIS table that can be used with this minimal
system design:
01 03 dc 03 ff
17 03 5b 09 ff
1a 05 01 01 e0 1f 0f
1b 13 c1 c1 7d 19 55 15 26 00 33 43 16 45 70 ff ff 48 40 00 00
14 00
f0 09 'WinICard' ff
21 02 06 03
20 04 u00 u01 u02 u03
15 14 04 01 u04 u05 u06 u07 u08 u09 u10 u11 u12 u13 u14 u15 u16 u17 u18 u19 00 ff
ff ff
FLASH MEMORY ACCESS
The flash access and the buffer SRAM share the same memory support bus. The address pins of the
flash memory are directly connected to MSA bus and data are accessed through the MSD bus.
EECS/
FCS
is active low if it is pulled high and the attribute memory is accessed in the range 00000H
to 03FFFH or the common memory is accessed in the range 04000H to 1FFFFH. Note that
CFB.FWE should be set to 1 before a flash write command is issued.
I/O MODE OPERATION
The I/O mode provides two DMA channels for system access. The remote DMA moves data between
system memory space and local memory space. The local DMA moves data between the FIFO of the
SLCT and local memory space. However, since the SLCT can handle local DMA operations
without system intervention (refer to the data sheet for the SLCT), the system has to perform only re-
mote DMA reads/writes.
In a transmit operation, the data should first be moved from the system to local buffer memory. This
is simply an "OUT" command on the PC. Then the system orders the SLCT to start transmission, and
the local DMA starts to move data from buffer memory to the transmit FIFO for transmission.
In a receive operation, the local DMA moves received data from the receive FIFO to the buffer and
asserts IREQ to the system when the buffer ring needs to be serviced. The system must move data
W89C926 PENTIC+
Publication Release Date: January 1996
- 23 - Revision A1
out before the buffer ring overflows. This is done through a remote DMA read operation, which is
simply a "IN" command on the PC.
SHARED MEMORY MODE OPERATION
In this mode, the local memory is mapped as part of the system memory. When it requires data
transmission, the host fills the transmit buffer SRAM by a memory move operation and then issues a
transmit command to the PENTIC+. When it receives data, the PENTIC+ will generate an interrupt
to the host by asserting
IREQ
when one or more packets have been received. The PENTIC+ will then
place the packets into the shared memory. The host should check the shared memory and remove
the data before the buffer ring overflows.
Bus arbitration is performed between the host and LCE core for shared memory usage. When
memory accesses are issued, the arbiter will grant the bus master an acknowledge signal, which is a
BACK to the LCE or a
signal to the host. There is no predefined priority in the PENTIC+; bus
arbitration is performed on a first-come, first-served basis.
To implement the shared memory mode, the PENTIC+ uses memory mapping register A (MMA) and
memory mapping register B (MMB) for memory mapping control. Since the PENTIC+ will operate in
16-bit shared memory operation at shared memory base address 00000H only, 0s should be written
to MMB and bit 0 to 5 of MMA. The contents of the MMA are described below.
MMA (Memory Mapping Register A)
MMA is used for memory enable and software reset. It is located in I/O space, 00H, and can be ac-
cessed only in shared memory mode.
Access Address: IOBASE + 00H
Access Type: write-only
BIT SYMBOL DESCRIPTION
0-5 -Reserved. Should be set to 0.
6MEN If this bit is high, the buffer memory may be accessed by the
system; if it is low, the buffer memory access is disabled. This
bit is 0 at power-on.
7SRESET A shared memory mode software reset is issued when a 1 is
written to this bit. Writing a 0 to this bit will clear the software
reset. This bit is 0 at power-on.
AUTO MEDIA-SWITCHING FUNCTION
The PENTIC+ also provides a user-friendly auto media-switching function. If the PENTIC+ is
configured at the TPI, link checking is enabled, and the UTP link is broken, the PENTIC+ will detect
the link status and switch to the BNC port immediately. After the UTP link is repaired, the PENTIC+
will detect the good link and switch back to the TPI again.
If, however, the PENTIC+ is not configured at the TPI or link checking is disabled, the auto media-
switching function will be disabled.
W89C926 PENTIC+
- 24 -
BUS ARBITRATION AND STATE DIAGRAM
The PENTIC+ handles bus arbitration automatically. It can operate in four modes: idle state, slave
read/write mode, DMA mode, and shared memory mode. The PENTIC+ controls the on-board
devices by decoding these modes.
At power-on, the PENTIC+ is in idle mode. If a register read/write command is issued, the PENTIC+
enters the slave read/write mode. If a local DMA or remote DMA (I/O mode only) is initiated by the
PENTIC+ core coprocessor, the PENTIC+ enters DMA mode. A memory command will place the
PENTIC+ in memory mode. At any given time, the PENTIC+ can be in only one state. The PENTIC+
handles state changes automatically. However, two events, such as a DMA command and a memory
command, may be requested at the same time; in this case, the PENTIC+ allocates the bus on a first-
come, first-served basis. No predefined priority is set within the PENTIC+.
Power-on
Reset Idle
Slave read/ write
DMA operation
Memory operation
Register
access
Core
Memory
access
access
In cases where the system has no authority on the requested bus, the PENTIC+ will drive the
pin low so that the system can insert wait states. After the PENTIC+ has released the bus authority,
is deasserted to instruct the system to stop inserting wait states.
SLCT CORE FUNCTION
The SLCT core coprocessor has five major logic blocks that control Ethernet operations: the register
files, transmit logic, receive logic, FIFO logic, and DMA logic. The relationship between these blocks
is depicted in the following block diagram.
PCMCIA
Slot
Interface
DMA
Interface
Logic
SNA
TX/RX
Logic
16-byte
FIFO
Transmit
Logic
Receive
Logic
Register
File
W89C926 PENTIC+
Publication Release Date: January 1996
- 25 - Revision A1
Core Register Files
The register files of the SLCT can be accessed by means of IO commands. The PENTIC+ should be
in slave mode when the system accesses the register files. The command register (CR) determines
the page number of the register file, while the system address HA<0:4> selects one register address
from 01H to 0FH (I/O mode) or from 10H to 1FH (shared memory mode). The PCMCIA
IORD
and
IOWR
are the read/write commands used to activate the I/O operations. Refer to the W89C90 data
sheet for more detailed information on the registers.
DMA Interface Logic
In I/O mapping mode, the SLCT provides two types of DMA operations, local DMA and remote DMA.
In shared memory mode, only local DMA is available.
Local DMA
The local DMA transfers data from/to the on-board buffers. To perform data reception or transmission
from/to remote nodes in the network, data must be moved from/to the FIFO. To enhance the effi-
ciency of the transmission, the local DMA transfers data in batches: data are first collected and then
moved in a batch. Up to 12 bytes of data can be moved in each transfer. This scheme reduces time
wasted in requesting the bus.
A local DMA begins by requesting the local bus. If the local bus is available to the SLCT core, the bus
arbiter inside the PENTIC+ responds at once by asserting the bus acknowledge (BACK, refer to
LCE); if, on the other hand, the bus is currently authorized to another device, the arbiter will not assert
the bus acknowledge and the SLCT must wait. Note that this sequence will not affect the host system
or system bus signals. After each batch of data is transferred, the SLCT checks the FIFO threshold
levels to determine if another batch transfer should be requested.
Remote DMA
A remote DMA can be performed only in I/O mode. The remote DMA moves data between the host
and the local buffers. Unlike a local DMA, the remote DMA is word-wide: the remote DMA operation
transfers one word each time.
Since a remote DMA is simply a system I/O operation, it sometimes affects the system bus. If the
remote DMA is interleaved with other devices,
is asserted to force the system to insert wait
states. The PENTIC+ will automatically handle any arbitration necessary.
W89C926 PENTIC+
- 26 -
FIFO Logic
The SLCT has a 16-byte FIFO, which acts as an internal buffer to compensate for differences in the
transmission/reception speed of different DMAs. The FIFO has FIFO threshold pointers to determine
the level at which it should initiate a local DMA. The threshold levels, Which are different
for reception and transmission, are defined in the DCR register.
The FIFO logic also provides FIFO overrun and underrun signals for network management purposes.
If received packets are flooding into the FIFO but the SLCT still does not have bus authority, the
FIFO may be overrun. On the other hand, if a transmission begins before data are fed into the FIFO,
it may be underrun. Either case results in a network error. FIFO overruns and underruns can be
prevented by changing the values of the FIFO thresholds.
Normally, the data in the FIFO cannot be read; reading FIFO data during normal operation may
cause
to be asserted and the system to hang. In loopback mode, however, the SLCT allows
FIFO data to be read by byte in order to check the correctness of the loopback operation.
Receive Logic
The receive logic is responsible for receiving the serial network data and packing the data in
byte/word sequence. The receive logic thus has serial-to-parallel logic in addition to network
detection capability.
The PENTIC+ accepts both physical addresses and group addresses (multicast and broadcast ad-
dresses). The SLCT extracts the address field from the serial input data. It then determines if the
address is acceptable according to the configurations defined in the Receive Configuration Register
(RCR). If the address is not acceptable, the packet reception is aborted. If the address is acceptable,
the data packet is sent to the serial-to-parallel logic before being fed into the FIFO.
After receiving a data packet, the SLCT automatically adds four bytes of data receive status, next
packet pointer, and two bytes of receive byte count into the FIFO for network management purposes.
The receive status contains the status of the incoming packet, so that the system can determine if the
packet is desired. The next packet pointer points to the starting address of the next packet in the
local receive ring. The receive byte count is the length of the packet received by the SLCT. Note that
the receive byte count may be different from the "length" field specified in the Ethernet packet format.
These four bytes of data will be transferred to the local buffer with the last batch of the local DMA.
However, these four bytes are stored at the first four addresses of the packet.
Transmit Logic
The SLCT must be filled before transmission may begin. That is, the local DMA read must begin
before the SLCT starts transmission. The SLCT first transmits 62 bits of preamble, then two bits of
SFD, and then the data packet. The parallel-to-serial logic serializes the data from the FIFO into a
data packet. After the data packet, the SLCT optionally adds four bytes of cyclic redundancy code
(CRC) to the tail of the packet.
A protocol PLA determines the network operations of the PENTIC+. Collision detection, random back-
off, and auto retransmit are implemented in the transmit logic. The protocol PLA ensures that
the PENTIC+ follows the IEEE 802.3 protocol.
SNA Module
The PENTIC+ also contains a serial network adaptor (SNA), which adapts the non-return-to-zero
(NRZ) used in the core processor and host system to Manchester coded network symbols. Two kinds
of interfacing signals are provided in the PENTIC+: an AUI interface for Ethernet and a coaxial
W89C926 PENTIC+
Publication Release Date: January 1996
- 27 - Revision A1
interface for Cheapernet. The SNA contains three blocks: a phase locked loop (PLL), a Manchester
encoder/decoder, and a collision decoder as well as crystal/oscillator logic.
TP or
Coax AUI
Interface PLL
Osc/
Crystal
Transmit
Logic
Receive
Logic
L
C
E
The Manchester encoder/decoder handles code interpretation between NRZ signals and Manchester
coded signals. The PLL locks the receiving signals with an internal voltage control oscillator (VCO) so
that network noise can be eliminated before the signals enter the core coprocessor. The collision de-
coder detects whether a collision has occurred on the network. The oscillator logic supplies the
PENTIC+ with the required 20 MHz clock. This clock also supplies the SNA clocking system.
TWISTED PAIR INTERFACE MODULE FUNCTION
Transmit Driver
There are two signals for data transmission: the true and complement Manchester differential data
(TXO+/-). These two signals are resistively combined to form a pre-equalized differential pair, which
is then passed to the twisted-pair cable via a transmitter filter and an optional common mode choke.
Smart Squelch
The main function of this block is to determine when valid data are present on the differential
receiving inputs (RXI+/-). To ensure that impulse noise on the medium will not be taken to be valid
data, this circuit adopts a combination of amplitude and timing measurements to determine the
validity of the input signals. To qualify incoming data, the smart squelch circuitry monitors the signals
for three peaks of alternating polarity that occur within a 400 nS window. Once this condition has been
satisfied, the squelch level is reduced to minimize the noise effect and the chances of causing
premature Start Of Idle (SOI) pulse detection. If the receiver detects activity on the receive line while
packets are being transmitted, incoming data are qualified on five peaks of alternating polarity so as
to prevent false collisions caused by impulse noise. The squelch function returns to its squelch state
under any of the following conditions:
•A normal SOI signal
•An inverted SOI signal
•A missing SOI signal
A missing SOI signal is assumed when no transitions have occurred on the receiver for 175 nS after a
packet has arrived. In this case, a normal SOI signal is generated and appended to the data.
W89C926 PENTIC+
- 28 -
Collision Detection
The collision detection logic determines when transmit and receive signals occur simultaneously on
the twisted pair cable. Collisions will not be reported when the device is in a link-fail state.
The collision signal is also generated when the transceiver has detected a jabber condition or when
the SQE test is being performed.
SQE Test
The Signal Quality Error (SQE) test is used to test the collision signaling circuitry in the twisted-pair
transceiver module. After each packet transmission, an SQE signal is sent to the SLCT. The
SLCT expects this signal and will flag an error if it does not exist.
Jabber
The jabber timer monitors the transmitter and disables the transmission if the transmitter is active for
greater than 26.2 mS. The jabber will re-enable the transmitter after the SLCT has been idle for at
least 420 mS.
Link Integrity
During periods of inactivity, link pulses are generated and received by both MAUs at either end of the
twisted pair to ensure that the cable has not been broken or shorted. A positive, 100 nS link integrity
signal is generated by the twisted-pair transceiver and transmitted on the twisted pair cable every 13
mS during periods of no transmission activity. The PENTIC+ assumes a link-good state if it detects
valid link pulse activity on the twisted-pair transceiver receive circuit. If neither receive data nor a link
pulse (positive or negative) is detected within 105 mS, the PENTIC+ enters a link-fail state. When a
link-fail condition occurs, four consecutive positive link pulses (or eight negative link pulses) must be
received before a link-good condition is assumed.
LCE CORE REGISTERS
This section lists the access addresses and access types of the LCE core registers. Refer to the
W89C90 or W89C901 data sheet for more detailed information.
Page 0 Address Assignments (PS1 = 0, PS0 = 0)
RA0-3 READ WRITE
00 Command (CR) Command (CR)
01 Current Local DMA Address 0 (CLDA0) Page Start Register (PSTART)
02 Current Local DMA Address 1 (CLDA1) Page Stop Register (PSTOP)
03 Boundary Pointer (BNRY) Boundary Pointer (BNRY)
04 Transmit Status Register (TSR) Transmit Page Start Address (TPSR)
05 Number of Collisions Register (NCR) Transmit Byte Count Register 0 (TBCR0)
06 FIFO (FIFO) Transmit Byte Count Register 1 (TBCR1)
07 Interrupt Status Register (ISR) Interrupt Status Register (ISR)
08 Current Remote DMA Address 0 (CRDA0) Remote Start Address Register 0 (RSAR0)
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Publication Release Date: January 1996
- 29 - Revision A1
Page 0 Address Assignments (PS1 = 0, PS0 = 0), continued
RA0-3 READ WRITE
09 Current Remote DMA Address 1 (CRDA1) Remote Start Address Register 1 (RSAR1)
0A Reserved Remote Byte Count Register 0 (RBCR0)
0B Reserved Remote Byte Count Register 1 (RBCR1)
0C Received Status Register (RSR) Receive Configuration Register (RCR)
0D Tally Counter 0 (Frame Alignment Errors)
(CNTR0) Transmit Configuration Register (TCR)
0E Tally Counter 1 (CRC Errors)(CNTR1) Data Configuration Register (DCR)
0F Tally Counter 2 (Missed Packet Errors)
(CNRT2) Interrupt Mask Register (IMR)
Page 1 Address Assignments (PS1 = 0, PS0 = 1)
RA0-3 READ WRITE
00 Command (CR) Command (CR)
01 Physical Address Register 0 (PAR 0) Physical Address Register 0 (PAR 0)
02 Physical Address Register 1 (PAR 1) Physical Address Register 1 (PAR 1)
03 Physical Address Register 2 (PAR 2) Physical Address Register 2 (PAR 2)
04 Physical Address Register 3 (PAR 3) Physical Address Register 3 (PAR 3)
05 Physical Address Register 4 (PAR 4) Physical Address Register 4 (PAR 4)
06 Physical Address Register 5 (PAR 5) Physical Address Register 5 (PAR 5)
07 Current Page Register (CURR) Current Page Register (CURR)
08 Multicast Address 0 (MAR 0) Multicast Address 1 (MAR 0)
09 Multicast Address 1 (MAR 1) Multicast Address 1 (MAR 1)
0A Multicast Address 2 (MAR 2) Multicast Address 2 (MAR 2)
0B Multicast Address 3 (MAR 3) Multicast Address 3 (MAR 3)
0C Multicast Address 4 (MAR 4) Multicast Address 4 (MAR 4)
0D Multicast Address 5 (MAR 5) Multicast Address 5 (MAR 5)
0E Multicast Address 6 (MAR 6) Multicast Address 6 (MAR 6)
0F Multicast Address 7 (MAR 7) Multicast Address 7 (MAR 7)
W89C926 PENTIC+
- 30 -
Page 2 Address Assignments (PS1 = 1, PS0 = 0)
RA0-3 READ WRITE
00 Command (CR) Command (CR)
01 Page Start Register (PSTART) Current Local DMA Address 0 (CLDA0)
02 Page Stop Register (PSTOP) Current Local DMA Address 1 (CLDA1)
03 Remote Next Packet Pointer Remote Next Package Pointer
04 Transmit Page Start Address (TPSR) Reserved
05 Local Next Packet Pointer Local Next Packet Pointer
06 Address Counter (Upper) Address Counter (Upper)
07 Address Counter (Lower) Address Counter (Lower)
08 Reserved Reserved
09 Reserved Reserved
0A Reserved Reserved
0B Reserved Reserved
0C Receive Configuration Register (RCR) Reserved
0D Transmit Configuration Register (TCR) Transmit Configuration
0E Data Configuration Register (DCR) Reserved
0F Interrupt Mask Register (IMR) Reserved
Note: Page 2 registers should be accessed only for diagnostic purposes. They should not be modified during operation. Page 3
should never be modified.
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
PARAMETER SYMBOL MIN. MAX. UNIT
Operating Temperature TA0 70 °C
Storage Temperature TS-55 150 °C
Supply Voltage VDD -0.5 7.0 V
Input Voltage VIN VSS-0.5 VDD+0.5 V
Output Voltage VOUT VSS-0.5 VDD+0.5 V
Lead Temperature (soldering 10 seconds maximum) TL-250 °C
ESD Tolerance ESD 2K -V
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
W89C926 PENTIC+
Publication Release Date: January 1996
- 31 - Revision A1
DC CHARACTERISTICS
Power Supply:
(VDD = 4.75V to 5.25V, VSS = 0V, TA = 0° C to 70° C)
PARAMETER SYM. CONDITIONS MIN. MAX. UNIT
Average Idle Supply Current Note 1 IAVI VDD = 5.25V -150 mA
Average Transmit Supply Current Note 2 IAVT VDD = 5.25V -250 mA
Notes:
1. X1 = 20 MHz, VIN = VCC or GND.
2. X1 = 20 MHz, normal transmitting operation.
Digital:
(VDD = 4.75V to 5.25V, VSS = 0V, TA = 0° C to 70° C)
PARAMETER SYM. CONDITIONS MIN. MAX. UNIT
Low Input Voltage VIL VSS-0.5 0.8 V
High Input Voltage VIH 2.0 VDD+0.5 V
Low Output Voltage VOL VDD = 4.75V,
IOL = IOL-MIN
-0.4 V
High Output Voltage VOH VDD = 4.75V,
IOH = IOL-MAX
2.4 -V
Low Output Sink Current IOL1 4mA
High Output Drive Current IOH1 --4 mA
Low Output Sink Current* IOL2 2-mA
High Output Drive Current* IOH2 --2 mA
Output 3-State Leakage Current IOTR VDD = 5.25V -10 µA
* These are the parameteres for MSD0-7 and MSA0-15.
AUI:
(VDD = 4.75V to 5.25V, VSS = 0V, TA = 0° C to 70° C)
PARAMETER SYM. CONDITIONS MIN. MAX. UNIT
Differential Output Voltage (TX+/-
)VDD With test load +/-550 +/-1200 mV
Differential Output Voltage
Imbalance (TX+/-) VOB With test load -40 mV
Undershoot Voltage (TX+/-) VUWith test load -100 mV
Differential Squelch Threshold
(CD+/-, RX+/-) VDS -175 -300 mV
Differential Input Common Mode
Voltage (CD+/-, RX+/-) VCM 2.0 4.0 V
W89C926 PENTIC+
- 32 -
Twisted Pair:
(VDD = 4.75V to 5.25V, VSS = 0V, TA = 0° C to 70° C)
PARAMETER SYM. CONDITIONS MIN. MAX. UNIT
RXI+/- Differential Input Resistance RTI 3 - KΩ
RXI+/- Open Circuit Input Voltage (bias) VTIB -2.75 VDD-1.0 V
RXI+/- Differential Input Voltage Range VTIV VDD = 5V -3.1 3.1 V
RXI+/- Positive Squelched Threshold VTPS 300 585 mV
RXI+/- Negative Squelched Threshold VTNS -585 -300 mV
RXI+/- Positive Unsquelched Threshold VTPU 200 350 mV
RXI+/- Negative Unsquelched Threshold VTNU -350 -200 mV
TXO+/- Differential Output Voltage VTO With test load 2.2 2.8 V
SWITCHING CHARACTERISTICS
Memory Support Bus Access (SRAM Access)
MSAn
T1
Even Address
MSDn
(Read)
RCS
MSRD
Odd Address
Valid
Valid
T3
MSWR
Valid
MSDn
(Write) Valid
T4
T12
T13
T7
T15
T2
T8
T11
T10 T6
T14
T5
T9
T16
W89C926 PENTIC+
Publication Release Date: January 1996
- 33 - Revision A1
SRAM (upper and lower values are for 70 nS and 15 nS SRAMs, respectively)
SYMBOL DESCRIPTION MIN. MAX. UNIT
T1 Read cycle time. 70
15 -
-nS
T2 MSA0-15 valid to MSD0-7 read data valid. -
-70
15 nS
T3 MSD0-7 read data hold valid from MSA0-15
change. 5
3-
-nS
T4 MSD0-7 read data hold from
MSRD
deasserted. 0
0-
-nS
T5
RCS
held valid after
MSRD
deasserted. 5
3-
-nS
T6 MSA0-15 held valid after
MSRD
deasserted. 5
3-
-nS
T7
RCS
asserted to
MSWR
asserted 0
0-
-nS
T8
MSWR
pulse width 60
15 -
-nS
T9
RCS
asserted to
MSWR
deasserted. 60
15 -
-nS
T10 MSA0-15 held valid after
MSWR
deasserted. 5
3-
-nS
T11 MSD0-7 write data setup before
MSWR
asserted. 35
10 -
-nS
T12 MSD0-7 write data hold after
MSWR
deasserted. 5
3-
-nS
T13 Even byte
MSWR
deasserted to odd byte
MSWR
asserted. (see note)
10
5-
-nS
T14
RCS
held valid after
MSWR
deasserted. 5
3-
-nS
T15 Even byte address invalid to odd byte address
valid. (see note) 0
0-
-nS
T16 Command recovery time. 30
10 -
-nS
Note: This timing is invalid for byte access, e.g, attribute memory reading on SRAM image.
W89C926 PENTIC+
- 34 -
Flash Memory
Memory Support Bus Access (Flash Access)
T9
MSAn
T1
T2
T3
T4
Valid
T7 T8
T6
T5
MSDn
(Read)
MSDn
(Write) Valid
FCS
MSRD
MSWR
T10
T11 T12
SYMBOL DESCRIPTION MIN. MAX. UNIT
T1 MSA0-16 valid to
FCS
asserted. 0-nS
T2
FCS
asserted to
MSRD
,
MSWR
asserted. 20 -nS
T3 MSA0-16 held valid after
MSRD
,
MSWR
deasserted. 5-nS
T4a
FCS
held valid after
MSRD
deasserted. 0-nS
T4b
FCS
held valid after
MSWR
deasserted. 5-nS
T5
MSRD
asserted to read data valid. -60 nS
T6 Read data hold from
MSRD
deasserted. 0 - nS
T7 Write data setup to
MSWR
deasserted. 55 -nS
T8 Write data hold from
MSWR
deasserted. 15 - nS
T9 Access cycle time 150 -nS
T10 Write pulse width 55 nS
T11
FCS
asserted to
MSWR
deasserted 75 -nS
T12a Write recovery time before read 6-µS
T12b Read recovery time before write 0-µS
T12c Consecutive same commands interval 20 -nS
W89C926 PENTIC+
Publication Release Date: January 1996
- 35 - Revision A1
Attribute Memory Access
HA0-16
CE1,2
OE
WE
WAIT
HD0-7
HD0-7
(Write)
(Read) T6
T5
T7
Valid
T4
T8
Valid
T3
T1
T2
T11
T10
T18
REG low
REG T12
T13
T14
T17
T9
T19
(even)
(even)
T15
T16
SYMBOL DESCRIPTION MIN. MAX. UNIT
T1 HA0-16,
REG
valid to
OE
,
WE
asserted 30 -nS
T2 CE1,2 asserted to
OE
,
WE
asserted 0-nS
T3
OE
,
WE
asserted to
asserted -35 nS
T4
OE
asserted to HD0-7 read data valid (see note) -150 nS
T5 HD0-7 write data setup before
WE
deasserted 80 -nS
T6 HD0-7 write data hold from
WE
deasserted 30 -nS
T7 HD0-7 read data disable from
OE
deasserted -100 nS
T8 Read data setup before
deasserted 0-nS
T9
deasserted to
OE
,
WE
deasserted 0-nS
T10 CE1,2 hold valid from
OE
,
WE
deasserted 20 -nS
T11 HA0-16,
REG
hold valid from
OE
,
WE
deasserted 20 -nS
T12 HA0-16,
REG
setup to
WE
deasserted 180 -nS
W89C926 PENTIC+
- 36 -
Attribute Memory Access, continued
SYMBOL DESCRIPTION MIN. MAX. UNIT
T13 CE1,2 asserted to
WE
deasserted 180 -nS
T14
WE
pulse width 150 -nS
T15 HA0-16,
REG
valid to read data valid (see note) -300 nS
T16 CE1,2 asserted to read data valid (see note) -300 nS
T17
pulse width -12 µS
T18a
OE
deasserted to next
WE
asserted 10 -nS
T18b
WE
deasserted to next
OE
asserted 10 -nS
T19a Read cycle time 300 -nS
T19b Write cycle time 250 -nS
Note: These timings are specified when the PENTIC+ does not assert WAIT .
Common Memory Access
HA0-16
CE1,2
OE
WE
WAIT
HD0-15
HD0-15
(Write)
(Read)
T5
T4
T6
Valid
T7
Valid
T3
T1
T10
T9
T15
REG high
REG T11
T12
T13
T14
T8
T16
T3
W89C926 PENTIC+
Publication Release Date: January 1996
- 37 - Revision A1
Common Memory Access, continued
SYMBOL DESCRIPTION MIN. MAX. UNIT
T1 HA0-16,
REG
valid to
OE
,
WE
assert. 20 -nS
T2 CE1,2 assert to
OE
,
WE
assert. 0-nS
T3
OE
,
WE
assert to
asserts. -35 nS
T4 HD0-15 write data setup before
WE
deasserts. 50 -nS
T5 HD0-15 write data hold from
WE
deasserts. 20 -nS
T6 HD0-15 read data disable from
OE
deasserts. -75 nS
T7 Read data setup before
deasserts. 0-nS
T8
deasserts to
OE
,
WE
deassert. 0-nS
T9 CE1,2 hold valid from
OE
,
WE
deassert 20 -nS
T10 HA0-16,
REG
hold valid from
OE
,
WE
deassert 20 -nS
T11 HA0-16,
REG
setup to
WE
deassert 100 -nS
T12 CE1,2 assert to
WE
deassert 100 -nS
T13
WE
pulse width 80 -nS
T14
pulse width -12 µS
T15a
OE
deassert to next
WE
assert 10 -nS
T15b
WE
deassert to next
OE
assert 10 -nS
T16a Read cycle time 150 -nS
T16b Write cycle time 150 -nS
W89C926 PENTIC+
- 38 -
PCMCIA Bus Slave Access
T15
T14
HAn
T1
T2
T3
T4
T7 T17
T16
T28
T10
T18
T9
T5
T6
HDn
(Read)
HDn
(Write)
MSAn
T20
T11 T13
Even Address
T23
T21
MSDn
(Read)
REG
CE
OE WE
,
IORD IOWR
,
IOIS16
WAIT
INPACK
RCS
MSRD
MSWR
Odd Address
MSDn
(Write)
T25
T26
T22
T24 T27
T8
T12
T19
W89C926 PENTIC+
Publication Release Date: January 1996
- 39 - Revision A1
PCMCIA Bus Slave Access
SYMBOL DESCRIPTION MIN. MAX. UNIT
T1a HA0-16 &
REG
valid to
OE
,
WE
asserted Note 2 10 -nS
T1b HA0-16 &
REG
valid to
IORD
,
IOWR
asserted.
Note 3 5-nS
T2a CE1,2 asserted to
OE
,
WE
asserted. 0-nS
T2b CE1,2 asserted to
IORD
,
IOWR
asserted. 5-nS
T3a HA0-16 valid to
OE
,
WE
asserted. 10 -nS
T3b HA0-16 valid to
IORD
,
IOWR
asserted. 70 -nS
T4 HA0-16 valid to
IOIS
16
asserted. Note 4 -35 nS
T5
OE
,
WE
,
IORD
,
IOWR
asserted to
asserted.
Note 1 -35 nS
T6
IORD
asserted to
INPACK
asserted. Note 8 -40 nS
T7a
IORD
asserted to HD0-15 read data valid. Note 6 -100 nS
T7b
OE
asserted to HD0-15 read data valid. Note 9 -50 nS
T8
IORD
,
IOWR
minimum width time. 165 -nS
T9a
deasserted to HD0-15 memory read data
valid. Note 1, 5 -0nS
T9b
deasserted to HD0-15 I/O read data valid.
Note 1, 5 -0nS
T10 HD0-15 read data hold after
OE
,
IORD
deasserted. 5-nS
T11 HD0-15 write data setup before
WE
deasserted. 40 -nS
T12 HD0-15 write data setup befor
IOWR
assert. 60 -
T13a HD0-15 write data hold after
WE
deasserted. 15 -nS
T13b HD0-15 write data hold after
IOWR
deasserted. 30 -nS
T14a
OE
,
WE
deasserted to
REG
deasserted. Note 7 15 -nS
T14b
IORD
,
IOWR
deasserted to
REG
deasserted.
Note 7 0-nS
T15a
OE
,
WE
deasserted to CE1,2 deasserted. 15 -nS
T15b
IORD
,
IOWR
deasserted to CE1,2 deasserted. 20 -nS
T16a
OE
,
WE
deasserted to HA0-16 deasserted. 15 -nS
W89C926 PENTIC+
- 40 -
PCMCIA bus slave access, continued
SYMBOL DESCRIPTION MIN. MAX. UNIT
T16b
IORD
,
IOWR
deasserted to HA0-16 deasserted. 20 -nS
T17 HA0-16 deasserted to
IOIS
16
deasserted. Note 4 -30 nS
T18
IORD
deasserted to
INPACK
deasserted. -40 nS
T19 MSA0-14 asserted t0
deasserted. Note 1 -265 nS
T20 CE1,2 asserted to
RCS
asserted. -265 nS
T21
OE
, asserted to
ROE
asserted. Note 2 -215 nS
T22 MSD odd byte read data valid to HD0-15 read data
valid. -35 nS
T23a MSD odd byte read data hold after
MSRD
deasserted. 5-nS
T23b MSD odd byte read data hold after
MSRD
deasserted. Note.10
3-nS
T24 MSA0-14 valid to
MSWR
asserted. 0-nS
T25 second
MSWR
asserted before
deasserted.
Note 1 -140 nS
T26a MSD write data setup before
MSWR
deasserted. 35 -nS
T26b MSD write data setup before
MSWR
deasserted.
Note.10 10 -nS
T27a MSD write data hold after
MSWR
deasserted. 5-nS
T27b MSD write data hold after
MSWR
deasserted. Note.10 3-nS
T28 Command deasserted to next command asserted 150 -nS
Notes: 1. This is the timing for insert wait states.
WAIT
is asserted if the core cannot service the access immediately; it will hold
asserted until the core is ready, causing the system to insert wait states.
2. This is the timing for shared memory access.
3. This is the timing for I/O access.
4.
IOIS
16
is asserted for 16-bit I/O transfers.
5. Read data valid is referenced to
WAIT
when wait states are inserted.
6. If no wait states are inserted, read data valid can be referenced from
OE
,
IORD
.
7.
REG
is asserted for I/O access and it is deasserted for common memory access.
8.
INPACK
is asserted only for I/O read operation.
9. This is a shared memory access without bus contention.
10. This is the timing for SRAM-15.
W89C926 PENTIC+
Publication Release Date: January 1996
- 41 - Revision A1
H/W Reset and Auto-Initialization Timing
CEn
RESET
IREQ
EECS/FCS sampling
EECS/FCS
MSRD
MSWR
EECS/FCS floating Auto-Loading
MSD0-7
MSAn
Flash Memory Loading
Flash Auto-Loading (if EECS/FCS pulled high)
Serial EEPROM loading SRAM Write
EEPROM Auto-Loading (if EECS/FCS pulled low)
SRAM Write
even byte odd byte
T4
T7 T6 T6
T5 T5
T1
T3
T2
Flash Memory Loading
SYMBOL DESCRIPTION MIN. MAX. UNIT
T1 Reset pulse width 500 -nS
T2 Reset deasserted to EECS/
FCS
sampling 400 -nS
T3 Reset deasserted to CE1,2 asserted 20 -mS
T4 Nonvolatile memory auto-load time -10 mS
T5 Flash memory auto-reading recovery time 60 -nS
T6 SRAM image auto-writing recovery time 20 -nS
T7 EEPROM auto-reading recovery time 50 -nS
W89C926 PENTIC+
- 42 -
Serial EEPROM Timing
T2
T1 T5
T6
T8
T3
T7
T4
EECS
MSD2
(SCK)
MSD1
(DI)
MSD0
(DO)
Serial EEPROM Timing
SYMBOL DESCRIPTION MIN. MAX. UNIT
T1 EECS asserted to SK 500 nS
T2 EECS hold from SK 0-nS
T3 MSD2 OFF time 500 -nS
T4 MSD2 ON time 500 -nS
T5 MSD2 clock period 1-µS
T6 MSD1 set up time to MSD2 high 500 -nS
T7 MSD1 hold time from MSD2 high 500 -nS
T8 MSD0 valid from MSD2 high 500 nS
AUI Transmit Timing (End of Transmit)
T
01 0
TX+/-
TX+/-
1 0 1
TOI
TTOH
W89C926 PENTIC+
Publication Release Date: January 1996
- 43 - Revision A1
SYMBOL DESCRIPTION MIN. MAX. UNIT
TTOH Transmit Output High Before Idle 200 nS
TTOI Transmit Output Idle Time 8000 nS
AUI Receive Timing (End of Receive)
1 1
RX+/RXI+
RX-/RXI-
RX+/RXI+
0 0
RX-/RXI-
TEOP0
TEOP1
SYMBOL DESCRIPTION MIN. MAX. UNIT
TEOP1 End of Packet Received Hold Time after Logic "1" 200 nS
TEOP0 End of Packet Received Hold Time after Logic "0" 200 nS
Note: These parameters are specified by design and are not tested.
Link Pulse Timing
TXO+
TXO-
T
LPW T
LPI
SYMBOL DESCRIPTION MIN. MAX. UNIT
TLPI
Link Output Pulse Interval 8 24 mS
TLPW Link Output Pulse Width 80 120 nS
W89C926 PENTIC+
- 44 -
TPI Transmit Timing (End of Transmit)
0 11
TXO+
TXO-
TXO+
TXO-
TETH1
TETH1
SYMBOL DESCRIPTION MIN. MAX. UNIT
TETH1 End of Packet Transmitted Hold Time 1
(TXP/N) 250 nS
Note: This parameter is specified by design and is not tested.
AC TIMING TEST CONDITIONS
PARAMETER TEST CONDITIONS
Supply Voltage (VDD/VSS)5V ± 0.25V
Temperature 25° C/70° C
Input Test Pattern Levels (TTL/CMOS) GND to 3.0V
Input Rise and Fall Times (TTL/CMOS) 5 nS
Input and Output Pattern Reference Level (TTL/CMOS) 1.3V
Input Waveform Level (Diff) -350 to -1315 mV
Input and Output Waveform Reference Levels (Diff) 50% Point of the Differential
3-State Reference Levels Float (V) ± 0.5V
Note: The above specifications are valid only if the mandatory isolations are properly employed and all differential signals are
taken to the AUI of the pulse transformer.
W89C926 PENTIC+
Publication Release Date: January 1996
- 45 - Revision A1
Output Load
0.1 F
DEVICE
Vcc
RL = 2.2K
SW1 (Note 3)
Output
CL (Note 1, 2)
UNDER
Input TEST
µ
Notes:
1. Load capacitance employed depends on output type:
For 3SL, MOS, TPI, AUI: CL = 50 pF
For 3SH, OCH: CL = 240 pF
2. Specifications which measure delays from an active state to a High-Z state are not guaranteed by production testing, but are
characterized using 240 pF and are correlated to determine true driver turn-off time by eliminating inherent R-C delay times in
measurements.
3. SW1 = Open for push-pull outputs during timing test.
SW1 = VCC for VOL test.
SW1 = GND for VOH test.
SW1 = VCC for High-Z to active low and active low to High-Z measurements.
SW1 = GND for High-Z to active high and active high to High-Z measurements.
Pin Capacitance
TA = 25° C, f = 1 MHz
SYMBOL PARAMETER TYP UNIT
CIN Input Capacitance 7pF
COUT Output Capacitance 10 pF
Derating Factor
Output timing is measured with a purely capacitive load of 50 pF or 240 pF. The following correction
factor can be used for other loads (this factor is preliminary):
Derating for 3SL, MOS = -0.05 nS/pF
Derating for 3SH, OCL, TPI = -0.03 nS/pF
W89C926 PENTIC+
- 46 -
AUI Transmit Test Load
R = 78
TX+
TX-
µ
27 H
Note: In the above diagram, the TX+ and TX- signals are taken from the AUI side of the pulse transformer. The pulse
transformer used for all testing is a 100µH +/-0.1% Pulse Engineering PE64103.
UTP Transmit Test Load
R = 100 1%
TXO+
TXO-
UTP
FILTER
R = 1.21K 1%
Note: In the above diagram, the UTP filter used for all testing is a Valor FL1012.
W89C926 PENTIC+
Publication Release Date: January 1996
- 47 - Revision A1
PACKAGE DIMENSIONS
The PENTIC+ is packaged in a 100-pin TQFP for type II PC card applications. Detailed dimensions
are shown below.
He
E
Hd D
eb
W89C926F
@
C
L1
L
A2
A1
D
Y
Symbol
A1
A2
b
C
D
E
e
Hd
He
L
L1
Y
@
Dimensions in inches Dimensions in mm
0 to 7
0.10 +/- 0.05
1.40 +/- 0.05
0.32 + 0.06
0.20 max
14.00 + 0.10
20.00 + 0.10
0.65 typ
16.00 + 0.10
22.00 + 0.10
0.60 + 0.15
1.00 typ
0.08 max
0 to 7
- 0.10
0.09 min
0.004 +/- 0.002
0.055 +/- 0.002
0.013 + 0.002
- 0.004
0.008 max
0.004 min
0.551 + 0.004
0.787 + 0.004
0.026 typ
0.630 + 0.004
0.866 + 0.004
0.024 + 0.006
0.039 typ
0.003 max
-
-
-
-
-
-
-
-
-
-
W89C926 PENTIC+
- 48 -
Headquarters
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5792668
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-7197006
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-7190505
FAX: 886-2-7197502
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II,
123 Hoi Bun Rd., Kwun Tong,
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.
2727 N. First Street, San Jose,
CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-5441798
Note: All data and specifications are subject to change without notice.