High Speed Super Low Power SRAM 8K-Word By 8 Bit CS18LV00640 Revision History Rev. No. 1.0 History Initial issue with new naming rule 1 Issue Date Aug. 18,2011 Rev. 1.0 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM CS18LV00640 8K-Word By 8 Bit GENERAL DESCRIPTION The CS18LV00640 is a high performance; high speed and super low power CMOS Static Random Access Memory organized as 8,192 words by 8bits and operates for a single 2.7 to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speeds, super low power features. Easy memory expansion is provided by an active LOW chip enable (/CE) and active LOW output enable (/OE). The CS18LV00640 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The CS18LV00640 is available in JEDEC standard 28-pin SOP (330 mil), PDIP (600 mil) and PDIP (300 mil) packages. FEATURES Wide operation voltage : 2.7V ~ 5.5V Ultra low power consumption : 2mA1MHz (Max.) , Vcc=5.0V. 10 uA (Max.) CMOS standby current High speed access time : 55/70ns. Automatic power down when chip is deselected. Three state outputs and TTL compatible. Data retention supply voltage as low as 2.0V. Easy expansion with /CE and /OE options. PRODUCT FAMILY Standby Current (Typ.) Product Family Operating Temp. Vcc Range Speed (ns) ICCSB1 Package Type 28 SOP o 0~70 C 70 1.0uA 28 PDIP Dice CS18LV00640 2.7~5.5V 28 SOP o -40~85 C 70 1.0uA 28 PDIP Dice 2 Rev. 1.0 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM CS18LV00640 8K-Word By 8 Bit PIN CONFIGURATIONS NC A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28L SOP 28L SOP VCC WE NC A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 28 27 26 25 24 23 22 21 20 19 18 17 16 15 FUNCTIONAL BLOCK DIAGRAM A6 A7 A8 A9 A10 A11 A12 Address Input Buffer 14 Row Decoder 128 Memory Array 128x512 512 8 DQ0 DQ7 Data Input Buffer 8 Data Output Buffer 8 Column I/O 8 Write Driver Sense Amp 64 Column Decoder /CE /WE /OE 12 Control Address Input Buffer VCC GND A0 A1 A2 A3 A4 A5 3 Rev. 1.0 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM CS18LV00640 8K-Word By 8 Bit PIN DESCRIPTIONS Name Type A0 - A12 Input Function Address inputs for selecting one of the 8,192 x 8 bit words in the RAM /CE is active LOW. Chip enable must be active when data read from or write to the Input /CE device. If chip enable is not active, the device is deselected and in a standby power mode. The DQ pins will be in high impedance state when the device is deselected. The Write enable input is active LOW. It controls read and write operations. With the Input /WE chip selected, when /WE is HIGH and /OE is LOW, output data will be present on the DQ pins, when /WE is LOW, the data present on the DQ pins will be written into the selected memory location. The output enable input is active LOW. If the output enable is active while the chip is Input /OE selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when /OE is inactive. DQ0~DQ7 I/O These 8 bi-directional ports are used to read data from or write data into the RAM. Vcc Power Power Supply Gnd Power Ground TRUTH TABLE Mode /CE /WE /OE DQ0~7 Vcc Current Standby H X X High Z ICCSB, ICCSB1 Output Disabled L H H High Z ICC Read L H L DOUT ICC Write L L X DIN ICC 4 Rev. 1.0 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM CS18LV00640 8K-Word By 8 Bit ABSOLUTE MAXIMUM RATINGS(1) Symbol Parameter Rating Unit V VCC Supply voltage, Vcc -0.5 to +7 VTERM Terminal Voltage with Respect to GND -0.5 to +7 V TBIAS Temperature Under Bias -40 to +125 O TSTG Storage Temperature -60 to +150 O PT Power Dissipation 1.0 W IOUT DC Output Current 20 mA C C 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING RANGE Range Ambient Temperature 0~70 C Commercial 2.7~5.5V o -40~85 C Industrial Vcc o 2.7~5.5V CAPACITANCE(1)(TA=25 ,f=1.0MHz) Symbol Parameter Conduction MAX. Unit CIN Input Capacitance VIN=0V 6 pF CDQ Input/Output Capacitance VI/O=0V 8 pF 1. This parameter is guaranteed, and not 100% tested. 5 Rev. 1.0 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM CS18LV00640 8K-Word By 8 Bit o DC ELECTRICAL CHARACTERISTICS Name Parameter o ( TA = 0 ~70 C, Vcc = 5.0/3.0V) Test Condition MIN Guaranteed Input Low VIL (1) MAX Unit 0.8 V Vcc=3.0V -0.5 Vcc=5.0V 2.2 VCC=MAX, VIN=0 to VCC -1 1 uA -1 1 uA 0.4 V Voltage Guaranteed Input High VIH (2) Vcc+0.2 V Voltage IIL Input Leakage Current IOL Output Leakage Current VOL Output Low Voltage VCC=MAX, IOL = 2.1mA VOH Output High Voltage VCC=MIN, IOH = -1mA Operating Power Supply /CE=VIL, IDQ=0mA, Current F=FMAX =1/ tRC ICCSB TTL Standby Supply /CE=VIH, IDQ=0mA, ICCSB1 CMOS Standby Current VCC=MAX, /CE=VIN, or /OE=VIN , VIO=0V to VCC ICC 2.4 V 30 mA 2.0 mA 10 uA /CEVCC-0.2V, VINVCC-0.2V or VIN0.2V, 1. Undershoot : -2.0V in case of pulse width 20ns 2. Overshoot : Vcc +2.0V in case of pulse width 20ns DATA RETENTION CHARACTERISTICS ( TA = 0o ~70oC) Name Parameter VCC for Data Retention VDR Test Condition /CE VCC-0.2V, VIN VCC-0.2V or VIN0.2V Data Retention Current ICCDR MIN Chip Deselect to Data /CEVCC-0.2V, VCC=2V Retention Time tR Refer to 2.0 uA ns 0 tRC Unit V 0.5 Retention Waveform Operation Recovery Time MAX 2.0 VINVCC-0.2V or VIN0.2V TCDR Typ (2) (1) ns 1. tRC= .Read Cycle Time. 2. O TA=25 C 6 Rev. 1.0 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM CS18LV00640 8K-Word By 8 Bit LOW Vcc DATA RETENTION WAVEFORM ( /CE Controlled ) AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Vcc/0V KEY TO SWITCHING WAVEFORMS WAVEFORMS 5ns INPUTS OUTPUTS MUST BE STEADY MUST BE STEADY 0.5Vcc MAY CHANGE FROM H TO L WILL BE CHANGE FROM H TO L MAY CHANGE FROM L TO H WILL BE CHANGE FROM L TO H DON'T CARE ANY CHANGE PERMITTED CHANGE STATE UNKNOWN DOES NOT APPLY CENTER LINE IS HIGH IMPEDANCE OFF STATE AC TEST LOADS AND WAVEFORMS FIGURE 1A FIGURE 1B 7 Rev. 1.0 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM CS18LV00640 8K-Word By 8 Bit AC ELECTRICAL CHARACTERISTICS ( TA = 0o ~70oC, Vcc = 5.0V ) < READ CYCLE > JEDEC Name Symbol -55 tAVAX tRC Read Cycle Time tAVQV tAA Address Access Time 55 70 ns tELQV tACE Chip Select Access Time 55 70 ns tGLQV tOE Output Enable to Output 30 50 ns Description MIN -70 MAX 55 MIN Unit MAX 70 ns Valid tELQX tCLZ Chip Select to Output Low Z 10 10 ns tGLQX tOLZ Output Enable to Output in 5 5 ns Low Z tEHQZ tCHZ Chip Deselect to Output in 0 35 0 35 ns 0 30 0 30 ns High Z tGHQZ tOHZ Output Disable to Output in High Z tAXOX tOH Address Change to Out 10 10 ns Disable SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE1 (1,2,4) tRC ADDRESS tOH tAA tOH DOUT 8 Rev. 1.0 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM CS18LV00640 8K-Word By 8 Bit READ CYCLE2 (1,3,4) READ CYCLE3 (1,4) tRC ADDRESS tAA tOH OE tOE tOHZ (1,5) tOLZ CE tCLZ (5) tCE tCHZ(5) DOUT NOTES: 1. /WE is high in read Cycle. 2. Device is continuously selected when /CE = VIL. 3. Address valid prior to or coincident with CE transition low. 4. /OE = VIL. 5. Test conditions assume signal transition times of 5ns or less, timing reference levels of 0.5VCC, input pulse levels of 0V to VCC and output loading specified in Figure 1A. 6. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. 9 Rev. 1.0 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM CS18LV00640 8K-Word By 8 Bit AC ELECTRICAL CHARACTERISTICS ( TA = 0o ~70oC, Vcc = 5.0V ) < WRITE CYCLE > JEDEC Name Symbol -55 Description -70 Unit MIN MAX MIN MAX tAVAX tWC Write Cycle Time 55 70 ns tE1LWH tCW Chip Select to End of Write 55 70 ns tAVWL tAS Address Setup Time 0 0 ns tAVWH tAW Address Valid to End of Write 55 70 ns tWLWH tWP Write Pulse Width 40 50 ns tWHAX tWR Write Recovery Time 0 0 ns tWLQZ tWHZ Write to Output in High Z tDVWH tDW Data to Write Time Overlap 20 30 ns tWHDX tDH Data Hold for Write End 0 0 ns tGHQZ tOHZ Output Disable to Output in 0 25 30 35 0 30 ns ns High Z tWHOX tOW End of Write to Output Active 10 5 5 ns Rev. 1.0 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM 8K-Word By 8 Bit CS18LV00640 SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE1 (Write Enable Controlled) WRITE CYCLE2 (Chip Enable Controlled) 11 Rev. 1.0 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM 8K-Word By 8 Bit CS18LV00640 NOTES: 1. /WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of /CE and /WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of /CE or /WE going high at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the /CE low transition occurs simultaneously with the /WE low transitions or after the /WE transition, output remain in a high impedance state. 6. It's recommended to keep /OE at high (/OE = VIH ) as /WE Controlled WRITE CYCLE. 7. DOUT is the read data of next address. 8. If /CE is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 9. Test conditions assume signal transition times of 5ns or less, timing reference levels of 0.5VCC, input pulse levels of 0V to VCC and output loading specified in Figure 1A. 10. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of /CE going low to the end of write. ORDER INFORMATION Note: Package material code "R" meets ROHS 12 Rev. 1.0 Chiplus reserves the right to change product or specification without notice.