High Speed Super Low Power SRAM
8K-Word By 8 Bit
CS18LV00640
1 Rev. 1.0
Chiplus reserves the right to change product or specification without notice.
Revision History
Rev. No. History Issue Date
1.0
Initial issue with new naming rule
Aug. 18,2011
High Speed Super Low Power SRAM
8K-Word By 8 Bit
CS18LV00640
2 Rev. 1.0
Chiplus reserves the right to change product or specification without notice.
GENERAL DESCRIPTION
The CS18LV00640 is a high performance; high speed and super low power CMOS Static Random
Access Memory organized as 8,192 words by 8bits and operates for a single 2.7 to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high speeds, super low power features.
Easy memory expansion is provided by an active LOW chip enable (/CE) and active LOW output enable
(/OE).
The CS18LV00640 has an automatic power down feature, reducing the power consumption
significantly when chip is deselected. The CS18LV00640 is available in JEDEC standard 28-pin SOP
(330 mil), PDIP (600 mil) and PDIP (300 mil) packages.
FEATURES
Wide operation voltage : 2.7V ~ 5.5V
Ultra low power consumption : 2mA＠1MHz (Max.) , Vcc=5.0V.
10 uA (Max.) CMOS standby current
High speed access time : 55/70ns.
Automatic power down when chip is deselected.
Three state outputs and TTL compatible.
Data retention supply voltage as low as 2.0V.
Easy expansion with /CE and /OE options.
PRODUCT FAMILY
Product Family Operating Temp.
Vcc Range
Speed (ns)
Standby Current (Typ.)
I
CCSB1
Package Type
28 SOP
28 PDIP
0~70
o
C 70 1.0uA
Dice
28 SOP
28 PDIP
CS18LV00640
-40~85
o
C
2.7~5.5V
70 1.0uA
Dice
High Speed Super Low Power SRAM
8K-Word By 8 Bit
CS18LV00640
3 Rev. 1.0
Chiplus reserves the right to change product or specification without notice.
PIN CONFIGURATIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
24
18
15
16
17
21
19
20
22
23
25
26
27
28
28L SOP
A5
DQ0
GND
DQ2
DQ1
A2
A0
A1
A3
A4
A6
A7
A12
NC
A9
DQ6
DQ3
DQ4
DQ5
A10
CE
DQ7
A11
OE
NC
A8
WE
VCC
28L SOP
FUNCTIONAL BLOCK DIAGRAM
Address
Input
Buffer
Row
Decoder 128x512
Memory Array
Data Output
Buffer Write Driver
Sense Amp
Column Decoder
Address Input Buffer
Control
Column I/O
Data Input
Buffer
A6
A7
A8
A9
A10
A11
A12
DQ0
DQ7
14 128
88
8 8
512
64
12
A0A1A2A3A4A5
/WE
/OE
/CE
VCC
GND
High Speed Super Low Power SRAM
8K-Word By 8 Bit
CS18LV00640
4 Rev. 1.0
Chiplus reserves the right to change product or specification without notice.
PIN DESCRIPTIONS
Name Type
Function
A0 – A12 Input Address inputs for selecting one of the 8,192 x 8 bit words in the RAM
/CE Input
/CE is active LOW. Chip enable must be active when data read from or write to the
device. If chip enable is not active, the device is deselected and in a standby power
mode. The DQ pins will be in high impedance state when the device is deselected.
/WE Input
The Write enable input is active LOW. It controls read and write operations. With the
chip selected, when /WE is HIGH and /OE is LOW, output data will be present on the
DQ pins, when /WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
/OE Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when /OE is inactive.
DQ0~DQ7 I/O These 8 bi-directional ports are used to read data from or write data into the RAM.
Vcc Power
Power Supply
Gnd Power
Ground
TRUTH TABLE
Mode /CE /WE /OE DQ0~7 Vcc Current
Standby H X X High Z
I
CCSB
, I
CCSB1
Output Disabled L H H High Z I
CC
Read L H L D
OUT
I
CC
Write L L X D
IN
I
CC
High Speed Super Low Power SRAM
8K-Word By 8 Bit
CS18LV00640
5 Rev. 1.0
Chiplus reserves the right to change product or specification without notice.
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Parameter Rating Unit
V
CC
Supply voltage, Vcc
-0.5 to +7 V
V
TERM
Terminal Voltage with Respect to GND -0.5 to +7 V
T
BIAS
Temperature Under Bias -40 to +125
O
C
T
STG
Storage Temperature -60 to +150
O
C
P
T
Power Dissipation 1.0 W
I
OUT
DC Output Current 20 mA
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
OPERATING RANGE
Range Ambient Temperature Vcc
Commercial 0~70
o
C 2.7~5.5V
Industrial -40~85
o
C 2.7~5.5V
CAPACITANCE
(1)
(TA=25℃
℃℃
℃,f=1.0MHz)
Symbol
Parameter Conduction MAX. Unit
C
IN
Input Capacitance VIN=0V 6 pF
C
DQ
Input/Output Capacitance VI/O=0V 8 pF
1. This parameter is guaranteed, and not 100% tested.
High Speed Super Low Power SRAM
8K-Word By 8 Bit
CS18LV00640
6 Rev. 1.0
Chiplus reserves the right to change product or specification without notice.
DC ELECTRICAL CHARACTERISTICS
( TA = 0
o
~70
o
C, Vcc = 5.0/3.0V)
Name
Parameter Test Condition MIN MAX Unit
V
IL
Guaranteed Input Low
Voltage Vcc=3.0V
-0.5
(1)
0.8 V
V
IH
Guaranteed Input High
Voltage Vcc=5.0V
2.2 Vcc+0.2
(2)
V
I
IL
Input Leakage Current V
CC
=MAX, V
IN
=0 to V
CC
-1 1 uA
I
OL
Output Leakage Current V
CC
=MAX, /CE=V
IN
, or /OE=V
IN
,
V
IO
=0V to V
CC
-1 1 uA
V
OL
Output Low Voltage V
CC
=MAX, I
OL
= 2.1mA
0.4 V
V
OH
Output High Voltage V
CC
=MIN, I
OH
= -1mA
2.4 V
I
CC
Operating Power Supply
Current
/CE=V
IL
, I
DQ
=0mA,
F=F
MAX
=1/ t
RC
30 mA
I
CCSB
TTL Standby Supply /CE=V
IH
, I
DQ
=0mA,
2.0 mA
I
CCSB1
CMOS Standby Current /CE≧V
CC
-0.2V, V
IN
≧V
CC
-0.2V or
V
IN
≦0.2V,
10 uA
1.
Undershoot : -2.0V in case of pulse width ≤ 20ns
2.
Overshoot : Vcc +2.0V in case of pulse width ≤ 20ns
DATA RETENTION CHARACTERISTICS
( TA = 0
o
~70
o
C)
Name Parameter Test Condition MIN
T
yp
(2)
MAX Unit
V
DR
V
CC
for Data Retention /CE ≧V
CC
-0.2V, V
IN
≧
V
CC
-0.2V or V
IN
≦0.2V 2.0 V
I
CCDR
Data Retention Current /CE≧V
CC
-0.2V, V
CC
=2V
V
IN
≧V
CC
-0.2V or V
IN
≦0.2V
0.5 2.0 uA
T
CDR
Chip Deselect to Data
Retention Time 0 ns
t
R
Operation Recovery Time
Refer to
Retention Waveform t
RC
(1)
ns
1. t
RC= .Read Cycle Time.
2. TA=25 O
C
High Speed Super Low Power SRAM
8K-Word By 8 Bit
CS18LV00640
7 Rev. 1.0
Chiplus reserves the right to change product or specification without notice.
LOW Vcc DATA RETENTION WAVEFORM
( /CE Controlled )
AC TEST CONDITIONS KEY TO SWITCHING WAVEFORMS
Input Pulse Levels Vcc/0V
WAVEFORMS INPUTS OUTPUTS
Input Rise and Fall Times 5ns
MUST BE STEADY
MUST BE STEADY
Input and Output Timing
Reference Level 0.5Vcc
MAY CHANGE
FROM H TO L WILL BE CHANGE FROM H
TO L
MAY CHANGE
FROM L TO H WILL BE CHANGE FROM L
TO H
DON’T CARE ANY
CHANGE
PERMITTED CHANGE STATE
UNKNOWN
DOES NOT APPLY
CENTER LINE IS HIGH
IMPEDANCE OFF STATE
AC TEST LOADS AND WAVEFORMS
FIGURE 1A
FIGURE 1B
High Speed Super Low Power SRAM
8K-Word By 8 Bit
CS18LV00640
8 Rev. 1.0
Chiplus reserves the right to change product or specification without notice.
AC ELECTRICAL CHARACTERISTICS
( TA = 0
o
~70
o
C, Vcc = 5.0V )
< READ CYCLE >
-55 -70 JEDEC
Name Symbol
Description
MIN
MAX
MIN
MAX
Unit
t
AVAX
t
RC
Read Cycle Time 55 70 ns
t
AVQV
t
AA
Address Access Time 55 70 ns
t
ELQV
t
ACE
Chip Select Access Time 55 70 ns
t
GLQV
t
OE
Output Enable to Output
Valid
30 50 ns
t
ELQX
t
CLZ
Chip Select to Output Low Z
10 10 ns
t
GLQX
t
OLZ
Output Enable to Output in
Low Z
5 5 ns
t
EHQZ
t
CHZ
Chip Deselect to Output in
High Z
0 35 0 35 ns
t
GHQZ
t
OHZ
Output Disable to Output in
High Z
0 30 0 30 ns
t
AXOX
t
OH
Address Change to Out
Disable
10 10 ns
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
(1,2,4)
t
AA
t
OH
t
OH
t
RC
ADDRESS
D
OUT
High Speed Super Low Power SRAM
8K-Word By 8 Bit
CS18LV00640
9 Rev. 1.0
Chiplus reserves the right to change product or specification without notice.
READ CYCLE2
(1,3,4)
READ CYCLE3
(1,4)
t
AA
t
OH
t
RC
ADDRESS
t
CE
t
CLZ(5)
t
CHZ(5)
CE
D
OUT
OE
t
OHZ(1,5)
t
OE
t
OLZ
NOTES:
1. /WE is high in read Cycle.
2. Device is continuously selected when /CE = V
IL.
3. Address valid prior to or coincident with CE transition low.
4. /OE = VIL.
5. Test conditions assume signal transition times of 5ns or less, timing reference levels of 0.5VCC, input
pulse levels of 0V to VCC and output loading specified in Figure 1A.
6. Transition is measured ±500mV from steady state with C
L
= 5pF as shown in Figure 1B. The parameter is
guaranteed but not 100% tested.
High Speed Super Low Power SRAM
8K-Word By 8 Bit
CS18LV00640
10 Rev. 1.0
Chiplus reserves the right to change product or specification without notice.
AC ELECTRICAL CHARACTERISTICS
( TA = 0
o
~70
o
C, Vcc = 5.0V )
< WRITE CYCLE >
-55 -70 JEDEC
Name Symbol Description
MIN
MAX
MIN
MAX
Unit
t
AVAX
t
WC
Write Cycle Time 55
70
ns
t
E1LWH
t
CW
Chip Select to End of Write 55
70
ns
t
AVWL
t
AS
Address Setup Time 0 0 ns
t
AVWH
t
AW
Address Valid to End of Write
55
70
ns
t
WLWH
t
WP
Write Pulse Width 40
50
ns
t
WHAX
t
WR
Write Recovery Time 0 0 ns
t
WLQZ
t
WHZ
Write to Output in High Z 25
35
ns
t
DVWH
t
DW
Data to Write Time Overlap 20
30
ns
t
WHDX
t
DH
Data Hold for Write End 0 0 ns
t
GHQZ
t
OHZ
Output Disable to Output in
High Z
0 30
0 30
ns
t
WHOX
t
OW
End of Write to Output Active 5 5 ns
High Speed Super Low Power SRAM
8K-Word By 8 Bit
CS18LV00640
11 Rev. 1.0
Chiplus reserves the right to change product or specification without notice.
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1
(Write Enable Controlled
)
WRITE CYCLE2
(Chip Enable Controlled
)
High Speed Super Low Power SRAM
8K-Word By 8 Bit
CS18LV00640
12 Rev. 1.0
Chiplus reserves the right to change product or specification without notice.
NOTES:
1. /WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of /CE and /WE low. All signals must be active
to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold
timing should be referenced to the second transition edge of the signal that terminates the write.
3. T
WR
is measured from the earlier of /CE or /WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs
must not be applied.
5. If the /CE low transition occurs simultaneously with the /WE low transitions or after the /WE transition, output
remain in a high impedance state.
6. It’s recommended to keep /OE at high (/OE = VIH ) as /WE Controlled WRITE CYCLE.
7. D
OUT
is the read data of next address.
8. If /CE is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase
to the outputs must not be applied to them.
9. Test conditions assume signal transition times of 5ns or less, timing reference levels of 0.5VCC, input pulse
levels of 0V to VCC and output loading specified in Figure 1A.
10. Transition is measured ±500mV from steady state with C
L
= 5pF as shown in Figure 1B. The parameter is
guaranteed but not 100% tested.
11. T
CW
is measured from the later of /CE going low to the end of write.
ORDER INFORMATION
Note: Package material code “R” meets ROHS
