LM2524D/LM3524D Regulating Pulse Width Modulator General Description The LM3524D family is an improved version of the industry standard LM3524. It has improved specifications and additional features yet is pin for pin compatible with existing 3524 families. New features reduce the need for additional external circuitry often required in the original version. The LM3524D has a 1% precision 5V reference. The current carrying capability of the output drive transistors has been raised to 200 mA while reducing VCEsat and increasing VCE breakdown to 60V. The common mode voltage range of the error-amp has been raised to 5.5V to eliminate the need for a resistive divider from the 5V reference. In the LM3524D the circuit bias line has been isolated from the shut-down pin. This prevents the oscillator pulse amplitude and frequency from being disturbed by shut-down. Also at high frequencies ( 300 kHz) the max. duty cycle per output has been improved to 44% compared to 35% max. duty cycle in other 3524s. In addition, the LM3524D can now be synchronized externally, through pin 3. Also a latch has been added to insure one pulse per period even in noisy environments. The LM3524D includes double pulse suppression logic that insures when a shut-down condition is removed the state of the T-flip-flop will change only after the first clock pulse has arrived. This feature prevents the same output from being pulsed twice in a row, thus reducing the possibility of core saturation in push-pull designs. Features n n n n n n n n n Fully interchangeable with standard LM3524 family 1% precision 5V reference with thermal shut-down Output current to 200 mA DC 60V output capability Wide common mode input range for error-amp One pulse per period (noise suppression) Improved max. duty cycle at high frequencies Double pulse suppression Synchronize through pin 3 Block Diagram DS008650-1 (c) 1999 National Semiconductor Corporation DS008650 www.national.com LM2524D/LM3524D Regulating Pulse Width Modulator June 1999 Absolute Maximum Ratings (Note 5) Internal Power Dissipation Operating Junction Temperature Range (Note 2) LM2524D LM3524D Maximum Junction Temperature Storage Temperature Range Lead Temperature (Soldering 4 sec.) M, N Pkg. If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage Collector Supply Voltage (LM2524D) (LM3524D) Output Current DC (each) Oscillator Charging Current (Pin 7) 40V 55V 40V 200 mA 5 mA 1W -40C to +125C 0C to +125C 150 -65C to +150C 260C Electrical Characteristics (Note 1) LM2524D Symbol Parameter Conditions Typ LM3524D Tested Design Limit Limit (Note 3) (Note 4) Typ Tested Design Limit Limit (Note 3) (Note 4) Units REFERENCE SECTION VREF Output Voltage 5 4.85 4.80 5.15 5.20 5 4.75 VMin 5.25 VMax VRLine Line Regulation VIN = 8V to 40V 10 15 30 10 25 50 mVMax VRLoad Load Regulation IL = 0 mA to 20 mA 10 15 25 10 25 50 mVMax Ripple Rejection f = 120 Hz 66 Short Circuit VREF = 0 IOS Current 66 25 25 50 Output Noise 10 Hz f 10 kHz 40 Long Term TA = 125C 20 RT = 1k, CT = 0.001 F 550 mA Min 50 180 NO dB 200 100 40 mA Max 100 Vrms Max 20 mV/kHr 350 kHzMin Stability OSCILLATOR SECTION fOSC Max. Freq. 500 (Note 7) fOSC Initial RT = 5.6k, CT = 0.01 F Accuracy (Note 7) 17.5 17.5 kHzMin 22.5 22.5 kHzMax 34 30 kHzMin 46 kHzMax 1.0 %Max 20 RT = 2.7k, CT = 0.01 F (Note 7) 38 VIN = 8 to 40V 0.5 20 38 42 fOSC Freq. Change 1 0.5 with VIN fOSC Freq. Change TA = -55C to +125C with Temp. at 20 kHz RT = 5.6k, 5 % 5 CT = 0.01 F VOSC Output Amplitude RT = 5.6k, CT = 0.01 F 3 2.4 3 2.4 VMin RT = 5.6k, CT = 0.01 F 0.5 1.5 0.5 1.5 sMax RT = 5.6k, CT = 0.01 F 3.4 3.6 3.8 3.8 VMax RT = 5.6k, CT = 0.01 F 1.1 0.8 0.6 0.6 VMin VCM = 2.5V 2 8 10 2 10 mVMax VCM = 2.5V 1 8 10 1 10 AMax (Pin 3) (Note 8) tPW Output Pulse Width (Pin 3) Sawtooth Peak Voltage Sawtooth Valley Voltage ERROR-AMP SECTION VIO Input Offset Voltage IIB www.national.com Input Bias 2 Electrical Characteristics (Continued) (Note 1) LM2524D Symbol Parameter Conditions Typ LM3524D Tested Design Limit Limit (Note 3) (Note 4) 1.0 1 Typ Tested Design Limit Limit (Note 3) (Note 4) Units ERROR-AMP SECTION Current IIO Input Offset VCM = 2.5V 0.5 0.5 1 AMax 65 AMin 125 125 AMax -125 -125 AMin Current ICOSI Compensation VIN(I) - VIN(NI) = 150 mV Current (Sink) ICOSO Compensation 65 95 VIN(NI) - VIN(I) = 150 mV Current (Source) 95 -95 -95 -65 AVOL Open Loop Gain VCMR CMRR RL = , VCM = 2.5 V -65 60 Common Mode 1.5 1.4 1.5 VMin Input Voltage Range 5.5 5.4 5.5 VMax 80 dBMin 90 80 80 90 70 AMax 74 Common Mode 80 60 dBMin Rejection Ratio GBW Unity Gain AVOL = 0 dB, VCM = 2.5V 3 2 MHz Bandwidth VO Output Voltage RL = Swing PSRR 0.5 0.5 VMin 5.5 5.5 VMax 80 65 dbMin VIN = 8 to 40V 80 Minimum Duty Pin 9 = 0.8V, 0 0 0 0 %Max Cycle [RT = 5.6k, CT = 0.01 F] Maximum Duty Pin 9 = 3.9V, 49 45 49 45 %Min Cycle [RT = 5.6k, CT = 0.01 F] Maximum Duty Pin 9 = 3.9V, 44 35 44 35 %Min Cycle [RT = 1k, CT = 0.001 F] Input Threshold Zero Duty Cycle Power Supply 70 Rejection Ratio COMPARATOR SECTION VCOMPZ 1 1 V 3.5 3.5 V -1 -1 A (Pin 9) VCOMPM Input Threshold Maximum Duty Cycle (Pin 9) IIB Input Bias Current CURRENT LIMIT SECTION VSEN Sense Voltage V(Pin 2) - V(Pin 1) 150 mV 180 200 220 TC-Vsense Sense Voltage T.C. 180 mVMin 220 mVMax 200 0.2 0.2 -0.7 -0.7 VMin V5 - V4 = 300 mV 1 1 VMax High Input V(Pin 2) - V(Pin 1) 1 Voltage 150 mV High Input I(pin 10) Common Mode Voltage Range mV/C SHUT DOWN SECTION VSD ISD 0.5 1 1.5 1 0.5 VMin 1.5 VMax 1 mA Current OUTPUT SECTION (EACH OUTPUT) VCES Collector Emitter IC 100 A 55 40 VMin Voltage Breakdown 3 www.national.com Electrical Characteristics (Continued) (Note 1) LM2524D Symbol Parameter Conditions Typ LM3524D Tested Design Limit Limit (Note 3) (Note 4) Typ Tested Design Limit Limit (Note 3) (Note 4) Units OUTPUT SECTION (EACH OUTPUT) ICES Collector Leakage Current VCE = 60V VCE = 55V 0.1 50 VCE = 40V VCESAT VEO AMax 0.1 50 Saturation IE = 20 mA 0.2 0.5 0.2 0.7 Voltage IE = 200 mA 1.5 2.2 1.5 2.5 Emitter Output IE = 50 mA 18 17 18 17 VMax VMin Voltage Rise Time tR VIN = 20V, IE = -250 A 200 200 ns 100 100 ns RC = 2k Fall Time tF RC = 2k SUPPLY CHARACTERISTICS SECTION VIN Input Voltage After Turn-on Range T Thermal Shutdown (Note 2) 8 8 VMin 40 40 VMax 160 160 C Temp. IIN Stand By Current VIN = 40V (Note 6) 5 10 5 10 mA Note 1: Unless otherwise stated, these specifications apply for TA = TJ = 25C. Boldface numbers apply over the rated temperature range: LM2524D is -40 to 85C and LM3524D is 0C to 70C. VIN = 20V and fOSC = 20 kHz. Note 2: For operation at elevated temperatures, devices in the N package must be derated based on a thermal resistance of 86C/W, junction to ambient. Devices in the M package must be derated at 125C/W, junction to ambient. Note 3: Tested limits are guaranteed and 100% tested in production. Note 4: Design limits are guaranteed (but not 100% production tested) over the indicated temperature and supply voltage range. These limits are not used to calculate outgoing quality level. Note 5: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its rated operating conditions. Note 6: Pins 1, 4, 7, 8, 11, and 14 are grounded; Pin 2 = 2V. All other inputs and outputs open. Note 7: The value of a Ct capacitor can vary with frequency. Careful selection of this capacitor must be made for high frequency operation. Polystyrene was used in this test. NPO ceramic or polypropylene can also be used. Note 8: OSC amplitude is measured open circuit. Available current is limited to 1 mA so care must be exercised to limit capacitive loading of fast pulses. Typical Performance Characteristics Switching Transistor Peak Output Current vs Temperature Maximum Average Power Dissipation (N, M Packages) Maximum & Minimum Duty Cycle Threshold Voltage DS008650-29 DS008650-28 DS008650-30 www.national.com 4 Typical Performance Characteristics Output Transistor Saturation Voltage (Continued) Output Transistor Emitter Voltage DS008650-31 Standby Current vs Voltage Reference Transistor Peak Output Current DS008650-32 Standby Current vs Temperature DS008650-33 Current Limit Sense Voltage DS008650-36 DS008650-34 DS008650-35 Test Circuit DS008650-4 5 www.national.com Functional Description INTERNAL VOLTAGE REGULATOR The LM3524D has an on-chip 5V, 50 mA, short circuit protected voltage regulator. This voltage regulator provides a supply for all internal circuitry of the device and can be used as an external reference. For input voltages of less than 8V the 5V output should be shorted to pin 15, VIN, which disables the 5V regulator. With these pins shorted the input voltage must be limited to a maximum of 6V. If input voltages of 6V-8V are to be used, a pre-regulator, as shown in Figure 1, must be added. DS008650-5 FIGURE 2. DS008650-10 *Minimum CO of 10 F required for stability. FIGURE 1. OSCILLATOR The LM3524D provides a stable on-board oscillator. Its frequency is set by an external resistor, RT and capacitor, CT. A graph of RT, CT vs oscillator frequency is shown is Figure 2. The oscillator's output provides the signals for triggering an internal flip-flop, which directs the PWM information to the outputs, and a blanking pulse to turn off both outputs during transitions to ensure that cross conduction does not occur. The width of the blanking pulse, or dead time, is controlled by the value of CT, as shown in Figure 3. The recommended values of RT are 1.8 k to 100 k, and for CT, 0.001 F to 0.1 F. If two or more LM3524D's must be synchronized together, the easiest method is to interconnect all pin 3 terminals, tie all pin 7's (together) to a single CT, and leave all pin 6's open except one which is connected to a single RT. This method works well unless the LM3524D's are more than 6" apart. A second synchronization method is appropriate for any circuit layout. One LM3524D, designated as master, must have its RTCT set for the correct period. The other slave LM3524D(s) should each have an RTCT set for a 10% longer period. All pin 3's must then be interconnected to allow the master to properly reset the slave units. The oscillator may be synchronized to an external clock source by setting the internal free-running oscillator frequency 10% slower than the external clock and driving pin 3 with a pulse train (approx. 3V) from the clock. Pulse width should be greater than 50 ns to insure full synchronization. DS008650-6 FIGURE 3. ERROR AMPLIFIER The error amplifier is a differential input, transconductance amplifier. Its gain, nominally 86 dB, is set by either feedback or output loading. This output loading can be done with either purely resistive or a combination of resistive and reactive components. A graph of the amplifier's gain vs output load resistance is shown in Figure 4. DS008650-7 FIGURE 4. The output of the amplifier, or input to the pulse width modulator, can be overridden easily as its output impedance is very high (ZO 5 M). For this reason a DC voltage can be www.national.com 6 Functional Description CURRENT LIMITING The function of the current limit amplifier is to override the error amplifier's output and take control of the pulse width. The output duty cycle drops to about 25% when a current limit sense voltage of 200 mV is applied between the +CL and -CLsense terminals. Increasing the sense voltage approximately 5% results in a 0% output duty cycle. Care should be taken to ensure the -0.7V to +1.0V input common-mode range is not exceeded. In most applications, the current limit sense voltage is produced by a current through a sense resistor. The accuracy of this measurement is limited by the accuracy of the sense resistor, and by a small offset current, typically 100 A, flowing from +CL to -CL. (Continued) applied to pin 9 which will override the error amplifier and force a particular duty cycle to the outputs. An example of this could be a non-regulating motor speed control where a variable voltage was applied to pin 9 to control motor speed. A graph of the output duty cycle vs the voltage on pin 9 is shown in Figure 5. The duty cycle is calculated as the percentage ratio of each output's ON-time to the oscillator period. Paralleling the outputs doubles the observed duty cycle. OUTPUT STAGES The outputs of the LM3524D are NPN transistors, capable of a maximum current of 200 mA. These transistors are driven 180 out of phase and have non-committed open collectors and emitters as shown in Figure 6. DS008650-8 FIGURE 5. The amplifier's inputs have a common-mode input range of 1.5V-5.5V. The on board regulator is useful for biasing the inputs to within this range. DS008650-9 FIGURE 6. 7 www.national.com Typical Applications DS008650-11 FIGURE 7. Positive Regulator, Step-Up Basic Configuration (IIN(MAX) = 80 mA) DS008650-12 FIGURE 8. Positive Regulator, Step-Up Boosted Current Configuration www.national.com 8 Typical Applications (Continued) DS008650-13 FIGURE 9. Positive Regulator, Step-Down Basic Configuration (IIN(MAX) = 80 mA) DS008650-14 FIGURE 10. Positive Regulator, Step-Down Boosted Current Configuration 9 www.national.com Typical Applications (Continued) DS008650-15 FIGURE 11. Boosted Current Polarity Inverter The circuit works as follows: Q1 is used as a switch, which has ON and OFF times controlled by the pulse width modulator. When Q1 is ON, power is drawn from VIN and supplied to the load through L1; VA is at approximately VIN, D1 is reverse biased, and Co is charging. When Q1 turns OFF the inductor L1 will force VA negative to keep the current flowing in it, D1 will start conducting and the load current will flow through D1 and L1. The voltage at VAis smoothed by the L1, Co filter giving a clean DC output. The current flowing through L1 is equal to the nominal DC load current plus some IL which is due to the changing voltage across it. A good rule of thumb is to set ILP-P 40% x Io. BASIC SWITCHING REGULATOR THEORY AND APPLICATIONS The basic circuit of a step-down switching regulator circuit is shown in Figure 12, along with a practical circuit design using the LM3524D in Figure 15. DS008650-16 FIGURE 12. Basic Step-Down Switching Regulator www.national.com 10 Typical Applications (Continued) DS008650-17 FIGURE 13. Relation of Switch Timing to Inductor Current in Step-Down Regulator where: L1 is in Henrys f is switching frequency in Hz Also, see LM1578 data sheet for graphical methods of inductor selection. Neglecting VSAT, VD, and settling IL = IL ; + - CALCULATING OUTPUT FILTER CAPACITOR Co: Figure 13 shows L1's current with respect to Q1's tON and tOFF times (VA is at the collector of Q1). This curent must flow to the load and Co. Co's current will then be the difference between IL, and Io. Ico = IL - Io From Figure 13 it can be seen that current will be flowing into Co for the second half of tON through the first half of tOFF, or a time, tON/2 + tOFF/2. The current flowing for this time is IL/4. The resulting Vc or Vo is described by: where T = Total Period The above shows the relation between VIN, Vo and duty cycle. as Q1 only conducts during tON. The efficiency, , of the circuit is: MAX will be further decreased due to switching losses in Q1. For this reason Q1 should be selected to have the maximum possible fT, which implies very fast rise and fall times. CALCULATING INDUCTOR L1 For best regulation, the inductor's current cannot be allowed to fall to zero. Some minimum load current Io, and thus inductor current, is required as shown below: Since IL+ = IL- = 0.4Io Solving the above for L1 11 www.national.com Typical Applications range. Since each output transistor is on for half the period, actually 45%, they have been paralleled to allow longer possible duty cycle, up to 90%. This makes a lower possible input voltage. The output voltage is set by: (Continued) where VNI is the voltage at the error amplifier's non-inverting input. DS008650-19 FIGURE 14. Inductor Current Slope in Step-Down Regulator Resistor R3 sets the current limit to: A complete step-down switching regulator schematic, using the LM3524D, is illustrated in Figure 15. Transistors Q1 and Q2 have been added to boost the output to 1A. The 5V regulator of the LM3524D has been divided in half to bias the error amplifier's non-inverting input to within its common-mode Figures 16, 17 and show a PC board layout and stuffing diagram for the 5V, 1A regulator of Figure 15. The regulator's performance is listed in Table 1. DS008650-20 *Mounted to Staver Heatsink No. V5-1. Q1 = BD344 Q2 = 2N5023 L1 = > 40 turns No. 22 wire on Ferroxcube No. K300502 Torroid core. FIGURE 15. 5V, 1 Amp Step-Down Switching Regulator www.national.com 12 Typical Applications (Continued) TABLE 1. Parameter Conditions Typical Characteristics Output Voltage Switching Frequency Short Circuit VIN = 10V, Io = 1A VIN = 10V, Io = 1A VIN = 10V 5V 20 kHz 1.3A Current Limit Load Regulation VIN = 10V Io = 0.2 - 1A 3 mV Line Regulation 6 mV Efficiency VIN = 10 - 20V, Io = 1A VIN = 10V, Io = 1A Output Ripple VIN = 10V, Io = 1A 10 mVp-p 80% DS008650-21 FIGURE 16. 5V, 1 Amp Switching Regulator, Foil Side DS008650-22 FIGURE 17. Stuffing Diagram, Component Side 13 www.national.com Typical Applications (Continued) THE STEP-UP SWITCHING REGULATOR Figure 18 shows the basic circuit for a step-up switching regulator. In this circuit Q1 is used as a switch to alternately apply VIN across inductor L1. During the time, tON, Q1 is ON and energy is drawn from VIN and stored in L1; D1 is reverse biased and Io is supplied from the charge stored in Co. When Q1 opens, tOFF, voltage V1 will rise positively to the point where D1 turns ON. The output current is now supplied through L1, D1 to the load and any charge lost from Co during tON is replenished. Here also, as in the step-down regulator, the current through L1 has a DC component plus some IL. IL is again selected to be approximately 40% of IL. Figure 19 shows the inductor's current in relation to Q1's ON and OFF times. DS008650-23 FIGURE 18. Basic Step-Up Switching Regulator DS008650-24 FIGURE 19. Relation of Switch Timing to Inductor Current in Step-Up Regulator So far it is assumed = 100%, where the actual efficiency or MAX will be somewhat less due to the saturation voltage of Q1 and forward on voltage of D1. The internal power loss due to these voltages is the average IL current flowing, or IIN, through either VSAT or VD1. For VSAT = VD1 = 1V this power loss becomes IIN(DC) (1V). MAX is then: Since IL+ = IL-, VINtON = VotOFF - VINtOFF, and neglecting VSAT and VD1 The above equation shows the relationship between VIN, Vo and duty cycle. In calculating input current IIN(DC), which equals the inductor's DC current, assume first 100% efficiency: for = 100%, POUT = PIN This equation assumes only DC losses, however MAX is further decreased because of the switching time of Q1 and D1. This equation shows that the input, or inductor, current is larger than the output current by the factor (1 + tON/tOFF). Since this factor is the same as the relation between Vo and VIN, IIN(DC) can also be expressed as: www.national.com 14 Typical Applications where: L1 is in henrys, f is the switching frequency in Hz To apply the above theory, a complete step-up switching regulator is shown in Figure 20. Since VIN is 5V, VREF is tied to VIN. The input voltage is divided by 2 to bias the error amplifier's inverting input. The output voltage is: (Continued) In calculating the output capacitor Co it can be seen that Co supplies Io during tON. The voltage change on Co during this time will be some Vc = Vo or the output ripple of the regulator. Calculation of Co is: The network D1, C1 forms a slow start circuit. This holds the output of the error amplifier initially low thus reducing the duty-cycle to a minimum. Without the slow start circuit the inductor may saturate at turn-on because it has to supply high peak currents to charge the output capacitor from 0V. It should also be noted that this circuit has no supply rejection. By adding a reference voltage at the non-inverting input to the error amplifier, see Figure 21, the input voltage variations are rejected. The LM3524D can also be used in inductorless switching regulators. Figure 22 shows a polarity inverter which if connected to Figure 20 provides a -15V unregulated output. where: Co is in farads, f is the switching frequency, Vo is the p-p output ripple Calculation of inductor L1 is as follows: VIN is applied across L1 15 www.national.com Typical Applications (Continued) DS008650-25 L1 = > 25 turns No. 24 wire on Ferroxcube No. K300502 Toroid core. FIGURE 20. 15V, 0.5A Step-Up Switching Regulator DS008650-27 FIGURE 22. Polarity Inverter Provides Auxiliary -15V Unregulated Output from Circuit of Figure 20 DS008650-26 FIGURE 21. Replacing R3/R4 Divider in Figure 20 with Reference Circuit Improves Line Regulation www.national.com 16 Connection Diagram DS008650-2 Top View Order Number LM2524DN or LM3524DN See NS Package Number N16E Order Number LM3524DM See NS Package Number M16A 17 www.national.com Physical Dimensions inches (millimeters) unless otherwise noted Molded Surface-Mount Package (M) Order Number LM3524DM NS Package Number M16A www.national.com 18 LM2524D/LM3524D Regulating Pulse Width Modulator Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Molded Dual-In-Line Package (N) Order Number LM2524DN or LM3524DN NS Package Number N16E LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Francais Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: sea.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. National P/N LM3524D - Regulating Pulse Width Modulator See A/D Converters Products Products > Analog - Regulators > Switching Voltage Regulators & PWM ICs > LM3524D LM3524D Product Folder Regulating Pulse Width Modulator Generic P/N 3524D General Description Features Package & Models Datasheet Parametric Table Samples & Pricing Application Notes Parametric Table Multiple Output Capability - Switching Frequency (Hz) 300000 On/Off Pin Yes Adjustable Switching Frequency Yes Error Flag No Sync Pin Yes Input Voltage, min (Volt) 5 Efficiency (%) - Input Voltage, max (Volt) 40 Flyback Yes Output Current, max 200 mA Inverting Yes Output Voltage (Volt) - Step-Up Yes Adjustable Output Voltage Yes Step-Down Yes Datasheet Size in Date Kbytes Title LM2524D LM3524D Regulating Pulse Width Modulator LM2524D LM3524D Regulating Pulse Width Modulator (JAPANESE) View Online Download 25676 Jun- View Online Kbytes 99 Download 997 Kbytes Download View Online Receive via Email Receive via Email Receive via Email If you have trouble printing or viewing PDF file(s), see Printing Problems. Package Availability, Models, Samples & Pricing Part Number LM3524DM Package Status Type SOIC NARROW Pins MSL 16 Budgetary Samples & Pricing Electronic $US Orders SPICE IBIS Qty each Models MSL Full production N/A N/A 24 Hour Samples Buy Now 1K+ $0.4500 Std Pack Size Package Marking rail of 48 [logo]UZ2T LM3524DM file:///H|/imaging/BITTING/cpl/20020808_1/08062002_10/NATL/08062002_HTML/LM3524D.html (1 of 3) [09-Aug-2002 12:33:45 PM] National P/N LM3524D - Regulating Pulse Width Modulator LM3524DMX LM3524DN SOIC NARROW MDIP LM3524D MDC LM3524D MWC 16 MSL 16 MSL Full production Full production Die Full production Wafer Full production N/A N/A 1K+ $0.4500 reel of 2500 [logo]UZ2T LM3524DM N/A 24 Hour N/A Samples Buy Now 1K+ $0.4500 rail of 25 [logo]UZ3TP LM3524DN N/A N/A tray of N/A - wafer jar of N/A - N/A Samples N/A General Description The LM3524D family is an improved version of the industry standard LM3524. It has improved specifications and additional features yet is pin for pin compatible with existing 3524 families. New features reduce the need for additional external circuitry often required in the original version. The LM3524D has a 1% precision 5V reference. The current carrying capability of the output drive transistors has been raised to 200 mA while reducing VCEsat and increasing VCE breakdown to 60V. The common mode voltage range of the error-amp has been raised to 5.5V to eliminate the need for a resistive divider from the 5V reference. In the LM3524D the circuit bias line has been isolated from the shut-down pin. This prevents the oscillator pulse amplitude and frequency from being disturbed by shut-down. Also at high frequencies ([Approximately_Equals]300 kHz) the max. duty cycle per output has been improved to 44% compared to 35% max. duty cycle in other 3524s. In addition, the LM3524D can now be synchronized externally, through pin 3. Also a latch has been added to insure one pulse per period even in noisy environments. The LM3524D includes double pulse suppression logic that insures when a shut-down condition is removed the state of the T-flip-flop will change only after the first clock pulse has arrived. This feature prevents the same output from being pulsed twice in a row, thus reducing the possibility of core saturation in push-pull designs. Features Fully interchangeable with standard LM3524 family 1% precision 5V reference with thermal shut-down Output current to 200 mA DC 60V output capability Wide common mode input range for error-amp One pulse per period (noise suppression) Improved max. duty cycle at high frequencies Double pulse suppression Synchronize through pin 3 Application Notes Title Size in Date Kbytes View Online Download Receive via Email file:///H|/imaging/BITTING/cpl/20020808_1/08062002_10/NATL/08062002_HTML/LM3524D.html (2 of 3) [09-Aug-2002 12:33:45 PM] National P/N LM3524D - Regulating Pulse Width Modulator AN-694: Application Note 694 A DMOS 3A, 55V, HBridge: The LMD18200 Application Note 694 A DMOS 3A, 55V, H-Bridge: The LMD18200 (JAPANESE) 13359 Dec- View Online Kbytes 99 Download 279 Kbytes Download View Online Receive via Email Receive via Email If you have trouble printing or viewing PDF file(s), see Printing Problems. [Information as of 5-Aug-2002] Search Design Purchasing Quality Company Home About Languages . Website Guide . About "Cookies" . National is QS 9000 Certified . Privacy/Security Statement . Contact Us . Site Terms & Conditions of Use . Copyright 2002 (c) National Semiconductor Corporation . My Preferences . Feedback file:///H|/imaging/BITTING/cpl/20020808_1/08062002_10/NATL/08062002_HTML/LM3524D.html (3 of 3) [09-Aug-2002 12:33:45 PM]