Data Sheet, Rev. 1.2, Oct. 2004 HYS72D32300[G/H]BR-[5/6/7]-C HYS72D64300[G/H]BR-[5/6/7]-C HYS72D64320[G/H]BR-[5/6]-C HYS72D128320[G/H]BR-[6/7]-C 184-Pin Registered Double Data Rate SDRAM Module Reg DIMM DDR SDRAM Memory Products N e v e r s t o p t h i n k i n g . Edition 2004-10 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 Munchen, Germany (c) Infineon Technologies AG 2004. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Data Sheet, Rev. 1.2, Oct. 2004 HYS72D32300[G/H]BR-[5/6/7]-C HYS72D64300[G/H]BR-[5/6/7]-C HYS72D64320[G/H]BR-[5/6]-C HYS72D128320[G/H]BR-[6/7]-C 184-Pin Registered Double Data Rate SDRAM Module Reg DIMM DDR SDRAM Memory Products N e v e r s t o p t h i n k i n g . HYS72D32300[G/H]BR-[5/6/7]-C, HYS72D64300[G/H]BR-[5/6/7]-C, HYS72D64320[G/H]BR-[5/6]-C, HYS72D128320[G/H]BR-[6/7]-C Revision History: Rev. 1.2 2004-10 Previous Version: Rev. 1.1 2004-03 Page Subjects (major changes since last revision) 7 added RoHS Product Types 21,22,23 updated Idd Values 32,38,44 updated SPD Codes We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc.mp@infineon.com Template: mp_a4_v2.2_2003-10-07.fm HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM Table of Contents 1 1.1 1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 3.1 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4 4.1 Current Specification and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5 SPD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6 6.1 6.2 6.3 6.4 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Raw Card A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Raw Card C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Raw Card B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Raw Card D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Application Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Data Sheet 5 47 47 48 49 50 Rev. 1.2, 2004-10 184-Pin Registered Double Data Rate SDRAM Module HYS72D32300[G/H]BR-[5/6/7]-C Reg DIMM HYS72D64300[G/H]BR-[5/6/7]-C HYS72D64320[G/H]BR-[5/6]-C HYS72D128320[G/H]BR-[6/7]-C 1 Overview 1.1 Features * * * * * * * * * * * * 184-Pin Registered 8-Byte Dual-In-Line DDR SDRAM Module for "1U" PC, Workstation and Server main memory applications One rank 32M x 72 and 64M x 72 and two ranks 64M x 72 and 128M x 72 organization JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM) with a single + 2.5 V ( 0.2 V) power supply and + 2.6 V ( 0.1 V) power supply for DDR400 Built with 256-Mbit DDR SDRAMs in P-TFBGA-60-1 packages Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) Auto Refresh (CBR) and Self Refresh All inputs and outputs SSTL_2 compatible Re-drive for all input signals using register and PLL devices. Serial Presence Detect with E2PROM Low Profile Modules form factor: 133.35 mm x 28.58 mm x 4.00 mm / 2.64 mm and for 1GB 133.35 mm x 30.48 mm (1.2")x 4.00 mm JEDEC standard reference layout for one rank 256MB, 512MB and two ranks 512MB, 1GB: PC2700 and PC3200 Registered DIMM Raw Cards A,B,C,D Gold plated contacts Table 1 Performance Part Number Speed Code -5 -6 -7 Unit Speed Grade Component DDR400B DDR333B DDR266A -- PC3200-3033 PC2700-2533 PC2100-2033 -- 200 166 - MHz 166 166 143 MHz 133 133 133 MHz Module max. Clock Frequency @CL3 @CL2.5 @CL2 1.2 fCK3 fCK2.5 fCK2 Description The HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C and HYS72D64320GBR-5-C are low profile versions of the standard Registered DIMM modules suitable for 1U Server Applications. The Low Profile DIMM versions are available as 32M x 72 (256 MB), 64M x 72 (512 MB) and 128M x 72 (1 GB) The memory array is designed with Double Data Rate Synchronous DRAMs for ECC applications. All control and address signals are re-driven on the DIMM using register devices and a PLL for the clock distribution. This reduces capacitive loading to the system bus, but adds one cycle to the SDRAM timing. A variety of decoupling capacitors are mounted on the PC board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer. Data Sheet 6 Rev. 1.2, 2004-10 07302003-2MI6-FOP1 HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM Overview Table 2 Ordering Information for Lead-Containing Products Product Type Compliance Code Description SDRAM Technology PC3200 (CL = 3.0) HYS72D32300GBR-5-C PC3200R-30330-A0 1 Rank 256 MB Registered DIMM ECC 256 Mbit (x8) HYS72D64300GBR-5-C PC3200R-30330-C0 1 Rank 512 MB Registered DIMM ECC 256 Mbit (x4) HYS72D64320GBR-5-C PC3200R-30330-B0 2 Ranks 512 MB Registered DIMM ECC 256 Mbit (x8) PC2700 (CL = 2.5) HYS72D32300GBR-6-C PC2700R-25330-A0 1 Rank 256 MB Registered DIMM ECC 256 Mbit (x8) HYS72D64300GBR-6-C PC2700R-25330-C0 1 Rank 512 MB Registered DIMM ECC 256 Mbit (x4) HYS72D64320GBR-6-C PC2700R-25330-B0 2 Ranks 512 MB Registered DIMM ECC 256 Mbit (x8) HYS72D128320GBR-6-C PC2700R-25330-D0 2 Ranks 1 GB Registered DIMM ECC 256 Mbit (x4) PC2100 (CL = 2.0) HYS72D32300GBR-7-C PC2100R-20330-A0 1 Rank 256 MB Registered DIMM ECC 256 Mbit (x8) HYS72D64300GBR-7-C PC2100R-20330-C0 1 Rank 512 MB Registered DIMM ECC 256 Mbit (x4) HYS72D128320GBR-7-C PC2100R-20330-D0 2 Ranks 1 GB Registered DIMM ECC Table 3 256 Mbit (x4) Ordering Information for Lead-Free (RoHS1) Compliant) Products Product Type 2) Compliance Code3) Description SDRAM Technology PC3200 (CL = 3.0) HYS72D32300HBR-5-C PC3200R-30330-A0 1 Rank 256 MB Registered DIMM ECC 256 Mbit (x8) HYS72D64300HBR-5-C PC3200R-30330-C0 1 Rank 512 MB Registered DIMM ECC 256 Mbit (x4) HYS72D64320HBR-5-C PC3200R-30330-B0 2 Ranks 512 MB Registered DIMM ECC 256 Mbit (x8) PC2700 (CL = 2.5) HYS72D32300HBR-6-C PC2700R-25330-A0 1 Rank 256 MB Registered DIMM ECC 256 Mbit (x8) HYS72D64300HBR-6-C PC2700R-25330-C0 1 Rank 512 MB Registered DIMM ECC 256 Mbit (x4) HYS72D64320HBR-6-C PC2700R-25330-B0 2 Ranks 512 MB Registered DIMM ECC 256 Mbit (x8) HYS72D128320HBR-6-C PC2700R-25330-D0 2 Ranks 1 GB Registered DIMM ECC 256 Mbit (x4) PC2100 (CL = 2.0) HYS72D32300HBR-7-C PC2100R-20330-A0 1 Rank 256 MB Registered DIMM ECC 256 Mbit (x8) HYS72D64300HBR-7-C PC2100R-20330-C0 1 Rank 512 MB Registered DIMM ECC 256 Mbit (x4) HYS72D128320HBR-7-C PC2100R-20330-D0 2 Ranks 1 GB Registered DIMM ECC Data Sheet 7 256 Mbit (x4) Rev. 1.2, 2004-10 07302003-2MI6-FOP1 HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM Overview 1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers. 2) All product types end with a place code designating the silicon-die revision. Reference information available on request. Example: HYS72D128300GBR-5-B, indicating Rev.B die are used for SDRAM components. 3) The Compliance Code is printed on the module labels and describes the speed sort (for example "PC2100R"), the latencies (for example "20330" means CAS latency of 2.0 clocks, Row-Column-Delay (RCD) latency of 3 clocks and Row Precharge latency of 3 clocks), JEDEC SPD code definition version 0, and the Raw Card used for this module. Data Sheet 8 Rev. 1.2, 2004-10 07302003-2MI6-FOP1 HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM Pin Configuration 2 Pin Configuration The pin configuration of the Registered DDR SDRAM DIMM is listed by function in Table 4 (184 pins). The abbreviations used in columns Pin and Buffer Type are explained in Table 5 and Table 6 respectively. The pin numbering is depicted in Figure 1. Table 4 Table 4 Pin Configuration of RDIMM (cont'd) Pin# Name Pin Buffer Function Type Type 125 A6 I SSTL 29 A7 I SSTL Pin Configuration of RDIMM 122 A8 I SSTL Pin Buffer Function Type Type 27 A9 I SSTL 141 A10 I SSTL AP I SSTL Pin# Name Clock Signals 137 CK0 I SSTL Clock Signal 118 A11 I SSTL 138 CK0 I SSTL Complement Clock 115 A12 I SSTL 21 CKE0 I SSTL Clock Enable Rank 0 111 CKE1 I SSTL Clock Enable Rank 1 NC NC SSTL Note: 1-rank module Control Signals S0 I SSTL Chip Select of Rank 0 158 S1 I SSTL Chip Select of Rank 1 167 NC NC - Note: 128 Mbit module A13 I SSTL Address Signal 13 Note: 1 Gbit module Note: 2-ranks module NC NC I/O SSTL Data Bus 63:0 I/O SSTL - Note: 1-rank module 154 RAS I SSTL Row Address Strobe 65 CAS I SSTL Column Address Strobe Data Signals 2 DQ0 63 WE I SSTL Write Enable 4 DQ1 10 RESET I 6 DQ2 I/O SSTL 8 DQ3 I/O SSTL 94 DQ4 I/O SSTL 95 DQ5 I/O SSTL 98 DQ6 I/O SSTL 99 DQ7 I/O SSTL 12 DQ8 I/O SSTL 13 DQ9 I/O SSTL 19 DQ10 I/O SSTL 20 DQ11 I/O SSTL 105 DQ12 I/O SSTL 106 DQ13 I/O SSTL Note: For detailed description of the Power Up and Power Management see the Application Note at the end of data sheet Address Signals 59 BA0 52 BA1 I SSTL Bank Address Bus 1:0 48 A0 I SSTL Address Bus 11:0 109 DQ14 I/O SSTL 43 A1 I SSTL 110 DQ15 I/O SSTL 41 A2 I SSTL 23 DQ16 I/O SSTL 130 A3 I SSTL 24 DQ17 I/O SSTL 37 A4 I SSTL 28 DQ18 I/O SSTL 32 A5 I SSTL 31 DQ19 I/O SSTL Data Sheet SSTL 9 based Note: Module based on 512 Mbit or smaller dies NC LVRegister Reset CMOS Forces registered inputs low based - NC I Address Signal 12 Note: Module based on 256 Mbit or larger dies Note: 2-rank module 157 Address Bus 11:0 Rev. 1.2, 2004-10 HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM Pin Configuration Table 4 Pin Configuration of RDIMM (cont'd) Table 4 Pin Configuration of RDIMM (cont'd) Pin# Name Pin Buffer Function Type Type Pin# Name Pin Buffer Function Type Type 114 DQ20 I/O SSTL 174 DQ60 I/O SSTL 117 DQ21 I/O SSTL 175 DQ61 I/O SSTL 121 DQ22 I/O SSTL 178 DQ62 I/O SSTL 123 DQ23 I/O SSTL 179 DQ63 I/O SSTL 33 DQ24 I/O SSTL 44 CB0 I/O SSTL 35 DQ25 I/O SSTL 45 CB1 I/O SSTL 39 DQ26 I/O SSTL 49 CB2 I/O SSTL 40 DQ27 I/O SSTL 51 CB3 I/O SSTL 126 DQ28 I/O SSTL 134 CB4 I/O SSTL 127 DQ29 I/O SSTL 135 CB5 I/O SSTL 131 DQ30 I/O SSTL 142 CB6 I/O SSTL 133 DQ31 I/O SSTL 144 CB7 I/O SSTL 53 DQ32 I/O SSTL 5 DQS0 I/O SSTL Data Strobes 8:0 55 DQ33 I/O SSTL 14 DQS1 I/O SSTL 57 DQ34 I/O SSTL 25 DQS2 I/O SSTL 60 DQ35 I/O SSTL 36 DQS3 I/O SSTL 146 DQ36 I/O SSTL 56 DQS4 I/O SSTL Note: See block diagram for corresponding DQ signals 147 DQ37 I/O SSTL 67 DQS5 I/O SSTL 150 DQ38 I/O SSTL 78 DQS6 I/O SSTL 151 DQ39 I/O SSTL 86 DQS7 I/O SSTL 61 DQ40 I/O SSTL 47 DQS8 I/O SSTL 64 DQ41 I/O SSTL 97 DM0 I SSTL 68 DQ42 I/O SSTL 69 DQ43 I/O SSTL 153 DQ44 I/O SSTL 155 DQ45 I/O SSTL 161 DQ46 I/O SSTL 162 DQ47 I/O SSTL 72 DQ48 I/O SSTL 73 DQ49 I/O SSTL 79 DQ50 I/O SSTL 80 DQ51 I/O SSTL 165 DQ52 I/O SSTL 166 DQ53 I/O SSTL 170 DQ54 I/O SSTL 171 DQ55 I/O SSTL 83 DQ56 I/O SSTL 84 DQ57 I/O SSTL 87 DQ58 I/O SSTL 88 DQ59 I/O SSTL Data Sheet Data Bus 63:0 Data Bus 63:0 Check Bits 7:0 Data Strobes 8:0 Data Mask 0 Note: x8 based module DQS9 I/O SSTL Data Strobe 9 Note: x4 based module 107 DM1 I SSTL Data Mask 1 Note: x8 based module DQS10 I/O SSTL Data Strobe 10 Note: x4 based module 119 DM2 I SSTL Data Mask 2 Note: x8 based module DQS11 I/O SSTL Data Strobe 11 Note: x4 based module 129 DM3 I SSTL Data Mask 3 Note: x8 based module DQS12 I/O SSTL Data Strobe 12 Note: x4 based module 10 Rev. 1.2, 2004-10 HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM Pin Configuration Table 4 Pin Configuration of RDIMM (cont'd) Table 4 Pin Configuration of RDIMM (cont'd) Pin# Name Pin Buffer Function Type Type Pin# Name Pin Buffer Function Type Type 149 I 15, VDDQ 22, 30, 54, 62, 77, 96, 104, 112, 128, 136, 143, 156, 164, 172, 180 PWR - I/O Driver Power Supply 7, VDD 38, 46, 70, 85, 108, 120, 148, 168 PWR - Power Supply VSS 3, 11, 18, 26, 34, 42, 50, 58, 66, 74, 81, 89, 93, 100, 116, 124, 132, 139, 145, 152, 160, 176 GND Ground Plane DM4 SSTL Data Mask 4 Note: x8 based module DQS13 I/O SSTL Data Strobe 13 Note: x4 based module 159 DM5 I SSTL Data Mask 5 Note: x8 based module DQS14 I/O SSTL Data Strobe 14 Note: x4 based module 169 DM6 I SSTL Data Mask 6 Note: x8 based module DQS15 I/O SSTL Data Strobe 15 Note: x4 based module 177 DM7 I SSTL Data Mask 7 Note: x8 based module DQS16 I/O SSTL Data Strobe 16 Note: x4 based module 140 DM8 I SSTL Data Mask 8 Note: x8 based module DQS17 I/O SSTL Data Strobe 17 Note: x4 based module EEPROM 92 SCL I CMOS Serial Bus Clock 91 SDA I/O OD 181 SA0 I 182 SA1 I CMOS Slave Address Select CMOS Bus 2:0 183 SA2 I CMOS Serial Bus Data Power Supplies 1 184 VREF AI - VDDSPD PWR - Data Sheet I/O Reference Voltage EEPROM Power Supply 11 - Rev. 1.2, 2004-10 HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM Pin Configuration Table 4 Pin# Name Pin Configuration of RDIMM (cont'd) Table 5 Pin Buffer Function Type Type Abbreviation Description Other Pins 82 VDDID O OD VDD Identification Note: Pin in tristate, indicating VDD and VDDQ nets connected on PCB NC 9, 16, 17, 71, 75, 76, 90, 101, 102, 103, 113, 163, 173 Data Sheet NC - Abbreviations for Pin Type Not connected Pins not connected on Infineon RDIMM's I Standard input-only pin. Digital levels. O Output. Digital levels. I/O I/O is a bidirectional input/output signal. AI Input. Analog levels. PWR Power GND Ground NU Not Usable (JEDEC Standard) NC Not Connected (JEDEC Standard) Table 6 Abbreviations for Buffer Type Abbreviation Description 12 SSTL Serial Stub Terminalted Logic (SSTL2) LV-CMOS Low Voltage CMOS CMOS CMOS Levels OD Open Drain. The corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-OR. Rev. 1.2, 2004-10 HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM Pin Configuration VREF VSS DQS0 VDD NC VSS DQ09 VDDQ NC DQ10 CKE0 DQ16 DQS2 A9 A7 DQ19 DQ24 DQ25 A4 DQ26 A2 A1 CB01 DQS8 CB02 CB03 - Pin 001 Pin 003 Pin 005 Pin 007 Pin 009 Pin 011 Pin 013 Pin 015 Pin 017 Pin 019 Pin 021 Pin 023 Pin 025 Pin 027 Pin 029 Pin 031 Pin 033 Pin 035 Pin 037 Pin 039 Pin 041 Pin 043 Pin 045 Pin 047 Pin 049 Pin 051 DQ32 DQ33 DQ34 BA0 DQ40 WE CAS DQS5 DQ43 NC DQ49 NC VDDQ DQ50 VSS DQ56 VDD DQ58 VSS SDA - Pin 053 Pin 055 Pin 057 Pin 059 Pin 061 Pin 063 Pin 065 Pin 067 Pin 069 Pin 071 Pin 073 Pin 075 Pin 077 Pin 079 Pin 081 Pin 083 Pin 085 Pin 087 Pin 089 Pin 091 Pin 002 Pin 004 Pin 006 Pin 008 Pin 010 Pin 012 Pin 014 Pin 016 Pin 018 Pin 020 Pin 022 Pin 024 Pin 026 Pin 028 Pin 030 Pin 032 Pin 034 Pin 036 Pin 038 Pin 040 Pin 042 Pin 044 Pin 046 Pin 048 Pin 050 Pin 052 Pin 094 - DQ04 Pin 096 - VDDQ Pin 098 - DQ06 Pin 100 - VSS Pin 102 - NC Pin 104 - VDDQ Pin 106 - DQ13 Pin 108 - VDD Pin 110 - DQ15 Pin 112 - VDDQ Pin 114 - DQ20 Pin 116 - VSS Pin 118 - A11 Pin 120 - VDD VDDQ - Pin 054 DQS4 - Pin 056 VSS - Pin 058 DQ35 - Pin 060 VDDQ - Pin 062 DQ41 - Pin 064 VSS - Pin 066 DQ42 - Pin 068 VDD - Pin 070 DQ48 - Pin 072 VSS - Pin 074 NC - Pin 076 DQS6 - Pin 078 DQ51 - Pin 080 VDDID - Pin 082 DQ57 - Pin 084 DQS7 - Pin 086 DQ59 - Pin 088 NC - Pin 090 SCL - Pin 092 Pin 146 - DQ36 Pin 148 - VDD Pin 150 - DQ38 Pin 152 - VSS Pin 154 - RAS Pin 156 - VDDQ Pin 158 - S1/NC Pin 160 - VSS Pin 162 - DQ47 Pin 164 - VDDQ Pin 166 - DQ53 Pin 168 - VDD Pin 170 - DQ54 Pin 172 - VDDQ Pin 174 - DQ60 Pin 176 - VSS Pin 178 - DQ62 Pin 180 - VDDQ Pin 182 - SA1 Pin 184 - VDDSPD DQ00 DQ01 DQ02 DQ03 RESET DQ08 DQS1 NC VSS DQ11 VDDQ DQ17 VSS DQ18 VDDQ A5 VSS DQS3 VDD DQ27 VSS CB00 VDD A0 VSS BA1 - Pin 122 Pin 124 Pin 126 Pin 128 Pin 130 Pin 132 Pin 134 Pin 136 Pin 138 Pin 140 Pin 142 Pin 144 - A8 VSS DQ28 VDDQ A3 VSS DQ04 VDDQ CK0 DM8/DQS17 CB06 CB07 VSS Pin 093 Pin 095 Pin 097 Pin 099 Pin 101 Pin 103 Pin 105 Pin 107 Pin 109 Pin 111 Pin 113 Pin 115 Pin 117 Pin 119 Pin 121 Pin 123 Pin 125 Pin 127 Pin 129 Pin 131 Pin 133 Pin 135 Pin 137 Pin 139 Pin 141 Pin 143 - DQ05 DQ00/DQS9 DQ07 NC NC DQ15 DM1/DQS10 DQ14 CKE1/NC NC A12/NC DQ21 DM2/DQS11 DQ22 DQ23 A6 DQ29 DM3/DQS12 DQ30 DQ31 CB5 CK0 VSS A10/AP VDDQ Pin 145 Pin 147 Pin 149 Pin 151 Pin 153 Pin 155 Pin 157 Pin 159 Pin 161 Pin 163 Pin 165 Pin 167 Pin 169 Pin 171 Pin 173 Pin 175 Pin 177 Pin 179 Pin 181 Pin 183 - DQ37 DM4/DQS13 DQ39 DQ44 DQ45 S0 DM5/DQS14 DQ46 NC DQ52 A13/NC DM6/DQS15 DQ55 NC DQ61 DM7/DQS16 DQ63 SA0 SA2 VSS MPPD0020 Figure 1 Pin Configuration 184 Pins, Reg Table 7 Address Table Density Organization 256 MB 32 M x72 Memory SDRAMs # of SDRAMs # of row/rank/ Refresh Ranks columns bits 1 32 M x8 9 13 / 2 / 10 8K Period Interval 64 ms 7.8 s 512 MB 64 M x72 1 64 M x4 18 13 / 2 / 11 8K 64 ms 7.8 s 512 MB 64 M x72 2 32 M x8 18 13 / 2 / 10 8K 64 ms 7.8 s 1 GB 128 M x72 2 64 M x4 36 13 / 2 / 11 8K 64 ms 7.8 s Data Sheet 13 Rev. 1.2, 2004-10 HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM Pin Configuration CK0 CK0 S0 CKE0 BA0 - BA1 A0 - An RAS CAS WE PCK PCK RESET PCK PCK RS0 RCKE0 RBA0 - RBA1 RA0-RAn RRAS RCAS RWE PLL R E G I S T E R CS: SDRAMs D0- D8 CKE: SDRAMs D0 - D8 BA0 - BA1: SDRAMs D0 - D8 A0 - An: SDRAMs D0 - D8 RAS: SDRAMs D0 - D8 CAS: SDRAMs D0 - D8 WE: SDRAMs D0 - D8 S0 DM0/DQS9 DQS0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM1/DQS10 DQS1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM2/DQS11 DQS2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 SCL SAD SA0 SA1 SA2 VSS Figure 2 SCL SAD A0 A1 A2 WP D0 D1 D2 DM3/DQS12 DQS3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM4/DQS13 DQS4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM5/DQS14 DQS5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 E0 VDD,SPD VDD/VDDQ VREF VSS VDDID D4 D5 DM6/DQS15 DQS6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM7/DQS16 DQS7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM8/DQS17 DQS8 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D6 D7 D8 VDD: SPD EEPROM E0 VDD/VDDQ: SDRAMs D0 - D8 VREF: SDRAMs D0 - D8 VSS: SDRAMs D0 - D8 Strap: see Note 1 MPBD1101 Block Diagram Raw Card A x72 1 Rank x8, ECC 3. BAn, An, RAS, CAS, WE resistors are 22 ohms 5% Notes 1. VDD = VDDQ, therefore VDDID strap open 2. DQ, DQS, DM resistors are 22 ohms 5% Data Sheet D3 14 Rev. 1.2, 2004-10 HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM Pin Configuration CK0 CK0 S0 CKE0 S1 CKE1 BA0 - BA1 A0 - An RAS CAS WE PCK PCK RESET PCK PCK RS0 RCKE0 RS1 RCKE1 RBA0 - RBA1 RA0 - RAn RRAS RCAS RWE PLL R E G I S T E R CKE: SDRAMs D0 - D8 CKE: SDRAMs D9 - D17 BA0 - BA1: SDRAMs D0 - D17 A0 - An: SDRAMs D0 - D17 RAS: SDRAMs D0 - D17 CAS: SDRAMs D0 - D17 WE: SDRAMs D0 - D17 SCL SAD SA0 SA1 SA2 VSS E0 SCL SAD A0 A1 A2 WP S0 S1 DM0/DQS9 DQS0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM1/DQS10 DQS1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM2/DQS11 DQS2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM3/DQS12 DQS3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 VDD,SPD VDD/VDDQ VREF VSS VDDID CS CS CS CS D0 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D1 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D2 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D3 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS CS CS CS D9 DM4/DQS13 DQS4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM5/DQS14 DQS5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM6/DQS15 DQS6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM7/DQS16 DQS7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM8/DQS17 DQS8 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D10 D11 D12 VDD: SPD EEPROM E0 VDD/VDDQ: SDRAMs D0 - D17 VREF: SDRAMs D0 - D17 VSS: SDRAMs D0 - D17 DM: SDRAMs D0 - D17 Strap: see Note 1 CS CS CS CS CS D4 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D5 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D6 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D7 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D8 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS CS CS CS CS D13 D14 D15 D16 D17 MPBD1401 Figure 3 Block Diagram Raw Card B x72, 2Ranks x8, ECC Notes 3. BAn, An, RAS, CAS, WE resistors are 22 ohms 5% 4. For Wire per Clock Loading please see Figure: "Diferential Clock Net Wiring" 1. VDD = VDDQ, therefore VDDID strap open 2. DQ, DQS, DM resistors are 22 ohms 5% Data Sheet 15 Rev. 1.2, 2004-10 HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM Pin Configuration CK0 CK0 S0 CKE0 BA0 - BA1 A0 - An RAS CAS WE PCK PCK RESET PCK PCK RS0 RCKE0 RBA0 - RBA1 RA0 - RAn RRAS RCAS RWE PLL R E G I S T E R CS: SDRAMs D0- D17 CKE: SDRAMs D0 - D17 BA0 - BA1: SDRAMs D0 - D17 A0 - An: SDRAMs D0 - D17 RAS: SDRAMs D0 - D17 CAS: SDRAMs D0 - D17 WE: SDRAMs D0 - D17 RS0 DQS0 DQ0 DQ1 DQ2 DQ3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS1 DQ8 DQ9 DQ10 DQ11 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS2 DQ16 DQ17 DQ18 DQ19 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS3 DQ24 DQ25 DQ26 DQ27 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS4 DQ32 DQ33 DQ34 DQ35 DQS5 DQ40 DQ41 DQ42 DQ43 VDD,SPD VDD/VDDQ VREF VSS VDDID DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS CS CS CS D0 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS7 DQ56 DQ57 DQ58 DQ59 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS8 CB0 CB1 CB2 CB3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS9 DQ4 DQ5 DQ6 DQ7 DQS I/O 0 I/O 1 I/O 2 I/O 3 D1 D2 D3 CS D4 CS DQS6 DQ48 DQ49 DQ50 DQ51 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS10 DQ12 DQ13 DQ14 DQ15 D5 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS11 DQ20 DQ21 DQ22 DQ23 VDD: SPD EEPROM E0 VDD/VDDQ: SDRAMs D0 - D17 VREF: SDRAMs D0 - D17 VSS: SDRAMs D0 - D17 CS D8 CS D9 CS D10 CS DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS13 DQ36 DQ37 DQ38 DQ39 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS14 DQ44 DQ45 DQ46 DQ47 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS15 DQ52 DQ53 DQ54 DQ55 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS16 DQ60 DQ61 DQ62 DQ63 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS17 CB4 CB5 CB6 CB7 DQS I/O 0 I/O 1 I/O 2 I/O 3 D11 SCL SAD A0 A1 A2 WP CS D12 CS D13 CS D14 CS D15 CS D16 CS D17 E0 MPBD1501 Block Diagram Raw Card C x72 1 Rank x4, ECC Notes 3. BAn, An, RAS, CAS, WE resistors are 22 ohms 5% 1. VDD = VDDQ, therefore VDDID strap open 2. DQ, DQS, DM resistors are 22 ohms 5% Data Sheet CS D7 DQS12 DQ28 DQ29 DQ30 DQ31 SCL SAD SA0 SA1 SA2 VSS Strap: see Note 1 Figure 4 CS D6 16 Rev. 1.2, 2004-10 HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM Pin Configuration CK0 CK0 S0 CKE0 S1 CKE1 BA0 - BA1 A0 - An RAS CAS WE PCK PCK RESET PLL R E G I S T E R PCK PCK RS0 RCKE0 RS1 RCKE1 RBA0 - RBA1 RA0-RAn RRAS RCAS RWE BA0 - BA1: SDRAMs D0 - D35 A0 - An: SDRAMs D0 - D35 RAS: SDRAMs D0 - D35 CAS: SDRAMs D0 - D35 WE: SDRAMs D0 - D35 VDD,SPD VDD/VDDQ VREF VSS VDDID Strap: see Note 1 VDD: SPD EEPROM E0 VDD/VDDQ: SDRAMs D0 - D35 VREF: SDRAMs D0 - D35 VSS: SDRAMs D0 - D35 DM: SDRAMs D0 - D35 SCL SAD SA0 SA1 SA2 VSS E0 SCL SAD A0 A1 A2 WP RS0 RCKE0 RS1 RCKE1 DQS0 DQ0 DQ1 DQ2 DQ3 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS1 DQ8 DQ9 DQ10 DQ11 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS10 DQ12 DQ13 DQ14 DQ15 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS9 DQ4 DQ5 DQ6 DQ7 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS11 DQ20 DQ21 DQ22 DQ23 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS2 DQ16 DQ17 DQ18 DQ19 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS3 DQ24 DQ25 DQ26 DQ27 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS17 CB4 CB5 CB6 CB7 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS12 DQ28 DQ29 DQ30 DQ31 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 D4 D0 D12 D8 D20 D16 D24 D28 D32 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 D6 DQS7 DQ56 DQ57 DQ58 DQ59 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS6 DQ48 DQ49 DQ50 DQ51 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS15 DQ52 DQ53 DQ54 DQ55 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS16 DQ60 DQ61 DQ62 DQ63 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS14 DQ44 DQ45 DQ46 DQ47 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS5 DQ40 DQ41 DQ42 DQ43 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS4 DQ32 DQ33 DQ34 DQ35 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS8 CB0 CB1 CB2 CB3 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS13 DQ36 DQ37 DQ38 DQ39 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 D2 D14 D10 D22 D18 D26 D30 D34 D5 D1 D13 D9 D21 D17 D25 D28 D33 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 D7 D3 D15 D11 D23 D19 D27 D31 D35 MPBD1061 Figure 5 Block Diagram Raw Card D x72 2 Ranks x4, ECC 3. BAn, An, RAS, CAS, WE resistors are 22 ohms 5% 4. For Wire per Clock Loading please see Figure "Differental Clock Net Wiring" Notes 1. VDD = VDDQ, therefore VDDID strap open 2. DQ, DQS, DM resistors are 18 ohms 5% Data Sheet 17 Rev. 1.2, 2004-10 HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM Electrical Characteristics 3 Electrical Characteristics 3.1 Operating Conditions Table 8 Absolute Maximum Ratings Parameter Symbol Voltage on I/O pins relative to VSS VIN, VOUT VIN VDD VDDQ TA TSTG PD IOUT Voltage on inputs relative to VSS Voltage on VDD supply relative to VSS Voltage on VDDQ supply relative to VSS Operating temperature (ambient) Storage temperature (plastic) Power dissipation (per SDRAM component) Short circuit output current Values min. typ. max. Unit Note/ Test Condition -0.5 - VDDQ +0.5 V - -1 - +3.6 V - -1 - +3.6 V - -1 - +3.6 V - 0 - +70 C - -55 - +150 C - - 1 - W - - 50 - mA - Attention: Permanent damage to the device may occur if "Absolute Maximum Ratings" are exceeded. This is a stress rating only, and functional operation should be restricted to recommended operation conditions. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability and exceeding only one of the values may cause irreversible damage to the integrated circuit. Table 9 Electrical Characteristics and DC Operating Conditions Parameter Symbol Unit Note/Test Condition 1) Values Min. Typ. Max. 2.3 2.5 2.7 V VDD Output Supply Voltage VDDQ Output Supply Voltage VDDQ EEPROM supply voltage VDDSPD Supply Voltage, I/O Supply VSS, Voltage VSSQ VREF Input Reference Voltage I/O Termination Voltage VTT 2.5 2.6 2.7 V 2.3 2.5 2.7 V 2.5 2.6 2.7 V fCK 166 MHz fCK > 166 MHz 2) fCK 166 MHz 3) fCK > 166 MHz 2)3) 2.3 2.5 3.6 V -- 0 V -- Device Supply Voltage VDD Device Supply Voltage 0 0.49 x VDDQ 0.5 x VDDQ 0.51 x VDDQ V 4) VREF - 0.04 VREF + 0.04 V 5) Input High (Logic1) Voltage VIH(DC) VREF + 0.15 8) Input Low (Logic0) Voltage VIL(DC) -0.3 Input Voltage Level, CK and CK Inputs VIN(DC) -0.3 VDDQ + 0.3 V VREF - 0.15 V VDDQ + 0.3 V Input Differential Voltage, CK and CK Inputs VID(DC) 0.36 VDDQ + 0.6 V 8)6) VI-Matching Pull-up Current to Pull-down Current VIRatio 0.71 1.4 -- 7) (System) Data Sheet 18 8) 8) Rev. 1.2, 2004-10 07302003-2MI6-FOP1 HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM Electrical Characteristics Table 9 Electrical Characteristics and DC Operating Conditions (cont'd) Parameter Symbol Unit Note/Test Condition 1) Values Min. Typ. Max. Input Leakage Current II -2 2 A Any input 0 V VIN VDD; All other pins not under test = 0 V 8)9) Output Leakage Current IOZ -5 5 A DQs are disabled; 0 V VOUT VDDQ Output High Current, Normal Strength Driver IOH -- -16.2 mA VOUT = 1.95 V Output Low Current, Normal Strength Driver IOL 16.2 -- mA VOUT = 0.35 V 1) 0 C TA 70 C 2) DDR400 conditions apply for all clock frequencies above 166 MHz 3) Under all conditions, VDDQ must be less than or equal to VDD. 4) Peak to peak AC noise on VREF may not exceed 2% VREF (DC). VREF is also expected to track noise variations in VDDQ. 5) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. 6) VID is the magnitude of the difference between the input level on CK and the input level on CK. 7) The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the maximum difference between pull-up and pull-down drivers due to process variation. 8) Inputs are not recognized as valid until VREF stabilizes. 9) Values are shown per DDR SDRAM component Data Sheet 19 Rev. 1.2, 2004-10 07302003-2MI6-FOP1 HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM Current Specification and Conditions 4 Current Specification and Conditions Table 10 IDD Conditions Parameter Symbol Operating Current 0 one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. IDD0 Operating Current 1 one bank; active/read/precharge; Burst Length = 4; see component data sheet. IDD1 Precharge Power-Down Standby Current all banks idle; power-down mode; CKE VIL,MAX IDD2P Precharge Floating Standby Current CS VIH,,MIN, all banks idle; CKE VIH,MIN; address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM. IDD2F Precharge Quiet Standby Current CS VIHMIN, all banks idle; CKE VIH,MIN; VIN = VREF for DQ, DQS and DM; address and other control inputs stable at VIH,MIN or VIL,MAX. IDD2Q Active Power-Down Standby Current one bank active; power-down mode; CKE VILMAX; VIN = VREF for DQ, DQS and DM. IDD3P Active Standby Current one bank active; CS VIH,MIN; CKE VIH,MIN; tRC = tRAS,MAX; DQ, DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle. IDD3N Operating Current Read one bank active; Burst Length = 2; reads; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B; IOUT = 0 mA IDD4R Operating Current Write one bank active; Burst Length = 2; writes; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B IDD4W Auto-Refresh Current tRC = tRFCMIN, burst refresh IDD5 Self-Refresh Current CKE 0.2 V; external clock on IDD6 Operating Current 7 four bank interleaving with Burst Length = 4; see component data sheet. IDD7 Data Sheet 20 Rev. 1.2, 2004-10 07302003-2MI6-FOP1 HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM Current Specification and Conditions Organization HYS72D64320GBR-5-C HYS72D64320HBR-5-C Product Type HYS72D64300GBR-5-C HYS72D64300HBR-5-C IDD Specification for HYS72D[128/64/32]3xxx[G/H]BR-5-C HYS72D32300GBR-5-C HYS72D32300HBR--5-C Table 11 256 MB 512 MB 512 MB x72 x72 x72 1 Rank 1 Rank 2 Ranks -5 -5 -5 Unit Note/ Test Conditions1) 2) Symbol Typ. Max. Typ. Max. Typ. Max. IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7 1140 1370 2070 2480 1780 2080 mA 3) 1360 1600 2380 2800 2000 2310 mA 3)4) 390 440 730 790 730 790 mA 5) 880 990 1450 1620 1450 1620 mA 5) 540 650 1020 1200 1020 1200 mA 5) 470 560 890 720 890 1020 mA 5) 950 1080 1590 1780 1590 1780 mA 5) 1400 1600 2470 2800 2040 2310 mA 3)4) 1450 1650 2560 2890 2090 2350 mA 3) 1630 2120 3190 4130 2270 2830 mA 3) 330 370 640 700 640 700 mA 5) 2530 2950 4720 5500 3170 3660 mA 3)4) 1) Test condition for maximum values: VDD = 2.7 V, TA = 10 C 2) Module IDD is calculated on the basis of component IDD and includes Register and PLL 3) The module IDD values are calculated from the component IDD datasheet values are: n * IDDx[component] for single bank modules (n: number of components per module bank) n * IDDx[component] + n * IDD3N[component] for two bank modules (n: number of components per module bank) 4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions 5) The module IDD values are calculated from the component IDD datasheet values are: n * IDDx[component] for single bank modules (n: number of components per module bank) 2 * n * IDDx[component] for single two bank modules (n: number of components per module bank) Data Sheet 21 Rev. 1.2, 2004-10 07302003-2MI6-FOP1 HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM Current Specification and Conditions IDD Specification for HYS72D[256/128/64/32]3xxx[G/H]BR-6-C HYS72D64320GBR-6-C HYS72D64320HBR-6-C HYS72D128320GBR-6-C HYS72D128320HBR-6-C Organization Unit Note/ Test Conditions1) 2) HYS72D64300GBR-6-C HYS72D64300HBR-6-C Product Type HYS72D32300GBR-6-C HYS72D32300HBR-6-C Table 12 256 MB 512 MB 512 MB 1 GB x72 x72 x72 x72 1 Rank 1 Rank 2 Ranks 2 Ranks -6 -6 -6 -6 Symbol Typ. Max. Typ. Max. Typ. IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7 1000 1190 1790 2110 1540 1780 2870 3290 mA 3) 1210 1410 2090 2420 1750 2000 3160 3600 mA 3)4) 370 410 650 1220 1300 mA 5) 780 880 1250 1400 1250 1400 2200 2440 mA 5) 480 580 890 1050 890 1050 1690 1980 mA 5) 430 500 780 640 890 1480 1660 mA 5) 840 950 1380 1540 1380 1540 2450 2730 mA 5) 710 650 780 Max. Typ. 710 Max. 1210 1410 2090 2420 1750 2000 3160 3600 mA 3)4) 1250 1450 2180 2510 1790 2040 3250 3690 mA 3) 1420 1820 2750 3510 1960 2410 3830 4690 mA 3) 320 5) 370 580 640 580 640 1110 1190 mA 2200 2580 4070 4760 2740 3170 5140 5940 mA 3)4) 1) Test condition for maximum values: VDD = 2.7 V, TA = 10 C 2) Module IDD is calculated on the basis of component IDD and includes Register and PLL 3) The module IDD values are calculated from the component IDD datasheet values are: n * IDDx[component] for single bank modules (n: number of components per module bank) n * IDDx[component] + n * IDD3N[component] for two bank modules (n: number of components per module bank) 4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions 5) The module IDD values are calculated from the component IDD datasheet values are: n * IDDx[component] for single bank modules (n: number of components per module bank) 2 * n * IDDx[component] for single two bank modules (n: number of components per module bank) Data Sheet 22 Rev. 1.2, 2004-10 07302003-2MI6-FOP1 HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM Current Specification and Conditions Organization HYS72D128320GBR-7-C HYS72D128320HBR-7-C Product Type HYS72D64300GBR-7-C HYS72D64300HBR-7-C IDD Specification for HYS72D[128/64/32]3xxx[G/H]BR-7-C HYS72D32300GBR-7-C HYS72D32300HBR-7-C Table 13 256 MB 512 MB 1 GB x72 x72 x72 1 Rank 1 Rank 2 Ranks -7 -7 -7 Unit Note/ Test Conditions1) 2) Symbol Typ. Max. Typ. Max. Typ. Max. IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7 860 1040 1510 1830 2410 2870 mA 3) 1100 1250 1890 2120 2790 3170 mA 3)4) 330 370 560 610 1010 1080 mA 5) 670 760 1050 1180 1810 2010 mA 5) 440 520 770 910 1440 1690 mA 5) 380 450 660 570 1230 1400 mA 5) 740 870 1200 1390 2100 2440 mA 5) 1060 1200 1800 2030 2700 3080 mA 3)4) 1100 1250 1890 2120 2790 3170 mA 3) 1210 1600 2310 3060 3210 4110 mA 3) 300 350 520 580 940 1030 mA 5) 1780 2100 3240 3830 4140 4880 mA 3)4) 1) Test condition for maximum values: VDD = 2.7 V, TA = 10 C 2) Module IDD is calculated on the basis of component IDD and includes Register and PLL 3) The module IDD values are calculated from the component IDD datasheet values are: n * IDDx[component] for single bank modules (n: number of components per module bank) n * IDDx[component] + n * IDD3N[component] for two bank modules (n: number of components per module bank) 4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions 5) The module IDD values are calculated from the component IDD datasheet values are: n * IDDx[component] for single bank modules (n: number of components per module bank) 2 * n * IDDx[component] for single two bank modules (n: number of components per module bank) Data Sheet 23 Rev. 1.2, 2004-10 07302003-2MI6-FOP1 HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM Current Specification and Conditions 4.1 AC Characteristics Table 14 AC Timing - Absolute Specifications for PC3200 and PC2700 Parameter Symbol -5 -6 DDR400B Unit Note/ Test Condition 1) DDR333 Min. Max. Min. Max. DQ output access time from CK/CK tAC -0.5 +0.5 -0.7 +0.7 ns 2)3)4)5) CK high-level width tCH tCK 0.45 0.55 0.45 0.55 tCK 2)3)4)5) 5 8 6 12 ns CL = 3.0 6 12 6 12 ns CL = 2.5 7.5 12 7.5 12 ns 0.45 0.55 0.45 0.55 tCK tCK 2)3)4)5) Clock cycle time tCL Auto precharge write recovery tDAL CK low-level width + precharge time (tWR/tCK)+(tRP/tCK) 2)3)4)5) 2)3)4)5) CL = 2.0 2)3)4)5) 2)3)4)5)6) tDH tDIPW 0.4 -- 0.45 -- ns 2)3)4)5) 1.75 -- 1.75 -- ns 2)3)4)5)6) DQS output access time from CK/CK tDQSCK -0.6 +0.6 -0.6 +0.6 ns 2)3)4)5) DQS input low (high) pulse width (write cycle) tDQSL,H 0.35 -- 0.35 -- tCK 2)3)4)5) DQS-DQ skew (DQS and associated DQ signals) tDQSQ -- +0.40 -- +0.40 ns TFBGA Write command to 1st DQS latching transition tDQSS 0.72 1.25 0.75 1.25 tCK 2)3)4)5) DQ and DM input setup time tDS tDSH 0.4 -- 0.45 -- ns 2)3)4)5) 0.2 -- 0.2 -- tCK 2)3)4)5) tDSS 0.2 -- 0.2 -- tCK 2)3)4)5) ns 2)3)4)5) DQ and DM input hold time DQ and DM input pulse width (each input) DQS falling edge hold time from CK (write cycle) DQS falling edge to CK setup time (write cycle) tHP Data-out high-impedance time tHZ Clock Half Period min. (tCL, tCH) min. (tCL, tCH) 2)3)4)5) -- +0.7 -0.7 +0.7 ns 2)3)4)5)7) 0.6 -- 0.75 -- ns fast slew rate 0.7 -- 0.8 -- ns slow slew rate3)4)5)6)8) from CK/CK Address and control input hold tIH time 3)4)5)6)8) Control and Addr. input pulse width (each input) tIPW 2.2 -- 2.2 -- ns 2)3)4)5)9) Address and control input setup time tIS 0.6 -- 0.75 -- ns fast slew rate 0.7 -- 0.8 -- ns slow slew rate3)4)5)6)8) Data Sheet 24 3)4)5)6)8) Rev. 1.2, 2004-10 07302003-2MI6-FOP1 HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM Current Specification and Conditions Table 14 AC Timing - Absolute Specifications for PC3200 and PC2700 Parameter Symbol -5 -6 DDR400B Unit Note/ Test Condition 1) DDR333 Min. Max. Min. Max. Data-out low-impedance time from CK/CK tLZ -0.7 +0.7 -0.7 +0.7 ns 2)3)4)5)7) Mode register set command cycle time tMRD 2 -- 2 -- tCK 2)3)4)5) ns 2)3)4)5) ns TFBGA 2)3)4)5) ns 2)3)4)5) tQH Data hold skew factor tQHS Active to Autoprecharge delay tRAP tHP -tQHS tRCD or tRASmin -- tRCD or tRASmin -- Active to Precharge command tRAS 40 70E+3 42 70E+3 ns 2)3)4)5) DQ/DQS output hold time tHP -tQHS -- +0.50 -- +0.50 Active to Active/Auto-refresh command period tRC 55 -- 60 -- ns 2)3)4)5) Active to Read or Write delay tRCD tREFI 15 -- 18 -- ns 2)3)4)5) -- 7.8 -- 7.8 s 2)3)4)5)10) tRFC 70 -- 72 -- ns 2)3)4)5) tRP Read preamble tRPRE Read postamble tRPST Active bank A to Active bank B tRRD 15 -- 18 -- ns 2)3)4)5) 0.9 1.1 0.9 1.1 2)3)4)5) 0.40 0.60 0.40 0.60 tCK tCK 10 -- 12 -- ns 2)3)4)5) tWPRE Write preamble setup time tWPRES Write postamble tWPST Write recovery time tWR Internal write to read command tWTR 0.25 -- 0.25 -- tCK 2)3)4)5) 0 -- 0 -- ns 2)3)4)5)11) 0.40 0.60 0.40 0.60 tCK 2)3)4)5)12) 15 -- 15 -- ns 2)3)4)5) 2 -- 1 -- tCK 2)3)4)5) Average Periodic Refresh Interval Auto-refresh to Active/Autorefresh command period Precharge command period 2)3)4)5) command Write preamble delay Exit self-refresh to non-read command tXSNR 75 -- 75 -- ns 2)3)4)5) Exit self-refresh to read command tXSRD 200 -- 200 -- tCK 2)3)4)5) 1) 0 C TA 70 C; VDDQ = 2.5 V 0.2 V, VDD = +2.5 V 0.2 V (DDR333); VDDQ = 2.6 V 0.1 V, VDD = +2.6 V 0.1 V (DDR400) 2) Input slew rate 1 V/ns for DDR400, DDR333 3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK, is VREF. CK/CK slew rate are 1.0 V/ns. 4) Inputs are not recognized as valid until VREF stabilizes. 5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT. 6) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. 7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). Data Sheet 25 Rev. 1.2, 2004-10 07302003-2MI6-FOP1 HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM Current Specification and Conditions 8) Fast slew rate 1.0 V/ns , slow slew rate 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured between VIH(ac) and VIL(ac). 9) These parameters guarantee device timing, but they are not necessarily tested on each device. 10) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device. 11) The specific requirement is that DQS be valid (HIGH,LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specificationsof the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW at this time, depending on tDQSS. 12) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. Table 15 AC Timing - Absolute Specifications for PC2700 Parameter Symbol -7 Unit Note/Test Condition 1) DDR266A Min. Max. -0.75 +0.75 ns 2)3)4)5) 0.45 0.55 tCK 2)3)4)5) 7.5 12 ns CL = 2.52)3)4)5) 7.5 12 ns CL = 2.02)3)4)5) 0.45 0.55 2)3)4)5) (tWR/tCK)+(tRP/tCK) -- tCK tCK tDH DQ and DM input pulse width (each input) tDIPW DQS output access time from CK/CK tDQSCK DQS input low (high) pulse width (write cycle) tDQSL,H DQS-DQ skew (DQS and associated DQ tDQSQ 0.5 -- ns 2)3)4)5) 1.75 -- ns 2)3)4)5)6) -0.75 +0.75 ns 2)3)4)5) 0.35 -- tCK 2)3)4)5) -- +0.5 ns FBGA2)3)4)5) Write command to 1st DQS latching transition tDQSS 0.75 1.25 tCK 2)3)4)5) tDS tDSH 0.5 -- ns 2)3)4)5) 0.2 -- tCK 2)3)4)5) DQS falling edge to CK setup time (write cycle) tDSS 0.2 -- tCK 2)3)4)5) Clock Half Period tHP tHZ tIH min. (tCL, tCH) -- ns 2)3)4)5) -0.75 +0.75 ns 2)3)4)5)7) 0.9 -- ns fast slew rate 1.0 -- ns slow slew rate 2.2 -- ns 2)3)4)5)9) DQ output access time from CK/CK CK high-level width Clock cycle time CK low-level width Auto precharge write recovery + precharge time tAC tCH tCK tCL tDAL DQ and DM input hold time 2)3)4)5)6) signals) DQ and DM input setup time DQS falling edge hold time from CK (write cycle) Data-out high-impedance time from CK/CK Address and control input hold time Control and Addr. input pulse width (each input) Data Sheet tIPW 26 3)4)5)6)8) 3)4)5)6)8) Rev. 1.2, 2004-10 07302003-2MI6-FOP1 HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM Current Specification and Conditions Table 15 AC Timing - Absolute Specifications for PC2700 Parameter Symbol -7 Unit Note/Test Condition 1) DDR266A Address and control input setup time Data-out low-impedance time from CK/CK Mode register set command cycle time DQ/DQS output hold time Data hold skew factor Active to Read w/AP delay Active to Precharge command Active to Active/Auto-refresh command period Active to Read or Write delay Average Periodic Refresh Interval Auto-refresh to Active/Auto-refresh command period Precharge command period Read preamble Read postamble Active bank A to Active bank B command Write preamble Write preamble setup time Write postamble Write recovery time Internal write to read command delay Exit self-refresh to non-read command Exit self-refresh to read command Min. Max. 0.9 -- ns fast slew rate 1.0 -- ns slow slew rate tLZ tMRD tQH tQHS tRAP tRAS tRC -0.75 +0.75 ns 2)3)4)5)7) tCK 2)3)4)5) ns 2)3)4)5) tIS 2 -- tHP - tQHS 3)4)5)6)8) 3)4)5)6)8) -- 0.75 ns FBGA2)3)4)5) tRCD or tRASmin -- ns 2)3)4)5) 45 120E+3 ns 2)3)4)5) 65 -- ns 2)3)4)5) tRCD tREFI tRFC 20 -- ns 2)3)4)5) 7.8 -- s 2)3)4)5)10) 75 -- ns 2)3)4)5) tRP tRPRE tRPST tRRD tWPRE tWPRES tWPST tWR tWTR tXSNR tXSRD 20 -- ns 2)3)4)5) 0.9 1.1 2)3)4)5) 0.4 0.6 tCK tCK 15 -- ns 2)3)4)5) 0.25 -- tCK 2)3)4)5) 0 -- ns 2)3)4)5)11) 0.4 -- tCK 2)3)4)5)12) 15 -- ns 2)3)4)5) 1 -- tCK 2)3)4)5) ns 2)3)4)5)13) tCK 2)3)4)5) 75 200 -- 2)3)4)5) 1) VDDQ = 2.5 V 0.2 V, VDD = +2.5 V 0.2 V ; 0 C TA 70 C 2) Input slew rate 1 V/ns 3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK, is VREF. CK/CK slew rate are 1.0 V/ns. 4) Inputs are not recognized as valid until VREF stabilizes. 5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT. 6) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. 7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 8) Fast slew rate 1.0 V/ns , slow slew rate 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured between VIH(ac) and VIL(ac). 9) These parameters guarantee device timing, but they are not necessarily tested on each device. 10) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device. Data Sheet 27 Rev. 1.2, 2004-10 07302003-2MI6-FOP1 HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM Current Specification and Conditions 11) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 12) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 13) In all circumstances, tXSNR can be satisfied using tXSNR = tRFC,min + 1 x tCK Data Sheet 28 Rev. 1.2, 2004-10 07302003-2MI6-FOP1 HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM SPD Contents HYS72D32300GBR-5-C SPD Codes for HYS72D[128/64/32]3xxGBR-5-C HYS72D64300GBR-5-C Table 16 HYS72D64320GBR-5-C SPD Contents Product Type & Organization 5 512 MB 512 MB 256 MB x72 x72 x72 2 Ranks 1 Rank 1 Rank Label Code PC3200R-30331 PC3200R-30331 PC3200R-30331 Jedec SPD Revision Rev 1.0 Rev 1.0 Rev 1.0 Byte# Description HEX HEX HEX 0 Programmed SPD Bytes in E2PROM 80 80 80 1 Total number of Bytes in E2PROM 08 08 08 2 Memory Type (DDR = 07h) 07 07 07 3 Number of Row Addresses 0D 0D 0D 4 Number of Column Addresses 0A 0B 0A 5 Number of DIMM Ranks 02 01 01 6 Data Width (LSB) 48 48 48 7 Data Width (MSB) 00 00 00 8 Interface Voltage Levels 04 04 04 9 50 50 50 10 tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns] 50 50 50 11 Error Correction Support 02 02 02 12 Refresh Rate 82 82 82 13 Primary SDRAM Width 08 04 08 14 Error Checking SDRAM Width 08 04 08 15 tCCD [cycles] 01 01 01 16 Burst Length Supported 0E 0E 0E 17 Number of Banks on SDRAM Device 04 04 04 18 CAS Latency 1C 1C 1C 19 CS Latency 01 01 01 20 Write Latency 02 02 02 21 DIMM Attributes 26 26 26 22 Component Attributes C1 C1 C1 23 tCK @ CLmax -0.5 (Byte 18) [ns] tAC SDRAM @ CLmax -0.5 [ns] tCK @ CLmax -1 (Byte 18) [ns] tAC SDRAM @ CLmax -1 [ns] 60 60 60 50 50 50 75 75 75 50 50 50 24 25 26 Data Sheet 29 Rev. 1.2, 2004-10 07302003-2MI6-FOP1 HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM SPD Contents HYS72D64320GBR-5-C HYS72D64300GBR-5-C HYS72D32300GBR-5-C SPD Codes for HYS72D[128/64/32]3xxGBR-5-C (cont'd) Product Type & Organization Table 16 512 MB 512 MB 256 MB x72 x72 x72 2 Ranks 1 Rank 1 Rank Label Code PC3200R-30331 PC3200R-30331 PC3200R-30331 Jedec SPD Revision Rev 1.0 Rev 1.0 Rev 1.0 Byte# Description HEX HEX HEX 27 3C 3C 3C 28 28 28 3C 3C 3C 30 tRPmin [ns] tRRDmin [ns] tRCDmin [ns] tRASmin [ns] 28 28 28 31 Module Density per Rank 40 80 40 32 60 60 60 60 60 60 40 40 40 35 tAS, tCS [ns] tAH, tCH [ns] tDS [ns] tDH [ns] 40 40 40 36 - 40 not used 00 00 00 41 37 37 37 41 41 41 28 28 28 28 28 28 45 tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns] 50 50 50 46 not used 00 00 00 47 DIMM PCB Height 01 01 01 48 - 61 not used 00 00 00 62 SPD Revision 10 10 10 63 Checksum of Byte 0-62 27 5F 26 64 JEDEC ID Code of Infineon (1) C1 C1 C1 28 29 33 34 42 43 44 65 - 71 JEDEC ID Code of Infineon (2 - 8) 00 00 00 72 Module Manufacturer Location xx xx xx 73 Part Number, Char 1 37 37 37 74 Part Number, Char 2 32 32 32 75 Part Number, Char 3 44 44 44 76 Part Number, Char 4 36 36 33 77 Part Number, Char 5 34 34 32 Data Sheet 30 Rev. 1.2, 2004-10 07302003-2MI6-FOP1 HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM SPD Contents HYS72D64320GBR-5-C HYS72D64300GBR-5-C HYS72D32300GBR-5-C SPD Codes for HYS72D[128/64/32]3xxGBR-5-C (cont'd) Product Type & Organization Table 16 512 MB 512 MB 256 MB x72 x72 x72 2 Ranks 1 Rank 1 Rank Label Code PC3200R-30331 PC3200R-30331 PC3200R-30331 Jedec SPD Revision Rev 1.0 Rev 1.0 Rev 1.0 Byte# Description HEX HEX HEX 78 Part Number, Char 6 33 33 33 79 Part Number, Char 7 32 30 30 80 Part Number, Char 8 30 30 30 81 Part Number, Char 9 47 47 47 82 Part Number, Char 10 42 42 42 83 Part Number, Char 11 52 52 52 84 Part Number, Char 12 35 35 35 85 Part Number, Char 13 43 43 43 86 Part Number, Char 14 20 20 20 87 Part Number, Char 15 20 20 20 88 Part Number, Char 16 20 20 20 89 Part Number, Char 17 20 20 20 90 Part Number, Char 18 20 20 20 91 Module Revision Code xx xx xx 92 Test Program Revision Code xx xx xx 93 Module Manufacturing Date Year xx xx xx 94 Module Manufacturing Date Week xx xx xx 95 - 98 Module Serial Number (1 - 4) xx xx xx 99 - 127 not used 00 00 00 Data Sheet 31 Rev. 1.2, 2004-10 07302003-2MI6-FOP1 HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM SPD Contents HYS72D64320HBR-5-C HYS72D64300GHR-5-C HYS72D32300HBR-5-C SPD Codes for HYS72D[128/64/32]3xxHBR-5-C Product Type & Organization Table 17 512 MB 512 MB 256 MB x72 x72 x72 2 Ranks 1 Rank 1 Rank Label Code PC3200R-30331 PC3200R-30331 PC3200R-30331 Jedec SPD Revision Rev 1.0 Rev 1.0 Rev 1.0 Byte# Description HEX HEX HEX 0 Programmed SPD Bytes in E2PROM 80 80 80 1 Total number of Bytes in E2PROM 08 08 08 2 Memory Type (DDR = 07h) 07 07 07 3 Number of Row Addresses 0D 0D 0D 4 Number of Column Addresses 0A 0B 0A 5 Number of DIMM Ranks 02 01 01 6 Data Width (LSB) 48 48 48 7 Data Width (MSB) 00 00 00 8 Interface Voltage Levels 04 04 04 9 50 50 50 10 tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns] 50 50 50 11 Error Correction Support 02 02 02 12 Refresh Rate 82 82 82 13 Primary SDRAM Width 08 04 08 14 Error Checking SDRAM Width 08 04 08 15 tCCD [cycles] 01 01 01 16 Burst Length Supported 0E 0E 0E 17 Number of Banks on SDRAM Device 04 04 04 18 CAS Latency 1C 1C 1C 19 CS Latency 01 01 01 20 Write Latency 02 02 02 21 DIMM Attributes 26 26 26 22 Component Attributes C1 C1 C1 23 tCK @ CLmax -0.5 (Byte 18) [ns] tAC SDRAM @ CLmax -0.5 [ns] tCK @ CLmax -1 (Byte 18) [ns] tAC SDRAM @ CLmax -1 [ns] 60 60 60 50 50 50 75 75 75 50 50 50 24 25 26 Data Sheet 32 Rev. 1.2, 2004-10 07302003-2MI6-FOP1 HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM SPD Contents HYS72D64320HBR-5-C HYS72D64300GHR-5-C HYS72D32300HBR-5-C SPD Codes for HYS72D[128/64/32]3xxHBR-5-C (cont'd) Product Type & Organization Table 17 512 MB 512 MB 256 MB x72 x72 x72 2 Ranks 1 Rank 1 Rank Label Code PC3200R-30331 PC3200R-30331 PC3200R-30331 Jedec SPD Revision Rev 1.0 Rev 1.0 Rev 1.0 Byte# Description HEX HEX HEX 27 3C 3C 3C 28 28 28 3C 3C 3C 30 tRPmin [ns] tRRDmin [ns] tRCDmin [ns] tRASmin [ns] 28 28 28 31 Module Density per Rank 40 80 40 32 60 60 60 60 60 60 40 40 40 35 tAS, tCS [ns] tAH, tCH [ns] tDS [ns] tDH [ns] 40 40 40 36 - 40 not used 00 00 00 41 37 37 37 41 41 41 28 28 28 28 28 28 45 tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns] 50 50 50 46 not used 00 00 00 47 DIMM PCB Height 01 01 01 48 - 61 not used 00 00 00 62 SPD Revision 10 10 10 63 Checksum of Byte 0-62 27 5F 26 64 JEDEC ID Code of Infineon (1) C1 C1 C1 28 29 33 34 42 43 44 65 - 71 JEDEC ID Code of Infineon (2 - 8) 00 00 00 72 Module Manufacturer Location xx xx xx 73 Part Number, Char 1 37 37 37 74 Part Number, Char 2 32 32 32 75 Part Number, Char 3 44 44 44 76 Part Number, Char 4 36 36 33 77 Part Number, Char 5 34 34 32 Data Sheet 33 Rev. 1.2, 2004-10 07302003-2MI6-FOP1 HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM SPD Contents HYS72D64320HBR-5-C HYS72D64300GHR-5-C HYS72D32300HBR-5-C SPD Codes for HYS72D[128/64/32]3xxHBR-5-C (cont'd) Product Type & Organization Table 17 512 MB 512 MB 256 MB x72 x72 x72 2 Ranks 1 Rank 1 Rank Label Code PC3200R-30331 PC3200R-30331 PC3200R-30331 Jedec SPD Revision Rev 1.0 Rev 1.0 Rev 1.0 Byte# Description HEX HEX HEX 78 Part Number, Char 6 33 33 33 79 Part Number, Char 7 32 30 30 80 Part Number, Char 8 30 30 30 81 Part Number, Char 9 48 48 48 82 Part Number, Char 10 42 42 42 83 Part Number, Char 11 52 52 52 84 Part Number, Char 12 35 35 35 85 Part Number, Char 13 43 43 43 86 Part Number, Char 14 20 20 20 87 Part Number, Char 15 20 20 20 88 Part Number, Char 16 20 20 20 89 Part Number, Char 17 20 20 20 90 Part Number, Char 18 20 20 20 91 Module Revision Code xx xx xx 92 Test Program Revision Code xx xx xx 93 Module Manufacturing Date Year xx xx xx 94 Module Manufacturing Date Week xx xx xx 95 - 98 Module Serial Number (1 - 4) xx xx xx 99 - 127 not used 00 00 00 Data Sheet 34 Rev. 1.2, 2004-10 07302003-2MI6-FOP1 HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM SPD Contents HYS72D128320GBR-6-C HYS72D64320GBR-6-C HYS72D64300GBR-6-C HYS72D32300GBR-6-C SPD Codes for HYS72D[128/64/32]3xxGBR-6-C Product Type & Organization Table 18 1 GByte 512 MB 512 MB 256 MB x72 x72 x72 x72 2 Ranks 2 Ranks 1 Rank 1 Rank Label Code PC2700R- 25330 PC2700R- 25330 PC2700R- 25330 PC2700R- 25330 Jedec SPD Revision Rev 0.0 Rev 0.0 Rev 0.0 Rev 0.0 Byte# Description HEX HEX HEX HEX 0 Programmed SPD Bytes in E2PROM 80 80 80 80 1 Total number of Bytes in E2PROM 08 08 08 08 2 Memory Type (DDR = 07h) 07 07 07 07 3 Number of Row Addresses 0D 0D 0D 0D 4 Number of Column Addresses 0B 0A 0B 0A 5 Number of DIMM Ranks 02 02 01 01 6 Data Width (LSB) 48 48 48 48 7 Data Width (MSB) 00 00 00 00 8 Interface Voltage Levels 04 04 04 04 9 60 60 60 60 10 tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns] 70 70 70 70 11 Error Correction Support 02 02 02 02 12 Refresh Rate 82 82 82 82 13 Primary SDRAM Width 04 08 04 08 14 Error Checking SDRAM Width 04 08 04 08 15 tCCD [cycles] 01 01 01 01 16 Burst Length Supported 0E 0E 0E 0E 17 Number of Banks on SDRAM Device 04 04 04 04 18 CAS Latency 0C 0C 0C 0C 19 CS Latency 01 01 01 01 20 Write Latency 02 02 02 02 21 DIMM Attributes 26 26 26 26 22 Component Attributes C1 C1 C1 C1 23 tCK @ CLmax -0.5 (Byte 18) [ns] tAC SDRAM @ CLmax -0.5 [ns] tCK @ CLmax -1 (Byte 18) [ns] 75 75 75 75 70 70 70 70 00 00 00 00 24 25 Data Sheet 35 Rev. 1.2, 2004-10 07302003-2MI6-FOP1 HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM SPD Contents HYS72D64300GBR-6-C HYS72D32300GBR-6-C 1 GByte 512 MB 512 MB 256 MB x72 x72 x72 x72 2 Ranks 2 Ranks 1 Rank 1 Rank Label Code PC2700R- 25330 PC2700R- 25330 PC2700R- 25330 PC2700R- 25330 Jedec SPD Revision Rev 0.0 Rev 0.0 Rev 0.0 Rev 0.0 Byte# Description HEX HEX HEX HEX 26 00 00 00 00 30 tAC SDRAM @ CLmax -1 [ns] tRPmin [ns] tRRDmin [ns] tRCDmin [ns] tRASmin [ns] 31 32 Product Type & Organization HYS72D64320GBR-6-C SPD Codes for HYS72D[128/64/32]3xxGBR-6-C (cont'd) HYS72D128320GBR-6-C Table 18 27 48 48 48 48 30 30 30 30 48 48 48 48 2A 2A 2A 2A Module Density per Rank 80 40 80 40 75 75 75 75 75 75 75 75 45 45 45 45 35 tAS, tCS [ns] tAH, tCH [ns] tDS [ns] tDH [ns] 45 45 45 45 36 - 40 not used 00 00 00 00 41 3C 3C 3C 3C 48 48 48 48 30 30 30 30 28 28 28 28 45 tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns] 50 50 50 50 46 not used 00 00 00 00 47 DIMM PCB Height 00 00 00 00 48 - 61 not used 00 00 00 00 62 SPD Revision 00 00 00 00 63 Checksum of Byte 0-62 49 10 48 0F 64 JEDEC ID Code of Infineon (1) C1 C1 C1 C1 65 - 71 JEDEC ID Code of Infineon (2 - 8) 00 00 00 00 72 Module Manufacturer Location xx xx xx xx 73 Part Number, Char 1 37 37 37 37 74 Part Number, Char 2 32 32 32 32 75 Part Number, Char 3 44 44 44 44 28 29 33 34 42 43 44 Data Sheet 36 Rev. 1.2, 2004-10 07302003-2MI6-FOP1 HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM SPD Contents HYS72D64300GBR-6-C HYS72D32300GBR-6-C 1 GByte 512 MB 512 MB 256 MB x72 x72 x72 x72 2 Ranks 2 Ranks 1 Rank 1 Rank Label Code PC2700R- 25330 PC2700R- 25330 PC2700R- 25330 PC2700R- 25330 Jedec SPD Revision Rev 0.0 Rev 0.0 Rev 0.0 Rev 0.0 Byte# Description HEX HEX HEX HEX 76 Part Number, Char 4 31 36 36 33 77 Part Number, Char 5 32 34 34 32 78 Part Number, Char 6 38 33 33 33 79 Part Number, Char 7 33 32 30 30 80 Part Number, Char 8 32 30 30 30 81 Part Number, Char 9 30 47 47 47 82 Part Number, Char 10 47 42 42 42 83 Part Number, Char 11 42 52 52 52 84 Part Number, Char 12 52 36 36 36 85 Part Number, Char 13 36 43 43 43 86 Part Number, Char 14 43 20 20 20 87 Part Number, Char 15 20 20 20 20 88 Part Number, Char 16 20 20 20 20 89 Part Number, Char 17 20 20 20 20 90 Part Number, Char 18 20 20 20 20 91 Module Revision Code xx xx xx xx 92 Test Program Revision Code xx xx xx xx 93 Module Manufacturing Date Year xx xx xx xx 94 Module Manufacturing Date Week xx xx xx xx 95 - 98 Module Serial Number (1 - 4) xx xx xx xx 99 -127 not used FF FF FF FF Product Type & Organization HYS72D64320GBR-6-C SPD Codes for HYS72D[128/64/32]3xxGBR-6-C (cont'd) HYS72D128320GBR-6-C Table 18 Data Sheet 37 Rev. 1.2, 2004-10 07302003-2MI6-FOP1 HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM SPD Contents HYS72D64300HBR-6-C HYS72D32300HBR-6-C 1 GByte 512 MB 512 MB 256 MB x72 x72 x72 x72 2 Ranks 2 Ranks 1 Rank 1 Rank Label Code PC2700R- 25330 PC2700R- 25330 PC2700R- 25330 PC2700R- 25330 Jedec SPD Revision Rev 0.0 Rev 0.0 Rev 0.0 Rev 0.0 Byte# Description HEX HEX HEX HEX 0 Programmed SPD Bytes in E2PROM 80 80 80 80 1 Total number of Bytes in E2PROM 08 08 08 08 2 Memory Type (DDR = 07h) 07 07 07 07 3 Number of Row Addresses 0D 0D 0D 0D 4 Number of Column Addresses 0B 0A 0B 0A 5 Number of DIMM Ranks 02 02 01 01 6 Data Width (LSB) 48 48 48 48 7 Data Width (MSB) 00 00 00 00 8 Interface Voltage Levels 04 04 04 04 9 60 60 60 60 10 tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns] 70 70 70 70 11 Error Correction Support 02 02 02 02 12 Refresh Rate 82 82 82 82 13 Primary SDRAM Width 04 08 04 08 14 Error Checking SDRAM Width 04 08 04 08 15 tCCD [cycles] 01 01 01 01 16 Burst Length Supported 0E 0E 0E 0E 17 Number of Banks on SDRAM Device 04 04 04 04 18 CAS Latency 0C 0C 0C 0C 19 CS Latency 01 01 01 01 20 Write Latency 02 02 02 02 21 DIMM Attributes 26 26 26 26 22 Component Attributes C1 C1 C1 C1 23 tCK @ CLmax -0.5 (Byte 18) [ns] tAC SDRAM @ CLmax -0.5 [ns] tCK @ CLmax -1 (Byte 18) [ns] 75 75 75 75 70 70 70 70 00 00 00 00 Product Type & Organization HYS72D64320HBR-6-C SPD Codes for HYS72D[128/64/32]3xxHBR-6-C HYS72D128320HBR-6-C Table 19 24 25 Data Sheet 38 Rev. 1.2, 2004-10 07302003-2MI6-FOP1 HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM SPD Contents HYS72D64300HBR-6-C HYS72D32300HBR-6-C 1 GByte 512 MB 512 MB 256 MB x72 x72 x72 x72 2 Ranks 2 Ranks 1 Rank 1 Rank Label Code PC2700R- 25330 PC2700R- 25330 PC2700R- 25330 PC2700R- 25330 Jedec SPD Revision Rev 0.0 Rev 0.0 Rev 0.0 Rev 0.0 Byte# Description HEX HEX HEX HEX 26 00 00 00 00 48 48 48 48 30 30 30 30 48 48 48 48 30 tAC SDRAM @ CLmax -1 [ns] tRPmin [ns] tRRDmin [ns] tRCDmin [ns] tRASmin [ns] 2A 2A 2A 2A 31 Module Density per Rank 80 40 80 40 32 75 75 75 75 75 75 75 75 45 45 45 45 35 tAS, tCS [ns] tAH, tCH [ns] tDS [ns] tDH [ns] 45 45 45 45 36 - 40 not used 00 00 00 00 41 3C 3C 3C 3C 48 48 48 48 30 30 30 30 28 28 28 28 45 tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns] 50 50 50 50 46 not used 00 00 00 00 47 DIMM PCB Height 00 00 00 00 48 - 61 not used 00 00 00 00 62 SPD Revision 00 00 00 00 63 Checksum of Byte 0-62 49 10 48 0F 64 JEDEC ID Code of Infineon (1) C1 C1 C1 C1 65 - 71 JEDEC ID Code of Infineon (2 - 8) 00 00 00 00 Product Type & Organization HYS72D64320HBR-6-C SPD Codes for HYS72D[128/64/32]3xxHBR-6-C (cont'd) HYS72D128320HBR-6-C Table 19 27 28 29 33 34 42 43 44 72 Module Manufacturer Location xx xx xx xx 73 Part Number, Char 1 37 37 37 37 74 Part Number, Char 2 32 32 32 32 75 Part Number, Char 3 44 44 44 44 Data Sheet 39 Rev. 1.2, 2004-10 07302003-2MI6-FOP1 HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM SPD Contents HYS72D64300HBR-6-C HYS72D32300HBR-6-C 1 GByte 512 MB 512 MB 256 MB x72 x72 x72 x72 2 Ranks 2 Ranks 1 Rank 1 Rank Label Code PC2700R- 25330 PC2700R- 25330 PC2700R- 25330 PC2700R- 25330 Jedec SPD Revision Rev 0.0 Rev 0.0 Rev 0.0 Rev 0.0 Byte# Description HEX HEX HEX HEX 76 Part Number, Char 4 31 36 36 33 77 Part Number, Char 5 32 34 34 32 78 Part Number, Char 6 38 33 33 33 79 Part Number, Char 7 33 32 30 30 80 Part Number, Char 8 32 30 30 30 81 Part Number, Char 9 30 48 48 48 82 Part Number, Char 10 48 42 42 42 83 Part Number, Char 11 42 52 52 52 84 Part Number, Char 12 52 36 36 36 85 Part Number, Char 13 36 43 43 43 86 Part Number, Char 14 43 20 20 20 87 Part Number, Char 15 20 20 20 20 88 Part Number, Char 16 20 20 20 20 89 Part Number, Char 17 20 20 20 20 90 Part Number, Char 18 20 20 20 20 91 Module Revision Code xx xx xx xx 92 Test Program Revision Code xx xx xx xx 93 Module Manufacturing Date Year xx xx xx xx 94 Module Manufacturing Date Week xx xx xx xx 95 - 98 Module Serial Number (1 - 4) xx xx xx xx 99 -127 not used FF FF FF FF Product Type & Organization HYS72D64320HBR-6-C SPD Codes for HYS72D[128/64/32]3xxHBR-6-C (cont'd) HYS72D128320HBR-6-C Table 19 Data Sheet 40 Rev. 1.2, 2004-10 07302003-2MI6-FOP1 HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM SPD Contents HYS72D32300GBR-7-C 1 GByte 512 MB 256 MB x72 x72 x72 2 Ranks 1 Rank 1 Rank Label Code PC2100R-20330 PC2100R-20330 PC2100R-20330 Jedec SPD Revision Rev 0.0 Rev 0.0 Rev 0.0 Byte# Description HEX HEX HEX 0 Programmed SPD Bytes in E2PROM 80 80 80 Product Type & Organization HYS72D64300GBR-7-C SPD Codes for HYS72D[128/64/32]3xxGBR-7-C HYS72D128320GBR-7-C Table 20 1 Total number of Bytes in E2PROM 08 08 08 2 Memory Type (DDR = 07h) 07 07 07 3 Number of Row Addresses 0D 0D 0D 4 Number of Column Addresses 0B 0B 0A 5 Number of DIMM Ranks 02 01 01 6 Data Width (LSB) 48 48 48 7 Data Width (MSB) 00 00 00 8 Interface Voltage Levels 04 04 04 9 tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns] 70 70 70 10 75 75 75 11 Error Correction Support 02 02 02 12 Refresh Rate 82 82 82 13 Primary SDRAM Width 04 04 08 14 Error Checking SDRAM Width 04 04 08 15 tCCD [cycles] 01 01 01 16 Burst Length Supported 0E 0E 0E 17 Number of Banks on SDRAM Device 04 04 04 18 CAS Latency 0C 0C 0C 19 CS Latency 01 01 01 20 Write Latency 02 02 02 21 DIMM Attributes 26 26 26 22 Component Attributes C1 C1 C1 23 tCK @ CLmax -0.5 (Byte 18) [ns] tAC SDRAM @ CLmax -0.5 [ns] tCK @ CLmax -1 (Byte 18) [ns] tAC SDRAM @ CLmax -1 [ns] 75 75 75 75 75 75 24 25 26 Data Sheet 00 00 00 00 00 00 41 Rev. 1.2, 2004-10 07302003-2MI6-FOP1 HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM SPD Contents HYS72D32300GBR-7-C 1 GByte 512 MB 256 MB x72 x72 x72 2 Ranks 1 Rank 1 Rank Label Code PC2100R-20330 PC2100R-20330 PC2100R-20330 Jedec SPD Revision Rev 0.0 Rev 0.0 Rev 0.0 Byte# Description HEX HEX HEX 27 50 50 50 30 tRPmin [ns] tRRDmin [ns] tRCDmin [ns] tRASmin [ns] 31 32 Product Type & Organization HYS72D64300GBR-7-C SPD Codes for HYS72D[128/64/32]3xxGBR-7-C (cont'd) HYS72D128320GBR-7-C Table 20 28 3C 3C 3C 50 50 50 2D 2D 2D Module Density per Rank 80 80 40 90 90 90 90 90 90 50 50 50 35 tAS, tCS [ns] tAH, tCH [ns] tDS [ns] tDH [ns] 50 50 50 36 - 40 not used 00 00 00 41 41 41 41 4B 4B 4B 30 30 30 32 32 32 45 tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns] 75 75 75 46 not used 00 00 00 47 DIMM PCB Height 00 00 00 48 -61 not used 00 00 00 62 SPD Revision 00 00 00 63 Checksum of Byte 0-62 05 04 CB 64 JEDEC ID Code of Infineon (1) C1 C1 C1 65 - 71 JEDEC ID Code of Infineon (2 - 8) 00 00 00 72 Module Manufacturer Location xx xx xx 73 Part Number, Char 1 37 37 37 74 Part Number, Char 2 32 32 32 75 Part Number, Char 3 44 44 44 76 Part Number, Char 4 31 36 33 77 Part Number, Char 5 32 34 32 29 33 34 42 43 44 Data Sheet 42 Rev. 1.2, 2004-10 07302003-2MI6-FOP1 HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM SPD Contents HYS72D32300GBR-7-C 1 GByte 512 MB 256 MB x72 x72 x72 2 Ranks 1 Rank 1 Rank Label Code PC2100R-20330 PC2100R-20330 PC2100R-20330 Jedec SPD Revision Rev 0.0 Rev 0.0 Rev 0.0 Byte# Description HEX HEX HEX 78 Part Number, Char 6 38 33 33 79 Part Number, Char 7 33 30 30 80 Part Number, Char 8 32 30 30 81 Part Number, Char 9 30 47 47 82 Part Number, Char 10 47 42 42 83 Part Number, Char 11 42 52 52 84 Part Number, Char 12 52 37 37 85 Part Number, Char 13 37 43 43 86 Part Number, Char 14 43 20 20 87 Part Number, Char 15 20 20 20 88 Part Number, Char 16 20 20 20 89 Part Number, Char 17 20 20 20 90 Part Number, Char 18 20 20 20 91 Module Revision Code 0x 0x 0x 92 Test Program Revision Code xx xx xx 93 Module Manufacturing Date Year xx xx xx 94 Module Manufacturing Date Week xx xx xx Product Type & Organization HYS72D64300GBR-7-C SPD Codes for HYS72D[128/64/32]3xxGBR-7-C (cont'd) HYS72D128320GBR-7-C Table 20 95 - 98 Module Serial Number (1 - 4) xx xx xx 99 - 127 not used 00 00 00 Data Sheet 43 Rev. 1.2, 2004-10 07302003-2MI6-FOP1 HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM SPD Contents HYS72D32300HBR-7-C 1 GByte 512 MB 256 MB x72 x72 x72 2 Ranks 1 Rank 1 Rank Label Code PC2100R-20330 PC2100R-20330 PC2100R-20330 Jedec SPD Revision Rev 0.0 Rev 0.0 Rev 0.0 Byte# Description HEX HEX HEX 0 Programmed SPD Bytes in E2PROM 80 80 80 Product Type & Organization HYS72D64300HBR-7-C SPD Codes for HYS72D[128/64/32]3xxHBR-7-C HYS72D128320HBR-7-C Table 21 1 Total number of Bytes in E2PROM 08 08 08 2 Memory Type (DDR = 07h) 07 07 07 3 Number of Row Addresses 0D 0D 0D 4 Number of Column Addresses 0B 0B 0A 5 Number of DIMM Ranks 02 01 01 6 Data Width (LSB) 48 48 48 7 Data Width (MSB) 00 00 00 8 Interface Voltage Levels 04 04 04 9 tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns] 70 70 70 10 75 75 75 11 Error Correction Support 02 02 02 12 Refresh Rate 82 82 82 13 Primary SDRAM Width 04 04 08 14 Error Checking SDRAM Width 04 04 08 15 tCCD [cycles] 01 01 01 16 Burst Length Supported 0E 0E 0E 17 Number of Banks on SDRAM Device 04 04 04 18 CAS Latency 0C 0C 0C 19 CS Latency 01 01 01 20 Write Latency 02 02 02 21 DIMM Attributes 26 26 26 22 Component Attributes C1 C1 C1 23 tCK @ CLmax -0.5 (Byte 18) [ns] tAC SDRAM @ CLmax -0.5 [ns] tCK @ CLmax -1 (Byte 18) [ns] tAC SDRAM @ CLmax -1 [ns] 75 75 75 75 75 75 24 25 26 Data Sheet 00 00 00 00 00 00 44 Rev. 1.2, 2004-10 07302003-2MI6-FOP1 HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM SPD Contents HYS72D32300HBR-7-C 1 GByte 512 MB 256 MB x72 x72 x72 2 Ranks 1 Rank 1 Rank Label Code PC2100R-20330 PC2100R-20330 PC2100R-20330 Jedec SPD Revision Rev 0.0 Rev 0.0 Rev 0.0 Byte# Description HEX HEX HEX 27 50 50 50 3C 3C 3C 50 50 50 30 tRPmin [ns] tRRDmin [ns] tRCDmin [ns] tRASmin [ns] 2D 2D 2D 31 Module Density per Rank 80 80 40 32 90 90 90 90 90 90 50 50 50 35 tAS, tCS [ns] tAH, tCH [ns] tDS [ns] tDH [ns] 50 50 50 36 - 40 not used 00 00 00 41 41 41 41 4B 4B 4B 30 30 30 32 32 32 45 tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns] 75 75 75 46 not used 00 00 00 47 DIMM PCB Height 00 00 00 48 -61 not used 00 00 00 62 SPD Revision 00 00 00 63 Checksum of Byte 0-62 05 04 CB 64 JEDEC ID Code of Infineon (1) C1 C1 C1 65 - 71 JEDEC ID Code of Infineon (2 - 8) 00 00 00 72 Module Manufacturer Location xx xx xx 73 Part Number, Char 1 37 37 37 74 Part Number, Char 2 32 32 32 75 Part Number, Char 3 44 44 44 76 Part Number, Char 4 31 36 33 77 Part Number, Char 5 32 34 32 Product Type & Organization HYS72D64300HBR-7-C SPD Codes for HYS72D[128/64/32]3xxHBR-7-C (cont'd) HYS72D128320HBR-7-C Table 21 28 29 33 34 42 43 44 Data Sheet 45 Rev. 1.2, 2004-10 07302003-2MI6-FOP1 HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM SPD Contents HYS72D32300HBR-7-C 1 GByte 512 MB 256 MB x72 x72 x72 2 Ranks 1 Rank 1 Rank Label Code PC2100R-20330 PC2100R-20330 PC2100R-20330 Jedec SPD Revision Rev 0.0 Rev 0.0 Rev 0.0 Product Type & Organization HYS72D64300HBR-7-C SPD Codes for HYS72D[128/64/32]3xxHBR-7-C (cont'd) HYS72D128320HBR-7-C Table 21 Byte# Description HEX HEX HEX 78 Part Number, Char 6 38 33 33 79 Part Number, Char 7 33 30 30 80 Part Number, Char 8 32 30 30 81 Part Number, Char 9 30 48 48 82 Part Number, Char 10 48 42 42 83 Part Number, Char 11 42 52 52 84 Part Number, Char 12 52 37 37 85 Part Number, Char 13 37 43 43 86 Part Number, Char 14 43 20 20 87 Part Number, Char 15 20 20 20 88 Part Number, Char 16 20 20 20 89 Part Number, Char 17 20 20 20 90 Part Number, Char 18 20 20 20 91 Module Revision Code 0x 0x 0x 92 Test Program Revision Code xx xx xx 93 Module Manufacturing Date Year xx xx xx 94 Module Manufacturing Date Week xx xx xx 95 - 98 Module Serial Number (1 - 4) xx xx xx 99 - 127 not used 00 00 00 Data Sheet 46 Rev. 1.2, 2004-10 07302003-2MI6-FOP1 HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM Package Outlines Package Outlines 6.1 Raw Card A 0.1 A B C 6 133.35 0.15 A B C 128.95 2.64 MAX. 28.58 0.13 4 0.1 A 1 2.5 0.1 o0.1 A B C 92 6.62 B 2.175 0.4 6.35 64.77 C 1.27 0.1 49.53 1.8 0.1 0.1 A B C 184 17.8 93 10 3.8 0.13 95 x 1.27 = 120.65 3 MIN. 0.2 2.5 0.2 Detail of contacts 1.27 1 0.05 0.1 A B C Burr max. 0.4 allowed Figure 6 Data Sheet L-DIMM-184-021 Package Outlines - Raw Card A HYS72D32300[G/H]BR-[5/6/7]-C (1 Rank x 8) 47 Rev. 1.2, 2004-10 HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM Package Outlines Raw Card C 0.1 A B C 6.2 133.35 0.15 A B C 128.95 4 MAX. 28.58 0.13 4 0.1 A 1 2.5 0.1 o0.1 A B C 92 6.62 B C 2.175 0.4 6.35 64.77 1.27 0.1 49.53 1.8 0.1 0.1 A B C 184 17.8 93 10 3.8 0.13 95 x 1.27 = 120.65 3 MIN. 0.2 2.5 0.2 Detail of contacts 1.27 1 0.05 0.1 A B C Burr max. 0.4 allowed Figure 7 Data Sheet L-DIMM-184-22-2 Package Outlines - Raw Card C HYS72D64300[G/H]BR-[5/6/7]-C (1 Rank x 4) 48 Rev. 1.2, 2004-10 HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM Package Outlines Raw Card B 0.1 A B C 6.3 133.35 0.15 A B C 128.95 4 MAX. 28.58 0.13 4 0.1 A 1 2.5 0.1 o0.1 A B C 92 6.62 B C 2.175 0.4 6.35 64.77 1.27 0.1 49.53 1.8 0.1 0.1 A B C 184 17.8 93 10 3.8 0.13 95 x 1.27 = 120.65 3 MIN. 0.2 2.5 0.2 Detail of contacts 1.27 1 0.05 0.1 A B C Burr max. 0.4 allowed Figure 8 Data Sheet L-DIMM-184-23 Package Outlines - Raw Card B HYS72D64320GBR-[5/6]-C (2 Ranks x8) 49 Rev. 1.2, 2004-10 HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM Package Outlines 6.4 Raw Card D 0.1 A B C 133.35 0.15 A B C 128.95 4 MAX. 30.48 0.13 4 0.1 A 1 2.5 0.1 o0.1 A B C 92 6.62 B C 2.175 0.4 6.35 64.77 1.27 0.1 49.53 0.1 A B C 93 184 17.8 1.8 0.1 10 3.8 0.13 95 x 1.27 = 120.65 3 MIN. 0.2 2.5 0.2 Detail of contacts 1.27 1 0.05 0.1 A B C L-DIMM-184-24-3 Burr max. 0.4 allowed Figure 9 Data Sheet Package Outlines - Raw Card D HYS72D128320[G/H]BR-[6/7]-C (2 Ranks x4) 50 Rev. 1.2, 2004-10 HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM Application Note 7 Application Note Power Up and Power Management on DDR Registered DIMMs (according to JEDEC ballot JC-42.5 Item 1173) 184-pin Double Data Rate (DDR) Registered DIMMs include two new features to facilitate controlled power-up and to minimize power consumption during low power mode. One feature is externally controlled via a systemgenerated RESET signal; the second is based on module detection of the input clocks. These enhancements permit the modules to power up with SDRAM outputs in a High-Z state (eliminating risk of high current dissipations and/or dotted I/Os), and result in the powering-down of module support devices (registers and Phase-Locked Loop) when the memory is in Self-Refresh mode. The new RESET pin controls power dissipation on the module's registers and ensures that CKE and other SDRAM inputs are maintained at a valid `low' level during power-up and self refresh. When RESET is at a low level, all the register outputs are forced to a low level, and all differential register input receivers are powered down, resulting in very low register power consumption. The RESET pin, located on DIMM tab #10, is driven from the system as an asynchronous signal according to the attached details. Using this function also permits the system and DIMM clocks to be stopped during memory Self Refresh operation, while ensuring that the SDRAMs stay in Self Refresh mode. Table 22 RESET Truth Table Register Inputs Register Outputs RESET CK CK Data in (D) Data out (Q) H Rising Falling H H H Rising Falling L L H L or H L or H X Qo H High Z High Z X Illegal input conditions L X or Hi-Z X or Hi-Z X or Hi-Z L X: Don't care, Hi-Z: High Impedance, Qo: Data latched at the previous of CK rising and CK falling As described in the table above, a low on the RESET input ensures that the Clock Enable (CKE) signal(s) are maintained low at the SDRAM pins (CKE being one of the 'Q' signals at the register output). Holding CKE low maintains a high impedance state on the SDRAM DQ, DQS and DM outputs -- where they will remain until activated by a valid `read' cycle. CKE low also maintains SDRAMs in Self Refresh mode when applicable. The DDR PLL devices automatically detect clock activity above 20MHz. When an input clock frequency of 20MHz or greater is detected, the PLL begins operation and initiates clock frequency lock (the minimum operating frequency at which all specifications will be met is 95MHz). If the clock input frequency drops below 20MHz (actual detect frequency will vary by vendor), the PLL VCO (Voltage Controlled Oscillator) is stopped, outputs are made High-Z, and the differential inputs are powered down -- resulting in a total PLL current consumption of less than 1mA. Use of this low power PLL function makes the use of the PLL RESET (or G pin) unnecessary, and it is tied inactive on the DIMM. This application note describes the required and optional system sequences associated with the DDR Registered DIMM 'RESET' function. It is important to note that all references to CKE refer to both CKE0 and CKE1 for a 2bank DIMM. Because RESET applies to all DIMM register devices, it is therefore not possible to uniquely control CKE to one physical DIMM bank through the use of the RESET pin. Data Sheet 51 Rev. 1.2, 2004-10 HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM Application Note Power-Up Sequence with RESET -- Required 1. The system sets RESET at a valid low level. This is the preferred default state during power-up. This input condition forces all register outputs to a low state independent of the condition on the register inputs (data and clock), ensuring that CKE is at a stable low-level at the DDR SDRAMs. 2. The power supplies should be initialized according to the JEDEC-approved initialization sequence for DDR SDRAMs. 3. Stabilization of Clocks to the SDRAM The system must drive clocks to the application frequency (PLL operation is not assured until the input clock reaches 20 MHz). Stability of clocks at the SDRAMs will be affected by all applicable system clock devices, and time must be allotted to permit all clock devices to settle. Once a stable clock is received at the DIMM PLL, the required PLL stabilization time (assuming power to the DIMM is stable) is 100 microseconds. When a stable clock is present at the SDRAM input (driven from the PLL), the DDR SDRAM requires 200 sec prior to SDRAM operation. 4. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM connector). CKE must be maintained low and all other inputs should be driven to a known state. In general these commands can be determined by the system designer. One option is to apply an SDRAM `NOP' command (with CKE low), as this is the first command defined by the JEDEC initialization sequence (ideally this would be a `NOP Deselect' command). A second option is to apply low levels on all of the register inputs to be consistent with the state of the register outputs. 5. The system switches RESET to a logic `high' level. The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous, setting the RESET timing in relation to a specific clock edge is not required (during this period, register inputs must remain stable). 6. The system must maintain stable register inputs until normal register operation is attained. The registers have an activation time that allows their clock receivers, data input receivers, and output drivers sufficient time to be turned on and become stable. During this time the system must maintain the valid logic levels described in step 5. It is also a functional requirement that the registers maintain a low state at the CKE outputs to guarantee that the DDR SDRAMs continue to receive a low level on CKE. Register activation time (t (ACT) ), from asynchronous switching of RESET from low to high until the registers are stable and ready to accept an input signal, is specified in the register and DIMM do-umentation. 7. The system can begin the JEDEC-defined DDR SDRAM power-up sequence (according to the JEDECpproved initialization sequence). Self Refresh Entry (RESET low, clocks powered off) -- Optional Self Refresh can be used to retain data in DDR SDRAM DIMMs even if the rest of the system is powered down and the clocks are off. This mode allows the DDR SDRAMs on the DIMM to retain data without external clocking. Self Refresh mode is an ideal time to utilize the RESET pin, as this can reduce register power consumption (RESET low deactivates register CK and CK, data input receivers, and data output drivers). 1. 1. The system applies Self Refresh entry command. (CKELow, CSLow, RAS Low, CAS Low, WE High) Note: Note: The commands reach the DDR SDRAM one clock later due to the additional register pipelining on a Registered DIMM. After this command is issued to the SDRAM, all of the address and control and clock input conditions to the SDRAM are Don't Cares-- with the exception of CKE. 2. The system sets RESET at a valid low level. This input condition forces all register outputs to a low state, independent of the condition on the registerm inputs (data and clock), and ensures that CKE, and all other control and address signals, are a stable low-level at the DDR SDRAMs. Since the RESET signal is asynchronous, setting the RESET timing in relation to a specific clock edge is not required. 3. The system turns off clock inputs to the DIMM. (Optional) a. In order to reduce DIMM PLL current, the clock inputs to the DIMM are turned off, resulting in High-Z clock Data Sheet 52 Rev. 1.2, 2004-10 HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM Application Note inputs to both the SDRAMs and the registers. This must be done after the RESET deactivate time of the register (t (INACT). The deactivate time defines the time in which the clocks and the control and address signals must maintain valid levels after RESET low has been applied and is specified in the register and DIMM documentation. b.The system may release DIMM address and control inputs to High-Z. This can be done after the RESET deactivate time of the register. The deactivate time defines the time in which the clocks and the control and the address signals must maintain valid levels after RESET low has been applied. It is highly recommended that CKE continue to remain low during this operation. 4. The DIMM is in lowest power Self Refresh mode. Self Refresh Exit (RESET low, clocks powered off) -- Optional 1. Stabilization of Clocks to the SDRAM. The system must drive clocks to the application frequency (PLL operation is not assured until the input clock reaches ~20MHz). Stability of clocks at the SDRAMs will be affected by all applicable system clock devices, and time must be allotted to permit all clock devices to settle. Once a stable clock is received at the DIMM PLL, the required PLL stabilization time (assuming power to the DIMM is stable) is 100 microseconds. 2. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM connector). CKE must be maintained low and all other inputs should be driven to a known state. In general these commands can be determined by the system designer. One option is to apply an SDRAM `NOP' command (with CKE low), as this is the first command defined by the JEDEC Self Refresh Exit sequence (ideally this would be a `NOP Deselect' command). A second option is to apply low levels on all of the register inputs, to be consistent with the state of the register outputs. 3. The system switches RESET to a logic `high' level. The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous, RESET timing relationship to a specific clock edge is not required (during this period, register inputs must remain stable). 4. The system must maintain stable register inputs until normal register operation is attained. The registers have an activation time that allows the clock receivers, input receivers, and output drivers sufficient time to be turned on and become stable. During this time the system must maintain the valid logic levels described in Step 2. It is also a functional requirement that the registers maintain a low state at the CKE outputs to guarantee that the DDR SDRAMs continue to receive a low level on CKE. Register activation time (t (ACT) ), from asynchronous switching of RESET from low to high until the registers are stable and ready to accept an input signal, is specified in the register and DIMM do-umentation. 5. System can begin the JEDEC-defined DDR SDRAM Self Refresh Exit Procedure. Self Refresh Entry (RESET low, clocks running) -- Optional Although keeping the clocks running increases power consumption from the on-DIMM PLL during self refresh, this is an alternate operating mode for these DIMMs. 1. 1. System enters Self Refresh entry command. (CKE Low, CS Low, RAS Low, CAS Low, WE High) Note: Note: The commands reach the DDR SDRAM one clock later due to the additional register pipelining on a Registered DIMM. After this command is issued to the SDRAM, all of the address and control and clock input conditions to the SDRAM are Don't Cares -- with the exception of CKE. 2. The system sets RESET at a valid low level. This input condition forces all register outputs to a low state, independent of the condition on the data and clock register inputs, and ensures that CKE is a stable low-level at the DDR SDRAMs. 3. The system may release DIMM address and control inputs to High-Z. This can be done after the RESET deactivate time of the register (t (INACT) ). The deactivate time describes the time in which the clocks and the control and the address signals must maintain valid levels after RESET low has been applied. It is highly recommended that CKE continue to remain low during the operation. 4. The DIMM is in a low power, Self Refresh mode. Data Sheet 53 Rev. 1.2, 2004-10 HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM Application Note Self Refresh Exit (RESET low, clocks running) -- Optional 1. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM connector). CKE must be maintained low and all other inputs should be driven to a known state. In general these commands can be determined by the system designer. One option is to apply an SDRAM `NOP' command (with CKE low), as this is the first command defined by the Self Refresh Exit sequence (ideally this would be a `NOP Deselect' command). A second option is to apply low levels on all of the register inputs to be consistent with the state of the register outputs. 2. The system switches RESET to a logic 'high' level. The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous, it does not need to be tied to a particular clock edge (during this period, register inputs must continue to remain stable). 3. The system must maintain stable register inputs until normal register operation is attained. The registers have an activation time that allows the clock receivers, input receivers, and output drivers sufficient time to be turned on and become stable. During this time the system must maintain the valid logic levels described in Step 1. It is also a functional requirement that the registers maintain a low state at the CKE outputs in order to guarantee that the DDR SDRAMs continue to receive a low level on CKE. This activation time, from asynchronous switching of RESET from low to high, until the registers are stable and ready to accept an input signal, is t (ACT ) as specified in the register and DIMM documentation. 4. The system can begin JEDEC defined DDR SDRAM Self Refresh Exit Procedure. Self Refresh Entry/Exit (RESET high, clocks running) -- Optional As this sequence does not involve the use of the RESET function, the JEDEC standard SDRAM specification explains in detail the method for entering and exiting Self Refresh for this case. Self Refresh Entry (RESET high, clocks powered off) -- Not Permissible In order to maintain a valid low level on the register output, it is required that either the clocks be running and the system drive a low level on CKE, or the clocks are powered off and RESET is asserted low according to the sequence defined in this application note. In the case where RESET remains high and the clocks are powered off, the PLL drives a High-Z clock input into the register clock input. Without the low level on RESET an unknown DIMM state will result. Data Sheet 54 Rev. 1.2, 2004-10 www.infineon.com Published by Infineon Technologies AG