Never stop thinking.
HYS72D32300[G/H]BR–[5/6/7]–C
HYS72D64300[G/H]BR–[5/6/7]–C
HYS72D64320[G/H]BR–[5/6]–C
HYS72D128320[G/H]BR–[6/7]–C
184-Pin Registered Double Data Rate SDRAM
Module
Reg DIMM
DDR SDRAM
Data Sheet, Rev. 1.2, Oct. 2004
Memory Products
Edition 2004-10
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2004.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Never stop thinking.
HYS72D32300[G/H]BR–[5/6/7]–C
HYS72D64300[G/H]BR–[5/6/7]–C
HYS72D64320[G/H]BR–[5/6]–C
HYS72D128320[G/H]BR–[6/7]–C
184-Pin Registered Double Data Rate SDRAM
Module
Reg DIMM
DDR SDRAM
Data Sheet, Rev. 1.2, Oct. 2004
Memory Products
Template: mp_a4_v2.2_2003-10-07.fm
HYS72D32300[G/H]BR–[5/6/7]–C, HYS72D64300[G/H]BR–[5/6/7]–C, HYS72D64320[G/H]BR–[5/6]–C,
HYS72D128320[G/H]BR–[6/7]–C
Revision History: Rev. 1.2 2004-10
Previous Version: Rev. 1.1 2004-03
Page Subjects (major changes since last revision)
7added RoHS Product Types
21,22,23 updated Idd Values
32,38,44 updated SPD Codes
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
techdoc.mp@infineon.com
Data Sheet 5 Rev. 1.2, 2004-10
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4 Current Specification and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5 SPD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.1 Raw Card A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.2 Raw Card C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.3 Raw Card B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.4 Raw Card D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
7 Application Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table of Contents
184-Pin Registered Double Data Rate SDRAM Module
Reg DIMM
HYS72D32300[G/H]BR–[5/6/7]–C
HYS72D64300[G/H]BR–[5/6/7]–C
HYS72D64320[G/H]BR–[5/6]–C
HYS72D128320[G/H]BR–[6/7]–C
Data Sheet 6 Rev. 1.2, 2004-10
07302003-2MI6-FOP1
1Overview
1.1 Features
• 184-Pin Registered 8-Byte Dual-In-Line
DDR SDRAM Module for “1U” PC, Workstation and Server main memory applications
• One rank 32M ×72 and 64M ×72 and two ranks 64M ×72 and 128M ×72 organization
• JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM) with a single + 2.5 V (± 0.2 V) power
supply and + 2.6 V (±0.1 V) power supply for DDR400
• Built with 256-Mbit DDR SDRAMs in P-TFBGA-60-1 packages
• Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave)
• Auto Refresh (CBR) and Self Refresh
• All inputs and outputs SSTL_2 compatible
• Re-drive for all input signals using register and PLL devices.
• Serial Presence Detect with E2PROM
• Low Profile Modules form factor:
133.35 mm × 28.58 mm × 4.00 mm / 2.64 mm and for 1GB 133.35 mm × 30.48 mm (1.2”)× 4.00 mm
• JEDEC standard reference layout for one rank 256MB, 512MB and two ranks 512MB, 1GB:
PC2700 and PC3200 Registered DIMM Raw Cards A,B,C,D
• Gold plated contacts
1.2 Description
The HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C and HYS72D64320GBR–5–C are low profile versions of the
standard Registered DIMM modules suitable for 1U Server Applications. The Low Profile DIMM versions are
available as 32M ×72 (256 MB), 64M ×72 (512 MB) and 128M ×72 (1 GB)
The memory array is designed with Double Data Rate Synchronous DRAMs for ECC applications. All control and
address signals are re-driven on the DIMM using register devices and a PLL for the clock distribution. This reduces
capacitive loading to the system bus, but adds one cycle to the SDRAM timing. A variety of decoupling capacitors
are mounted on the PC board. The DIMMs feature serial presence detect based on a serial E2PROM device using
the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are
available to the customer.
Table 1 Performance
Part Number Speed Code -5 –6-7 Unit
Speed Grade Component DDR400B DDR333B DDR266A —
Module PC3200-3033 PC2700–2533 PC2100-2033 —
max. Clock
Frequency
@CL3 fCK3 200 166 – MHz
@CL2.5 fCK2.5 166 166 143 MHz
@CL2 fCK2 133 133 133 MHz
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Overview
Data Sheet 7 Rev. 1.2, 2004-10
07302003-2MI6-FOP1
Table 2 Ordering Information for Lead-Containing Products
Product Type Compliance Code Description SDRAM
Technology
PC3200 (CL = 3.0)
HYS72D32300GBR–5–C PC3200R–30330–A0 1 Rank 256 MB Registered DIMM ECC 256 Mbit (×8)
HYS72D64300GBR–5–C PC3200R–30330–C0 1 Rank 512 MB Registered DIMM ECC 256 Mbit (×4)
HYS72D64320GBR–5–C PC3200R–30330–B0 2 Ranks 512 MB Registered DIMM ECC 256 Mbit (×8)
PC2700 (CL = 2.5)
HYS72D32300GBR–6–C PC2700R–25330–A0 1 Rank 256 MB Registered DIMM ECC 256 Mbit (×8)
HYS72D64300GBR–6–C PC2700R–25330–C0 1 Rank 512 MB Registered DIMM ECC 256 Mbit (×4)
HYS72D64320GBR–6–C PC2700R–25330–B0 2 Ranks 512 MB Registered DIMM ECC 256 Mbit (×8)
HYS72D128320GBR–6–C PC2700R–25330–D0 2 Ranks 1 GB Registered DIMM ECC 256 Mbit (×4)
PC2100 (CL = 2.0)
HYS72D32300GBR–7–C PC2100R–20330–A0 1 Rank 256 MB Registered DIMM ECC 256 Mbit (×8)
HYS72D64300GBR–7–C PC2100R–20330–C0 1 Rank 512 MB Registered DIMM ECC 256 Mbit (×4)
HYS72D128320GBR–7–C PC2100R–20330–D0 2 Ranks 1 GB Registered DIMM ECC 256 Mbit (×4)
Table 3 Ordering Information for Lead-Free (RoHS1) Compliant) Products
Product Type 2) Compliance Code3) Description SDRAM
Technology
PC3200 (CL = 3.0)
HYS72D32300HBR–5–C PC3200R–30330–A0 1 Rank 256 MB Registered DIMM ECC 256 Mbit (×8)
HYS72D64300HBR–5–C PC3200R–30330–C0 1 Rank 512 MB Registered DIMM ECC 256 Mbit (×4)
HYS72D64320HBR–5–C PC3200R–30330–B0 2 Ranks 512 MB Registered DIMM ECC 256 Mbit (×8)
PC2700 (CL = 2.5)
HYS72D32300HBR–6–C PC2700R–25330–A0 1 Rank 256 MB Registered DIMM ECC 256 Mbit (×8)
HYS72D64300HBR–6–C PC2700R–25330–C0 1 Rank 512 MB Registered DIMM ECC 256 Mbit (×4)
HYS72D64320HBR–6–C PC2700R–25330–B0 2 Ranks 512 MB Registered DIMM ECC 256 Mbit (×8)
HYS72D128320HBR–6–C PC2700R–25330–D0 2 Ranks 1 GB Registered DIMM ECC 256 Mbit (×4)
PC2100 (CL = 2.0)
HYS72D32300HBR–7–C PC2100R–20330–A0 1 Rank 256 MB Registered DIMM ECC 256 Mbit (×8)
HYS72D64300HBR–7–C PC2100R–20330–C0 1 Rank 512 MB Registered DIMM ECC 256 Mbit (×4)
HYS72D128320HBR–7–C PC2100R–20330–D0 2 Ranks 1 GB Registered DIMM ECC 256 Mbit (×4)
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Overview
Data Sheet 8 Rev. 1.2, 2004-10
07302003-2MI6-FOP1
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic
equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January
2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and
polybrominated biphenyl ethers.
2) All product types end with a place code designating the silicon-die revision. Reference information available on request.
Example: HYS72D128300GBR-5-B, indicating Rev.B die are used for SDRAM components.
3) The Compliance Code is printed on the module labels and describes the speed sort (for example “PC2100R”), the latencies
(for example “20330” means CAS latency of 2.0 clocks, Row-Column-Delay (RCD) latency of 3 clocks and Row Precharge
latency of 3 clocks), JEDEC SPD code definition version 0, and the Raw Card used for this module.
Data Sheet 9 Rev. 1.2, 2004-10
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Pin Configuration
2 Pin Configuration
The pin configuration of the Registered DDR SDRAM
DIMM is listed by function in Table 4 (184 pins). The
abbreviations used in columns Pin and Buffer Type are
explained in Table 5 and Table 6 respectively. The pin
numbering is depicted in Figure 1.
Table 4 Pin Configuration of RDIMM
Pin# Name Pin
Type
Buffer
Type
Function
Clock Signals
137 CK0 I SSTL Clock Signal
138 CK0 ISSTLComplement Clock
21 CKE0 I SSTL Clock Enable Rank 0
111 CKE1 I SSTL Clock Enable Rank 1
Note: 2-rank module
NC NC SSTL Note: 1-rank module
Control Signals
157 S0 ISSTLChip Select of Rank 0
158 S1 ISSTLChip Select of Rank 1
Note: 2-ranks module
NC NC – Note: 1-rank module
154 RAS ISSTLRow Address Strobe
65 CAS ISSTLColumn Address
Strobe
63 WE ISSTLWrite Enable
10 RESET ILV-
CMOS
Register Reset
Forces registered
inputs low
Note: For detailed
description of the
Power Up and
Power
Management see
the Application
Note at the end of
data sheet
Address Signals
59 BA0 I SSTL Bank Address Bus
1:0
52 BA1 I SSTL
48 A0 I SSTL Address Bus 11:0
43 A1 I SSTL
41 A2 I SSTL
130 A3 I SSTL
37 A4 I SSTL
32 A5 I SSTL
125 A6 I SSTL Address Bus 11:0
29 A7 I SSTL
122 A8 I SSTL
27 A9 I SSTL
141 A10 I SSTL
AP I SSTL
118 A11 I SSTL
115 A12 I SSTL Address Signal 12
Note: Module based on
256 Mbit or larger
dies
NC NC – Note: 128 Mbit based
module
167 A13 I SSTL Address Signal 13
Note: 1 Gbit based
module
NC NC – Note: Module based on
512 Mbit or
smaller dies
Data Signals
2 DQ0 I/O SSTL Data Bus 63:0
4 DQ1 I/O SSTL
6 DQ2 I/O SSTL
8 DQ3 I/O SSTL
94 DQ4 I/O SSTL
95 DQ5 I/O SSTL
98 DQ6 I/O SSTL
99 DQ7 I/O SSTL
12 DQ8 I/O SSTL
13 DQ9 I/O SSTL
19 DQ10 I/O SSTL
20 DQ11 I/O SSTL
105 DQ12 I/O SSTL
106 DQ13 I/O SSTL
109 DQ14 I/O SSTL
110 DQ15 I/O SSTL
23 DQ16 I/O SSTL
24 DQ17 I/O SSTL
28 DQ18 I/O SSTL
31 DQ19 I/O SSTL
Table 4 Pin Configuration of RDIMM (cont’d)
Pin# Name Pin
Type
Buffer
Type
Function
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Pin Configuration
Data Sheet 10 Rev. 1.2, 2004-10
114 DQ20 I/O SSTL Data Bus 63:0
117 DQ21 I/O SSTL
121 DQ22 I/O SSTL
123 DQ23 I/O SSTL
33 DQ24 I/O SSTL
35 DQ25 I/O SSTL
39 DQ26 I/O SSTL
40 DQ27 I/O SSTL
126 DQ28 I/O SSTL
127 DQ29 I/O SSTL
131 DQ30 I/O SSTL
133 DQ31 I/O SSTL
53 DQ32 I/O SSTL
55 DQ33 I/O SSTL
57 DQ34 I/O SSTL
60 DQ35 I/O SSTL
146 DQ36 I/O SSTL
147 DQ37 I/O SSTL
150 DQ38 I/O SSTL
151 DQ39 I/O SSTL
61 DQ40 I/O SSTL
64 DQ41 I/O SSTL
68 DQ42 I/O SSTL
69 DQ43 I/O SSTL
153 DQ44 I/O SSTL
155 DQ45 I/O SSTL
161 DQ46 I/O SSTL
162 DQ47 I/O SSTL
72 DQ48 I/O SSTL
73 DQ49 I/O SSTL
79 DQ50 I/O SSTL
80 DQ51 I/O SSTL
165 DQ52 I/O SSTL
166 DQ53 I/O SSTL
170 DQ54 I/O SSTL
171 DQ55 I/O SSTL
83 DQ56 I/O SSTL
84 DQ57 I/O SSTL
87 DQ58 I/O SSTL
88 DQ59 I/O SSTL
Table 4 Pin Configuration of RDIMM (cont’d)
Pin# Name Pin
Type
Buffer
Type
Function
174 DQ60 I/O SSTL Data Bus 63:0
175 DQ61 I/O SSTL
178 DQ62 I/O SSTL
179 DQ63 I/O SSTL
44 CB0 I/O SSTL Check Bits 7:0
45 CB1 I/O SSTL
49 CB2 I/O SSTL
51 CB3 I/O SSTL
134 CB4 I/O SSTL
135 CB5 I/O SSTL
142 CB6 I/O SSTL
144 CB7 I/O SSTL
5 DQS0 I/O SSTL Data Strobes 8:0
Note: See block
diagram for
corresponding
DQ signals
14 DQS1 I/O SSTL
25 DQS2 I/O SSTL
36 DQS3 I/O SSTL
56 DQS4 I/O SSTL
67 DQS5 I/O SSTL
78 DQS6 I/O SSTL Data Strobes 8:0
86 DQS7 I/O SSTL
47 DQS8 I/O SSTL
97 DM0 I SSTL Data Mask 0
Note:
×
8 based module
DQS9 I/O SSTL Data Strobe 9
Note:
×
4 based module
107 DM1 I SSTL Data Mask 1
Note:
×
8 based module
DQS10 I/O SSTL Data Strobe 10
Note:
×
4 based module
119 DM2 I SSTL Data Mask 2
Note:
×
8 based module
DQS11 I/O SSTL Data Strobe 11
Note:
×
4 based module
129 DM3 I SSTL Data Mask 3
Note:
×
8 based module
DQS12 I/O SSTL Data Strobe 12
Note:
×
4 based module
Table 4 Pin Configuration of RDIMM (cont’d)
Pin# Name Pin
Type
Buffer
Type
Function
Data Sheet 11 Rev. 1.2, 2004-10
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Pin Configuration
149 DM4 I SSTL Data Mask 4
Note:
×
8 based module
DQS13 I/O SSTL Data Strobe 13
Note:
×
4 based module
159 DM5 I SSTL Data Mask 5
Note:
×
8 based module
DQS14 I/O SSTL Data Strobe 14
Note:
×
4 based module
169 DM6 I SSTL Data Mask 6
Note:
×
8 based module
DQS15 I/O SSTL Data Strobe 15
Note:
×
4 based module
177 DM7 I SSTL Data Mask 7
Note:
×
8 based module
DQS16 I/O SSTL Data Strobe 16
Note:
×
4 based module
140 DM8 I SSTL Data Mask 8
Note:
×
8 based module
DQS17 I/O SSTL Data Strobe 17
Note:
×
4 based module
EEPROM
92 SCL I CMOS Serial Bus Clock
91 SDA I/O OD Serial Bus Data
181 SA0 I CMOS Slave Address Select
Bus 2:0
182 SA1 I CMOS
183 SA2 I CMOS
Power Supplies
1VREF AI – I/O Reference Voltage
184 VDDSPD PWR – EEPROM Power
Supply
Table 4 Pin Configuration of RDIMM (cont’d)
Pin# Name Pin
Type
Buffer
Type
Function
15,
22,
30,
54,
62,
77,
96,
104,
112,
128,
136,
143,
156,
164,
172,
180
VDDQ PWR – I/O Driver Power
Supply
7,
38,
46,
70,
85,
108,
120,
148,
168
VDD PWR – Power Supply
3,
11,
18,
26,
34,
42,
50,
58,
66,
74,
81,
89,
93,
100,
116,
124,
132,
139,
145,
152,
160,
176
VSS GND – Ground Plane
Table 4 Pin Configuration of RDIMM (cont’d)
Pin# Name Pin
Type
Buffer
Type
Function
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Pin Configuration
Data Sheet 12 Rev. 1.2, 2004-10
Other Pins
82 VDDID OODVDD Identification
Note: Pin in tristate,
indicating VDD
and VDDQ nets
connected on
PCB
9,
16,
17,
71,
75,
76,
90,
101,
102,
103,
113,
163,
173
NC NC – Not connected
Pins not connected on
Infineon RDIMM’s
Table 4 Pin Configuration of RDIMM (cont’d)
Pin# Name Pin
Type
Buffer
Type
Function Table 5 Abbreviations for Pin Type
Abbreviation Description
I Standard input-only pin. Digital levels.
O Output. Digital levels.
I/O I/O is a bidirectional input/output signal.
AI Input. Analog levels.
PWR Power
GND Ground
NU Not Usable (JEDEC Standard)
NC Not Connected (JEDEC Standard)
Table 6 Abbreviations for Buffer Type
Abbreviation Description
SSTL Serial Stub Terminalted Logic (SSTL2)
LV-CMOS Low Voltage CMOS
CMOS CMOS Levels
OD Open Drain. The corresponding pin has 2
operational states, active low and tristate,
and allows multiple devices to share as a
wire-OR.
Data Sheet 13 Rev. 1.2, 2004-10
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Pin Configuration
Figure 1 Pin Configuration 184 Pins, Reg
Table 7 Address Table
Density Organization Memory
Ranks
SDRAMs # of SDRAMs # of row/rank/
columns bits
Refresh Period Interval
256MB 32M ×72 1 32 M ×8 9 13 / 2 / 10 8 K 64 ms 7.8 µs
512MB 64M ×72 1 64 M ×4 18 13 / 2 / 11 8 K 64 ms 7.8 µs
512MB 64M ×72 2 32 M ×8 18 13 / 2 / 10 8 K 64 ms 7.8 µs
1GB 128M ×72 2 64 M ×4 36 13 / 2 / 11 8 K 64 ms 7.8 µs
MPPD0020
Pin 001
Pin 003
Pin 005
Pin 007
Pin 009
Pin 011
Pin 013
Pin 015
Pin 017
Pin 019
Pin 021
Pin 023
Pin 025
Pin 027
Pin 029
Pin 031
Pin 033
Pin 035
Pin 037
Pin 039
Pin 041
Pin 043
Pin 045
Pin 047
Pin 049
Pin 051
-
-
-
-
-
-
-
-
-
-
Pin 002
Pin 004
Pin 006
Pin 008
Pin 010
Pin 012
Pin 014
Pin 016
Pin 018
Pin 020
Pin 022
Pin 024
Pin 026
Pin 028
Pin 030
Pin 032
Pin 034
Pin 036
Pin 038
Pin 040
Pin 042
Pin 044
Pin 046
Pin 048
Pin 050
Pin 052
-
-
-
-
-
-
-
-
-
-
VREF
DQS0
NC
DQ09
NC
DQ10
DQ00
DQ01
DQ02
DQ03
RESET
DQ08
DQS1
NC
DQ11
Pin 054
Pin 056
Pin 058
Pin 060
Pin 062
Pin 064
Pin 066
Pin 068
Pin 070
Pin 072
Pin 074
Pin 076
Pin 078
Pin 080
Pin 082
Pin 084
Pin 086
Pin 088
Pin 090
Pin 092
DQ17
DQ18
A5
DQS3
DQ27
CB00
A0
BA1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Pin 053
Pin 055
Pin 057
Pin 059
Pin 061
Pin 063
Pin 065
Pin 067
Pin 069
Pin 071
Pin 073
Pin 075
Pin 077
Pin 079
Pin 081
Pin 083
Pin 085
Pin 087
Pin 089
Pin 091
CKE0
DQ16
DQS2
A9
A7
DQ19
DQ24
DQ25
A4
DQ26
A2
A1
CB01
DQS8
CB02
CB03
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VSS
VSS
VDD
VSS
VDDQ
VDDQ
VSS
VSS
VDD
VDDQ
VSS
VDDQ
VSS
VDD
VSS
VDD
VSS
VDDQ
VSS
VDDQ
VSS
VDD
VSS
VDDID
DQ32
DQ33
DQ34
BA0
DQ40
WE
CAS
DQS5
DQ43
NC
DQ49
NC
DQ50
DQ56
DQ58
SDA
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DQS4
DQ35
DQ41
DQ42
DQ48
NC
DQS6
DQ51
DQ57
DQS7
DQ59
NC
SCL
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Pin 093
Pin 095
Pin 097
Pin 099
Pin 101
Pin 103
Pin 105
Pin 107
Pin 109
Pin 111
-
-
-
-
-
-
-
-
-
-
Pin 094
Pin 096
Pin 098
Pin 100
Pin 102
Pin 104
Pin 106
Pin 108
Pin 110
Pin 112
-
-
-
-
-
-
-
-
-
-
DQ05
DQ00/DQS9
DQ07
NC
NC
DQ15
DM1/DQS10
DQ14
CKE1/NC
NC
A12/NC
DQ21
DM2/DQS11
DQ22
DQ23
A6
DQ29
DM3/DQS12
DQ30
DQ31
CB5
CK0
A10/AP
DQ04
DQ06
NC
DQ13
DQ15
Pin 114
Pin 116
Pin 118
Pin 120
Pin 122
Pin 124
Pin 126
Pin 128
Pin 130
Pin 132
Pin 134
Pin 136
Pin 138
Pin 140
Pin 142
Pin 144
DQ20
A11
A8
DQ28
A3
DQ04
CK0
DM8/DQS17
CB06
CB07
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Pin 113
Pin 115
Pin 117
Pin 119
Pin 121
Pin 123
Pin 125
Pin 127
Pin 129
Pin 131
Pin 133
Pin 135
Pin 137
Pin 139
Pin 141
Pin 143
DQ37
DM4/DQS13
DQ39
DQ44
DQ45
S0
DM5/DQS14
DQ46
NC
DQ52
A13/NC
DM6/DQS15
DQ55
NC
DQ61
DM7/DQS16
DQ63
SA0
SA2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VDDQ
VDDQ
VDDQ
VDD
VDD
VSS
VSS
VSS
VSS
VDDQ
VSS
VSS
VDDQ
VDDQ
VDD
VDDQ
VSS
VDDQ
VDDQ
VSS
VDDQ
VSS
VDD
VSS
Pin 146
Pin 148
Pin 150
Pin 152
Pin 154
Pin 156
Pin 158
Pin 160
Pin 162
Pin 164
Pin 166
Pin 168
Pin 170
Pin 172
Pin 174
Pin 176
Pin 178
Pin 180
Pin 182
Pin 184
DQ36
DQ38
RAS
S1/NC
DQ47
DQ53
DQ54
DQ60
DQ62
SA1
VDDSPD
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Pin 145
Pin 147
Pin 149
Pin 151
Pin 153
Pin 155
Pin 157
Pin 159
Pin 161
Pin 163
Pin 165
Pin 167
Pin 169
Pin 171
Pin 173
Pin 175
Pin 177
Pin 179
Pin 181
Pin 183
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Pin Configuration
Data Sheet 14 Rev. 1.2, 2004-10
Figure 2 Block Diagram Raw Card A ×72 1 Rank ×8, ECC
Notes
1. VDD = VDDQ, therefore VDDID strap open
2. DQ, DQS, DM resistors are 22 ohms
±
5%
3. BAn, An, RAS, CAS, WE resistors are 22 ohms
±
5%
MPBD1101
S0
D6
DM0/DQS9
DQS0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
D0
DM1/DQS10
DQS1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
D1
DM2/DQS11
DQS2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
D2 DM5/DQS14
DQS5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D5
DM4/DQS13
DQS4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D4
DM3/DQS12
DQS3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
D3
D8
D7
DM CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM6/DQS15
DQS6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM8/DQS17
DQS8
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DM7/DQS16
DQS7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS: SDRAMs D0- D8
CKE: SDRAMs D0 - D8
BA0 - BA1: SDRAMs D0 - D8
A0 - An: SDRAMs D0 - D8
RAS: SDRAMs D0 - D8
CAS: SDRAMs D0 - D8
WE: SDRAMs D0 - D8
R
E
G
I
S
T
E
R
S0
CKE0
BA0 - BA1
A0 - An
RAS
CAS
WE
PCK
PCK
RESET
RS0
RCKE0
RBA0 - RBA1
RA0-RAn
RRAS
RCAS
RWE
SCL
SAD
SA0
SA1
SA2
V
SS
SCL
SAD
A0
A1
A2
WP
E0 V
DD
: SPD EEPROM E0
V
DD
/V
DDQ
: SDRAMs D0 - D8
V
REF
: SDRAMs D0 - D8
V
SS
: SDRAMs D0 - D8
Strap: see Note 1
V
DD,SPD
V
DD
/V
DDQ
V
REF
V
SS
V
DDID
CK0
CK0
PCK
PCK
PLL
Data Sheet 15 Rev. 1.2, 2004-10
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Pin Configuration
Figure 3 Block Diagram Raw Card B ×72, 2Ranks ×8, ECC
Notes
1. VDD = VDDQ, therefore VDDID strap open
2. DQ, DQS, DM resistors are 22 ohms ±5%
3. BAn, An, RAS, CAS, WE resistors are 22 ohms
±5%
4. For Wire per Clock Loading please see Figure:
“Diferential Clock Net Wiring“
MPBD1401
DM1/DQS10
DQS1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
D1
DM2/DQS11
DQS2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
D2
DM3/DQS12
DQS3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
D3
D0
D8
D9
D10
D11
D12
DM8/DQS17
DQS8
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
D17
SCL
SAD
SA0
SA1
SA2
V
SS
E0
SCL
SAD
A0
A1
A2
WP
R
E
G
I
S
T
E
R
S0
CKE0
S1
CKE1
BA0 - BA1
A0 - An
RAS
CAS
WE
PCK
PCK
RESET
RS0
RCKE0
RS1
RCKE1
RBA0 - RBA1
RA0 - RAn
RRAS
RCAS
RWE
CKE: SDRAMs D0 - D8
CKE: SDRAMs D9 - D17
BA0 - BA1: SDRAMs D0 - D17
A0 - An: SDRAMs D0 - D17
RAS: SDRAMs D0 - D17
CAS: SDRAMs D0 - D17
WE: SDRAMs D0 - D17
V
DD
: SPD EEPROM E0
V
DD
/V
DDQ
: SDRAMs D0 - D17
V
REF
: SDRAMs D0 - D17
V
SS
: SDRAMs D0 - D17
DM: SDRAMs D0 - D17
V
DD,SPD
V
DD
/V
DDQ
V
REF
V
SS
V
DDID
Strap: see Note 1
S1
S0
DM0/DQS9
DQS0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM6/DQS15
DQS6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D6
DM7/DQS16
DQS7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D7
DM4/DQS13
DQS4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D4
D15
D14
D13
DM5/DQS14
DQS5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D5
D16
CS
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
PLL PCK
PCK
CK0
CK0
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Pin Configuration
Data Sheet 16 Rev. 1.2, 2004-10
Figure4Block Diagram Raw Card C ×72 1 Rank ×4, ECC
Notes
1. VDD = VDDQ, therefore VDDID strap open
2. DQ, DQS, DM resistors are 22 ohms
±
5%
3. BAn, An, RAS, CAS, WE resistors are 22 ohms
±
5%
MPBD1501
DQS0
DQ0
DQ1
DQ2
DQ3
D0
D1
DQS1
DQ8
DQ9
DQ10
DQ11
D2
D3
D4
D5
DQS2
DQ16
DQ17
DQ18
DQ19
DQS3
DQ24
DQ25
DQ26
DQ27
DQS17
CB4
CB5
CB6
CB7
DQS12
DQ28
DQ29
DQ30
DQ31
DQS15
DQ52
DQ53
DQ54
DQ55
D12
DQS16
DQ60
DQ61
DQ62
DQ63
D13
DQS14
DQ44
DQ45
DQ46
DQ47
D14
DQS5
DQ40
DQ41
DQ42
DQ43
D15
DQS4
DQ32
DQ33
DQ34
DQ35
D16
D17
DQS13
DQ36
DQ37
DQ38
DQ39
D6
D7
D8
DQS7
DQ56
DQ57
DQ58
DQ59
DQS6
DQ48
DQ49
DQ50
DQ51
DQS8
CB0
CB1
CB2
CB3
DQS10
DQ12
DQ13
DQ14
DQ15
DQS9
DQ4
DQ5
DQ6
DQ7
DQS11
DQ20
DQ21
DQ22
DQ23
D9
D10
D11
SCL
SAD
SA0
SA1
SA2
V
SS
SCL
SAD
A0
A1
A2
WP
E0
RS0
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS: SDRAMs D0- D17
CKE: SDRAMs D0 - D17
BA0 - BA1: SDRAMs D0 - D17
A0 - An: SDRAMs D0 - D17
RAS: SDRAMs D0 - D17
CAS: SDRAMs D0 - D17
WE: SDRAMs D0 - D17
R
E
G
I
S
T
E
R
S0
CKE0
BA0 - BA1
A0 - An
RAS
CAS
WE
PCK
PCK
RESET
RS0
RCKE0
RBA0 - RBA1
RA0 - RAn
RRAS
RCAS
RWE
V
DD
: SPD EEPROM E0
V
DD
/V
DDQ
: SDRAMs D0 - D17
V
REF
: SDRAMs D0 - D17
V
SS
: SDRAMs D0 - D17
Strap: see Note 1
V
DD,SPD
V
DD
/V
DDQ
V
REF
V
SS
V
DDID
CK0
CK0
PCK
PCK
PLL
Data Sheet 17 Rev. 1.2, 2004-10
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Pin Configuration
Figure 5 Block Diagram Raw Card D ×72 2 Ranks ×4, ECC
Notes
1. VDD = VDDQ, therefore VDDID strap open
2. DQ, DQS, DM resistors are 18 ohms
±
5%
3. BAn, An, RAS, CAS, WE resistors are 22 ohms
±
5%
4. For Wire per Clock Loading please see Figure
“Differental Clock Net Wiring“
MPBD1061
DQS0
DQ0
DQ1
DQ2
DQ3
D4 D6
D0 D2
DQS1
DQ8
DQ9
DQ10
DQ11
D12 D14
DQS10
DQ12
DQ13
DQ14
DQ15
D8 D10
DQS9
DQ4
DQ5
DQ6
DQ7
D20 D22
DQS11
DQ20
DQ21
DQ22
DQ23
D16 D18
DQS2
DQ16
DQ17
DQ18
DQ19
D24 D26
DQS3
DQ24
DQ25
DQ26
DQ27
D28 D30
DQS17
CB4
CB5
CB6
CB7
D32 D34
DQS12
DQ28
DQ29
DQ30
DQ31
DQS7
DQ56
DQ57
DQ58
DQ59
D5 D7
D1 D3
DQS6
DQ48
DQ49
DQ50
DQ51
D13 D15
DQS15
DQ52
DQ53
DQ54
DQ55
D9 D11
DQS16
DQ60
DQ61
DQ62
DQ63
D21 D23
DQS14
DQ44
DQ45
DQ46
DQ47
D17 D19
DQS5
DQ40
DQ41
DQ42
DQ43
D25 D27
DQS4
DQ32
DQ33
DQ34
DQ35
D28 D31
DQS8
CB0
CB1
CB2
CB3
D33 D35
DQS13
DQ36
DQ37
DQ38
DQ39
RS0
RCKE0
RS1
RCKE1
CKE CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CKE CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
BA0 - BA1: SDRAMs D0 - D35
A0 - An: SDRAMs D0 - D35
RAS: SDRAMs D0 - D35
CAS: SDRAMs D0 - D35
WE: SDRAMs D0 - D35
R
E
G
I
S
T
E
R
S0
CKE0
S1
CKE1
BA0 - BA1
A0 - An
RAS
CAS
WE
PCK
PCK
RESET
RS0
RCKE0
RS1
RCKE1
RBA0 - RBA1
RA0-RAn
RRAS
RCAS
RWE
SCL
SAD
SA0
SA1
SA2
V
SS
E0
SCL
SAD
A0
A1
A2
WP
V
DD
: SPD EEPROM E0
V
DD
/V
DDQ
: SDRAMs D0 - D35
V
REF
: SDRAMs D0 - D35
V
SS
: SDRAMs D0 - D35
DM: SDRAMs D0 - D35
V
DD,SPD
V
DD
/V
DDQ
V
REF
V
SS
V
DDID
Strap: see Note 1
CKE CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CKE CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CKE CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CKE CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CKE CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CKE CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CKE CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CKE CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CKE CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CKE CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CKE CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CKE CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CKE CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CKE CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CKE CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CKE CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CKE CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CKE CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CKE CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CKE CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CKE CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CKE CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CKE CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CKE CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CKE CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CKE CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CKE CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CKE CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CKE CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CKE CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CKE CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CKE CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CKE CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CKE CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
PLL PCK
PCK
CK0
CK0
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Electrical Characteristics
Data Sheet 18 Rev. 1.2, 2004-10
07302003-2MI6-FOP1
3 Electrical Characteristics
3.1 Operating Conditions
Attention: Permanent damage to the device may occur if “Absolute Maximum Ratings” are exceeded. This
is a stress rating only, and functional operation should be restricted to recommended operation
conditions. Exposure to absolute maximum rating conditions for extended periods of time may
affect device reliability and exceeding only one of the values may cause irreversible damage to
the integrated circuit.
Table 8 Absolute Maximum Ratings
Parameter Symbol Values Unit Note/ Test
Condition
min. typ. max.
Voltage on I/O pins relative to VSS VIN, VOUT –0.5 – VDDQ +0.5 V –
Voltage on inputs relative to VSS VIN –1 – +3.6 V –
Voltage on VDD supply relative to VSS VDD –1 – +3.6 V –
Voltage on VDDQ supply relative to VSS VDDQ –1 – +3.6 V –
Operating temperature (ambient) TA0–+70°C–
Storage temperature (plastic) TSTG -55 – +150 °C–
Power dissipation (per SDRAM component) PD–1– W–
Short circuit output current IOUT –50– mA–
Table 9 Electrical Characteristics and DC Operating Conditions
Parameter Symbol Values Unit Note/Test Condition 1)
Min. Typ. Max.
Device Supply Voltage VDD 2.3 2.5 2.7 V fCK ≤166 MHz
Device Supply Voltage VDD 2.5 2.6 2.7 V fCK >166MHz
2)
Output Supply Voltage VDDQ 2.3 2.5 2.7 V fCK ≤166 MHz 3)
Output Supply Voltage VDDQ 2.5 2.6 2.7 V fCK >166MHz
2)3)
EEPROM supply voltage VDDSPD 2.3 2.5 3.6 V —
Supply Voltage, I/O Supply
Voltage
VSS,
VSSQ
00V—
Input Reference Voltage VREF 0.49 × VDDQ 0.5 × VDDQ 0.51 × VDDQ V4)
I/O Termination Voltage
(System)
VTT VREF – 0.04 VREF + 0.04 V 5)
Input High (Logic1) Voltage VIH(DC) VREF + 0.15 VDDQ + 0.3 V 8)
Input Low (Logic0) Voltage VIL(DC) –0.3 VREF – 0.15 V 8)
Input Voltage Level,
CK and CK Inputs
VIN(DC) –0.3 VDDQ + 0.3 V 8)
Input Differential Voltage,
CK and CK Inputs
VID(DC) 0.36 VDDQ + 0.6 V 8)6)
VI-Matching Pull-up
Current to Pull-down
Current
VIRatio 0.71 1.4 — 7)
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Electrical Characteristics
Data Sheet 19 Rev. 1.2, 2004-10
07302003-2MI6-FOP1
Input Leakage Current II–2 2 µA Any input 0 V ≤VIN ≤VDD;
All other pins not under test
=0V
8)9)
Output Leakage Current IOZ –5 5 µA DQs are disabled;
0V ≤ VOUT ≤ VDDQ
Output High Current,
Normal Strength Driver
IOH — –16.2 mA VOUT = 1.95 V
Output Low
Current, Normal Strength
Driver
IOL 16.2 — mA VOUT = 0.35 V
1) 0 °C ≤ TA ≤ 70 °C
2) DDR400 conditions apply for all clock frequencies above 166 MHz
3) Under all conditions, VDDQ must be less than or equal to VDD.
4) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC). VREF is also expected to track noise variations in VDDQ.
5) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal
to VREF, and must track variations in the DC level of VREF.
6) VID is the magnitude of the difference between the input level on CK and the input level on CK.
7) The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire
temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the
maximum difference between pull-up and pull-down drivers due to process variation.
8) Inputs are not recognized as valid until VREF stabilizes.
9) Values are shown per DDR SDRAM component
Table 9 Electrical Characteristics and DC Operating Conditions (cont’d)
Parameter Symbol Values Unit Note/Test Condition 1)
Min. Typ. Max.
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Current Specification and Conditions
Data Sheet 20 Rev. 1.2, 2004-10
07302003-2MI6-FOP1
4 Current Specification and Conditions
Table 10 IDD Conditions
Parameter Symbol
Operating Current 0
one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle;
address and control inputs changing once every two clock cycles.
IDD0
Operating Current 1
one bank; active/read/precharge; Burst Length = 4; see component data sheet.
IDD1
Precharge Power-Down Standby Current
all banks idle; power-down mode; CKE ≤ VIL,MAX
IDD2P
Precharge Floating Standby Current
CS ≥ VIH,,MIN, all banks idle; CKE ≥ VIH,MIN;
address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM.
IDD2F
Precharge Quiet Standby Current
CS ≥ VIHMIN, all banks idle; CKE ≥VIH,MIN; VIN = VREF for DQ, DQS and DM;
address and other control inputs stable at ≥ VIH,MIN or ≤ VIL,MAX.
IDD2Q
Active Power-Down Standby Current
one bank active; power-down mode; CKE ≤ VILMAX; VIN = VREF for DQ, DQS and DM.
IDD3P
Active Standby Current
one bank active; CS ≥ VIH,MIN; CKE ≥ VIH,MIN; tRC =tRAS,MAX;
DQ, DM and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle.
IDD3N
Operating Current Read
one bank active; Burst Length = 2; reads; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B; IOUT =0mA
IDD4R
Operating Current Write
one bank active; Burst Length = 2; writes; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B
IDD4W
Auto-Refresh Current
tRC = tRFCMIN, burst refresh
IDD5
Self-Refresh Current
CKE ≤ 0.2 V; external clock on
IDD6
Operating Current 7
four bank interleaving with Burst Length = 4; see component data sheet.
IDD7
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Current Specification and Conditions
Data Sheet 21 Rev. 1.2, 2004-10
07302003-2MI6-FOP1
Table 11 IDD Specification for HYS72D[128/64/32]3xxx[G/H]BR–5–C
Product Type
HYS72D32300GBR–5–C
HYS72D32300HBR-–5–C
HYS72D64300GBR–5–C
HYS72D64300HBR–5–C
HYS72D64320GBR–5–C
HYS72D64320HBR–5–C
Unit Note/ Test Conditions1) 2)
1) Test condition for maximum values: VDD =2.7V, TA=10°C
2) Module IDD is calculated on the basis of component IDD and includes Register and PLL
Organization 256 MB 512 MB 512 MB
×72 ×72 ×72
1 Rank 1 Rank 2 Ranks
–5 –5 –5
Symbol Typ. Max. Typ. Max. Typ. Max.
IDD0 1140 1370 2070 2480 1780 2080 mA 3)
3) The module IDD values are calculated from the component IDD datasheet values are:
n*IDD×[component] for single bank modules (n: number of components per module bank)
n*IDD×[component] + n*IDD3N[component] for two bank modules (n: number of components per module bank)
IDD1 1360 1600 2380 2800 2000 2310 mA 3)4)
4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load
conditions
IDD2P 390 440 730 790 730 790 mA 5)
5) The module IDD values are calculated from the component IDD datasheet values are:
n*IDD×[component] for single bank modules (n: number of components per module bank)
2*n*IDD×[component] for single two bank modules (n: number of components per module bank)
IDD2F 880 990 1450 1620 1450 1620 mA 5)
IDD2Q 540 650 1020 1200 1020 1200 mA 5)
IDD3P 470 560 890 720 890 1020 mA 5)
IDD3N 950 1080 1590 1780 1590 1780 mA 5)
IDD4R 1400 1600 2470 2800 2040 2310 mA 3)4)
IDD4W 1450 1650 2560 2890 2090 2350 mA 3)
IDD5 1630 2120 3190 4130 2270 2830 mA 3)
IDD6 330 370 640 700 640 700 mA 5)
IDD7 2530 2950 4720 5500 3170 3660 mA 3)4)
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Current Specification and Conditions
Data Sheet 22 Rev. 1.2, 2004-10
07302003-2MI6-FOP1
Table 12 IDD Specification for HYS72D[256/128/64/32]3xxx[G/H]BR–6–C
Product Type
HYS72D32300GBR–6–C
HYS72D32300HBR–6–C
HYS72D64300GBR–6–C
HYS72D64300HBR–6–C
HYS72D64320GBR–6–C
HYS72D64320HBR–6–C
HYS72D128320GBR–6–C
HYS72D128320HBR–6–C
Unit Note/ Test Conditions1) 2)
1) Test condition for maximum values: VDD =2.7V, TA=10°C
2) Module IDD is calculated on the basis of component IDD and includes Register and PLL
Organization 256 MB 512 MB 512 MB 1 GB
×72 ×72 ×72 ×72
1 Rank 1 Rank 2 Ranks 2 Ranks
–6 –6 –6 –6
Symbol Typ. Max. Typ. Max. Typ. Max. Typ. Max.
IDD0 1000 1190 1790 2110 1540 1780 2870 3290 mA 3)
3) The module IDD values are calculated from the component IDD datasheet values are:
n*IDD×[component] for single bank modules (n: number of components per module bank)
n*IDD×[component] + n*IDD3N[component] for two bank modules (n: number of components per module bank)
IDD1 1210 1410 2090 2420 1750 2000 3160 3600 mA 3)4)
4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load
conditions
IDD2P 370 410 650 710 650 710 1220 1300 mA 5)
5) The module IDD values are calculated from the component IDD datasheet values are:
n*IDD×[component] for single bank modules (n: number of components per module bank)
2*n*IDD×[component] for single two bank modules (n: number of components per module bank)
IDD2F 780 880 1250 1400 1250 1400 2200 2440 mA 5)
IDD2Q 480 580 890 1050 890 1050 1690 1980 mA 5)
IDD3P 430 500 780 640 780 890 1480 1660 mA 5)
IDD3N 840 950 1380 1540 1380 1540 2450 2730 mA 5)
IDD4R 1210 1410 2090 2420 1750 2000 3160 3600 mA 3)4)
IDD4W 1250 1450 2180 2510 1790 2040 3250 3690 mA 3)
IDD5 1420 1820 2750 3510 1960 2410 3830 4690 mA 3)
IDD6 320 370 580 640 580 640 1110 1190 mA 5)
IDD7 2200 2580 4070 4760 2740 3170 5140 5940 mA 3)4)
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Current Specification and Conditions
Data Sheet 23 Rev. 1.2, 2004-10
07302003-2MI6-FOP1
Table 13 IDD Specification for HYS72D[128/64/32]3xxx[G/H]BR–7–C
Product Type
HYS72D32300GBR-7-C
HYS72D32300HBR-7-C
HYS72D64300GBR-7-C
HYS72D64300HBR-7-C
HYS72D128320GBR-7-C
HYS72D128320HBR-7-C
Unit Note/ Test Conditions1) 2)
1) Test condition for maximum values: VDD =2.7V, TA=10°C
2) Module IDD is calculated on the basis of component IDD and includes Register and PLL
Organization 256 MB 512 MB 1 GB
×72 ×72 ×72
1 Rank 1 Rank 2 Ranks
–7 –7 –7
Symbol Typ. Max. Typ. Max. Typ. Max.
IDD0 860 1040 1510 1830 2410 2870 mA 3)
3) The module IDD values are calculated from the component IDD datasheet values are:
n*IDD×[component] for single bank modules (n: number of components per module bank)
n*IDD×[component] + n*IDD3N[component] for two bank modules (n: number of components per module bank)
IDD1 1100 1250 1890 2120 2790 3170 mA 3)4)
4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load
conditions
IDD2P 330 370 560 610 1010 1080 mA 5)
5) The module IDD values are calculated from the component IDD datasheet values are:
n*IDD×[component] for single bank modules (n: number of components per module bank)
2*n*IDD×[component] for single two bank modules (n: number of components per module bank)
IDD2F 670 760 1050 1180 1810 2010 mA 5)
IDD2Q 440 520 770 910 1440 1690 mA 5)
IDD3P 380 450 660 570 1230 1400 mA 5)
IDD3N 740 870 1200 1390 2100 2440 mA 5)
IDD4R 1060 1200 1800 2030 2700 3080 mA 3)4)
IDD4W 1100 1250 1890 2120 2790 3170 mA 3)
IDD5 1210 1600 2310 3060 3210 4110 mA 3)
IDD6 300 350 520 580 940 1030 mA 5)
IDD7 1780 2100 3240 3830 4140 4880 mA 3)4)
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Current Specification and Conditions
Data Sheet 24 Rev. 1.2, 2004-10
07302003-2MI6-FOP1
4.1 AC Characteristics
Table 14 AC Timing - Absolute Specifications for PC3200 and PC2700
Parameter Symbol –5 –6 Unit Note/ Test
Condition 1)
DDR400B DDR333
Min. Max. Min. Max.
DQ output access time from
CK/CK
tAC –0.5 +0.5 –0.7 +0.7 ns 2)3)4)5)
CK high-level width tCH 0.45 0.55 0.45 0.55 tCK
2)3)4)5)
Clock cycle time tCK 5 8 6 12 ns CL = 3.0
2)3)4)5)
6 12 6 12 ns CL = 2.5
2)3)4)5)
7.5 12 7.5 12 ns CL = 2.0
2)3)4)5)
CK low-level width tCL 0.45 0.55 0.45 0.55 tCK
2)3)4)5)
Auto precharge write recovery
+ precharge time
tDAL (tWR/tCK)+(tRP/tCK)tCK
2)3)4)5)6)
DQ and DM input hold time tDH 0.4 — 0.45 — ns 2)3)4)5)
DQ and DM input pulse width
(each input)
tDIPW 1.75 — 1.75 — ns 2)3)4)5)6)
DQS output access time from
CK/CK
tDQSCK –0.6 +0.6 –0.6 +0.6 ns 2)3)4)5)
DQS input low (high) pulse
width (write cycle)
tDQSL,H 0.35 — 0.35 — tCK
2)3)4)5)
DQS-DQ skew (DQS and
associated DQ signals)
tDQSQ — +0.40 — +0.40 ns TFBGA
2)3)4)5)
Write command to 1st DQS
latching transition
tDQSS 0.72 1.25 0.75 1.25 tCK
2)3)4)5)
DQ and DM input setup time tDS 0.4 — 0.45 — ns 2)3)4)5)
DQS falling edge hold time
from CK (write cycle)
tDSH 0.2 — 0.2 — tCK
2)3)4)5)
DQS falling edge to CK setup
time (write cycle)
tDSS 0.2 — 0.2 — tCK
2)3)4)5)
Clock Half Period tHP min. (tCL, tCH)min. (tCL, tCH)ns
2)3)4)5)
Data-out high-impedance time
from CK/CK
tHZ — +0.7 –0.7 +0.7 ns 2)3)4)5)7)
Address and control input hold
time
tIH 0.6 — 0.75 — ns fast slew rate
3)4)5)6)8)
0.7 — 0.8 — ns slow slew
rate3)4)5)6)8)
Control and Addr. input pulse
width (each input)
tIPW 2.2 — 2.2 — ns 2)3)4)5)9)
Address and control input
setup time
tIS 0.6 — 0.75 — ns fast slew rate
3)4)5)6)8)
0.7 — 0.8 — ns slow slew
rate3)4)5)6)8)
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Current Specification and Conditions
Data Sheet 25 Rev. 1.2, 2004-10
07302003-2MI6-FOP1
Data-out low-impedance time
from CK/CK
tLZ –0.7 +0.7 –0.7 +0.7 ns 2)3)4)5)7)
Mode register set command
cycle time
tMRD 2—2—tCK
2)3)4)5)
DQ/DQS output hold time tQH tHP –tQHS tHP –tQHS ns 2)3)4)5)
Data hold skew factor tQHS — +0.50 — +0.50 ns TFBGA 2)3)4)5)
Active to Autoprecharge delay tRAP tRCD or tRASmin —tRCD or tRASmin —ns
2)3)4)5)
Active to Precharge command tRAS 40 70E+3 42 70E+3 ns 2)3)4)5)
Active to Active/Auto-refresh
command period
tRC 55 — 60 — ns 2)3)4)5)
Active to Read or Write delay tRCD 15 — 18 — ns 2)3)4)5)
Average Periodic Refresh
Interval
tREFI — 7.8 — 7.8 µs2)3)4)5)10)
Auto-refresh to Active/Auto-
refresh command period
tRFC 70 — 72 — ns 2)3)4)5)
Precharge command period tRP 15 — 18 — ns 2)3)4)5)
Read preamble tRPRE 0.9 1.1 0.9 1.1 tCK
2)3)4)5)
Read postamble tRPST 0.40 0.60 0.40 0.60 tCK
2)3)4)5)
Active bank A to Active bank B
command
tRRD 10 — 12 — ns 2)3)4)5)
Write preamble tWPRE 0.25 — 0.25 — tCK
2)3)4)5)
Write preamble setup time tWPRES 0—0—ns
2)3)4)5)11)
Write postamble tWPST 0.40 0.60 0.40 0.60 tCK
2)3)4)5)12)
Write recovery time tWR 15 — 15 — ns 2)3)4)5)
Internal write to read command
delay
tWTR 2—1—tCK
2)3)4)5)
Exit self-refresh to non-read
command
tXSNR 75 — 75 — ns 2)3)4)5)
Exit self-refresh to read
command
tXSRD 200 — 200 — tCK
2)3)4)5)
1) 0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V (DDR333); VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ±0.1 V
(DDR400)
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until VREF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT.
6) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock
cycle time.
7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
Table 14 AC Timing - Absolute Specifications for PC3200 and PC2700
Parameter Symbol –5 –6 Unit Note/ Test
Condition 1)
DDR400B DDR333
Min. Max. Min. Max.
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Current Specification and Conditions
Data Sheet 26 Rev. 1.2, 2004-10
07302003-2MI6-FOP1
8) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns,
measured between VIH(ac) and VIL(ac).
9) These parameters guarantee device timing, but they are not necessarily tested on each device.
10) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
11) The specific requirement is that DQS be valid (HIGH,LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specificationsof the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW at this time, depending on tDQSS.
12) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
Table 15 AC Timing - Absolute Specifications for PC2700
Parameter Symbol –7 Unit Note/Test
Condition 1)
DDR266A
Min. Max.
DQ output access time from CK/CK tAC –0.75 +0.75 ns 2)3)4)5)
CK high-level width tCH 0.45 0.55 tCK
2)3)4)5)
Clock cycle time tCK 7.5 12 ns CL = 2.52)3)4)5)
7.5 12 ns CL = 2.02)3)4)5)
CK low-level width tCL 0.45 0.55 tCK
2)3)4)5)
Auto precharge write recovery + precharge
time
tDAL (tWR/tCK)+(tRP/tCK)— tCK
2)3)4)5)6)
DQ and DM input hold time tDH 0.5 — ns 2)3)4)5)
DQ and DM input pulse width (each input) tDIPW 1.75 — ns 2)3)4)5)6)
DQS output access time from CK/CK tDQSCK –0.75 +0.75 ns 2)3)4)5)
DQS input low (high) pulse width (write cycle) tDQSL,H 0.35 — tCK
2)3)4)5)
DQS-DQ skew (DQS and associated DQ
signals)
tDQSQ —+0.5nsFBGA
2)3)4)5)
Write command to 1st DQS latching transition tDQSS 0.75 1.25 tCK
2)3)4)5)
DQ and DM input setup time tDS 0.5 — ns 2)3)4)5)
DQS falling edge hold time from CK (write
cycle)
tDSH 0.2 — tCK
2)3)4)5)
DQS falling edge to CK setup time (write
cycle)
tDSS 0.2 — tCK
2)3)4)5)
Clock Half Period tHP min. (tCL, tCH)— ns
2)3)4)5)
Data-out high-impedance time from CK/CK tHZ –0.75 +0.75 ns 2)3)4)5)7)
Address and control input hold time tIH 0.9 — ns fast slew rate
3)4)5)6)8)
1.0 — ns slow slew rate
3)4)5)6)8)
Control and Addr. input pulse width (each
input)
tIPW 2.2 — ns 2)3)4)5)9)
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Current Specification and Conditions
Data Sheet 27 Rev. 1.2, 2004-10
07302003-2MI6-FOP1
Address and control input setup time tIS 0.9 — ns fast slew rate
3)4)5)6)8)
1.0 — ns slow slew rate
3)4)5)6)8)
Data-out low-impedance time from CK/CK tLZ –0.75 +0.75 ns 2)3)4)5)7)
Mode register set command cycle time tMRD 2—tCK
2)3)4)5)
DQ/DQS output hold time tQH tHP – tQHS ns 2)3)4)5)
Data hold skew factor tQHS —0.75nsFBGA
2)3)4)5)
Active to Read w/AP delay tRAP tRCD or tRASmin —ns
2)3)4)5)
Active to Precharge command tRAS 45 120E+3 ns 2)3)4)5)
Active to Active/Auto-refresh command
period
tRC 65 — ns 2)3)4)5)
Active to Read or Write delay tRCD 20 — ns 2)3)4)5)
Average Periodic Refresh Interval tREFI 7.8 — µs2)3)4)5)10)
Auto-refresh to Active/Auto-refresh
command period
tRFC 75 — ns 2)3)4)5)
Precharge command period tRP 20 — ns 2)3)4)5)
Read preamble tRPRE 0.9 1.1 tCK
2)3)4)5)
Read postamble tRPST 0.4 0.6 tCK
2)3)4)5)
Active bank A to Active bank B command tRRD 15 — ns 2)3)4)5)
Write preamble tWPRE 0.25 — tCK
2)3)4)5)
Write preamble setup time tWPRES 0—ns
2)3)4)5)11)
Write postamble tWPST 0.4 — tCK
2)3)4)5)12)
Write recovery time tWR 15 — ns 2)3)4)5)
Internal write to read command delay tWTR 1—tCK
2)3)4)5)
Exit self-refresh to non-read command tXSNR 75 ns 2)3)4)5)13)
Exit self-refresh to read command tXSRD 200 — tCK
2)3)4)5)
1) VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V ; 0 °C≤ TA ≤ 70 °C
2) Input slew rate ≥ 1 V/ns
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until VREF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT.
6) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock
cycle time.
7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns,
measured between VIH(ac) and VIL(ac).
9) These parameters guarantee device timing, but they are not necessarily tested on each device.
10) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Table 15 AC Timing - Absolute Specifications for PC2700
Parameter Symbol –7 Unit Note/Test
Condition 1)
DDR266A
Min. Max.
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Current Specification and Conditions
Data Sheet 28 Rev. 1.2, 2004-10
07302003-2MI6-FOP1
11) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.
12) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
13) In all circumstances, tXSNR can be satisfied using tXSNR =tRFC,min +1×tCK
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
SPD Contents
Data Sheet 29 Rev. 1.2, 2004-10
07302003-2MI6-FOP1
5SPDContents
Table 16 SPD Codes for HYS72D[128/64/32]3xxGBR–5–C
Product Type & Organization
HYS72D64320GBR–5–C
HYS72D64300GBR–5–C
HYS72D32300GBR–5–C
512 MB 512 MB 256 MB
×72 ×72 ×72
2 Ranks 1 Rank 1 Rank
Label Code PC3200R–30331 PC3200R–30331 PC3200R–30331
Jedec SPD Revision Rev 1.0 Rev 1.0 Rev 1.0
Byte# Description HEX HEX HEX
0 Programmed SPD Bytes in E2PROM 80 80 80
1 Total number of Bytes in E2PROM 08 08 08
2 Memory Type (DDR = 07h) 07 07 07
3 Number of Row Addresses 0D 0D 0D
4 Number of Column Addresses 0A 0B 0A
5 Number of DIMM Ranks 02 01 01
6 Data Width (LSB) 48 48 48
7 Data Width (MSB) 00 00 00
8 Interface Voltage Levels 04 04 04
9tCK @ CLmax (Byte 18) [ns] 50 50 50
10 tAC SDRAM @ CLmax (Byte 18) [ns] 50 50 50
11 Error Correction Support 02 02 02
12 Refresh Rate 82 82 82
13 Primary SDRAM Width 08 04 08
14 Error Checking SDRAM Width 08 04 08
15 tCCD [cycles] 010101
16 Burst Length Supported 0E 0E 0E
17 Number of Banks on SDRAM Device 04 04 04
18 CAS Latency 1C 1C 1C
19 CS Latency 01 01 01
20 Write Latency 02 02 02
21 DIMM Attributes 26 26 26
22 Component Attributes C1 C1 C1
23 tCK @ CLmax -0.5 (Byte 18) [ns] 60 60 60
24 tAC SDRAM @ CLmax -0.5 [ns] 50 50 50
25 tCK @ CLmax -1 (Byte 18) [ns] 75 75 75
26 tAC SDRAM @ CLmax -1 [ns] 50 50 50
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
SPD Contents
Data Sheet 30 Rev. 1.2, 2004-10
07302003-2MI6-FOP1
27 tRPmin [ns] 3C 3C 3C
28 tRRDmin [ns] 28 28 28
29 tRCDmin [ns] 3C 3C 3C
30 tRASmin [ns] 28 28 28
31 Module Density per Rank 40 80 40
32 tAS, tCS [ns] 60 60 60
33 tAH, tCH [ns] 60 60 60
34 tDS [ns] 40 40 40
35 tDH [ns] 40 40 40
36 - 40 not used 00 00 00
41 tRCmin [ns] 37 37 37
42 tRFCmin [ns] 41 41 41
43 tCKmax [ns] 28 28 28
44 tDQSQmax [ns] 28 28 28
45 tQHSmax [ns] 50 50 50
46 not used 00 00 00
47 DIMM PCB Height 01 01 01
48 - 61 not used 00 00 00
62 SPD Revision 10 10 10
63 Checksum of Byte 0-62 27 5F 26
64 JEDEC ID Code of Infineon (1) C1 C1 C1
65 - 71 JEDEC ID Code of Infineon (2 - 8) 00 00 00
72 Module Manufacturer Location xx xx xx
73 Part Number, Char 1 37 37 37
74 Part Number, Char 2 32 32 32
75 Part Number, Char 3 44 44 44
76 Part Number, Char 4 36 36 33
77 Part Number, Char 5 34 34 32
Table 16 SPD Codes for HYS72D[128/64/32]3xxGBR–5–C (cont’d)
Product Type & Organization
HYS72D64320GBR–5–C
HYS72D64300GBR–5–C
HYS72D32300GBR–5–C
512 MB 512 MB 256 MB
×72 ×72 ×72
2 Ranks 1 Rank 1 Rank
Label Code PC3200R–30331 PC3200R–30331 PC3200R–30331
Jedec SPD Revision Rev 1.0 Rev 1.0 Rev 1.0
Byte# Description HEX HEX HEX
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
SPD Contents
Data Sheet 31 Rev. 1.2, 2004-10
07302003-2MI6-FOP1
78 Part Number, Char 6 33 33 33
79 Part Number, Char 7 32 30 30
80 Part Number, Char 8 30 30 30
81 Part Number, Char 9 47 47 47
82 Part Number, Char 10 42 42 42
83 Part Number, Char 11 52 52 52
84 Part Number, Char 12 35 35 35
85 Part Number, Char 13 43 43 43
86 Part Number, Char 14 20 20 20
87 Part Number, Char 15 20 20 20
88 Part Number, Char 16 20 20 20
89 Part Number, Char 17 20 20 20
90 Part Number, Char 18 20 20 20
91 Module Revision Code xx xx xx
92 Test Program Revision Code xx xx xx
93 Module Manufacturing Date Year xx xx xx
94 Module Manufacturing Date Week xx xx xx
95 - 98 Module Serial Number (1 - 4) xx xx xx
99 - 127 not used 00 00 00
Table 16 SPD Codes for HYS72D[128/64/32]3xxGBR–5–C (cont’d)
Product Type & Organization
HYS72D64320GBR–5–C
HYS72D64300GBR–5–C
HYS72D32300GBR–5–C
512 MB 512 MB 256 MB
×72 ×72 ×72
2 Ranks 1 Rank 1 Rank
Label Code PC3200R–30331 PC3200R–30331 PC3200R–30331
Jedec SPD Revision Rev 1.0 Rev 1.0 Rev 1.0
Byte# Description HEX HEX HEX
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
SPD Contents
Data Sheet 32 Rev. 1.2, 2004-10
07302003-2MI6-FOP1
Table 17 SPD Codes for HYS72D[128/64/32]3xxHBR–5–C
Product Type & Organization
HYS72D64320HBR–5–C
HYS72D64300GHR–5–C
HYS72D32300HBR–5–C
512 MB 512 MB 256 MB
×72 ×72 ×72
2 Ranks 1 Rank 1 Rank
Label Code PC3200R–30331 PC3200R–30331 PC3200R–30331
Jedec SPD Revision Rev 1.0 Rev 1.0 Rev 1.0
Byte# Description HEX HEX HEX
0 Programmed SPD Bytes in E2PROM 80 80 80
1 Total number of Bytes in E2PROM 08 08 08
2 Memory Type (DDR = 07h) 07 07 07
3 Number of Row Addresses 0D 0D 0D
4 Number of Column Addresses 0A 0B 0A
5 Number of DIMM Ranks 02 01 01
6 Data Width (LSB) 48 48 48
7 Data Width (MSB) 00 00 00
8 Interface Voltage Levels 04 04 04
9tCK @ CLmax (Byte 18) [ns] 50 50 50
10 tAC SDRAM @ CLmax (Byte 18) [ns] 50 50 50
11 Error Correction Support 02 02 02
12 Refresh Rate 82 82 82
13 Primary SDRAM Width 08 04 08
14 Error Checking SDRAM Width 08 04 08
15 tCCD [cycles] 010101
16 Burst Length Supported 0E 0E 0E
17 Number of Banks on SDRAM Device 04 04 04
18 CAS Latency 1C 1C 1C
19 CS Latency 01 01 01
20 Write Latency 02 02 02
21 DIMM Attributes 26 26 26
22 Component Attributes C1 C1 C1
23 tCK @ CLmax -0.5 (Byte 18) [ns] 60 60 60
24 tAC SDRAM @ CLmax -0.5 [ns] 50 50 50
25 tCK @ CLmax -1 (Byte 18) [ns] 75 75 75
26 tAC SDRAM @ CLmax -1 [ns] 50 50 50
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
SPD Contents
Data Sheet 33 Rev. 1.2, 2004-10
07302003-2MI6-FOP1
27 tRPmin [ns] 3C 3C 3C
28 tRRDmin [ns] 28 28 28
29 tRCDmin [ns] 3C 3C 3C
30 tRASmin [ns] 28 28 28
31 Module Density per Rank 40 80 40
32 tAS, tCS [ns] 60 60 60
33 tAH, tCH [ns] 60 60 60
34 tDS [ns] 40 40 40
35 tDH [ns] 40 40 40
36 - 40 not used 00 00 00
41 tRCmin [ns] 37 37 37
42 tRFCmin [ns] 41 41 41
43 tCKmax [ns] 28 28 28
44 tDQSQmax [ns] 28 28 28
45 tQHSmax [ns] 50 50 50
46 not used 00 00 00
47 DIMM PCB Height 01 01 01
48 - 61 not used 00 00 00
62 SPD Revision 10 10 10
63 Checksum of Byte 0-62 27 5F 26
64 JEDEC ID Code of Infineon (1) C1 C1 C1
65 - 71 JEDEC ID Code of Infineon (2 - 8) 00 00 00
72 Module Manufacturer Location xx xx xx
73 Part Number, Char 1 37 37 37
74 Part Number, Char 2 32 32 32
75 Part Number, Char 3 44 44 44
76 Part Number, Char 4 36 36 33
77 Part Number, Char 5 34 34 32
Table 17 SPD Codes for HYS72D[128/64/32]3xxHBR–5–C (cont’d)
Product Type & Organization
HYS72D64320HBR–5–C
HYS72D64300GHR–5–C
HYS72D32300HBR–5–C
512 MB 512 MB 256 MB
×72 ×72 ×72
2 Ranks 1 Rank 1 Rank
Label Code PC3200R–30331 PC3200R–30331 PC3200R–30331
Jedec SPD Revision Rev 1.0 Rev 1.0 Rev 1.0
Byte# Description HEX HEX HEX
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
SPD Contents
Data Sheet 34 Rev. 1.2, 2004-10
07302003-2MI6-FOP1
78 Part Number, Char 6 33 33 33
79 Part Number, Char 7 32 30 30
80 Part Number, Char 8 30 30 30
81 Part Number, Char 9 48 48 48
82 Part Number, Char 10 42 42 42
83 Part Number, Char 11 52 52 52
84 Part Number, Char 12 35 35 35
85 Part Number, Char 13 43 43 43
86 Part Number, Char 14 20 20 20
87 Part Number, Char 15 20 20 20
88 Part Number, Char 16 20 20 20
89 Part Number, Char 17 20 20 20
90 Part Number, Char 18 20 20 20
91 Module Revision Code xx xx xx
92 Test Program Revision Code xx xx xx
93 Module Manufacturing Date Year xx xx xx
94 Module Manufacturing Date Week xx xx xx
95 - 98 Module Serial Number (1 - 4) xx xx xx
99 - 127 not used 00 00 00
Table 17 SPD Codes for HYS72D[128/64/32]3xxHBR–5–C (cont’d)
Product Type & Organization
HYS72D64320HBR–5–C
HYS72D64300GHR–5–C
HYS72D32300HBR–5–C
512 MB 512 MB 256 MB
×72 ×72 ×72
2 Ranks 1 Rank 1 Rank
Label Code PC3200R–30331 PC3200R–30331 PC3200R–30331
Jedec SPD Revision Rev 1.0 Rev 1.0 Rev 1.0
Byte# Description HEX HEX HEX
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
SPD Contents
Data Sheet 35 Rev. 1.2, 2004-10
07302003-2MI6-FOP1
Table 18 SPD Codes for HYS72D[128/64/32]3xxGBR–6–C
Product Type & Organization
HYS72D128320GBR–6–C
HYS72D64320GBR–6–C
HYS72D64300GBR–6–C
HYS72D32300GBR–6–C
1 GByte 512 MB 512 MB 256 MB
×72 ×72 ×72 ×72
2 Ranks 2 Ranks 1 Rank 1 Rank
Label Code PC2700R–
25330
PC2700R–
25330
PC2700R–
25330
PC2700R–
25330
Jedec SPD Revision Rev 0.0 Rev 0.0 Rev 0.0 Rev 0.0
Byte# Description HEX HEX HEX HEX
0 Programmed SPD Bytes in E2PROM 80 80 80 80
1 Total number of Bytes in E2PROM 08 08 08 08
2 Memory Type (DDR = 07h) 07 07 07 07
3 Number of Row Addresses 0D 0D 0D 0D
4 Number of Column Addresses 0B 0A 0B 0A
5 Number of DIMM Ranks 02 02 01 01
6 Data Width (LSB) 48 48 48 48
7 Data Width (MSB) 00 00 00 00
8 Interface Voltage Levels 04 04 04 04
9 tCK @ CLmax (Byte 18) [ns] 60 60 60 60
10 tAC SDRAM @ CLmax (Byte 18) [ns] 70 70 70 70
11 Error Correction Support 02 02 02 02
12 Refresh Rate 82 82 82 82
13 Primary SDRAM Width 04 08 04 08
14 Error Checking SDRAM Width 04 08 04 08
15 tCCD [cycles] 01 01 01 01
16 Burst Length Supported 0E 0E 0E 0E
17 Number of Banks on SDRAM Device 04 04 04 04
18 CAS Latency 0C 0C 0C 0C
19 CS Latency 01 01 01 01
20 Write Latency 02 02 02 02
21 DIMM Attributes 26 26 26 26
22 Component Attributes C1 C1 C1 C1
23 tCK @ CLmax -0.5 (Byte 18) [ns] 75 75 75 75
24 tAC SDRAM @ CLmax -0.5 [ns] 70 70 70 70
25 tCK @ CLmax -1 (Byte 18) [ns] 00 00 00 00
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
SPD Contents
Data Sheet 36 Rev. 1.2, 2004-10
07302003-2MI6-FOP1
26 tAC SDRAM @ CLmax -1 [ns] 00 00 00 00
27 tRPmin [ns] 48 48 48 48
28 tRRDmin [ns] 30 30 30 30
29 tRCDmin [ns] 48 48 48 48
30 tRASmin [ns] 2A 2A 2A 2A
31 Module Density per Rank 80 40 80 40
32 tAS, tCS [ns] 75 75 75 75
33 tAH, tCH [ns] 75 75 75 75
34 tDS [ns] 45 45 45 45
35 tDH [ns] 45 45 45 45
36 - 40 not used 00 00 00 00
41 tRCmin [ns] 3C 3C 3C 3C
42 tRFCmin [ns] 48 48 48 48
43 tCKmax [ns] 30 30 30 30
44 tDQSQmax [ns] 28 28 28 28
45 tQHSmax [ns] 50 50 50 50
46 not used 00 00 00 00
47 DIMM PCB Height 00 00 00 00
48 - 61 not used 00 00 00 00
62 SPD Revision 00 00 00 00
63 Checksum of Byte 0-62 49 10 48 0F
64 JEDEC ID Code of Infineon (1) C1 C1 C1 C1
65 - 71 JEDEC ID Code of Infineon (2 - 8) 00 00 00 00
72 Module Manufacturer Location xx xx xx xx
73 Part Number, Char 1 37 37 37 37
74 Part Number, Char 2 32 32 32 32
75 Part Number, Char 3 44 44 44 44
Table 18 SPD Codes for HYS72D[128/64/32]3xxGBR–6–C (cont’d)
Product Type & Organization
HYS72D128320GBR–6–C
HYS72D64320GBR–6–C
HYS72D64300GBR–6–C
HYS72D32300GBR–6–C
1 GByte 512 MB 512 MB 256 MB
×72 ×72 ×72 ×72
2 Ranks 2 Ranks 1 Rank 1 Rank
Label Code PC2700R–
25330
PC2700R–
25330
PC2700R–
25330
PC2700R–
25330
Jedec SPD Revision Rev 0.0 Rev 0.0 Rev 0.0 Rev 0.0
Byte# Description HEX HEX HEX HEX
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
SPD Contents
Data Sheet 37 Rev. 1.2, 2004-10
07302003-2MI6-FOP1
76 Part Number, Char 4 31 36 36 33
77 Part Number, Char 5 32 34 34 32
78 Part Number, Char 6 38 33 33 33
79 Part Number, Char 7 33 32 30 30
80 Part Number, Char 8 32 30 30 30
81 Part Number, Char 9 30 47 47 47
82 Part Number, Char 10 47 42 42 42
83 Part Number, Char 11 42 52 52 52
84 Part Number, Char 12 52 36 36 36
85 Part Number, Char 13 36 43 43 43
86 Part Number, Char 14 43 20 20 20
87 Part Number, Char 15 20 20 20 20
88 Part Number, Char 16 20 20 20 20
89 Part Number, Char 17 20 20 20 20
90 Part Number, Char 18 20 20 20 20
91 Module Revision Code xx xx xx xx
92 Test Program Revision Code xx xx xx xx
93 Module Manufacturing Date Year xx xx xx xx
94 Module Manufacturing Date Week xx xx xx xx
95 - 98 Module Serial Number (1 - 4) xx xx xx xx
99 -127 not used FF FF FF FF
Table 18 SPD Codes for HYS72D[128/64/32]3xxGBR–6–C (cont’d)
Product Type & Organization
HYS72D128320GBR–6–C
HYS72D64320GBR–6–C
HYS72D64300GBR–6–C
HYS72D32300GBR–6–C
1 GByte 512 MB 512 MB 256 MB
×72 ×72 ×72 ×72
2 Ranks 2 Ranks 1 Rank 1 Rank
Label Code PC2700R–
25330
PC2700R–
25330
PC2700R–
25330
PC2700R–
25330
Jedec SPD Revision Rev 0.0 Rev 0.0 Rev 0.0 Rev 0.0
Byte# Description HEX HEX HEX HEX
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
SPD Contents
Data Sheet 38 Rev. 1.2, 2004-10
07302003-2MI6-FOP1
Table 19 SPD Codes for HYS72D[128/64/32]3xxHBR–6–C
Product Type & Organization
HYS72D128320HBR–6–C
HYS72D64320HBR–6–C
HYS72D64300HBR–6–C
HYS72D32300HBR–6–C
1 GByte 512 MB 512 MB 256 MB
×72 ×72 ×72 ×72
2 Ranks 2 Ranks 1 Rank 1 Rank
Label Code PC2700R–
25330
PC2700R–
25330
PC2700R–
25330
PC2700R–
25330
Jedec SPD Revision Rev 0.0 Rev 0.0 Rev 0.0 Rev 0.0
Byte# Description HEX HEX HEX HEX
0 Programmed SPD Bytes in E2PROM 80 80 80 80
1 Total number of Bytes in E2PROM 08 08 08 08
2 Memory Type (DDR = 07h) 07 07 07 07
3 Number of Row Addresses 0D 0D 0D 0D
4 Number of Column Addresses 0B 0A 0B 0A
5 Number of DIMM Ranks 02 02 01 01
6 Data Width (LSB) 48 48 48 48
7 Data Width (MSB) 00 00 00 00
8 Interface Voltage Levels 04 04 04 04
9 tCK @ CLmax (Byte 18) [ns] 60 60 60 60
10 tAC SDRAM @ CLmax (Byte 18) [ns] 70 70 70 70
11 Error Correction Support 02 02 02 02
12 Refresh Rate 82 82 82 82
13 Primary SDRAM Width 04 08 04 08
14 Error Checking SDRAM Width 04 08 04 08
15 tCCD [cycles] 01 01 01 01
16 Burst Length Supported 0E 0E 0E 0E
17 Number of Banks on SDRAM Device 04 04 04 04
18 CAS Latency 0C 0C 0C 0C
19 CS Latency 01 01 01 01
20 Write Latency 02 02 02 02
21 DIMM Attributes 26 26 26 26
22 Component Attributes C1 C1 C1 C1
23 tCK @ CLmax -0.5 (Byte 18) [ns] 75 75 75 75
24 tAC SDRAM @ CLmax -0.5 [ns] 70 70 70 70
25 tCK @ CLmax -1 (Byte 18) [ns] 00 00 00 00
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
SPD Contents
Data Sheet 39 Rev. 1.2, 2004-10
07302003-2MI6-FOP1
26 tAC SDRAM @ CLmax -1 [ns] 00 00 00 00
27 tRPmin [ns] 48 48 48 48
28 tRRDmin [ns] 30 30 30 30
29 tRCDmin [ns] 48 48 48 48
30 tRASmin [ns] 2A 2A 2A 2A
31 Module Density per Rank 80 40 80 40
32 tAS, tCS [ns] 75 75 75 75
33 tAH, tCH [ns] 75 75 75 75
34 tDS [ns] 45 45 45 45
35 tDH [ns] 45 45 45 45
36 - 40 not used 00 00 00 00
41 tRCmin [ns] 3C 3C 3C 3C
42 tRFCmin [ns] 48 48 48 48
43 tCKmax [ns] 30 30 30 30
44 tDQSQmax [ns] 28 28 28 28
45 tQHSmax [ns] 50 50 50 50
46 not used 00 00 00 00
47 DIMM PCB Height 00 00 00 00
48 - 61 not used 00 00 00 00
62 SPD Revision 00 00 00 00
63 Checksum of Byte 0-62 49 10 48 0F
64 JEDEC ID Code of Infineon (1) C1 C1 C1 C1
65 - 71 JEDEC ID Code of Infineon (2 - 8) 00 00 00 00
72 Module Manufacturer Location xx xx xx xx
73 Part Number, Char 1 37 37 37 37
74 Part Number, Char 2 32 32 32 32
75 Part Number, Char 3 44 44 44 44
Table 19 SPD Codes for HYS72D[128/64/32]3xxHBR–6–C (cont’d)
Product Type & Organization
HYS72D128320HBR–6–C
HYS72D64320HBR–6–C
HYS72D64300HBR–6–C
HYS72D32300HBR–6–C
1 GByte 512 MB 512 MB 256 MB
×72 ×72 ×72 ×72
2 Ranks 2 Ranks 1 Rank 1 Rank
Label Code PC2700R–
25330
PC2700R–
25330
PC2700R–
25330
PC2700R–
25330
Jedec SPD Revision Rev 0.0 Rev 0.0 Rev 0.0 Rev 0.0
Byte# Description HEX HEX HEX HEX
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
SPD Contents
Data Sheet 40 Rev. 1.2, 2004-10
07302003-2MI6-FOP1
76 Part Number, Char 4 31 36 36 33
77 Part Number, Char 5 32 34 34 32
78 Part Number, Char 6 38 33 33 33
79 Part Number, Char 7 33 32 30 30
80 Part Number, Char 8 32 30 30 30
81 Part Number, Char 9 30 48 48 48
82 Part Number, Char 10 48 42 42 42
83 Part Number, Char 11 42 52 52 52
84 Part Number, Char 12 52 36 36 36
85 Part Number, Char 13 36 43 43 43
86 Part Number, Char 14 43 20 20 20
87 Part Number, Char 15 20 20 20 20
88 Part Number, Char 16 20 20 20 20
89 Part Number, Char 17 20 20 20 20
90 Part Number, Char 18 20 20 20 20
91 Module Revision Code xx xx xx xx
92 Test Program Revision Code xx xx xx xx
93 Module Manufacturing Date Year xx xx xx xx
94 Module Manufacturing Date Week xx xx xx xx
95 - 98 Module Serial Number (1 - 4) xx xx xx xx
99 -127 not used FF FF FF FF
Table 19 SPD Codes for HYS72D[128/64/32]3xxHBR–6–C (cont’d)
Product Type & Organization
HYS72D128320HBR–6–C
HYS72D64320HBR–6–C
HYS72D64300HBR–6–C
HYS72D32300HBR–6–C
1 GByte 512 MB 512 MB 256 MB
×72 ×72 ×72 ×72
2 Ranks 2 Ranks 1 Rank 1 Rank
Label Code PC2700R–
25330
PC2700R–
25330
PC2700R–
25330
PC2700R–
25330
Jedec SPD Revision Rev 0.0 Rev 0.0 Rev 0.0 Rev 0.0
Byte# Description HEX HEX HEX HEX
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
SPD Contents
Data Sheet 41 Rev. 1.2, 2004-10
07302003-2MI6-FOP1
Table 20 SPD Codes for HYS72D[128/64/32]3xxGBR–7–C
Product Type & Organization
HYS72D128320GBR–7–C
HYS72D64300GBR–7–C
HYS72D32300GBR–7–C
1 GByte 512 MB 256 MB
×72 ×72 ×72
2Ranks 1Rank 1Rank
Label Code PC2100R–20330 PC2100R–20330 PC2100R–20330
Jedec SPD Revision Rev 0.0 Rev 0.0 Rev 0.0
Byte# Description HEX HEX HEX
0 Programmed SPD Bytes in E2PROM 80 80 80
1 Total number of Bytes in E2PROM 08 08 08
2 Memory Type (DDR = 07h) 07 07 07
3 Number of Row Addresses 0D 0D 0D
4 Number of Column Addresses 0B 0B 0A
5 Number of DIMM Ranks 02 01 01
6 Data Width (LSB) 48 48 48
7 Data Width (MSB) 00 00 00
8 Interface Voltage Levels 04 04 04
9 tCK @ CLmax (Byte 18) [ns] 70 70 70
10 tAC SDRAM @ CLmax (Byte 18) [ns] 75 75 75
11 Error Correction Support 02 02 02
12 Refresh Rate 82 82 82
13 Primary SDRAM Width 04 04 08
14 Error Checking SDRAM Width 04 04 08
15 tCCD [cycles] 01 01 01
16 Burst Length Supported 0E 0E 0E
17 Number of Banks on SDRAM Device 04 04 04
18 CAS Latency 0C 0C 0C
19 CS Latency 01 01 01
20 Write Latency 02 02 02
21 DIMM Attributes 26 26 26
22 Component Attributes C1 C1 C1
23 tCK @ CLmax -0.5 (Byte 18) [ns] 75 75 75
24 tAC SDRAM @ CLmax -0.5 [ns] 75 75 75
25 tCK @ CLmax -1 (Byte 18) [ns] 00 00 00
26 tAC SDRAM @ CLmax -1 [ns] 00 00 00
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
SPD Contents
Data Sheet 42 Rev. 1.2, 2004-10
07302003-2MI6-FOP1
27 tRPmin [ns] 50 50 50
28 tRRDmin [ns] 3C 3C 3C
29 tRCDmin [ns] 50 50 50
30 tRASmin [ns] 2D 2D 2D
31 Module Density per Rank 80 80 40
32 tAS, tCS [ns] 90 90 90
33 tAH, tCH [ns] 90 90 90
34 tDS [ns] 50 50 50
35 tDH [ns] 50 50 50
36 - 40 not used 00 00 00
41 tRCmin [ns] 41 41 41
42 tRFCmin [ns] 4B 4B 4B
43 tCKmax [ns] 30 30 30
44 tDQSQmax [ns] 32 32 32
45 tQHSmax [ns] 75 75 75
46 not used 00 00 00
47 DIMM PCB Height 00 00 00
48 -61 not used 00 00 00
62 SPD Revision 00 00 00
63 Checksum of Byte 0-62 05 04 CB
64 JEDEC ID Code of Infineon (1) C1 C1 C1
65 - 71 JEDEC ID Code of Infineon (2 - 8) 00 00 00
72 Module Manufacturer Location xx xx xx
73 Part Number, Char 1 37 37 37
74 Part Number, Char 2 32 32 32
75 Part Number, Char 3 44 44 44
76 Part Number, Char 4 31 36 33
77 Part Number, Char 5 32 34 32
Table 20 SPD Codes for HYS72D[128/64/32]3xxGBR–7–C (cont’d)
Product Type & Organization
HYS72D128320GBR–7–C
HYS72D64300GBR–7–C
HYS72D32300GBR–7–C
1 GByte 512 MB 256 MB
×72 ×72 ×72
2Ranks 1Rank 1Rank
Label Code PC2100R–20330 PC2100R–20330 PC2100R–20330
Jedec SPD Revision Rev 0.0 Rev 0.0 Rev 0.0
Byte# Description HEX HEX HEX
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
SPD Contents
Data Sheet 43 Rev. 1.2, 2004-10
07302003-2MI6-FOP1
78 Part Number, Char 6 38 33 33
79 Part Number, Char 7 33 30 30
80 Part Number, Char 8 32 30 30
81 Part Number, Char 9 30 47 47
82 Part Number, Char 10 47 42 42
83 Part Number, Char 11 42 52 52
84 Part Number, Char 12 52 37 37
85 Part Number, Char 13 37 43 43
86 Part Number, Char 14 43 20 20
87 Part Number, Char 15 20 20 20
88 Part Number, Char 16 20 20 20
89 Part Number, Char 17 20 20 20
90 Part Number, Char 18 20 20 20
91 Module Revision Code 0x 0x 0x
92 Test Program Revision Code xx xx xx
93 Module Manufacturing Date Year xx xx xx
94 Module Manufacturing Date Week xx xx xx
95 - 98 Module Serial Number (1 - 4) xx xx xx
99 - 127 not used 00 00 00
Table 20 SPD Codes for HYS72D[128/64/32]3xxGBR–7–C (cont’d)
Product Type & Organization
HYS72D128320GBR–7–C
HYS72D64300GBR–7–C
HYS72D32300GBR–7–C
1 GByte 512 MB 256 MB
×72 ×72 ×72
2Ranks 1Rank 1Rank
Label Code PC2100R–20330 PC2100R–20330 PC2100R–20330
Jedec SPD Revision Rev 0.0 Rev 0.0 Rev 0.0
Byte# Description HEX HEX HEX
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
SPD Contents
Data Sheet 44 Rev. 1.2, 2004-10
07302003-2MI6-FOP1
Table 21 SPD Codes for HYS72D[128/64/32]3xxHBR–7–C
Product Type & Organization
HYS72D128320HBR–7–C
HYS72D64300HBR–7–C
HYS72D32300HBR–7–C
1 GByte 512 MB 256 MB
×72 ×72 ×72
2Ranks 1Rank 1Rank
Label Code PC2100R–20330 PC2100R–20330 PC2100R–20330
Jedec SPD Revision Rev 0.0 Rev 0.0 Rev 0.0
Byte# Description HEX HEX HEX
0 Programmed SPD Bytes in E2PROM 80 80 80
1 Total number of Bytes in E2PROM 08 08 08
2 Memory Type (DDR = 07h) 07 07 07
3 Number of Row Addresses 0D 0D 0D
4 Number of Column Addresses 0B 0B 0A
5 Number of DIMM Ranks 02 01 01
6 Data Width (LSB) 48 48 48
7 Data Width (MSB) 00 00 00
8 Interface Voltage Levels 04 04 04
9 tCK @ CLmax (Byte 18) [ns] 70 70 70
10 tAC SDRAM @ CLmax (Byte 18) [ns] 75 75 75
11 Error Correction Support 02 02 02
12 Refresh Rate 82 82 82
13 Primary SDRAM Width 04 04 08
14 Error Checking SDRAM Width 04 04 08
15 tCCD [cycles] 01 01 01
16 Burst Length Supported 0E 0E 0E
17 Number of Banks on SDRAM Device 04 04 04
18 CAS Latency 0C 0C 0C
19 CS Latency 01 01 01
20 Write Latency 02 02 02
21 DIMM Attributes 26 26 26
22 Component Attributes C1 C1 C1
23 tCK @ CLmax -0.5 (Byte 18) [ns] 75 75 75
24 tAC SDRAM @ CLmax -0.5 [ns] 75 75 75
25 tCK @ CLmax -1 (Byte 18) [ns] 00 00 00
26 tAC SDRAM @ CLmax -1 [ns] 00 00 00
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
SPD Contents
Data Sheet 45 Rev. 1.2, 2004-10
07302003-2MI6-FOP1
27 tRPmin [ns] 50 50 50
28 tRRDmin [ns] 3C 3C 3C
29 tRCDmin [ns] 50 50 50
30 tRASmin [ns] 2D 2D 2D
31 Module Density per Rank 80 80 40
32 tAS, tCS [ns] 90 90 90
33 tAH, tCH [ns] 90 90 90
34 tDS [ns] 50 50 50
35 tDH [ns] 50 50 50
36 - 40 not used 00 00 00
41 tRCmin [ns] 41 41 41
42 tRFCmin [ns] 4B 4B 4B
43 tCKmax [ns] 30 30 30
44 tDQSQmax [ns] 32 32 32
45 tQHSmax [ns] 75 75 75
46 not used 00 00 00
47 DIMM PCB Height 00 00 00
48 -61 not used 00 00 00
62 SPD Revision 00 00 00
63 Checksum of Byte 0-62 05 04 CB
64 JEDEC ID Code of Infineon (1) C1 C1 C1
65 - 71 JEDEC ID Code of Infineon (2 - 8) 00 00 00
72 Module Manufacturer Location xx xx xx
73 Part Number, Char 1 37 37 37
74 Part Number, Char 2 32 32 32
75 Part Number, Char 3 44 44 44
76 Part Number, Char 4 31 36 33
77 Part Number, Char 5 32 34 32
Table 21 SPD Codes for HYS72D[128/64/32]3xxHBR–7–C (cont’d)
Product Type & Organization
HYS72D128320HBR–7–C
HYS72D64300HBR–7–C
HYS72D32300HBR–7–C
1 GByte 512 MB 256 MB
×72 ×72 ×72
2Ranks 1Rank 1Rank
Label Code PC2100R–20330 PC2100R–20330 PC2100R–20330
Jedec SPD Revision Rev 0.0 Rev 0.0 Rev 0.0
Byte# Description HEX HEX HEX
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
SPD Contents
Data Sheet 46 Rev. 1.2, 2004-10
07302003-2MI6-FOP1
78 Part Number, Char 6 38 33 33
79 Part Number, Char 7 33 30 30
80 Part Number, Char 8 32 30 30
81 Part Number, Char 9 30 48 48
82 Part Number, Char 10 48 42 42
83 Part Number, Char 11 42 52 52
84 Part Number, Char 12 52 37 37
85 Part Number, Char 13 37 43 43
86 Part Number, Char 14 43 20 20
87 Part Number, Char 15 20 20 20
88 Part Number, Char 16 20 20 20
89 Part Number, Char 17 20 20 20
90 Part Number, Char 18 20 20 20
91 Module Revision Code 0x 0x 0x
92 Test Program Revision Code xx xx xx
93 Module Manufacturing Date Year xx xx xx
94 Module Manufacturing Date Week xx xx xx
95 - 98 Module Serial Number (1 - 4) xx xx xx
99 - 127 not used 00 00 00
Table 21 SPD Codes for HYS72D[128/64/32]3xxHBR–7–C (cont’d)
Product Type & Organization
HYS72D128320HBR–7–C
HYS72D64300HBR–7–C
HYS72D32300HBR–7–C
1 GByte 512 MB 256 MB
×72 ×72 ×72
2Ranks 1Rank 1Rank
Label Code PC2100R–20330 PC2100R–20330 PC2100R–20330
Jedec SPD Revision Rev 0.0 Rev 0.0 Rev 0.0
Byte# Description HEX HEX HEX
Data Sheet 47 Rev. 1.2, 2004-10
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Package Outlines
6 Package Outlines
6.1 Raw Card A
Figure 6 Package Outlines – Raw Card A HYS72D32300[G/H]BR–[5/6/7]–C (1 Rank × 8)
L-DIMM-184-021
6.35
0.1
2.5
±0.1
4
±0.1
16.62
95
64.77
ø0.1ABC
1.27
x=120.65
2.175
A
C
A B
128.95
133.35
B
49.53
92
28.58
±0.13
0.15 BA
C
2.64 MA
X.
1.27
0.4
C
±0.1
±0.13
Detail of contacts
0.2
1.27
±0.2
±0.05
10.1 A
2.5
93
3.8
CB
17.8
10
184
Burr max. 0.4 allowed
3 MIN.
±0.1
1.8 BA
0.1 C
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Package Outlines
Data Sheet 48 Rev. 1.2, 2004-10
6.2 Raw Card C
Figure 7 Package Outlines – Raw Card C HYS72D64300[G/H]BR–[5/6/7]–C (1 Rank × 4)
L-DIMM-184-22-2
128.95
2.5
1
64.77
ø0.1
±0.1
ABC
4±0.1 0.1A
120.65
6.35
1.2795 x =
2.175
49.53
A
CB
133.35
92 B
±0.13
28.58
0.15 BA C
±0.13
±0.05
1
1.27 0.1 ABC
Detail of contacts
0.2
2.5 ±0.2
3.8
93
1.8
±0.1
C
0.1AB
17.8
184
10
1.27
0.4
C
±0.1
4 MAX.
Burr max. 0.4 allowed
3 MIN.
6.62
Data Sheet 49 Rev. 1.2, 2004-10
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Package Outlines
6.3 Raw Card B
Figure 8 Package Outlines – Raw Card B HYS72D64320GBR–[5/6]–C (2 Ranks ×8)
L-DIMM-184-23
4 MAX.
1.27
C
±0.1
0.4
0.1
ø0.1
±0.1
2.5
±0.1
4
1
x95
C
64.77
AB
120.651.27 =
2.175 6.35
A
B CA
133.35
128.95
49.53
92
0.15
C
AB
±0.13
B
28.58
BA
0.1 C
1.8
C
1B
0.1 A
Detail of contacts
0.2
1.27
3.8
±0.13
93
±0.2
2.5
±0.05
17.8
184
10
±0.1
3 MIN.
Burr max. 0.4 allowed
6.62
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Package Outlines
Data Sheet 50 Rev. 1.2, 2004-10
6.4 Raw Card D
Figure 9 Package Outlines – Raw Card D HYS72D128320[G/H]BR–[6/7]–C (2 Ranks ×4)
L-DIMM-184-24-3
192
93 184
17.8
10
3.8
±0.13
3 MIN.
A
±0.1
1.8 0.1 CB
±0.05
1
1.27 CA
0.1 B
0.2
Detail of contacts
2.5 ±0.2
A
4
±0.1 0.1 BC
±0.1
2.5 ø0.1ABC 6.62
2.175
1.27
64.77
95 x 120.65=
6.35 49.53
B
±0.13
30.48
128.95
AA
133.35 0.15 ABC
4 MAX.
1.27
0.4
C
±0.1
Burr max. 0.4 allowed
Data Sheet 51 Rev. 1.2, 2004-10
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Application Note
7 Application Note
Power Up and Power Management on DDR Registered DIMMs (according to JEDEC ballot JC-42.5 Item
1173)
184-pin Double Data Rate (DDR) Registered DIMMs include two new features to facilitate controlled power-up and
to minimize power consumption during low power mode. One feature is externally controlled via a system-
generated RESET signal; the second is based on module detection of the input clocks. These enhancements
permit the modules to power up with SDRAM outputs in a High-Z state (eliminating risk of high current dissipations
and/or dotted I/Os), and result in the powering-down of module support devices (registers and Phase-Locked
Loop) when the memory is in Self-Refresh mode.
The new RESET pin controls power dissipation on the module’s registers and ensures that CKE and other SDRAM
inputs are maintained at a valid ‘low’ level during power-up and self refresh. When RESET is at a low level, all the
register outputs are forced to a low level, and all differential register input receivers are powered down, resulting
in very low register power consumption. The RESET pin, located on DIMM tab #10, is driven from the system as
an asynchronous signal according to the attached details. Using this function also permits the system and DIMM
clocks to be stopped during memory Self Refresh operation, while ensuring that the SDRAMs stay in Self Refresh
mode.
As described in the table above, a low on the RESET input ensures that the Clock Enable (CKE) signal(s) are
maintained low at the SDRAM pins (CKE being one of the 'Q' signals at the register output). Holding CKE low
maintains a high impedance state on the SDRAM DQ, DQS and DM outputs — where they will remain until
activated by a valid ‘read’ cycle. CKE low also maintains SDRAMs in Self Refresh mode when applicable.
The DDR PLL devices automatically detect clock activity above 20MHz. When an input clock frequency of 20MHz
or greater is detected, the PLL begins operation and initiates clock frequency lock (the minimum operating
frequency at which all specifications will be met is 95MHz). If the clock input frequency drops below 20MHz (actual
detect frequency will vary by vendor), the PLL VCO (Voltage Controlled Oscillator) is stopped, outputs are made
High-Z, and the differential inputs are powered down — resulting in a total PLL current consumption of less than
1mA. Use of this low power PLL function makes the use of the PLL RESET (or G pin) unnecessary, and it is tied
inactive on the DIMM.
This application note describes the required and optional system sequences associated with the DDR Registered
DIMM 'RESET' function. It is important to note that all references to CKE refer to both CKE0 and CKE1 for a 2-
bank DIMM. Because RESET applies to all DIMM register devices, it is therefore not possible to uniquely control
CKE to one physical DIMM bank through the use of the RESET pin.
Table 22 RESET Truth Table
Register Inputs Register
Outputs
RESET CK CK Data in (D) Data out (Q)
H Rising Falling H H
H Rising Falling L L
H L or H L or H X Qo
H High Z High Z X Illegal input
conditions
L X or Hi-Z X or Hi-Z X or Hi-Z L
X: Don’t care, Hi-Z: High Impedance, Qo: Data latched at the previous of CK rising and CK falling
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Application Note
Data Sheet 52 Rev. 1.2, 2004-10
Power-Up Sequence with RESET — Required
1. The system sets RESET at a valid low level.
This is the preferred default state during power-up. This input condition forces all register outputs to a low state
independent of the condition on the register inputs (data and clock), ensuring that CKE is at a stable low-level
at the DDR SDRAMs.
2. The power supplies should be initialized according to the JEDEC-approved initialization sequence for DDR
SDRAMs.
3. Stabilization of Clocks to the SDRAM
The system must drive clocks to the application frequency (PLL operation is not assured until the input clock
reaches 20 MHz). Stability of clocks at the SDRAMs will be affected by all applicable system clock devices,
and time must be allotted to permit all clock devices to settle. Once a stable clock is received at the DIMM PLL,
the required PLL stabilization time (assuming power to the DIMM is stable) is 100 microseconds. When a
stable clock is present at the SDRAM input (driven from the PLL), the DDR SDRAM requires 200 µsec prior to
SDRAM operation.
4. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM
connector).
CKE must be maintained low and all other inputs should be driven to a known state. In general these
commands can be determined by the system designer. One option is to apply an SDRAM ‘NOP’ command
(with CKE low), as this is the first command defined by the JEDEC initialization sequence (ideally this would
be a ‘NOP Deselect’ command). A second option is to apply low levels on all of the register inputs to be
consistent with the state of the register outputs.
5. The system switches RESET to a logic ‘high’ level.
The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous,
setting the RESET timing in relation to a specific clock edge is not required (during this period, register inputs
must remain stable).
6. The system must maintain stable register inputs until normal register operation is attained.
The registers have an activation time that allows their clock receivers, data input receivers, and output drivers
sufficient time to be turned on and become stable. During this time the system must maintain the valid logic
levels described in step 5. It is also a functional requirement that the registers maintain a low state at the CKE
outputs to guarantee that the DDR SDRAMs continue to receive a low level on CKE. Register activation time
(t (ACT) ), from asynchronous switching of RESET from low to high until the registers are stable and ready to
accept an input signal, is specified in the register and DIMM do-umentation.
7. The system can begin the JEDEC-defined DDR SDRAM power-up sequence (according to the JEDEC-
pproved initialization sequence).
Self Refresh Entry (RESET low, clocks powered off) — Optional
Self Refresh can be used to retain data in DDR SDRAM DIMMs even if the rest of the system is powered down
and the clocks are off. This mode allows the DDR SDRAMs on the DIMM to retain data without external clocking.
Self Refresh mode is an ideal time to utilize the RESET pin, as this can reduce register power consumption
(RESET low deactivates register CK and CK, data input receivers, and data output drivers).
1. 1. The system applies Self Refresh entry command.
(CKE→Low, CS→Low, RAS → Low, CAS→ Low, WE→ High)
Note: Note: The commands reach the DDR SDRAM one clock later due to the additional register pipelining on a
Registered DIMM. After this command is issued to the SDRAM, all of the address and control and clock input
conditions to the SDRAM are Don’t Cares— with the exception of CKE.
2. The system sets RESET at a valid low level.
This input condition forces all register outputs to a low state, independent of the condition on the registerm
inputs (data and clock), and ensures that CKE, and all other control and address signals, are a stable low-level
at the DDR SDRAMs. Since the RESET signal is asynchronous, setting the RESET timing in relation to a
specific clock edge is not required.
3. The system turns off clock inputs to the DIMM. (Optional)
a. In order to reduce DIMM PLL current, the clock inputs to the DIMM are turned off, resulting in High-Z clock
Data Sheet 53 Rev. 1.2, 2004-10
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Application Note
inputs to both the SDRAMs and the registers. This must be done after the RESET deactivate time of the
register (t (INACT). The deactivate time defines the time in which the clocks and the control and address
signals must maintain valid levels after RESET low has been applied and is specified in the register and DIMM
documentation.
b.The system may release DIMM address and control inputs to High-Z.
This can be done after the RESET deactivate time of the register. The deactivate time defines the time in which
the clocks and the control and the address signals must maintain valid levels after RESET low has been
applied. It is highly recommended that CKE continue to remain low during this operation.
4. The DIMM is in lowest power Self Refresh mode.
Self Refresh Exit (RESET low, clocks powered off) — Optional
1. Stabilization of Clocks to the SDRAM.
The system must drive clocks to the application frequency (PLL operation is not assured until the input clock
reaches ~20MHz). Stability of clocks at the SDRAMs will be affected by all applicable system clock devices,
and time must be allotted to permit all clock devices to settle. Once a stable clock is received at the DIMM PLL,
the required PLL stabilization time (assuming power to the DIMM is stable) is 100 microseconds.
2. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM
connector).
CKE must be maintained low and all other inputs should be driven to a known state. In general these
commands can be determined by the system designer. One option is to apply an SDRAM ‘NOP’ command
(with CKE low), as this is the first command defined by the JEDEC Self Refresh Exit sequence (ideally this
would be a ‘NOP Deselect’ command). A second option is to apply low levels on all of the register inputs, to
be consistent with the state of the register outputs.
3. The system switches RESET to a logic ‘high’ level.
The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous,
RESET timing relationship to a specific clock edge is not required (during this period, register inputs must
remain stable).
4. The system must maintain stable register inputs until normal register operation is attained.
The registers have an activation time that allows the clock receivers, input receivers, and output drivers
sufficient time to be turned on and become stable. During this time the system must maintain the valid logic
levels described in Step 2. It is also a functional requirement that the registers maintain a low state at the CKE
outputs to guarantee that the DDR SDRAMs continue to receive a low level on CKE. Register activation time
(t (ACT) ), from asynchronous switching of RESET from low to high until the registers are stable and ready to
accept an input signal, is specified in the register and DIMM do-umentation.
5. System can begin the JEDEC-defined DDR SDRAM Self Refresh Exit Procedure.
Self Refresh Entry (RESET low, clocks running) — Optional
Although keeping the clocks running increases power consumption from the on-DIMM PLL during self refresh, this
is an alternate operating mode for these DIMMs.
1. 1. System enters Self Refresh entry command.
(CKE→ Low, CS→ Low, RAS→ Low, CAS→ Low, WE→ High)
Note: Note: The commands reach the DDR SDRAM one clock later due to the additional register pipelining on a
Registered DIMM. After this command is issued to the SDRAM, all of the address and control and clock input
conditions to the SDRAM are Don’t Cares — with the exception of CKE.
2. The system sets RESET at a valid low level.
This input condition forces all register outputs to a low state, independent of the condition on the data and clock
register inputs, and ensures that CKE is a stable low-level at the DDR SDRAMs.
3. The system may release DIMM address and control inputs to High-Z.
This can be done after the RESET deactivate time of the register (t (INACT) ). The deactivate time describes
the time in which the clocks and the control and the address signals must maintain valid levels after RESET
low has been applied. It is highly recommended that CKE continue to remain low during the operation.
4. The DIMM is in a low power, Self Refresh mode.
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Application Note
Data Sheet 54 Rev. 1.2, 2004-10
Self Refresh Exit (RESET low, clocks running) — Optional
1. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM
connector). CKE must be maintained low and all other inputs should be driven to a known state. In general
these commands can be determined by the system designer. One option is to apply an SDRAM ‘NOP’
command (with CKE low), as this is the first command defined by the Self Refresh Exit sequence (ideally this
would be a ‘NOP Deselect’ command). A second option is to apply low levels on all of the register inputs to be
consistent with the state of the register outputs.
2. The system switches RESET to a logic 'high' level.
The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous,
it does not need to be tied to a particular clock edge (during this period, register inputs must continue to remain
stable).
3. The system must maintain stable register inputs until normal register operation is attained.
The registers have an activation time that allows the clock receivers, input receivers, and output drivers
sufficient time to be turned on and become stable. During this time the system must maintain the valid logic
levels described in Step 1. It is also a functional requirement that the registers maintain a low state at the CKE
outputs in order to guarantee that the DDR SDRAMs continue to receive a low level on CKE. This activation
time, from asynchronous switching of RESET from low to high, until the registers are stable and ready to accept
an input signal, is t (ACT ) as specified in the register and DIMM documentation.
4. The system can begin JEDEC defined DDR SDRAM Self Refresh Exit Procedure.
Self Refresh Entry/Exit (RESET high, clocks running) — Optional
As this sequence does not involve the use of the RESET function, the JEDEC standard SDRAM specification
explains in detail the method for entering and exiting Self Refresh for this case.
Self Refresh Entry (RESET high, clocks powered off) — Not Permissible
In order to maintain a valid low level on the register output, it is required that either the clocks be running and the
system drive a low level on CKE, or the clocks are powered off and RESET is asserted low according to the
sequence defined in this application note. In the case where RESET remains high and the clocks are powered off,
the PLL drives a High-Z clock input into the register clock input. Without the low level on RESET an unknown DIMM
state will result.
