W965L6ABN 2M WORD x 16 BIT LOW POWER PSEUDO SRAM Table of Contents1. GENERAL DESCRIPTION.................................................................................................................. 3 2. FEATURES ......................................................................................................................................... 3 3. PRODUCT OPTIONS ......................................................................................................................... 3 4. BALL CONFIGURATION .................................................................................................................... 4 5. BALL DESCRIPTION .......................................................................................................................... 4 6. BLOCK DIAGRAM .............................................................................................................................. 5 7. FUNCTION TRUTH TABLE ................................................................................................................ 6 8. ELECTRICAL CHARACTERISTICS ................................................................................................... 7 Absolute Maximum Ratings .............................................................................................................. 7 Recommended Operating Conditions............................................................................................... 7 Capacitance ...................................................................................................................................... 8 DC Characteristics ............................................................................................................................ 8 AC Characteristics ............................................................................................................................ 9 Read Operation ..........................................................................................................................................9 Write Operation.........................................................................................................................................11 Power Down and Power Down Program Parameters ...............................................................................13 Other Timing Parameters .........................................................................................................................13 AC Test Conditions...................................................................................................................................13 9. TIMING WAVEFORMS ..................................................................................................................... 14 Read Timing #1( OE Control Access)............................................................................................ 14 Read Timing #2 ( CE1 Control Access) ......................................................................................... 15 Read Timing #3 (Address Access after OE Control Access)....................................................... 16 Read Timing #4 (Address Access after CE1 Control Access) ..................................................... 17 Write Timing #1 ( CE1 Control) ...................................................................................................... 18 Write Timing #2-1 ( WE Control, Single Write Operation) ............................................................. 19 Write Timing #2 ( WE Control, Continuous Write Operation)......................................................... 20 Read/Write Timing #1-1 ( CE1 Control) .......................................................................................... 21 -1- Publication Release Date: March 14, 2003 Revision A1 W965L6ABN Read/Write Timing #1-2 ( CE1 Control) .......................................................................................... 22 Read ( OE Control) / Write ( WE Control) Timing #2-1................................................................. 23 Read ( OE Control) / Write ( WE Control) Timing #2-2................................................................. 24 Power Down Program Timing ......................................................................................................... 25 Power Down Entry and Exit Timing................................................................................................. 25 Power-up Timing #1 ........................................................................................................................ 25 Power-up Timing #2 ........................................................................................................................ 26 Standby Entry Timing after Read or Write ...................................................................................... 26 Data Retention ................................................................................................................................ 27 Low VDD Characteristics...........................................................................................................................27 Data Retention Timing ..............................................................................................................................27 10. PACKAGE DIMENSION.................................................................................................................. 28 TFBGA 48 Balls (6 x 8 mm^2, pitch 0.75 mm)................................................................................ 28 11. ORDERING INFORMATION........................................................................................................... 29 12. VERSION HISTORY ....................................................................................................................... 30 -2- W965L6ABN 1. GENERAL DESCRIPTION W965L6ABN is a 32M bits CMOS pseudo static random access memory (Pseudo SRAM), organized as 2M words x 16 bits. Using advanced single transistor DRAM architecture and 0.175 m process technology; W964L6BN delivers fast access cycle time and low power consumption. It is suitable for mobile device application such as Cellular Phone and PDA, which high-density buffer is needed and power dissipation is most concerned. 2. FEATURES * Asynchronous SRAM interface * Wide operating conditions: VDD = +2.3V to +2.7V or * Fast access cycle time: tRC = 70 nS (-70), 80 nS (-80) +2.7V to +3.3V * Low power consumption: * Temperature IDDA1 = 25 mA max. TA = 0C to +70C IDDS1 = 100 A max. TA = -25C to +85C (Extended temperature) TA = -40C to +85C (Industrial temperature) * Byte write control 3. PRODUCT OPTIONS PARAMETER W965L6ABN70 W965L6ABN80 tRC 70 nS Min. 80 nS Min. IDDS1 100 A Max. 100 A Max. IDDA1 25 mA 25 mA 2.3V to 2.7V 2.3V to 2.7V 2.7V to 3.3V 2.7V to 3.3V VDD -3- Publication Release Date: March 14, 2003 Revision A1 W965L6ABN 4. BALL CONFIGURATION Top view 1 2 3 4 5 6 A LB OE A0 A1 A2 CE2 B DQ9 UB A3 A4 CE1 DQ1 C DQ10 DQ11 A5 A6 DQ2 DQ3 D VSS DQ12 A17 A7 DQ4 VDD E VDD DQ13 NC A16 DQ5 VSS F DQ15 DQ14 A14 A15 DQ6 DQ7 G DQ16 A19 A12 A13 WE DQ8 H A18 A8 A9 A10 A11 A20 ( FBGA48 , 8 x 10mm , pitch 0.75mm ) 5. BALL DESCRIPTION SYMBOL A0 - A20 DESCRIPTION Address Input CE1 Chip Enable Input 1, Low: Enable CE2 Chip Enable Input 2, High: Enable, Low: Enter Power Down Mode WE Write Enable Input OE Output Enable Input LB Lower Byte Write Control UB Upper Byte Write Control I/O0 - I/O15 VDD VSS NC Data Inputs/Outputs Power Supply Ground No Connection -4- W965L6ABN 6. BLOCK DIAGRAM VDD VSS A0 to A18 DQ1 to DQ8 DQ9 to DQ16 ADDRESS LATCH & BUFFER ROW DECODER MEMORY CELL ARRAY 33,554,432 bits INPUT / OUTPUT BUFFER INPUT DATA LATCH & CONTROL SENSE / SWITCH OUTPUT DATA CONTROL COLUMN / DECODER ADDRESS LATCH & BUFFER CE2 PE CE1 POWER CONTROL TIMING CONTROL WE LB UB OE -5- Publication Release Date: March 14, 2003 Revision A1 W965L6ABN 7. FUNCTION TRUTH TABLE MODE NOTE CE2 Standby (Deselect) Output Disable CE1 WE OE LB UB A0-18 DQ1-8 DQ9-16 IDD DATA RETENTION H X X X X X High-Z High-Z IDDS Yes H H X X *5 High-Z High-Z H H Valid High-Z High-Z H L L *4 Valid Output Output Valid Valid H L Valid IDDA Yes L H Valid L L Valid X X X IDDP No/Yes *1 No Read Read *2 Write (Upper Byte) H L L Write (Lower Byte) H Write (Word) Power Down *3 L X X X Invalid Input Valid Input Valid Invalid Input Input Valid Valid High-Z High-Z Notes: L = VIL, H = VIH, X can be either VIL or VIH, High-Z = High impedance, KEY = Key Address. *1: Output Disable mode should not be kept longer than 1S. *2: Byte control at Read mode is not supported. *3: Power Down mode can be entered from Standby state and all DQ pins are in High-Z state. IDDP current and data retention depend on the selection of Power Down Program. *4: Either or both LB and UB must be Low for Read operation. *5: Can be either VIL or VIH but must be valid before Read or Write. -6- W965L6ABN 8. ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings PARAMETER SYMBOL VALUE UNIT VDD -0.5 to +3.6 V VIN, VOUT -0.5 to +3.6 V Short Circuit Output Current IOUT 50 mA Storage Temperature TSTG -55 to +125 C Voltage of VDD Supply Relative to VSS Voltage at Any Pin Relative to VSS WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Recommended Operating Conditions (Reference to VSS) PARAMETER NOTES SYMBOL MIN. MAX. UNIT VDD (27) 2.7 3.3 V VDD (23) 2.3 2.7 V VSS 0 0 V VIH (27) 2.2 VDD + 0.3 V VIH (23) 2.0 VDD + 0.3 V VIL (27) -0.3 0.5 V VIL (23) -0.3 0.4 V Ambient Temperature TA 0 70 C Ambient Temperature TA -25 85 C Ambient Temperature TA -40 85 C Supply Voltage High Level Input Voltage *1 Low Level Input Voltage *2 Notes: *1: Maximum DC voltage on input and I/O pins are VDD +0.3V. During voltage transitions, inputs may positive overshoot to VDD +1.0V for periods of up to 5 nS. *2: Minimum DC voltage on input and I/O pins are -0.3V. During voltage transitions, inputs may negative overshoot to 1.0V for periods of up to 5 nS. WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the datasheet. Users considering application outside the listed conditions are advised to contact their Winbond representative beforehand. -7- Publication Release Date: March 14, 2003 Revision A1 W965L6ABN Capacitance Test conditions: TA = 25C, f = 1.0 MHz SYMBOL DESCRIPTION TEST SETUP TYP. MAX. UNIT CIN1 Address Input Capacitance VIN = 0V - 5 pF CIN2 Control Input Capacitance VIN = 0V - 5 pF CIO Data Input/Output Capacitance VIO = 0V - 8 pF DC Characteristics (Under Recommended Operating Conditions unless otherwise noted) PARAMETER SYM. notes *1, *2, *3 TEST CONDITIONS MIN. MAX. UNIT Input Leakage Current ILI VIN = VSS to VDD -1.0 +1.0 A Output Leakage Current ILO VOUT = VSS to VDD, Output Disable -1.0 +1.0 A VOH (27) VDD = VDD (27), IOH = -0.5 mA 2.2 - V VOH (23) VDD = VDD (23), IOH = -0.5 mA 1.8 - V Output High Voltage Level Output Low Voltage Level (TTL) VOL IOL = 1mA - 0.4 V IDDS VDD = VDD Max., VIN = VIH or VIL - 3 mA - 100 A CE1 = CE2 = VIH Standby Current (CMOS) IDDS1 VDD = VDD Max., VIN 0.2V or VIN VDD -0.2V, CE1 = CE2 VDD -0.2V IDDA1 VDD = VDD Max., VIN = VIH or VIL, tRC / tWC = Minimum - 25 mA IDDA2 CE1 = VIL and CE2 = VIH, IOUT = 0 mA tRC / tWC = 1S - 3 mA Active Current Notes: *1: All voltages are reference to VSS. *2: DC Characteristics are measured after following POWER-UP timing. *3: IOUT depends on the output load conditions. -8- W965L6ABN AC Characteristics (Under Recommended Operating Conditions unless otherwise noted) Read Operation PARAMETER SYM. -70 -80 Min. Max. Min. Max. UNIT NOTES Read Cycle Time tRC 70 - 80 - nS Chip Enable Access Time tCE - 65 - 75 nS *1, *3 Output Enable Access Time tOE - 40 - 45 nS *1 Address Access Time tAA - 65 - 75 nS *1 Output Data Hold Time tOH 5 - 5 - nS *1 CE1 Low to Output Low-Z tCLZ 5 - 5 - nS *2 OE Low to Output Low-Z tOLZ 0 - 0 - nS *2 CE1 High to Output High-Z tCHZ - 20 - 25 nS *2 OE High to Output High-Z tOHZ - 20 - 25 nS *2 Address Setup Time to CE1 Low tASC -5 - -5 - nS *4 tASO 30 - 35 - nS *3, *5 tASO[ABS] 10 - 10 - nS *6 LB / UB Setup Time to CE1 Low tBSC -5 - -5 - nS LB / UB Setup Time to OE Low tBSO 10 - 10 - nS Address Invalid Time tAX - 5 - 5 nS Address Hold Time from CE1 Low tCLAH 70 - 80 - nS Address Hold Time from OE Low tOLAH 40 - 45 - nS Address Hold Time from CE1 High tCHAH -5 - -5 - nS Address Hold Time from OE High tOHAH -5 - -5 - nS LB / UB Hold Time from CE1 High tCHBH -5 - -5 - nS LB / UB Hold Time from OE High tOHBH -5 - -5 - nS CE1 Low to OE Low Delay Time tCLOL 25 1000 30 1000 nS *3, *5, *7, *8 OE Low to CE1 High Delay Time tOLCH 35 - 40 - nS *7 tCP 12 - 15 - nS tOP 25 1000 30 1000 nS *5, *7, *8 tOP[ABS] 12 - 15 - nS *6 Address Setup Time to OE Low CE1 High Pulse Width OE High Pulse Width -9- *9 Publication Release Date: March 14, 2003 Revision A1 W965L6ABN Read Operation, Continued Notes: *1: The output load is 50 pF at VDD (27) and 30pF at VDD (23). *2: The output load is 5 pF. *3: The tCE is applicable if OE is brought to Low before CE1 goes Low and is also applicable if actual value of both or either tASO or tCLOL is shorter than specified value. *4: Applicable if OE is brought to Low before CE1 goes Low. *5: The tASO, tCLOL(min.) and tOP(min.) are reference values when the access time is determined by tOE. If actual value of each parameter is shorter than specified minimum value, tOE become longer by the amount of subtracting actual value from specified minimum value. For example, if actual tASO, tASO(actual), is shorter than specified minimum value, tASO(min.), during OE control access (ie., CE1 stays Low), the tOE become tOE(max) + tASO(min.) - tASO(actual). *6: The tASO[ABS] and tOP[ABS] is the absolute minimum value during OE control access. *7: If actual value of either tCLOL or tOP is shorter than specified minimum value, both tOLAH and tOLCH become tRC(min.) tCLOL(actual) or tRC(min) - tOP(actual). *8: Maximum value is applicable if CE1 is kept at low. - 10 - W965L6ABN AC Characteristics, Continued Write Operation PARAMETER SYM. -70 -80 Min. Max. Min. Max. UNIT NOTES Write Cycle Time tWC 70 - 80 - nS *1 Address Setup Time tAS 0 - 0 - nS *2 Address Hold Time tAH 35 - 40 - nS *2 CE1 Write Setup Time tCS 0 1000 0 1000 nS CE1 Write Hold Time tCH 0 1000 0 1000 nS WE Setup Time tWS 0 - 0 - nS WE Hold Time tWH 0 - 0 - nS LB and UB Setup Time tBS -5 - -5 - nS LB and UB Hold Time tBH -5 - -5 - nS OE Setup Time tOES 0 1000 0 1000 nS *3 tOEH 30 1000 35 1000 nS *3, *4 tOEH[ABS] 12 - 15 - nS *5 OE High to CE1 Low Setup Time tOHCL -5 - -5 - nS *6 OE High to Address Hold Time tOHAH -5 - -5 - nS *7 CE1 Write Pulse Width tCW 45 - 50 - nS *1, *8 WE Write Pulse Width TWP 45 - 50 - nS *1, *8 CE1 Write Recovery Time tWRC 10 - 15 - nS *1, *9 WE Write Recovery Time tWR 10 1000 15 1000 nS *1, *3, *9 Data Setup Time tDS 15 - 20 - nS Data Hold Time tDH 0 - 0 - nS CE1 High Pulse Width tCP 12 - 15 - nS OE Hold Time - 11 - *9 Publication Release Date: March 14, 2003 Revision A1 W965L6ABN Write Operation, Continued Notes: *1: Minimum value must be equal or greater than the sum of actual tCW (or tWP) and tWRC (or tWR). *2: New write address is valid from either CE1 or WE is brought to High. *3: The tOEH is specified from end of tWC(min.). The tOEH(min.) is a reference value when the access time is determined by tOE. If actual value, tOEH(actual) is shorter than specified minimum value, tOE become longer by the amount of subtracting actual value from specified minimum value. *4: The tOEH(max.) is applicable if CE1 is kept at Low and both WE and OE are kept at High. *5: The tOEH[ABS] is the absolute minimum value if write cycle is terminated by WE and CE1 *6: tOHCL(min.) must be satisfied if read operation is not performed prior to write operation. stays Low. In case OE is disabled after tOHCL(min.), WE Low must be asserted after tRC(min.) from CE1 Low. In other words, read operation is initiated if tOHCL(min.) is not satisfied. *7: Applicable if CE1 stays Low after read operation. *8: tCW and tWP is applicable if write operation is initiated by CE1 and WE , respectively. *9: tWRC and tWR is applicable if write operation is terminated by CE1 and WE , respectively. The tWR(min.) can be ignored if CE1 is brought to High together or after WE is brought to High. In such case, the tCP(min.) must be satisfied. - 12 - W965L6ABN AC Characteristics, Continued Power Down and Power Down Program Parameters PARAMETER SYM. -70 -80 Min. Max. Min. Max. UNIT NOTES CE2 Low Setup Time for Power Down Entry tCSP 10 - 10 - nS CE2 Low Hold Time after Power Down Entry tC2LP 70 - 80 - nS CE1 High Setup Time following CE2 High after Power Down Exit tCHS 10 - 10 - nS CE1 High to PE Low Setup Time tEPS 70 - 80 - nS Min. Max. Min. Max. *1 Note: *1: Applicable to Power Down Program Other Timing Parameters -70 -80 UNIT NOTES PARAMETER SYM. CE1 High to OE Invalid Time for Standby Entry tCHOX 10 - 10 - nS CE1 High to WE Invalid Time for Standby Entry tCHWX 10 - 10 - nS *1 CE2 Low Hold Time after Power-up tC2LH 50 - 50 - S *2 CE2 High Hold Time after Power-up tC2HL 50 - 50 - S *3 CE1 High Hold Time following CE2 High after Power-up tCHH 350 - 350 - S *2 tT 1 25 1 25 nS *4 Input Transition Time Notes: *1: Some data might be written into any address location if tCHWX(min.) is not satisfied. *2: Must satisfy tCHH(min.) after tC2LH(min.). *3: Requires Power Down mode entry and exit after tC2HL. *4: The Input Transition Time (tT) at AC testing is 5 nS as shown in below. If actual tT is longer than 5 nS, it may violate AC specified of some timing parameters. AC Test Conditions SYMBOL DESCRIPTION VIH Input High Level VIL Input Low Level VREF TT Input Timing Measurement Level Input Transition Time TEST SETUP VALUE VDD = 2.7V to 3.3V 2.3 VDD = 2.3V to 2.7V 2.0 VDD = 2.7V to 3.3V 0.4 VDD = 2.3V to 2.7V 0.4 VDD = 2.7V to 3.3V 1.3 VDD = 2.3V to 2.7V Between VIL and VIH 1.1 - 13 - 5 UNIT NOTE V V V nS Publication Release Date: March 14, 2003 Revision A1 W965L6ABN 9. TIMING WAVEFORMS Read Timing #1( OE Control Access) tRC ADDRESS tRC ADDRESS VALID ADDRESS VALID tCE tOHAH tASO tOHAH CE1 tOLCH tCLOL OE tOE tOP tOE tASO tBSO tOHBH tBSO tOHBH LB / UB tOHZ tOH tOLZ tOLZ tOHZ tOH DQ (Output) VALID DATA OUTPUT Note: CE2, PE and WE must be High for entire read cycle. Either or both LB and UB must be Low when both CE1 and OE are Low. - 14 - VALID DATA OUTPUT W965L6ABN Timing Waveforms, Continued Read Timing #2 ( CE1 Control Access) tRC ADDRESS tRC ADDRESS VALID tASC tCE ADDRESS VALID tCHAH tASC tCE tCHAH CE1 tCP OE tBSC tCHBH tBSC tCHBH LB / UB tOLZ tCHZ tOH tCLZ tCHZ tOH DQ (Output) VALID DATA OUTPUT Note: VALID DATA OUTPUT CE2, PE and WE must be High for entire read cycle. Either or both LB and UB must be Low when both CE1 and OE are Low. - 15 - Publication Release Date: March 14, 2003 Revision A1 W965L6ABN Timing Waveforms, Continued Read Timing #3 (Address Access after OE Control Access) ADDRESS tRC tRC ADDRESS VALID ADDRESS VALID tASO tOLAH tAX tAA tOHAH CE1 tOE tOHZ OE tOHBH tBSO LB / UB tOLZ tOH tOH DQ (Output) VALID DATA OUTPUT Note: CE2, PE and WE must be High for entire read cycle. Either or both LB and UB must be Low when both CE1 and OE are Low. - 16 - VALID DATA OUTPUT W965L6ABN Timing Waveforms, Continued Read Timing #4 (Address Access after CE1 Control Access) ADDRESS tRC tRC ADDRESS VALID ADDRESS VALID tASC tCLAH tAX tAA tCHAH CE1 tCE tCHZ OE tCHBH tBSC LB / UB tCLZ tOH tOH DQ (Output) VALID DATA OUTPUT Note: VALID DATA OUTPUT CE2, PE and WE must be High for entire read cycle. Either or both LB and UB must be Low when both CE1 and OE are Low. - 17 - Publication Release Date: March 14, 2003 Revision A1 W965L6ABN Timing Waveforms, Continued Write Timing #1 ( CE1 Control) tWC ADDRESS ADDRESS VALID tAS tAS tAH CE1 tWS tWC tWRC tWH tWS tBH tBS WE tBS LB / UB tOHCL OE tDS tDH DQ (Intput) VALID DATA INTPUT Note: CE2 and PE must be High for entire write cycle. - 18 - W965L6ABN Timing Waveforms, Continued Write Timing #2-1 ( WE Control, Single Write Operation) tWC ADDRESS tOHAH tAS ADDRESS VALID tAH tCS tWP tAS tCH CE1 tCP tOHCL tWR WE tBH tBS tBH LB / UB tOES OE tOHZ tDS tDH DQ (Intput) VALID DATA INTPUT Note: CE2 and PE must be High for entire write cycle. - 19 - Publication Release Date: March 14, 2003 Revision A1 W965L6ABN Timing Waveforms, Continued Write Timing #2 ( WE Control, Continuous Write Operation) tWC ADDRESS ADDRESS VALID tOHAH tAS tAH tAS CE1 tOHCL tCS tWP tWR WE tOHBH tBS tBH LB / UB tOES OE tOHZ tDS tDH DQ (Intput) VALID DATA INTPUT Note: CE2 and PE must be High for entire write cycle. - 20 - tBS W965L6ABN Timing Waveforms, Continued Read/Write Timing #1-1 ( CE1 Control) tWC ADDRESS ADDRESS VALID tCHAH tAS tAH tAS CE1 tCP tWH tCW tWRC tWS tWH tWS tCLOL WE tCHBH tBS tBH tBSO LB / UB tOHCL OE tCHZ tOH tDS tDH tOLZ DQ (Intput) VALID DATA INTPUT VALID DATA INTPUT Note: Write address is valid from either CE1 or WE of last falling edge. - 21 - Publication Release Date: March 14, 2003 Revision A1 W965L6ABN Timing Waveforms, Continued Read/Write Timing #1-2 ( CE1 Control) tRC ADDRESS ADDRESS VALID tWRC CE1 tASC WRITE ADDRESS tCHAH tWRC(min) tWH tWS tAS tCP tWS tWH WE tBH tBSC tOE tBS tCHBH LB / UB tOEH tOHCL OE tCHZ tDH tCLZ tOH DQ VALID DATA OUTPUT VALID DATA OUTPUT Note: The tOEH is specified from the time satisfied both tWRC and tWR(min.). - 22 - W965L6ABN Timing Waveforms, Continued Read ( OE Control) / Write ( WE Control) Timing #2-1 tWC ADDRESS WRITE ADDRESS tOHAH CE1 tAS READ ADDRESS tAH tASO Low tWP tWR tOEH WE tOHBH tBS tBH tOEH LB / UB tOES OE tOHZ tOH tDS tDH tOLZ DQ (Intput) VALID DATA INTPUT VALID DATA INTPUT Note: CE1 can be tied to Low for WE and OE controlled operation. When CE1 is tied to Low, output is exclusively controlled by OE . - 23 - Publication Release Date: March 14, 2003 Revision A1 W965L6ABN Timing Waveforms, Continued Read ( OE Control) / Write ( WE Control) Timing #2-2 tRC ADDRESS ADDRESS VALID tASO CE1 WRITE ADDRESS tOHAH tAS tOHBH tBS Low tWR tOEH WE tBH tBSO LB / UB tOE tOES OE tOHZ tDH tOLZ tOH DQ VALID DATA OUTPUT Note: VALID DATA OUTPUT CE1 can be tied to Low for WE and OE controlled operation. When CE1 is tied to Low, output is exclusively controlled by OE . - 24 - W965L6ABN Timing Waveforms, Continued Power Down Program Timing CE1 tEPS tEP tEPH PE tEAS ADDRESS (A20-16) Note: tEAH KEY CE2 must be High for Power Down Program operation. Any other inputs not specified above can be either High or Low. Power Down Entry and Exit Timing CE1 tCHS CE2 tCSP tC2LP tCHH (tCHHN) High-Z DQ Power Down Entry Power Down Mode Power Down Exit Note: This Power Down mode can be also used for Power-up #2 below except that tCHHN can not be used at Power-up timing. Power-up Timing #1 CE1 tCHS tC2LH tCHH CE2 VDD VDD min 0V Note: The tC2LH specifies after VDD reaches specified minimum level. - 25 - Publication Release Date: March 14, 2003 Revision A1 W965L6ABN Timing Waveforms, Continued Power-up Timing #2 CE1 tCHS tC2HL tCSP tC2LP tCHH CE2 tC2HL VDD VDD min 0V Note: The tC2HL specifies from CE2 low to High transition after VDD reaches specified minimum level. CE1 must be brought to High prior to or together with CE2 Low to High transition. Standby Entry Timing after Read or Write CE1 tCHOX tCHWX OE WE Active (Read) Standby Active (Write) Standby Note: Both tCHOX and tCHWX define the earliest entry timing for Standby mode. If either of timing is not satisfied, it takes tRC(min) period from either last address transition of A0, A1 and A2, or CE1 Low to High transition. - 26 - W965L6ABN Data Retention Low VDD Characteristics PARAMETER SYM. VDD Data Retention Supply Voltage TEST CONDITIONS MIN. MAX. UNIT 2.1 3.6 V - 5 CE1 = CE2 = VIH (23), IOUT = 0 mA - 1.5 VDD = VDD (23), VIN 0.2V or VIN VDD -0.2V, - 200 - 100 0 - nS 200 - nS 0.2 - V/S CE1 = CE2 VDD -0.2V or, VDR CE1 = CE2 = VIH VDD = VDD (23), VIN = VDD -0.2V to VIH (23) or VIL L version IDR L version IDR1 Data Retention Setup Time tDRS VDD = VDD (27) at data retention entry Data Retention Recovery Time tDRR VDD = VDD (27) after data retention VDD Data Retention Supply Current VDD Voltage Transition Time CE1 = CE2 VDD -0.2V, IOUT = 0 mA V/t mA A Data Retention Timing tDRS tDRR 3.1V VDD V/t V/t 2.7V CE2 2.1V CE1 VDD-0.2V or VIH(23) min 0.4V VSS Data Retention Mode Data bus must be in High-Z at data retention entry. - 27 - Publication Release Date: March 14, 2003 Revision A1 W965L6ABN 10. PACKAGE DIMENSION TFBGA 48 Balls (6 x 8 mm^2, pitch 0.75 mm) - 28 - W965L6ABN 11. ORDERING INFORMATION SPEED OPERATING TEMPERATURE PACKAGE W965L6ABN70 70 nS 0 to 70 TFBGA 48, 8 mm x 10 mm, BALL PITCH 0.75 mm W965L6ABN70E 70 nS -25 to 85 TFBGA 48, 8 mm x 10 mm, BALL PITCH 0.75 mm W965L6ABN70I 70 nS -40 to 85 TFBGA 48, 8 mm x 10 mm, BALL PITCH 0.75 mm W965L6ABN80 80 nS 0 to 70 TFBGA 48, 8 mm x 10 mm, BALL PITCH 0.75 mm W965L6ABN80E 80 nS -25 to 85 TFBGA 48, 8 mm x 10 mm, BALL PITCH 0.75 mm W965L6ABN80I 80 nS -40 to 85 TFBGA 48, 8 mm x 10 mm, BALL PITCH 0.75 mm PART NO. Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. - 29 - Publication Release Date: March 14, 2003 Revision A1 W965L6ABN 12. VERSION HISTORY VERSION DATE PAGE A1 March 14, 2003 - DESCRIPTION Create new document Headquarters Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd. No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/ 2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Taipei Office Winbond Electronics Corporation Japan Winbond Electronics (H.K.) Ltd. 9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. - 30 -