RT8279 5A, 36V, 500kHz Step-Down Converter General Description Features The RT8279 is a step-down regulator with an internal power MOSFET. It achieves 5A of continuous output current over a wide input supply range with excellent load and line regulation. Current mode operation provides fast transient response and eases loop stabilization. z 5A Output Current z Internal Soft-Start 110m Internal Power MOSFET Switch Internal Compensation Minimizes External Parts Count High Efficiency up to 90% 25 A Shutdown Mode Fixed 500kHz Frequency Thermal Shutdown Cycle-by-Cycle Over Current Protection Wide 5.5V to 36V Operating Input Range Adjustable Output Voltage from 1.222V to 26V Available In an SOP8 (Exposed Pad) Package RoHS Compliant and Halogen Free For protection, the RT8279 provides cycle-by-cycle current limiting and thermal shutdown protection. An adjustable soft-start reduces the stress on the input source at startup. In shutdown mode, the regulator draws only 25A of supply current. z z z z z z z z The RT8279 requires a minimum number of readily available external components, providing a compact solution. The RT8279 is available in the SOP-8 (Exposed Pad) package. Ordering Information RT8279 z z z Applications z Package Type SP : SOP-8 (Exposed Pad-Option 1) z Lead Plating System G : Green (Halogen Free and Pb Free) z z Distributive Power Systems Battery Charger DSL Modems Pre-regulator for Linear Regulators Pin Configurations (TOP VIEW) Note : Richtek products are : BOOT RoHS compliant and compatible with the current require- NC 2 ments of IPC/JEDEC J-STD-020. NC 3 Suitable for use in SnPb or Pb-free soldering processes. FB 4 GND 9 8 SW 7 VIN 6 GND 5 EN SOP-8 (Exposed Pad) Marking Information RT8279GSP : Product Number RT8279 GSPYMDNN DS8279-01 YMDNN : Date Code December 2011 www.richtek.com 1 RT8279 Typical Application Circuit 7 VIN 5.5V to 36V CIN 4.7F/ 50V x 2 Chip Enable VIN BOOT RT8279 5 EN 1 SW 8 D1 B550A Open = Automatic Startup 6, 9 (Exposed Pad) GND CBOOT 10nF L1 VOUT CFF R1 FB 4 COUT 22F x 2 R2 Table 1. Recommended Component Selection R1 (k) R2 (k) CFF (pF) L (H) 100 100 82 6.8 100 58.6 82 10 100 31.6 82 15 100 18 82 22 VOUT (V) 2.5 3.3 5 8 COUT (F) 22 x 2 22 x 2 22 x 2 22 x 2 Functional Pin Description Pin No. Pin Name Pin Function BOOT High Side Gate Drive Boost Input. BOOT supplies the drive for the high side N-MOSFET switch. Connect a 10nF or greater capacitor from SW to BOOT to power the high side switch. 2, 3 NC No Internal Connection. 4 FB 5 EN Feedback Input. The feedback threshold is 1.222V. Enable Input. EN is a digital input that turns the regulator on or off. Drive EN higher than 1.4V to turn on the regulator, lower than 0.4V to turn it off. For automatic startup, leave EN unconnected. 1 6, 9 (Exposed Pad) GND Ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. 7 VIN Power Input. A suitable large capacitor should be bypassed from VIN to GND to eliminate noise on the input to the IC. 8 SW Power Switching Output. Note that a capacitor is required from SW to BOOT to power the high side switch. www.richtek.com 2 DS8279-01 December 2011 RT8279 Function Block Diagram VIN Current Sense Amplifier - Ramp Generator + BOOT EN Regulator Oscillator 500kHz S Q + Reference FB 12k Error + Amplifier - 400k 30pF Driver R PWM Comparator SW Bootstrap Control GND 13pF DS8279-01 December 2011 www.richtek.com 3 RT8279 Absolute Maximum Ratings z z z z z z z z z z (Note 1) Supply Voltage, VIN -----------------------------------------------------------------------------------------Switching Voltage, SW ------------------------------------------------------------------------------------BOOT Voltage ------------------------------------------------------------------------------------------------The Other Pins -----------------------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25C SOP-8 (Exposed Pad) -------------------------------------------------------------------------------------Package Thermal Resistance (Note 2) SOP-8 (Exposed Pad), JA --------------------------------------------------------------------------------SOP-8 (Exposed Pad), JC -------------------------------------------------------------------------------Junction Temperature ---------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) -----------------------------------------------------------------Storage Temperature Range ------------------------------------------------------------------------------ESD Susceptibility (Note 3) HBM (Human Body Mode) --------------------------------------------------------------------------------MM (Machine Mode) ----------------------------------------------------------------------------------------- Recommended Operating Conditions z z z -0.3V to 40V -0.3V to VIN + 0.3V (VSW - 0.3V) to (VSW + 6V) -0.3V to 6V 1.333W 75C/W 15C/W 150C 260C -65C to 150C 2kV 200V (Note 4) Supply Voltage, VIN ------------------------------------------------------------------------------------------ 5.5V to 36V Junction Temperature Range ------------------------------------------------------------------------------- -40C to 125C Ambient Temperature Range ------------------------------------------------------------------------------- -40C to 85C Electrical Characteristics (VIN = 12V, TA = 25C unless otherwise specified) Parameter Symbol Reference Voltage High Side Switch-On Resistance VREF RDS(ON)1 Low Side Switch-On Resistance RDS(ON)2 High Side Switch Leakage Current Limit Oscillator Frequency Short Circuit Frequency Maximum Duty Cycle Minimum On-Time Under Voltage Lockout Threshold Rising Under Voltage Lockout Threshold Hysteresis Logic-High EN Threshold Voltage Logic-Low Enable Pull Up Current Shutdown Current Quiescent Current Soft-Start Period Thermal Shutdown www.richtek.com 4 ILIM fOSC DMAX Test Conditions 5.5V VIN 36V VEN = 0V, VSW = 0V Duty = 90%, VBOOT-SW = 4.8V VFB = 0V VFB = 0.8V tON VIH VIL EN_hys = 350mV ISHDN IQ VEN = 0V VEN = 2V, VFB = 1.5V CSS = 0.1F TSD Min Typ Max Unit 1.202 1.222 1.239 -110 160 V m -- 10 15 -6 425 -85 -7.5 500 150 90 10 9 575 -95 A A kHz kHz % -- 100 150 ns 3.8 4.2 4.5 V -- 315 -- mV 1.4 --- --1 -0.4 -- A --3 -- 25 0.6 5 150 45 1 8.2 -- A mA ms C DS8279-01 V December 2011 RT8279 Note 1. Stresses beyond those listed "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. JA is measured at TA = 25C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. JC is measured at the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. DS8279-01 December 2011 www.richtek.com 5 RT8279 Typical Operating Characteristics Efficiency vs. Output Current Reference Voltage vs. Input Voltage 100 1.230 90 VIN = 12V VIN = 32V VIN = 36V 70 Reference Voltage (V) Efficiency (%) 80 60 50 40 30 20 10 VOUT = 5V 0 0 1 2 3 4 1.226 1.222 1.218 1.214 VOUT = 5V, IOUT = 0A 1.210 4 5 8 12 16 Output Current (A) 24 28 32 36 Output Voltage vs. Output Current 5.008 1.228 5.004 5.000 1.226 Output Voltage (V) Reference Voltage (V) Reference Voltage vs. Temperature 1.230 1.224 1.222 VIN = 12V VIN = 24V VIN = 36V 1.220 1.218 1.216 1.214 VIN = 36V VIN = 24V VIN = 12V 4.996 4.992 4.988 4.984 4.980 4.976 4.972 4.968 1.212 IOUT = 0A 1.210 -50 -25 0 25 50 75 100 4.964 VOUT = 5V 4.960 0 125 1 2 3 4 Frequency vs. Input Voltage Frequency vs. Temperature 540 530 530 520 520 Frequency (kHz) 540 510 500 490 480 470 510 500 490 480 VIN = 12V VIN = 24V VIN = 36V 470 460 460 450 450 VOUT = 5V, IOUT = 0A 440 4 8 12 16 20 24 Input Voltage (V) www.richtek.com 6 5 Output Current (A) Temperature (C) Frequency (kHz) 20 Input Voltage (V) 28 32 VOUT = 5V 440 36 -50 -25 0 25 50 75 100 125 Temperature (C) DS8279-01 December 2011 RT8279 Shutdown Current vs. Input Voltage 60 11 50 Shutdown Current (A) Current Limit (A) Current Limit vs. Temperature 12 10 9 8 7 6 VIN = 12V 5 -50 -25 0 25 50 75 100 40 30 20 10 VEN = 0V 0 4 125 8 12 16 20 24 28 Temperature (C) Input Voltage (V) Quiescent Current vs. Temperature Load Transient Response 32 36 1 Quiescent Current (mA) 0.9 VOUT (200mV/Div) 0.8 0.7 0.6 VIN = 36V VIN = 24V VIN = 12V 0.5 0.4 0.3 0.2 IOUT (2A/Div) 0.1 VIN = 12V, VOUT = 5V, IOUT = 0.2A to 5A 0 -50 -25 0 25 50 75 100 Time (100s/Div) 125 Temperature (C) Switching Load Transient Response VOUT (200mV/Div) VOUT (10mV/Div) VSW (10V/Div) IOUT (2A/Div) VIN = 12V, VOUT = 5V, IOUT = 2.5A to 5A Time (100s/Div) DS8279-01 December 2011 IL (5A/Div) VIN = 12V, VOUT = 5V, IOUT = 5A Time (1s/Div) www.richtek.com 7 RT8279 Power On from EN Power Off from EN VEN (5V/Div) VEN (5V/Div) VOUT (5V/Div) VOUT (5V/Div) IL (5A/Div) IL (5A/Div) VIN = 12V, VOUT = 5V, IOUT = 5A Time (2.5ms/Div) www.richtek.com 8 VIN = 12V, VOUT = 5V, IOUT = 5A Time (2.5ms/Div) DS8279-01 December 2011 RT8279 Application Information The RT8279 is an asynchronous high voltage buck converter that can support the input voltage range from 5.5V to 32V and the output current can be up to 5A. Output Voltage Setting The resistive divider allows the FB pin to sense the output voltage as shown in Figure 1. VOUT R1 FB RT8279 R2 GND Figure 1. Output Voltage Setting The output voltage is set by an external resistive divider according to the following equation : VOUT = VREF 1+ R1 R2 Where VREF is the reference voltage (1.222V typ.). Where R1 = 100k. External Bootstrap Diode Connect a 10nF low ESR ceramic capacitor between the BOOT pin and SW pin. This capacitor provides the gate driver voltage for the high side MOSFET. It is recommended to add an external bootstrap diode between an external 5V and BOOT pin for efficiency improvement when input voltage is lower than 5.5V or duty ratio is higher than 65% .The bootstrap diode can be a low cost one such as IN4148 or BAT54. The external 5V can be a 5V fixed input from system or a 5V output of the RT8279. 5V BOOT RT8279 10nF SW Soft-Start The RT8279 contains an internal soft-start clamp that gradually raises the output voltage. The typical soft-start time is 5ms. Chip Enable Operation The EN pin is the chip enable input. Pull the EN pin low (<0.4V) will shutdown the device. During shutdown mode, the RT8279 quiescent current drops to lower than 25A. Drive the EN pin to high (>1.4V, <5.5V) will turn on the device again. If the EN pin is open, it will be pulled to high by internal circuit. For external timing control (e.g.RC),the EN pin can also be externally pulled to High by adding a 100k or greater resistor from the VIN pin (see Figure 3). Inductor Selection The inductor value and operating frequency determine the ripple current according to a specific input and output voltage. The ripple current IL increases with higher VIN and decreases with higher inductance. V V IL = OUT x 1- OUT f x L VIN Having a lower ripple current reduces not only the ESR losses in the output capacitors but also the output voltage ripple. High frequency with small ripple current can achieve highest efficiency operation. However, it requires a large inductor to achieve this goal. For the ripple current selection, the value of IL = 0.2(IMAX) will be a reasonable starting point. The largest ripple current occurs at the highest VIN. To guarantee that the ripple current stays below the specified maximum, the inductor value should be chosen according to the following equation : VOUT VOUT L = x 1 - f I V x L(MAX) IN(MAX) The inductor's current rating (caused a 40C temperature rising from 25C ambient) should be greater than the maximum load current and its saturation current should be greater than the short circuit peak current limit. Please see Table 2 for the inductor selection reference. Figure 2. External Bootstrap Diode DS8279-01 December 2011 www.richtek.com 9 RT8279 Table 2. Suggested Inductors for Typical Application Circuit Component Dimensions Series Supplier (mm) TAIYO NR10050 10 x 9.8 x 5 YUDEN TDK SLF12565 12.5 x 12.5 x 6.5 Diode Selection When the power switch turns off, the path for the current is through the diode connected between the switch output and ground. This forward biased diode must have a minimum voltage drop and recovery times. Schottky diode is recommended and it should be able to handle those current. The reverse voltage rating of the diode should be greater than the maximum input voltage, and current rating should be greater than the maximum load current. For more detail please refer to Table 4. CIN and COUT Selection The input capacitance, C IN, is needed to filter the trapezoidal current at the source of the high side MOSFET. To prevent large ripple current, a low ESR input capacitor sized for the maximum RMS current should be used. The RMS current is given by : V IRMS = IOUT(MAX) OUT VIN VIN -1 VOUT This formula has a maximum at VIN = 2VOUT, where I RMS = I OUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. For the input capacitor, two 4.7F low ESR ceramic capacitors are recommended. For the recommended capacitor, please refer to table 3 for more detail. The selection of COUT is determined by the required ESR to minimize voltage ripple. Moreover, the amount of bulk capacitance is also a key for COUT selection to ensure that the control loop is stable. Loop stability can be checked by viewing the load transient response as described in a later section. www.richtek.com 10 The output ripple, VOUT , is determined by : 1 VOUT IL ESR + 8fCOUT The output ripple will be highest at the maximum input voltage since IL increases with input voltage. Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirement. Dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Special polymer capacitors offer very low ESR value. However, it provides lower capacitance density than other types. Although Tantalum capacitors have the highest capacitance density, it is important to only use types that pass the surge test for use in switching power supplies. Aluminum electrolytic capacitors have significantly higher ESR. However, it can be used in cost-sensitive applications for ripple current rating and long term reliability considerations. Ceramic capacitors have excellent low ESR characteristics but can have a high voltage coefficient and audible piezoelectric effects. The high Q of ceramic capacitors with trace inductance can also lead to significant ringing. Higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. However, care must be taken when these capacitors are used at input and output. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, VIN. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at VIN large enough to damage the part. Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to ILOAD (ESR) also begins to charge or discharge COUT generating a feedback error signal for the regulator to return VOUT to its steady-state value. During this DS8279-01 December 2011 RT8279 recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problem. snubber between SW and GND and make them as close as possible to the SW pin (see Figure 3). Another method is to add a resistor in series with the bootstrap capacitor, CBOOT. But this method will decrease the driving capability to the high side MOSFET. It is strongly recommended to reserve the R-C snubber during PCB layout for EMI improvement. Moreover, reducing the SW trace area and keeping the main power in a small loop will be helpful on EMI performance. For detailed PCB layout guide, please refer to the section of Layout Consideration. EMI Consideration Since parasitic inductance and capacitance effects in PCB circuitry would cause a spike voltage on SW pin when high side MOSFET is turned-on/off, this spike voltage on SW may impact on EMI performance in the system. In order to enhance EMI performance, there are two methods to suppress the spike voltage. One is to place an R-C 7 VIN 5.5V to 32V REN* CIN 4.7F x 2 VIN BOOT RT8279 5 EN 1 CBOOT L 10nF 10H SW 8 RS* CEN* 6, 9 (Exposed Pad) RBOOT* CS* GND * : Optional D B550C VOUT 5V/5A R1 10k FB 4 COUT 47Fx2 (POSCAP) R2 3.16k Figure 3. Reference Circuit with Snubber and Enable Timing Control Thermal Considerations For continuous operation, do not exceed the maximum operation junction temperature. The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation can be calculated by following formula : PD(MAX) = (TJ(MAX) - TA ) / JA Where T J(MAX) is the maximum operation junction temperature , TA is the ambient temperature and the JA is the junction to ambient thermal resistance. For recommended operating conditions specification of RT8279, the maximum junction temperature is 125C. The junction to ambient thermal resistance JA is layout dependent. For PSOP-8 package, the thermal resistance JA is 75C/W on the standard JEDEC 51-7 four-layers thermal test board. The maximum power dissipation at TA = 25C can be calculated by following formula : DS8279-01 December 2011 P D(MAX) = (125C - 25C) / (75C/W) = 1.333W (min.copper area PCB layout) PD(MAX) = (125C - 25C) / (49C/W) = 2.04W (70mm2 copper area PCB layout) The thermal resistance JA of SOP-8 (Exposed Pad) is determined by the package architecture design and the PCB layout design. However, the package architecture design had been designed. If possible, it's useful to increase thermal performance by the PCB layout copper design. The thermal resistance JA can be decreased by adding copper area under the exposed pad of SOP-8 (Exposed Pad) package. As shown in Figure 4, the amount of copper area to which the SOP-8 (Exposed Pad) is mounted affects thermal performance. When mounted to the standard SOP-8 (Exposed Pad) pad (Figure 4a), JA is 75C/W. Adding copper area of pad under the SOP-8 (Exposed Pad) (Figure 4.b) reduces the JA to 64C/W. Even further, increasing the copper area of pad to 70mm2 (Figure 4.e) reduces the JA to 49C/W. www.richtek.com 11 RT8279 The maximum power dissipation depends on operating ambient temperature for fixed T J (MAX) and thermal resistance JA. For the RT8279, the Figure 5 of derating curves allows the designer to see the effect of rising ambient temperature on the maximum power dissipation allowed. 2.2 Four Layer PCB 2.0 Power Dissipation (W) (d) Copper Area = 50mm2 , JA = 51C/W 1.8 Copper Area 70mm2 50mm2 30mm2 10mm2 Min.Layout 1.6 1.4 1.2 1.0 0.8 0.6 (e) Copper Area = 70mm2 , JA = 49C/W 0.4 0.2 Figure 4. Thermal Resistance vs. Copper Area Layout Design 0.0 0 25 50 75 100 125 Ambient Temperature (C) Figure 5. Derating Curves for RT8279 Package Layout Consideration Follow the PCB layout guidelines for optimal performance of the RT8279. Keep the traces of the main current paths as short and wide as possible. Put the input capacitor as close as possible to the device pins (VIN and GND). SW node is with high frequency voltage swing and should (a) Copper Area = (2.3 x 2.3) mm , JA = 75C/W 2 be kept at small area. Keep analog components away from the SW node to prevent stray capacitive noise pickup. Connect feedback network behind the output capacitors. Keep the loop area small. Place the feedback components near the RT8279. Connect all analog grounds to a common node and then (b) Copper Area = 10mm2, JA = 64C/W connect the common node to the power ground behind the output capacitors. An example of PCB layout guide is shown in Figure 6 for reference. (c) Copper Area = 30mm2 , JA = 54C/W www.richtek.com 12 DS8279-01 December 2011 RT8279 SW should be connected to inductor by wide and short trace. Keep sensitive components away from this trace. SW VOUT CBOOT VOUT R1 COUT L1 BOOT NC NC 3 FB 4 GND 9 D1 SW 8 2 7 VIN 6 GND 5 EN R2 COUT CIN CIN Input capacitor should be placed as close to the IC as possible. The feedback components should be connected as close to the device as possible. GND Figure 6. PCB Layout Guide Table 3. Suggested Capacitors for CIN and COUT Location Component Supplier Part No. Capacitance (F) Case Size CIN MURATA GRM32ER71H475K 4.7 1206 CIN TAIYO YUDEN UMK325BJ475MM-T 4.7 1206 COUT MURATA GRM31CR60J476M 47 1206 COUT TDK C3225X5R0J476M 47 1210 COUT MURATA GRM32ER71C226M 22 1210 COUT TDK C3225X5R1C22M 22 1210 Table 4. Suggested Diode Component Supplier Series VRRM (V) IOUT (A) Package DIODES B550C 50 5 SMC PANJIT SK55 50 5 SMC DS8279-01 December 2011 www.richtek.com 13 RT8279 Outline Dimension H A M EXPOSED THERMAL PAD (Bottom of Package) Y J X B F C I D Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 4.801 5.004 0.189 0.197 B 3.810 4.000 0.150 0.157 C 1.346 1.753 0.053 0.069 D 0.330 0.510 0.013 0.020 F 1.194 1.346 0.047 0.053 H 0.170 0.254 0.007 0.010 I 0.000 0.152 0.000 0.006 J 5.791 6.200 0.228 0.244 M 0.406 1.270 0.016 0.050 X 2.000 2.300 0.079 0.091 Y 2.000 2.300 0.079 0.091 X 2.100 2.500 0.083 0.098 Y 3.000 3.500 0.118 0.138 Option 1 Option 2 8-Lead SOP (Exposed Pad) Plastic Package Richtek Technology Corporation Richtek Technology Corporation Headquarter Taipei Office (Marketing) 5F, No. 20, Taiyuen Street, Chupei City 5F, No. 95, Minchiuan Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)86672399 Fax: (8862)86672377 Email: marketing@richtek.com Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek. www.richtek.com 14 DS8279-01 December 2011