FEMTOCLOCKS™ CRYSTAL-TO-
3.3V, 2.5V LVPECL CLOCK GENERATOR
ICS843022I-48
IDT™ / ICS™ 3.3V, 2.5V LVPECL CLOCK GENERATOR 1 ICS843022AGI-48 REV A OCTOBER 31, 2006
GENERAL DESCRIPTION
The ICS843022I-48 is a Fibre Channel Clock
Generator and a member of the HiPerClocksTM fam-
ily of high performance devices from IDT. The
ICS843022I-48 uses a 25MHz crystal to synthe-
size 125MHz or 75MHz. The ICS843022I-48 has
excellent phase jitter performance, over the 12kHz – 20MHz
integration range. The ICS843022I-48 is packaged in a small
8-pin TSSOP, making it ideal for use in systems with limited
board space.
FEATURES
•One differential 3.3V or 2.5V LVPECL output
•Crystal oscillator interface designed for 25MHz,
18pF parallel resonant crystal
•Output frequencies: 125MHz or 75MHz (selectable)
•RMS phase jitter @ 125MHz, using a 25MHz crystal
(12kHz - 20MHz): 0.72ps (typical) @ 3.3V
•Full 3.3V and 2.5V operating supply
•-40°C to 85°C ambient operating temperature
•Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
HiPerClockS™
ICS
ICS843022I-48
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm package body
G Package
Top View
VCCA
VEE
XTAL_OUT
XTAL_IN
1
2
3
4
VCC
Q
nQ
FREQ_SEL
8
7
6
5
OSC PLL
DIV. N
÷4, ÷8
0 = ÷20
(default)
1 = ÷24
XTAL_IN
XTAL_OUT
FREQ_SEL
Q
nQ
Pulldown
BLOCK DIAGRAM PIN ASSIGNMENT
FUNCTION TABLE
stupnI seicneuqerFtuptuO
)latsyrczHM52ahtiw(
LES_QERFediviDMediviDN
002÷4÷)tluafed(zHM521
142÷8÷zHM57
IDT™ / ICS™ 3.3V, 2.5V LVPECL CLOCK GENERATOR 2 ICS843022AGI-48 REV A OCTOBER 31, 2006
ICS843022I-48
FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR
TABLE 2. PIN CHARACTERISTICS
TABLE 1. PIN DESCRIPTIONS
rebmuNemaNepyTnoitpircseD
1V
ACC
rewoP.nipylppusgolanA
2V
EE
rewoP.nipylppusevitageN
4,3 ,TUO_LATX
NI_LATX tupnI ,tupniehtsiNI_LATX.ecafretnirotallicsolatsyrC
.tuptuoehtsiTUO_LATX
5LES_QERFtupnInwodlluP.slevelecafretniLTTVL/SOMCVL.niptcelesycneuqerF
7,6Q,QntuptuO.slevelecafretniLCEPVL.tuptuokcolclaitnereffiD
8V
CC
rewoP.nipylppuseroC
:ETON
nwodlluP
.seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotsrefer
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
C
NI
ecnaticapaCtupnI 4Fp
R
NWODLLUP
rotsiseRnwodlluPtupnI 15kΩ
IDT™ / ICS™ 3.3V, 2.5V LVPECL CLOCK GENERATOR 3 ICS843022AGI-48 REV A OCTOBER 31, 2006
ICS843022I-48
FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = -40°C TO 85°C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
CC 4.6V
Inputs, VI-0.5V to VCC + 0.5V
Outputs, IO
Continuous Current 50mA
Surge Current 100mA
Package Thermal Impedance, θJA 101.7°C/W (0 mps)
Storage Temperature, T
STG -65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
TABLE 3C. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = -40°C TO 85°C
TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 2.5V±5%, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HI
egatloVhgiHtupnI 3.1V
CC
3.0+V
V
LI
egatloVwoLtupnI 3.0-7.0V
I
HI
tnerruChgiHtupnIV
CC
V=
NI
V564.3=051Aµ
I
LI
tnerruCwoLtupnIV
CC
V,V564.3=
NI
V0=5-Aµ
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
CC
egatloVylppuSeroC 531.33.3564.3V
V
ACC
egatloVylppuSgolanAV
CC
01.0–3.3V
CC
V
I
ACC
tnerruCylppuSgolanA 01Am
I
EE
tnerruCylppuSrewoP 08Am
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
CC
egatloVylppuSeroC 573.25.2526.2V
V
ACC
egatloVylppuSgolanAV
CC
01.0–5.2V
CC
V
I
ACC
tnerruCylppuSgolanA 01V
I
EE
tnerruCylppuSrewoP 57Am
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HI
egatloVhgiHtupnI 1.1V
CC
3.0+V
V
LI
egatloVwoLtupnI 3.0-5.0V
I
HI
tnerruChgiHtupnIV
CC
V=
NI
V526.2=051Aµ
I
LI
tnerruCwoLtupnIV
CC
V,V526.2=
NI
V0=5-Aµ
TABLE 3D. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = 2.5V±5%, TA = -40°C TO 85°C
IDT™ / ICS™ 3.3V, 2.5V LVPECL CLOCK GENERATOR 4 ICS843022AGI-48 REV A OCTOBER 31, 2006
ICS843022I-48
FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR
TABLE 5A. AC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
f
TUO
ycneuqerFtuptuO 521zHM
57zHM
t
)Ø(tij1ETON;rettiJesahPSMR
,zHM521
zHM02-zHk21:egnaRnoitargetnI 27.0sp
,zHM57
zHM5.7-zHk009:egnaRnoitargetnI 15.0sp
t
R
t/
F
emiTllaF/esiRtuptuO%08ot%02052054sp
cdoelcyCytuDtuptuO 8425%
.tolPesioNesahPehtotreferesaelP:1ETON
TABLE 4. CRYSTAL CHARACTERISTICS
retemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
noitallicsOfoedoM latnemadnuF
ycneuqerF 52zHM
)RSE(ecnatsiseRseireStnelaviuqE 05 Ω
ecnaticapaCtnuhS 7Fp
leveLevirD 001Wµ
TABLE 5B. AC CHARACTERISTICS, VCC = VCCA = 2.5V±5%, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
f
TUO
ycneuqerFtuptuO 521zHM
57zHM
t
)Ø(tij1ETON;rettiJesahPSMR
,zHM521
zHM02-zHk21:egnaRnoitargetnI 66.0sp
,zHM57
zHM5.7-zHk009:egnaRnoitargetnI 06.0sp
t
R
t/
F
emiTllaF/esiRtuptuO%08ot%02052054sp
cdoelcyCytuDtuptuO 8425%
.tolPesioNesahPehtotreferesaelP:1ETON
TABLE 3E. LVPECL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HO
1ETON;egatloVhgiHtuptuOV
CC
4.1-V
CC
9.0-V
V
LO
1ETON;egatloVwoLtuptuOV
CC
0.2-V
CC
7.1-V
V
GNIWS
gniwSegatloVtuptuOkaeP-ot-kaeP6.00.1V
05htiwdetanimretstuptuO:1ETON ΩVot
CC
.V2-
IDT™ / ICS™ 3.3V, 2.5V LVPECL CLOCK GENERATOR 5 ICS843022AGI-48 REV A OCTOBER 31, 2006
ICS843022I-48
FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR
TYPICAL PHASE NOISE AT 75MHZ @ 3.3V
OFFSET FREQUENCY (HZ)
NOISE POWER dBc
Hz
Phase Noise Result by adding
Fibre Channel Filter to raw data
Raw Phase Noise Data
Fibre Channel Filter
➤
➤
75MHz
RMS Phase Jitter (Random)
900kHz to 7.5MHz = 0.51ps (typical)
➤
TYPICAL PHASE NOISE AT 125MHZ @ 3.3V
125MHz
RMS Phase Noise Jitter
12kHz to 20MHz = 0.72ps (typical)
OFFSET FREQUENCY (HZ)
dBc
Hz
NOISE POWER
➤
➤
➤
Phase Noise Result by adding
a Fibre Channel Filter to raw data
Raw Phase Noise Data
Fibre Channel Filter
IDT™ / ICS™ 3.3V, 2.5V LVPECL CLOCK GENERATOR 6 ICS843022AGI-48 REV A OCTOBER 31, 2006
ICS843022I-48
FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD OUTPUT RISE/FALL TIME
3.3V OUTPUT LOAD AC TEST CIRCUIT
SCOPE
Qx
nQx
LVPECL
VEE
2V
-1.3V ± 0.165V
Clock
Outputs 20%
80% 80%
20%
t
R
t
F
V
SWING
t
PW
t
PERIOD
t
PW
t
PERIOD
odc = x 100%
Q
nQ
VCC
2.5V OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Mas
k
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise Power
2V
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
SCOPE
Qx
nQx
LVPECL
VEE
2V
-0.5V ± 0.125V
VCC
2V
VCCA VCCA
IDT™ / ICS™ 3.3V, 2.5V LVPECL CLOCK GENERATOR 7 ICS843022AGI-48 REV A OCTOBER 31, 2006
ICS843022I-48
FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR
APPLICATION INFORMATION
FIGURE 2. CRYSTAL INPUt INTERFACE
CRYSTAL INPUT INTERFACE
The ICS843022I-48 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2
below were determined using a 25MHz, 18pF parallel
resonant crystal and were chosen to minimize the ppm error. The
optimum C1 and C2 values can be slightly adjusted for different
board layouts.
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS843022I-48 provides
separate power supplies to isolate any high switching noise
from the outputs to the internal PLL. VCC and VCCA should be
individually connected to the power supply plane through vias,
and bypass capacitors should be used for each pin. To
achieve optimum jitter performance, power supply isolation is
required.
Figure 1
illustrates how a 10Ω resistor along with a
10µF and a .01µF bypass capacitor should be connected to
each VCCA pin.
POWER SUPPLY FILTERING T ECHNIQUES
FIGURE 1. POWER SUPPLY FILTERING
10Ω
VCCA
10 µF
.01µF
3.3V or 2.5V
.01µF
VCC
C1
27p
X1
18pF Parallel Crystal
C2
27p
XTAL_OUT
XTAL_IN
IDT™ / ICS™ 3.3V, 2.5V LVPECL CLOCK GENERATOR 8 ICS843022AGI-48 REV A OCTOBER 31, 2006
ICS843022I-48
FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS
signal through an AC couple capacitor. A general interface
diagram is shown in
Figure 3.
The XTAL_OUT pin can be left
floating. The input edge rate can be as slow as 10ns. For
LVCMOS inputs, it is recommended that the amplitude be
reduced from full swing to half swing in order to prevent signal
interference with the power rail and to reduce noise. This
configuration requires that the output impedance of the driver
Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface
(Ro) plus the series resistance (Rs) equals the transmission
line impedance. In addition, matched termination at the crystal
input will attenuate the signal in half. This can be done in one
of two ways. First, R1 and R2 in parallel should equal the
transmission line impedance. For most 50Ω applications, R1
and R2 can be 100Ω. This can also be accomplished by remov-
ing R1 and making R2 50Ω.
R2
Zo = 50
VDD
Ro
Zo = Ro + Rs
R1
VDD
XTA L _ I N
XTA L _ O U T
.1uf
Rs
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
FIGURE 4B. LVPECL OUTPUT TERMINATIONFIGURE 4A. LVPECL OUTPUT TERMINATION
designed to drive 50Ω transmission lines. Matched impedance
techniques should be used to maximize operating frequency
and minimize signal distortion.
Figures 4A and 4B
show two
different layouts which are recommended only as guidelines.
Other suitable clock layouts may exist and it would be recom-
mended that the board designers simulate to guarantee com-
patibility across all printed circuit and clock component pro-
cess variations.
V
CC
- 2V
50Ω50Ω
RTT
Z
o
= 50Ω
Z
o
= 50Ω
FOUT FIN
RTT = Z
o
1
((V
OH
+ V
OL
) / (V
CC
– 2)) – 2
3.3V
125Ω125Ω
84Ω84Ω
Z
o
= 50Ω
Z
o
= 50Ω
FOUT FIN
IDT™ / ICS™ 3.3V, 2.5V LVPECL CLOCK GENERATOR 9 ICS843022AGI-48 REV A OCTOBER 31, 2006
ICS843022I-48
FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 5A
and
Figure 5B
show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating
50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to ground
level. The R3 in Figure 5B can be eliminated and the termination
is shown in
Figure 5C.
FIGURE 5C. 2.5V LVPECL TERMINATION EXAMPLE
FIGURE 5B. 2.5V LVPECL DRIVER TERMINATION EXAMPLEFIGURE 5A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
R2
62.5
Zo = 50 Ohm
R1
250
+
-
2.5V
2,5V LVPECL
Driv er
R4
62.5
R3
250
Zo = 50 Ohm
2.5V
VCC=2.5V
R1
50
R3
18
Zo = 50 Ohm
Zo = 50 Ohm
+
-
2,5V LVPECL
Driv er
VCC=2.5V
2.5V
R2
50
2,5V LVPECL
Driv er
VCC=2.5V
R1
50
R2
50
2.5V
Zo = 50 Ohm
Zo = 50 Ohm
+
-
IDT™ / ICS™ 3.3V, 2.5V LVPECL CLOCK GENERATOR 10 ICS843022AGI-48 REV A OCTOBER 31, 2006
ICS843022I-48
FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843022I-48.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843022I-48 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 80mA = 277.2mW
•Power (outputs)MAX = 30mW/Loaded Output pair
Total Power_MAX (3.465V, with all outputs switching) = 277.2mW + 30mW = 307.2mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA
must be used. Assuming a
moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.307W * 125.5°C/W = 123.5°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θθ
θθ
θJA FOR 8-PIN TSSOP, FORCED CONVECTION
θθ
θθ
θJA by Velocity (Meters per Second)
0 1 2.5
Multi-Layer PCB, JEDEC Standard Test Boards 129.5°C/W 125.5°C/W 123.5°C/W
IDT™ / ICS™ 3.3V, 2.5V LVPECL CLOCK GENERATOR 11 ICS843022AGI-48 REV A OCTOBER 31, 2006
ICS843022I-48
FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in
Figure 6.
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V
CC
- 2V.
• For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V
(VCCO_MAX - VOH_MAX
) = 0.9V
• For logic low, VOUT = VOL_MAX = VCC_MAX
– 1.7V
(VCCO_MAX - VOL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX
– (VCC_MAX
- 2V))/R
L
] * (VCC_MAX
- VOH_MAX) = [(2V - (V
CC_MAX - VOH_MAX
))/R
L
] * (VCC_MAX
- VOH_MAX) =
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX
– (VCC_MAX
- 2V))/R
L
] * (VCC_MAX
- VOL_MAX) = [(2V - (V
CC_MAX - VOL_MAX
))/R
L
] * (VCC_MAX
- VOL_MAX) =
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
Q1
VOUT
VCC
RL
50
VCC - 2V
IDT™ / ICS™ 3.3V, 2.5V LVPECL CLOCK GENERATOR 12 ICS843022AGI-48 REV A OCTOBER 31, 2006
ICS843022I-48
FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR
RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for ICS843022I-48 is: 2086
TABLE 7. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP
θθ
θθ
θJA by Velocity (Meters per Second)
0 1 2.5
Multi-Layer PCB, JEDEC Standard Test Boards 129.5°C/W 125.5°C/W 123.5°C/W
IDT™ / ICS™ 3.3V, 2.5V LVPECL CLOCK GENERATOR 13 ICS843022AGI-48 REV A OCTOBER 31, 2006
ICS843022I-48
FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR
PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
Reference Document: JEDEC Publication 95, MO-153
LOBMYS sretemilliM
muminiMmumixaM
N8
A--02.1
1A50.051.0
2A08.050.1
b91.003.0
c90.002.0
D09.201.3
ECISAB04.6
1E03.405.4
eCISAB56.0
L54.057.0
α°0°8
aaa--01.0
IDT™ / ICS™ 3.3V, 2.5V LVPECL CLOCK GENERATOR 14 ICS843022AGI-48 REV A OCTOBER 31, 2006
ICS843022I-48
FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and
industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT
reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
TABLE 9. ORDERING INFORMATION
rebmuNredrO/traPgnikraMegakcaPgnigakcaPgnippihSerutarepmeT
84-IGA220348SCI84IA2POSSTdael8ebutC°58otC°04-
T84-IGA220348SCI84IA2POSSTdael8leer&epat0052C°58otC°04-
FL84-IGA220348SCIL84IAPOSST"eerF-daeL"dael8ebutC°58otC°04-
TFL84-IGA220348SCIL84IAPOSST"eerF-daeL"dael8leer&epat0052C°58otC°04-
.tnailpmocSHoReradnanoitarugifnoceerF-bPehterarebmuntrapehtotxiffus"FL"nahtiwderedroeratahtstraP:ETON
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Integrated Device Technology
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+44 (0) 1372 363 339
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© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
ICS843022I-48
FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR
