1.8V 4K/8K/16K x 16 and 8K/16K x 8
ConsuMoBL Dual-Port Static RAM
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 001-01638 Rev. *C Revised May 18, 2006
Features
• True dual-ported memory cells which allow simulta-
neous access of the same memory location
• 4/8/16K × 16 and 8/16K × 8 organization
• High-speed access: 40 ns
• Ultra Low operating power
— Active: ICC = 15 mA (typical) at 55 ns
— Active: ICC = 25 mA (typical) at 40 ns
— Standby: ISB3 = 2 µA (typical)
• Small footprint: Available in a 14 x 14 x 1.4 mm 100-pin
Lead (Pb)-free TQFP
• Port-independent 1.8V, 2.5V, and 3.0V I/Os
• Full asynchronous operation
• Automatic power-down
• Pin select for Master or Slave
• Expandable data bus to 32 bits with Master/Slave chip
select when using more than one device
• On-chip arbitration logic
• Semaphores included to permit software handshaking
between ports
• Input Read Registers and Output Drive Registers
•INT
flag for port-to-port communication
• Separate upper-byte and lower-byte control
• Industrial temperature ranges
Selection Guide for VCC = 1.8V
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
-40
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
-55
UnitPort I/O Voltages (P1-P2) 1.8V-1.8V 1.8V-1.8V
Maximum Access Time 40 55 ns
Typical Operating Current 25 15 mA
Typical Standby Current for ISB1 22µA
Typical Standby Current for ISB3 22µA
Selection Guide for VCC = 2.5V
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
-40
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
-55
UnitPort I/O Voltages (P1-P2) 2.5V-2.5V 2.5V-2.5V
Maximum Access Time 40 55 ns
Typical Operating Current 39 28 mA
Typical Standby Current for ISB1 66µA
Typical Standby Current for ISB3 44µA
Selection Guide for VCC = 3.0V
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
-40
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
-55
UnitPort I/O Voltages (P1-P2) 3.0V-3.0V 3.0V-3.0V
Maximum Access Time 40 55 ns
Typical Operating Current 49 42 mA
Typical Standby Current for ISB1 77µA
Typical Standby Current for ISB3 66µA
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
Document #: 001-01638 Rev. *C Page 2 of 26
Notes:
1. A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K devices.
2. BUSY is an output in master mode and an input in slave mode.
IO
Control
Address Decode
MailboxesINTLINTR
Address Decode
16K X 16
Dual Ported Array
IO
Control
Interrupt
Arbitration
Semaphore
A [13:0]R
CE R
BUSY R
I/O[15:0]R
LBR
I/O[15:0]L
LBL
OE L
BUSY L
A[13:0]L
R/W L
CE L
M/S
UBL
UBR
SEMLSEMR
Input Read
Register and
Output Drive
Register
CE R
OE R
OE R
R/W R
R/W R
ODR0 - ODR4
CEL
OEL
R/WL
IRR0 ,IRR1
SFEN
Figure 1. Top Level Block Diagram[1, 2]
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
Document #: 001-01638 Rev. *C Page 3 of 26
Pin Configurations [3, 4, 5, 6, 7]
Notes:
3. A12L and A12R are NC pins for CYDC064B16.
4. IRR functionality is not supported for the CYDC256B16 device.
5. This pin is A13L for CYDC256B16 device.
6. This pin is A13R for CYDC256B16 device.
7. Leave this pin unconnected. No trace or power component can be connected to this pin.
100-Pin TQFP (Top View)
1
3
2
92 91 90 848587 868889 83 82 81 7678 77798093949596979899100
59
60
61
67
66
64
65
63
62
68
69
70
75
73
74
72
71
A4R
A5R
A6R
A7R
A8R
CER
A10R
INTR
A9R
VCC
A11R
NC[7]
VDDIOR
BUSYR
SEMR
A12R[3]
IRR1[6]
I/O15R
I/O14R
I/O13R
VSS
I/O12R
I/O11R
I/O10R
VSS
58
57
56
55
54
53
52
51
A4L
A5L
A6L
A7L
A8L
CEL
A10L
INTL
A9L
VCC
A11L
M/S
VDDIOL
BUSYL
SEML
A12L[3]
IRR0[5]
I/O0L
I/O1L
I/O2L
VSS
I/O3L
I/O4L
I/O5L
VSS
17
16
15
9
10
12
11
13
14
8
7
6
4
5
18
19
20
21
22
23
24
25
A3L
A2L
A1L
A0L
UBL
LBL
ODR0
R/WL
VSS
VSS
ODR2
VSS
R/WR
SFEN
OEL
ODR3
ODR4
OER
LBR
UBR
A0R
A1R
A2R
A3R
ODR1
34 35 36 424139 403837 43 44 45 5048 494746
I/O9R
I/O8R
VDDIOR
I/O7R
I/O6R
I/O5R
I/O1R
I/O4R
I/O2R
NC[7]
I/O15L
I/O12L
I/O11L
I/O3R
VSS
I/O14L
I/O13L
VSS
I/O10L
I/O9L
I/O8L
VDDIOL
I/O7L
I/O6L
I/O0R
3332313029282726
CYDC064B16
CYDC128B16
CYDC256B16
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
Document #: 001-01638 Rev. *C Page 4 of 26
Notes:
8. IRR functionality is not supported for the CYDC128B08 device.
9. This pin is A13L for CYDC128B08 devices.
10. This pin is A13R for CYDC128B08 devices.
Pin Configurations (continued)[7, 8, 9, 10]
1
3
2
92 91 90 848587 868889 83 82 81 7678 77798093949596979899100
59
60
61
67
66
64
65
63
62
68
69
70
75
73
74
72
71
A4R
A5R
A6R
A7R
A8R
CER
A10R
INTR
A9R
VCC
A11R
NC[11]
VDDIOR
BUSYR
SEMR
A12R
IRR1[10]
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
58
57
56
55
54
53
52
51
CYDC064B08
A4L
A5L
A6L
A7L
A8L
CEL
A10L
INTL
A9L
VCC
A11L
M/S
VDDIOL
BUSYL
SEML
A12L
IRR0[9]
I/O0L
I/O1L
I/O2L
VSS
I/O3L
I/O4L
I/O5L
VSS
17
16
15
9
10
12
11
13
14
8
7
6
4
5
18
19
20
21
22
23
24
25
A3L
A2L
A1L
A0L
UBL
LBL
ODR0
R/WL
VSS
VSS
ODR2
VSS
R/WR
SFEN
OEL
ODR3
ODR4
OER
LBR
UBR
A0R
A1R
A2R
A3R
ODR1
34 35 36 424139 403837 43 44 45 5048 494746
VSS
VSS
VDDIOR
I/O7R
I/O6R
I/O5R
I/O1R
I/O4R
I/O2R
NC[11]
VSS
VSS
VSS
I/O3R
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDIOL
I/O7L
I/O6L
I/O0R
3332313029282726
CYDC128B08
100-pin TQFP (Top View)
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
Document #: 001-01638 Rev. *C Page 5 of 26
Functional Description
The CYDC256B16, CYDC128B16, CYDC064B16,
CYDC128B08, CYDC064B08 are low-power CMOS 4K,
8K,16K x 16, and 8/16K x 8 dual-port static RAMs. Arbitration
schemes are included on the devices to handle situations
when multiple processors access the same piece of data. Two
ports are provided, permitting independent, asynchronous
access for reads and writes to any location in memory. The
devices can be utilized as standalone 16-bit dual-port static
RAMs or multiple devices can be combined in order to function
as a 32-bit or wider master/slave dual-port static RAM. An M/S
pin is provided for implementing 32-bit or wider memory appli-
cations without the need for separate master and slave
devices or additional discrete logic. Application areas include
interprocessor/multiprocessor designs, communications
status buffering, and dual-port video/graphics memory.
Each port has independent control pins: Chip Enable (CE),
Read or Write Enable (R/W), and Output Enable (OE). Two
flags are provided on each port (BUSY and INT). BUSY
signals that the port is trying to access the same location
currently being accessed by the other port. The Interrupt flag
(INT) permits communication between ports or systems by
means of a mail box. The semaphores are used to pass a flag,
or token, from one port to the other to indicate that a shared
resource is in use. The semaphore logic is comprised of eight
shared latches. Only one side can control the latch
(semaphore) at any time. Control of a semaphore indicates
that a shared resource is in use. An automatic power-down
feature is controlled independently on each port by a Chip
Enable (CE) pin.
The CYDC256B16, CYDC128B16, CYDC064B16,
CYDC128B08, CYDC064B08 are available in 100-pin TQFP
packages.
Power Supply
The core voltage (VCC) can be 1.8V, 2.5V or 3.3V, as long as
it is lower than or equal to the I/O voltage.
Each port can operate on independent I/O voltages. This is
determined by what is connected to the VDDIOL and VDDIOR
pins. The supported I/O standards are 1.8V/2.5V LVCMOS
and 3.0V LVTTL.
Write Operation
Data must be set up for a duration of tSD before the rising edge
of R/W in order to guarantee a valid write. A write operation is
controlled by either the R/W pin (see Write Cycle No. 1
waveform) or the CE pin (see Write Cycle No. 2 waveform).
Required inputs for non-contention operations are summa-
rized in Table 1.
If a location is being written to by one port and the opposite
port attempts to read that location, a port-to-port flowthrough
delay must occur before the data is read on the output;
otherwise the data read is not deterministic. Data will be valid
on the port tDDD after the data is presented on the other port.
Read Operation
When reading the device, the user must assert both the OE
and CE pins. Data will be available tACE after CE or tDOE after
OE is asserted. If the user wishes to access a semaphore flag,
Pin Definitions
Left Port Right Port Description
CELCERChip Enable
R/WLR/WRRead/Write Enable
OELOEROutput Enable
A0L–A13L A0R–A13R Address (A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K devices).
I/O0L–I/O15L I/O0R–I/O15R Data Bus Input/Output for x16 devices; I/O0–I/O7 for x8 devices.
SEML SEMRSemaphore Enable
UBLUBRUpper Byte Select (I/O8–I/O15 for x16 devices; Not applicable for x8 devices).
LBLLBRLower Byte Select (I/O0–I/O7 for x16 devices; Not applicable for x8 devices).
INTLINTRInterrupt Flag
BUSYLBUSYRBusy Flag
IRR0, IRR1 Input Read Register for CYDC064B16, CYDC064B08, CYDC128B16.
A13L, A13R for CYDC256B16 and CYDC128B08 devices.
ODR0-ODR4 Output Drive Register; These outputs are Open Drain.
SFEN Special Function Enable
M/S Master or Slave Select
VCC Core Power
GND Ground
VDDIOL Left Port I/O Voltage
VDDIOR Right Port I/O Voltage
NC No Connect. Leave this pin Unconnected.
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
Document #: 001-01638 Rev. *C Page 6 of 26
then the SEM pin must be asserted instead of the CE pin, and
OE must also be asserted.
Interrupts
The upper two memory locations may be used for message
passing. The highest memory location (FFF for the
CYDC064B16, 1FFF for the CYDC128B16 and CYDC064B08,
3FFF for the CYDC256B16 and CYDC128B08) is the mailbox
for the right port and the second-highest memory location (FFE
for the CYDC064B16, 1FFE for the CYDC128B16 and
CYDC064B08, 3FFE for the CYDC256B16 and CYDC128B08)
is the mailbox for the left port. When one port writes to the
other port’s mailbox, an interrupt is generated to the owner.
The interrupt is reset when the owner reads the contents of the
mailbox. The message is user-defined.
Each port can read the other port’s mailbox without resetting
the interrupt. The active state of the busy signal (to a port)
prevents the port from setting the interrupt to the winning port.
Also, an active busy to a port prevents that port from reading
its own mailbox and, thus, resetting the interrupt to it.
If an application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request
input pin. On power up, an initialization program should be run
and the interrupts for both ports must be read to reset them.
The operation of the interrupts and their interaction with Busy
are summarized in Table 2.
Busy
The CYDC256B16, CYDC128B16, CYDC064B16,
CYDC128B08, CYDC064B08 provide on-chip arbitration to
resolve simultaneous memory location access (contention). If
both ports’ CEs are asserted and an address match occurs
within tPS of each other, the busy logic will determine which
port has access. If tPS is violated, one port will definitely gain
permission to the location, but it is not predictable which port
will get that permission. BUSY will be asserted tBLA after an
address match or tBLC after CE is taken LOW.
Master/Slave
A M/S pin is provided in order to expand the word width by
configuring the device as either a master or a slave. The BUSY
output of the master is connected to the BUSY input of the
slave. This will allow the device to interface to a master device
with no external components. Writing to slave devices must be
delayed until after the BUSY input has settled (tBLC or tBLA),
otherwise, the slave chip may begin a write cycle during a
contention situation. When tied HIGH, the M/S pin allows the
device to be used as a master and, therefore, the BUSY line
is an output. BUSY can then be used to send the arbitration
outcome to a slave.
Input Read Register
The Input Read Register (IRR) captures the status of two
external input devices that are connected to the Input Read
pins.
The contents of the IRR read from address x0000 from either
port. During reads from the IRR, DQ0 and DQ1 are valid bits
and DQ<15:2> are don’t care. Writes to address x0000 are not
allowed from either port.
Address x0000 is not available for standard memory accesses
when SFEN = VIL. When SFEN = VIH, address x0000 is
available for memory accesses.
The inputs will be 1.8V/2.5V LVCMOS or 3.0V LVTTL,
depending on the core voltage supply (VCC). Refer to Table 3
for Input Read Register operation.
IRR is not available in the CYDC256B16 and CYDC128B08,
as the IRR pins are used as extra address pins A13L and A13R.
Output Drive Register
The Output Drive Register (ODR) determines the state of up
to five external binary state devices by providing a path to VSS
for the external circuit. These outputs are Open Drain.
The five external devices can operate at different voltages
(1.5V ≤ VDDIO ≤ 3.5V) but the combined current cannot exceed
40 mA (8 mA max for each external device). The status of the
ODR bits are set using standard write accesses from either
port to address x0001 with a “1” corresponding to on and “0”
corresponding to off.
The status of the ODR bits can be read with a standard read
access to address x0001. When SFEN = VIL, the ODR is active
and address x0001 is not available for memory accesses.
When SFEN = VIH, the ODR is inactive and address x0001 can
be used for standard accesses.
During reads and writes to ODR DQ<4:0> are valid and
DQ<15:5> are don’t care. Refer to Table 4 for Output Drive
Register operation.
Semaphore Operation
The CYDC256B16, CYDC128B16, CYDC064B16,
CYDC128B08, CYDC064B08 provide eight semaphore
latches, which are separate from the dual-port memory
locations. Semaphores are used to reserve resources that are
shared between the two ports. The state of the semaphore
indicates that a resource is in use. For example, if the left port
wants to request a given resource, it sets a latch by writing a
zero to a semaphore location. The left port then verifies its
success in setting the latch by reading it. After writing to the
semaphore, SEM or OE must be deasserted for tSOP before
attempting to read the semaphore. The semaphore value will
be available tSWRD + tDOE after the rising edge of the
semaphore write. If the left port was successful (reads a zero),
it assumes control of the shared resource, otherwise (reads a
one) it assumes the right port has control and continues to poll
the semaphore. When the right side has relinquished control
of the semaphore (by writing a one), the left side will succeed
in gaining control of the semaphore. If the left side no longer
requires the semaphore, a one is written to cancel its request.
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip select for the semaphore latches (CE
must remain HIGH during SEM LOW). A0–2 represents the
semaphore address. OE and R/W are used in the same
manner as a normal memory access. When writing or reading
a semaphore, the other address pins have no effect.
When writing to the semaphore, only I/O0 is used. If a zero is
written to the left port of an available semaphore, a one will
appear at the same semaphore address on the right port. That
semaphore can now only be modified by the side showing zero
(the left port in this case). If the left port now relinquishes
control by writing a one to the semaphore, the semaphore will
be set to one for both sides. However, if the right port had
requested the semaphore (written a zero) while the left port
had control, the right port would immediately own the
semaphore as soon as the left port released it. Table 5 shows
sample semaphore operations.
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
Document #: 001-01638 Rev. *C Page 7 of 26
When reading a semaphore, all sixteen/eight data lines output
the semaphore value. The read value is latched in an output
register to prevent the semaphore from changing state during
a write from the other port. If both ports attempt to access the
semaphore within tSPS of each other, the semaphore will
definitely be obtained by one side or the other, but there is no
guarantee which side will control the semaphore. On
power-up, both ports should write “1” to all eight semaphores.
Architecture
The CYDC256B16, CYDC128B16, CYDC064B16,
CYDC128B08, CYDC064B08 consist of an array of 4K, 8K, or
16K words of 16 dual-port RAM cells, I/O and address lines,
and control signals (CE, OE, R/W). The CYDC064B08 and
CYDC128B08 consist of an array of 8K and 16K words of 8
each of dual-port RAM cells, I/O and address lines, and control
signals (CE, OE, R/W).These control pins permit independent
access for reads or writes to any location in memory. To handle
simultaneous writes/reads to the same location, a BUSY pin is
provided on each port. Two Interrupt (INT) pins can be utilized
for port-to-port communication. Two Semaphore (SEM)
control pins are used for allocating shared resources. With the
M/S pin, the devices can function as a master (BUSY pins are
outputs) or as a slave (BUSY pins are inputs). The devices
also have an automatic power-down feature controlled by CE.
Each port is provided with its own output enable control (OE),
which allows data to be read from the device.
Notes:
11. This column applies to x16 devices only.
12. See Interrupts Functional Description for specific highest memory locations by device.
13. If BUSYR = L, then no change.
14. If BUSYL = L, then no change.
15. See Functional Description for specific addresses by device.
Table 1. Non-Contending Read/Write
Inputs Outputs
OperationCE R/W OE UB LB SEM I/O8–I/O15[11] I/O0–I/O7
H X X X X H High Z High Z Deselected: Power-down
X X X H H H High Z High Z Deselected: Power-down
L L X L H H Data In High Z Write to Upper Byte Only
L L X H L H High Z Data In Write to Lower Byte Only
L L X L L H Data In Data In Write to Both Bytes
L H L L H H Data Out High Z Read Upper Byte Only
L H L H L H High Z Data Out Read Lower Byte Only
L H L L L H Data Out Data Out Read Both Bytes
X X H X X X High Z High Z Outputs Disabled
H H L X X L Data Out Data Out Read Data in Semaphore Flag
X H L H H L Data Out Data Out Read Data in Semaphore Flag
H X X X L Data In Data In Write DIN0 into Semaphore Flag
X X H H L Data In Data In Write DIN0 into Semaphore Flag
LXXLXL Not Allowed
L X X X L L Not Allowed
Table 2. Interrupt Operation Example (Assumes BUSYL = BUSYR = HIGH)[12]
Function
Left Port Right Port
R/WLCELOELA0L–13L INTLR/WRCEROERA0R–13R INTR
Set Right INTR Flag L L X 3FFF[15] XXXX X L
[14]
Reset Right INTR Flag X X X X X X L L 3FFF[15] H[13]
Set Left INTL Flag X X X X L[13] LLX 3FFE
[15] X
Reset Left INTL Flag X L L 3FFE[15] H
[14] XXX X X
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
Document #: 001-01638 Rev. *C Page 8 of 26
Table 3. Input Read Register Operation[16, 19]
SFEN CE R/W OE UB LB ADDR I/O0–I/O1I/O2–I/O15 Mode
HLHLLLx0000-MaxVALID
[17] VALID[17] Standard Memory Access
L L H L X L x0000 VALID[18] X IRR Read
Table 4. Output Drive Register [20]
SFEN CE R/W OE UB LB ADDR I/O0–I/O4I/O5–I/O15 Mode
HLHX
[21] L[17] L[17] x0000-Max VALID[17] VALID[17] Standard Memory Access
LLLXXLx0001VALID
[18] X ODR Write[20, 22]
LLHLXLx0001VALID
[18] X ODR Read[20]
Table 5. Semaphore Operation Example
Function I/O0–I/O15 Left I/O0–I/O15 Right Status
No action 1 1 Semaphore-free
Left port writes 0 to semaphore 0 1 Left Port has semaphore token
Right port writes 0 to semaphore 0 1 No change. Right side has no write access to semaphore
Left port writes 1 to semaphore 1 0 Right port obtains semaphore token
Left port writes 0 to semaphore 1 0 No change. Left port has no write access to semaphore
Right port writes 1 to semaphore 0 1 Left port obtains semaphore token
Left port writes 1 to semaphore 1 1 Semaphore-free
Right port writes 0 to semaphore 1 0 Right port has semaphore token
Right port writes 1 to semaphore 1 1 Semaphore free
Left port writes 0 to semaphore 0 1 Left port has semaphore token
Left port writes 1 to semaphore 1 1 Semaphore-free
Notes:
16. SFEN = VIL for IRR reads.
17. UB or LB = VIL. If LB = VIL, then DQ<7:0> are valid. If UB = VIL then DQ<15:8> are valid.
18. LB must be active (LB = VIL) for these bits to be valid.
19. SFEN active when either CEL = VIL or CER = VIL. It is inactive when CEL = CER = VIH.
20. SFEN = VIL for ODR reads and writes.
21. Output enable must be low (OE = VIL) during reads for valid data to be output.
22. During ODR writes data will also be written to the memory.
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
Document #: 001-01638 Rev. *C Page 9 of 26
Maximum Ratings[23]
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage to Ground Potential ............... –0.5V to +3.3V
DC Voltage Applied to
Outputs in High-Z State..........................–0.5V to VCC + 0.5V
DC Input Voltage[24] ...............................–0.5V to VCC + 0.5V
Output Current into Outputs (LOW)............................. 90 mA
Static Discharge Voltage.......................................... > 2000V
Latch-up Current.................................................... > 200 mA
Operating Range
Range Ambient Temperature VCC
Commercial 0°C to +70°C 1.8V ± 100 mV
2.5V ± 100 mV
3.0V ± 300 mV
Industrial –40°C to +85°C 1.8V ± 100 mV
2.5V ± 100 mV
3.0V ± 300 mV
Electrical Characteristics for VCC = 1.8V Over the Operating Range
Parameter Description
CYDC256B16,
CYDC128B16,
CYDC064B16,
CYDC128B08,
CYDC064B08
CYDC256B16,
CYDC128B16,
CYDC064B16,
CYDC128B08,
CYDC064B08
Unit
-40 -55
P1 I/O
Voltage
P2 I/O
Voltage Min. Typ. Max. Min. Typ. Max.
VOH Output HIGH Voltage (IOH = –100 µA) 1.8V (any port) VDDIO
– 0.2
VDDIO
– 0.2
V
Output HIGH Voltage (IOH = –2 mA) 2.5V (any port) 2.0 2.0 V
Output HIGH Voltage (IOH = –2 mA) 3.0V (any port) 2.1 2.1 V
VOL Output LOW Voltage (IOL = 100 µA)1.8V (any port) 0.2 0.2 V
Output HIGH Voltage (IOL = 2 mA) 2.5V (any port) 0.4 0.4 V
Output HIGH Voltage (IOL = 2 mA) 3.0V (any port) 0.4 0.4 V
VOL ODR ODR Output LOW Voltage (IOL = 8 mA)1.8V (any port) 0.2 0.2 V
2.5V (any port) 0.2 0.2 V
3.0V (any port) 0.2 0.2 V
VIH Input HIGH Voltage 1.8V (any port) 1.2 VDDIO
+ 0.2
1.2 VDDIO
+ 0.2
V
2.5V (any port) 1.7 VDDIO
+ 0.3
1.7 VDDIO
+ 0.3
V
3.0V (any port) 2.0 VDDIO
+ 0.2
2.0 VDDIO
+ 0.2
V
VIL Input LOW Voltage 1.8V (any port) –0.2 0.4 –0.2 0.4 V
2.5V (any port) –0.3 0.6 –0.3 0.6 V
3.0V (any port) –0.2 0.7 –0.2 0.7 V
IOZ Output Leakage Current 1.8V 1.8V –1 1 –1 1 µA
2.5V 2.5V –1 1 –1 1 µA
3.0V 3.0V –1 1 –1 1 µA
ICEX ODR ODR Output Leakage Current.
VOUT =V
DDIO
1.8V 1.8V –1 1 –1 1 µA
2.5V 2.5V –1 1 –1 1 µA
3.0V 3.0V –1 1 –1 1 µA
Notes:
23. The voltage on any input or I/O pin can not exceed the power pin during power-up.
24. Pulse width < 20 ns.
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
Document #: 001-01638 Rev. *C Page 10 of 26
IIX Input Leakage Current 1.8V 1.8V –1 1 –1 1 µA
2.5V 2.5V –1 1 –1 1 µA
3.0V 3.0V –1 1 –1 1 µA
ICC Operating Current (VCC = Max.,
IOUT = 0 mA) Outputs Disabled
Ind. 1.8V 1.8V 25 40 15 25 mA
ISB1 Standby Current (Both Ports TTL
Level) CEL and CER ≥ VCC – 0.2,
SEML = SEMR = VCC – 0.2, f = fMAX
Ind. 1.8V 1.8V 2 6 2 6 µA
ISB2 Standby Current (One Port TTL
Level) CEL | CER ≥ VIH, f = fMAX
Ind. 1.8V 1.8V 8.5 18 8.5 14 mA
ISB3 Standby Current (Both Ports
CMOS Level) CEL & CER ≥
VCC −0.2V, SEML and SEMR >
VCC – 0.2V, f = 0
Ind. 1.8V 1.8V 2 6 2 6 µA
ISB4 Standby Current (One Port CMOS
Level) CEL | CER ≥ VIH, f = fMAX[25] Ind. 1.8V 1.8V 8.5 18 8.5 14 mA
Notes:
25. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level
standby ISB3.
Electrical Characteristics for VCC = 1.8V (continued) Over the Operating Range
Parameter Description
CYDC256B16,
CYDC128B16,
CYDC064B16,
CYDC128B08,
CYDC064B08
CYDC256B16,
CYDC128B16,
CYDC064B16,
CYDC128B08,
CYDC064B08
Unit
-40 -55
P1 I/O
Voltage
P2 I/O
Voltage Min. Typ. Max. Min. Typ. Max.
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
Document #: 001-01638 Rev. *C Page 11 of 26
Electrical Characteristics for VCC = 2.5V Over the Operating Range
Parameter Description
CYDC256B16,
CYDC128B16,
CYDC064B16,
CYDC128B08,
CYDC064B08
CYDC256B16,
CYDC128B16,
CYDC064B16,
CYDC128B08,
CYDC064B08
Unit
-40 -55
P1 I/O
Voltage
P2 I/O
Voltage Min. Typ. Max. Min. Typ. Max.
VOH Output HIGH Voltage (IOH = –2 mA) 2.5V (any port) 2.0 2.0 V
Output HIGH Voltage (IOH = –2 mA) 3.0V (any port) 2.1 2.1 V
VOL Output LOW Voltage (IOL = 2 mA)2.5V (any port) 0.4 0.4 V
Output LOW Voltage (IOL = 2 mA)3.0V (any port) 0.4 0.4 V
VOL ODR ODR Output LOW Voltage (IOL = 8 mA)2.5V (any port) 0.2 0.2 V
3.0V (any port) 0.2 0.2 V
VIH Input HIGH Voltage 2.5V (any port) 1.7 VDDIO
+ 0.3
1.7 VDDIO
+ 0.3
V
3.0V (any port) 2.0 VDDIO
+ 0.2
2.0 VDDIO
+ 0.2
V
VIL Input LOW Voltage 2.5V (any port) –0.3 0.6 –0.3 0.6 V
3.0V (any port) –0.2 0.7 –0.2 0.7 V
IOZ Output Leakage Current 2.5V 2.5V –1 1 –1 1 µA
3.0V 3.0V –1 1 –1 1 µA
ICEX ODR ODR Output Leakage Current.
VOUT =V
CC
2.5V 2.5V –1 1 –1 1 µA
3.0V 3.0V –1 1 –1 1 µA
IIX Input Leakage Current 2.5V 2.5V –1 1 –1 1 µA
3.0V 3.0V –1 1 –1 1 µA
ICC Operating Current (VCC = Max.,
IOUT = 0 mA) Outputs Disabled
Ind. 2.5V 2.5V 39 55 28 40 mA
ISB1 Standby Current (Both Ports TTL
Level) CEL and CER ≥ VCC – 0.2,
SEM L= SEMR = VCC – 0.2, f=fMAX
Ind. 2.5V 2.5V 6 8 6 8 µA
ISB2 Standby Current (One Port TTL
Level) CEL | CER ≥ VIH, f = fMAX
Ind. 2.5V 2.5V 21 30 18 25 mA
ISB3 Standby Current (Both Ports
CMOS Level) CEL & CER ≥
VCC −0.2V, SEML and SEMR >
VCC – 0.2V, f = 0
Ind. 2.5V 2.5V 4 6 4 6 µA
ISB4 Standby Current (One Port CMOS
Level) CEL | CER ≥ VIH, f = fMAX[25] Ind. 2.5V 2.5V 21 30 18 25 mA
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
Document #: 001-01638 Rev. *C Page 12 of 26
Electrical Characteristics for 3.0V Over the Operating Range
Parameter Description
CYDC256B16,
CYDC128B16,
CYDC064B16,
CYDC128B08,
CYDC064B08
CYDC256B16,
CYDC128B16,
CYDC064B16,
CYDC128B08,
CYDC064B08
Unit
-40 -55
P1 I/O
Voltage
P2 I/O
Voltage Min. Typ. Max. Min. Typ. Max.
VOH Output HIGH Voltage (IOH = –2 mA) 3.0V (any port) 2.1 2.1 V
VOL Output LOW Voltage (IOL = 2 mA) 3.0V (any port) 0.4 0.4 V
VOL ODR ODR Output LOW Voltage (IOL = 8 mA)3.0V (any port) 0.2 0.2 V
VIH Input HIGH Voltage 3.0V (any port) 2.0 VDDIO
+ 0.2
2.0 VDDIO
+ 0.2
V
VIL Input LOW Voltage 3.0V (any port) –0.2 0.7 –0.2 0.7 V
IOZ Output Leakage Current 3.0V 3.0V –1 1 –1 1 µA
ICEX ODR ODR Output Leakage Current.
VOUT =V
CC
3.0V 3.0V –1 1 –1 1 µA
IIX Input Leakage Current 3.0V 3.0V –1 1 –1 1 µA
ICC Operating Current (VCC = Max.,
IOUT = 0 mA) Outputs Disabled
Ind. 3.0V 3.0V 49 70 42 60 mA
ISB1 Standby Current (Both Ports TTL
Level) CEL and CER ≥ VCC – 0.2,
SEML = SEMR = VCC – 0.2, f = fMAX
Ind. 3.0V 3.0V 7 10 7 10 µA
ISB2 Standby Current (One Port TTL
Level) CEL | CER ≥ VIH, f = fMAX
Ind. 3.0V 3.0V 28 40 25 35 mA
ISB3 Standby Current (Both Ports
CMOS Level) CEL & CER ≥
VCC −0.2V, SEML and SEMR >
VCC – 0.2V, f = 0
Ind. 3.0V 3.0V 6 8 6 8 µA
ISB4 Standby Current (One Port CMOS
Level) CEL | CER ≥ VIH, f = fMAX[25] Ind. 3.0V 3.0V 28 40 25 35 mA
Capacitance[26]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VCC = 3.0V
9pF
COUT Output Capacitance 10 pF
Note:
26. Tested initially and after any design or process changes that may affect these parameters.
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
Document #: 001-01638 Rev. *C Page 13 of 26
7
AC Test Loads and Waveforms
Switching Characteristics for VCC = 1.8V Over the Operating Range[27]
Parameter Description
CYDC256B16,
CYDC128B16,
CYDC064B16,
CYDC128B08,
CYDC064B08
CYDC256B16,
CYDC128B16,
CYDC064B16,
CYDC128B08,
CYDC064B08
Unit
-40 -55
Min. Max. Min. Max.
Read Cycle
tRC Read Cycle Time 40 55 ns
tAA Address to Data Valid 40 55 ns
tOHA Output Hold From Address Change 5 5 ns
tACE[28] CE LOW to Data Valid 40 55 ns
tDOE OE LOW to Data Valid 25 30 ns
tLZOE[29, 30, 31] OE Low to Low Z 5 5 ns
tHZOE[29, 30, 31] OE HIGH to High Z 15 25 ns
tLZCE[29, 30, 31] CE LOW to Low Z 5 5 ns
tHZCE[29, 30, 31] CE HIGH to High Z 15 25 ns
tPU[31] CE LOW to Power-Up 0 0 ns
tPD[31] CE HIGH to Power-Down 40 55 ns
tABE[28] Byte Enable Access Time 40 55 ns
Write Cycle
tWC Write Cycle Time 40 55 ns
tSCE[28] CE LOW to Write End 30 45 ns
tAW Address Valid to Write End 30 45 ns
Notes:
27. Test conditions assume signal transition time of 3 ns or less, timing reference levels of VCC/2, input pulse levels of 0 to VCC, and output loading of the specified
IOI/IOH and 30-pF load capacitance.
28. To access RAM, CE = L, UB = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire tSCE time.
29. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
30. Test conditions used are Load 3.
31. This parameter is guaranteed but not tested. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with
Busy waveform
1.8V
GND 90% 90%
10%
10%
ALL INPUT PULSES
(a) Normal Load (Load 1)
R1
3.0V/2.5V/1.8V
OUTPUT
R2
C = 30 pF
VTH = 0.8V
OUTPUT
(b) Thévenin Equivalent (Load 1) (c) Three-State Delay (Load 2)
R1
R2
3.0V/2.5V/1.8V
OUTPUT
RTH = 6 kΩ
≤ 3 ns ≤ 3 ns
including scope and jig)
(Used for tLZ, tHZ, tHZWE, and tLZWE
3.0V/2.5V 1.8V
R1 1022Ω13500Ω
R2 792Ω10800Ω
C = 30 pF
C = 5 pF
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
Document #: 001-01638 Rev. *C Page 14 of 26
tHA Address Hold From Write End 0 0 ns
tSA[28] Address Set-up to Write Start 0 0 ns
tPWE Write Pulse Width 25 40 ns
tSD Data Set-up to Write End 20 30 ns
tHD Data Hold From Write End 0 0 ns
tHZWE[30, 31] R/W LOW to High Z 15 25 ns
tLZWE[30, 31] R/W HIGH to Low Z 0 0 ns
tWDD[32] Write Pulse to Data Delay 55 80 ns
tDDD[32] Write Data Valid to Read Data Valid 45 65 ns
Busy Timing[33]
tBLA BUSY LOW from Address Match 30 45 ns
tBHA BUSY HIGH from Address Mismatch 30 45 ns
tBLC BUSY LOW from CE LOW 30 45 ns
tBHC BUSY HIGH from CE HIGH 30 45 ns
tPS[34] Port Set-up for Priority 5 5 ns
tWB R/W HIGH after BUSY (Slave) 0 0 ns
tWH R/W HIGH after BUSY HIGH (Slave) 20 35 ns
tBDD[35] BUSY HIGH to Data Valid 30 40 ns
Interrupt Timing[33]
tINS INT Set Time 35 45 ns
tINR INT Reset Time 35 45 ns
Semaphore Timing
tSOP SEM Flag Update Pulse (OE or SEM)10 15 ns
tSWRD SEM Flag Write to Read Time 10 10 ns
tSPS SEM Flag Contention Window 10 10 ns
tSAA SEM Address Access Time 40 55 ns
Notes:
32. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
33. Test conditions used are Load 2.
34. Add 2ns to this value when the I/O ports are operating at different voltages.
35. tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual).
Switching Characteristics for VCC = 1.8V Over the Operating Range[27] (continued)
Parameter Description
CYDC256B16,
CYDC128B16,
CYDC064B16,
CYDC128B08,
CYDC064B08
CYDC256B16,
CYDC128B16,
CYDC064B16,
CYDC128B08,
CYDC064B08
Unit
-40 -55
Min. Max. Min. Max.
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
Document #: 001-01638 Rev. *C Page 15 of 26
Switching Characteristics for VCC = 2.5V Over the Operating Range
Parameter Description
CYDC256B16,
CYDC128B16,
CYDC064B16,
CYDC128B08,
CYDC064B08
CYDC256B16,
CYDC128B16,
CYDC064B16,
CYDC128B08,
CYDC064B08
Unit
-40 -55
Min. Max. Min. Max.
Read Cycle
tRC Read Cycle Time 40 55 ns
tAA Address to Data Valid 40 55 ns
tOHA Output Hold From Address Change 5 5 ns
tACE[28] CE LOW to Data Valid 40 55 ns
tDOE OE LOW to Data Valid 25 30 ns
tLZOE[29, 30, 31] OE Low to Low Z 2 2 ns
tHZOE[29, 30, 31] OE HIGH to High Z 15 15 ns
tLZCE[29, 30, 31] CE LOW to Low Z 2 2 ns
tHZCE[29, 30, 31] CE HIGH to High Z 15 15 ns
tPU[31] CE LOW to Power-Up 0 0 ns
tPD[31] CE HIGH to Power-Down 40 55 ns
tABE[28] Byte Enable Access Time 40 55 ns
Write Cycle
tWC Write Cycle Time 40 55 ns
tSCE[28] CE LOW to Write End 30 45 ns
tAW Address Valid to Write End 30 45 ns
tHA Address Hold From Write End 0 0 ns
tSA[28] Address Set-up to Write Start 0 0 ns
tPWE Write Pulse Width 25 40 ns
tSD Data Set-up to Write End 20 30 ns
tHD Data Hold From Write End 0 0 ns
tHZWE[30, 31] R/W LOW to High Z 15 25 ns
tLZWE[30, 31] R/W HIGH to Low Z 0 0 ns
tWDD[32] Write Pulse to Data Delay 55 80 ns
tDDD[32] Write Data Valid to Read Data Valid 45 65 ns
Busy Timing[33]
tBLA BUSY LOW from Address Match 30 45 ns
tBHA BUSY HIGH from Address Mismatch 30 45 ns
tBLC BUSY LOW from CE LOW 30 45 ns
tBHC BUSY HIGH from CE HIGH 30 45 ns
tPS[34] Port Set-up for Priority 5 5 ns
tWB R/W HIGH after BUSY (Slave) 0 0 ns
tWH R/W HIGH after BUSY HIGH (Slave) 20 35 ns
tBDD[35] BUSY HIGH to Data Valid 30 40 ns
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
Document #: 001-01638 Rev. *C Page 16 of 26
Interrupt Timing[33]
tINS INT Set Time 35 45 ns
tINR INT Reset Time 35 45 ns
Semaphore Timing
tSOP SEM Flag Update Pulse (OE or SEM)10 15 ns
tSWRD SEM Flag Write to Read Time 10 10 ns
tSPS SEM Flag Contention Window 10 10 ns
tSAA SEM Address Access Time 40 55 ns
Switching Characteristics for VCC = 3.0V Over the Operating Range
Parameter Description
CYDC256B16,
CYDC128B16,
CYDC064B16,
CYDC128B08,
CYDC064B08
CYDC256B16,
CYDC128B16,
CYDC064B16,
CYDC128B08,
CYDC064B08 Unit
-40 -55
Min. Max. Min. Max.
Read Cycle
tRC Read Cycle Time 40 55 ns
tAA Address to Data Valid 40 55 ns
tOHA Output Hold From Address Change 5 5 ns
tACE[28] CE LOW to Data Valid 40 55 ns
tDOE OE LOW to Data Valid 25 30 ns
tLZOE[29, 30, 31] OE Low to Low Z 1 1 ns
tHZOE[29, 30, 31] OE HIGH to High Z 15 15 ns
tLZCE[29, 30, 31] CE LOW to Low Z 1 1 ns
tHZCE[29, 30, 31] CE HIGH to High Z 15 15 ns
tPU[31] CE LOW to Power-Up 0 0 ns
tPD[31] CE HIGH to Power-Down 40 55 ns
tABE[28] Byte Enable Access Time 40 55 ns
Write Cycle
tWC Write Cycle Time 40 55 ns
tSCE[28] CE LOW to Write End 30 45 ns
tAW Address Valid to Write End 30 45 ns
tHA Address Hold From Write End 0 0 ns
tSA[28] Address Set-up to Write Start 0 0 ns
tPWE Write Pulse Width 25 40 ns
tSD Data Set-up to Write End 20 30 ns
tHD Data Hold From Write End 0 0 ns
Switching Characteristics for VCC = 2.5V Over the Operating Range (continued)
Parameter Description
CYDC256B16,
CYDC128B16,
CYDC064B16,
CYDC128B08,
CYDC064B08
CYDC256B16,
CYDC128B16,
CYDC064B16,
CYDC128B08,
CYDC064B08
Unit
-40 -55
Min. Max. Min. Max.
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
Document #: 001-01638 Rev. *C Page 17 of 26
tHZWE[30, 31] R/W LOW to High Z 15 25 ns
tLZWE[30, 31] R/W HIGH to Low Z 0 0 ns
tWDD[32] Write Pulse to Data Delay 55 80 ns
tDDD[32] Write Data Valid to Read Data Valid 45 65 ns
Busy Timing[33]
tBLA BUSY LOW from Address Match 30 45 ns
tBHA BUSY HIGH from Address Mismatch 30 45 ns
tBLC BUSY LOW from CE LOW 30 45 ns
tBHC BUSY HIGH from CE HIGH 30 45 ns
tPS[34] Port Set-up for Priority 5 5 ns
tWB R/W HIGH after BUSY (Slave) 0 0 ns
tWH R/W HIGH after BUSY HIGH (Slave) 20 35 ns
tBDD[35] BUSY HIGH to Data Valid 30 40 ns
Interrupt Timing[33]
tINS INT Set Time 35 45 ns
tINR INT Reset Time 35 45 ns
Semaphore Timing
tSOP SEM Flag Update Pulse (OE or SEM)10 15 ns
tSWRD SEM Flag Write to Read Time 10 10 ns
tSPS SEM Flag Contention Window 10 10 ns
tSAA SEM Address Access Time 40 55 ns
Switching Characteristics for VCC = 3.0V Over the Operating Range (continued)
Parameter Description
CYDC256B16,
CYDC128B16,
CYDC064B16,
CYDC128B08,
CYDC064B08
CYDC256B16,
CYDC128B16,
CYDC064B16,
CYDC128B08,
CYDC064B08 Unit
-40 -55
Min. Max. Min. Max.
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
Document #: 001-01638 Rev. *C Page 18 of 26
Switching Waveforms
Read Cycle No.1 (Either Port Address Access)[36, 37, 38]
Read Cycle No.2 (Either Port CE/OE Access)[36, 39, 40]
Read Cycle No. 3 (Either Port)[36, 38, 41, 42]
Notes:
36. R/W is HIGH for read cycles.
37. Device is continuously selected CE = VIL and UB or LB = VIL. This waveform cannot be used for semaphore reads.
38. OE = VIL.
39. Address valid prior to or coincident with CE transition LOW.
40. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL.
41. R/W must be HIGH during all address transitions.
42. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM and a LOW UB or LB.
tRC
tAA
tOHA
DATA VALIDPREVIOUS DATA VALID
DATA OUT
ADDRESS
tOHA
tACE
tLZOE
tDOE
tHZOE
tHZCE
DATA VALID
tLZCE
tPU tPD
ISB
ICC
DATA OUT
OE
CE and
LB or UB
CURRENT
UB or LB
DATA OUT
tRC
ADDRESS
tAA tOHA
CE
tLZCE
tABE
tHZCE
tHZCE
tACE
tLZCE
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
Document #: 001-01638 Rev. *C Page 19 of 26
Write Cycle No.1: R/W Controlled Timing[41, 42, 43, 44, 45, 46]
Write Cycle No. 2: CE Controlled Timing[41, 42, 43, 48]
Notes:
43. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
44. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to
be placed on the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short
as the specified tPWE.
45. To access RAM, CE = VIL, SEM = VIH.
46. To access upper byte, CE = VIL, UB = VIL, SEM = VIH.
To access lower byte, CE = VIL, LB = VIL, SEM = VIH.
47. Transition is measured ±0 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.
48. During this period, the I/O pins are in the output state, and input signals must not be applied.
Switching Waveforms (continued)
tAW
tWC
tPWE
tHD
tSD
tHA
CE
R/W
OE
DATA OUT
DATA IN
ADDRESS
tHZOE
tSA
tHZWE tLZWE
[47]
[47]
[44]
[45, 46]
NOTE 48 NOTE 48
tAW
tWC
tSCE
tHD
tSD
tHA
CE
R/W
DATA IN
ADDRESS
tSA
[45, 46]
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
Document #: 001-01638 Rev. *C Page 20 of 26
Semaphore Read After Write Timing, Either Side[49, 50]
Timing Diagram of Semaphore Contention[51, 52]
Notes:
49. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
50. CE = HIGH for the duration of the above timing (both write and read cycle).
51. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH.
52. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable.
Switching Waveforms (continued)
tSOP
tSAA
VALID ADRESS VALID ADRESS
tHD
DATAIN VALID
tOHA
tAW
tHA
tACE
tSOP
tSCE
tSD
tSA tPWE
tSWRD tDOE
WRITE CYCLE READ CYCLE
OE
R/W
I/O0
SEM
A0–A2
DATAOUT VALID
MATCH
tSPS
MATCH
R/WL
SEML
R/WR
SEMR
A0L–A2L
A0R–A2R
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
Document #: 001-01638 Rev. *C Page 21 of 26
Timing Diagram of Read with BUSY (M/S=HIGH)[53]
Write Timing with Busy Input (M/S = LOW)
Note:
53. CEL = CER = LOW.
Switching Waveforms (continued)
VALID
tDDD
tWDD
MATCH
MATCH
R/WR
DATA INR
DATAOUTL
tWC
ADDRESSR
tPWE
VALID
tSD tHD
ADDRESSL
tPS
tBLA tBHA
tBDD
BUSYL
tPWE
R/W
BUSY
tWB tWH
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
Document #: 001-01638 Rev. *C Page 22 of 26
Busy Timing Diagram No.1 (CE Arbitration)
Busy Timing Diagram No.2 (Address Arbitration)[54]
Note:
54. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.
Switching Waveforms (continued)
ADDRESS MATCH
tPS
tBLC tBHC
ADDRESS MATCH
tPS
tBLC tBHC
CER Valid First
ADDRESSL,R
BUSYR
CEL
CER
BUSYL
CER
CEL
ADDRESSL,R
CEL Valid First[54]
ADDRESS MATCH
tPS
ADDRESSL
BUSYR
ADDRESS MISMATCH
tRC or tWC
tBLA tBHA
ADDRESSR
ADDRESS MATCH ADDRESS MISMATCH
tPS
ADDRESSL
BUSYL
tRC or tWC
tBLA tBHA
ADDRESSR
Right Address Valid First
Left Address Valid First
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
Document #: 001-01638 Rev. *C Page 23 of 26
Interrupt Timing Diagrams
Notes:
55. tHA depends on which enable pin (CEL or R/WL) is deasserted first.
56. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last.
Switching Waveforms (continued)
WRITE 1FFF (OR 1/3FFF)
tWC
Right Side Clears INTR:
tHA
READ 1FFF
tRC
tINR
WRITE 1FFE (OR 1/3FFE)
tWC
Right Side Sets INTL:
Left Side Sets INTR:
Left Side Clears INTL:
READ 1FFE
tINR
tRC
ADDRESSR
CEL
R/WL
INTL
OEL
ADDRESSR
R/WR
CER
INTL
ADDRESSR
CER
R/WR
INTR
OER
ADDRESSL
R/WL
CEL
INTR
tINS
tHA
tINS
(OR 1/3FFF)
OR 1/3FFE)
[55]
[56]
[56]
[56]
[55]
[56]
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
Document #: 001-01638 Rev. *C Page 24 of 26
Ordering Information
16K x16 1.8V Asynchronous Dual-Port SRAM
Speed
(ns) Ordering Code
Package
Name Package Type
Operating
Range
40 CYDC256B16-40BVXC AZ0AB 100-pin Lead-free TQFP Commercial
55 CYDC256B16-55BVXC AZ0AB 100-pin Lead-free TQFP Commercial
55 CYDC256B16-55BVXI AZ0AB 100-pin Lead-free TQFP Industrial
8K x16 1.8V Asynchronous Dual-Port SRAM
Speed
(ns) Ordering Code
Package
Name Package Type
Operating
Range
40 CYDC128B16-40BVXC AZ0AB 100-pin Lead-free TQFP Commercial
55 CYDC128B16-55BVXC AZ0AB 100-pin Lead-free TQFP Commercial
55 CYDC128B16-55BVXI AZ0AB 100-pin Lead-free TQFP Industrial
4K x16 1.8V Asynchronous Dual-Port SRAM
Speed
(ns) Ordering Code
Package
Name Package Type
Operating
Range
40 CYDC064B16-40BVXC AZ0AB 100-pin Lead-free TQFP Commercial
55 CYDC064B16-55BVXC AZ0AB 100-pin Lead-free TQFP Commercial
55 CYDC064B16-55BVXI AZ0AB 100-pin Lead-free TQFP Industrial
16K x8 1.8V Asynchronous Dual-Port SRAM
Speed
(ns) Ordering Code
Package
Name Package Type
Operating
Range
40 CYDC128B08-40BVXC AZ0AB 100-pin Lead-free TQFP Commercial
55 CYDC128B08-55BVXC AZ0AB 100-pin Lead-free TQFP Commercial
55 CYDC128B08-55BVXI AZ0AB 100-pin Lead-free TQFP Industrial
8K x8 1.8V Asynchronous Dual-Port SRAM
Speed
(ns) Ordering Code
Package
Name Package Type
Operating
Range
40 CYDC064B08-40BVXC AZ0AB 100-pin Lead-free TQFP Commercial
55 CYDC064B08-55BVXC AZ0AB 100-pin Lead-free TQFP Commercial
55 CYDC064B08-55BVXI AZ0AB 100-pin Lead-free TQFP Industrial
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
Document #: 001-01638 Rev. *C Page 25 of 26
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
All products and company names mentioned in this document may be the trademarks of their respective holders.
Package Diagram
100-Pin Thin Plastic Quad Flat Pack (TQFP) A100
51-85048-*C
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
Document #: 001-01638 Rev. *C Page 26 of 26
Document History Page*C
Document Title: CYDC064B16/CYDC128B16/CYDC256B16/CYDC064B08/CYDC128B08 1.8V 4K/8K/16K x 16 and 8K/16K
x 8 ConsuMoBL Dual-Port Static RAM
Document Number: 001-01638
REV. ECN NO. Issue Date
Orig. of
Change Description of Change
** 385185 SEE ECN YDT New data sheet
*A 396697 SEE ECN KGH Updated ISB2 and ISB4 typo to mA.
Updated tINS and tINR for -55 to 31ns.
*B 404777 SEE ECN KGH Updated IOH and IOL values for the 1.8V, 2.5V and 3.0V parameters VOH and
VOL
Replaced -35 speed bin with -40
Updated Switching Characteristics for VCC = 2.5V and VCC = 3.0V
Included note 34
*C 463014 SEE ECN HKH Changed spec title to from “Consumer Dual-Port” to “ConsuMoBL Dual-Port”
Cypress Internet Release
