SW06GSZ-REEL - ANALOG DEVICES

FUNCTIONAL BLOCK DIAGRAM

LEVEL

SHIFT

V+

V–

IN 1

IN 2

IN 3

IN 4

DIS 13

GND

REV. A

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

Quad SPST JFET

Analog Switch

SW06

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 617/329-4700 Fax: 617/326-8703

FEATURES

Two Normally Open and Two Normally Closed SPST

Switches with Disable

Switches Can Be Easily Configured as a Dual SPDT or

a DPDT

Highly Resistant to Static Discharge Destruction

Higher Resistance to Radiation than Analog Switches

Designed with MOS Devices

Guaranteed RON Matching: 10% max

Guaranteed Switching Speeds

TON = 500 ns max

TOFF = 400 ns max

Guaranteed Break-Before-Make Switching

Low “ON” Resistance: 80 V max

Low RON Variation from Analog Input Voltage: 5%

Low Total Harmonic Distortion: 0.01%

Low Leakage Currents at High Temperature

TA = +1258C: 100 nA max

TA = +858C: 30 nA max

Digital Inputs TTL/CMOS Compatible and Independent

of V+

Improved Specifications and Pin Compatible to

LF-11333/13333

Dual or Single Power Supply Operation

Available in Die Form

GENERAL DESCRIPTION

The SW06 is a four channel single-pole, single-throw analog

switch that employs both bipolar and ion-implanted FET

devices. The SW06 FET switches use bipolar digital logic inputs

which are more resistant to static electricity than CMOS devices.

Ruggedness and reliability are inherent in the SW06 design and

construction technology.

Increased reliability is complemented by excellent electrical

specifications. Potential error sources are reduced by minimizing

“ON” resistance and controlling leakage currents at high tem-

peratures. The switching FET exhibits minimal R

variation

over a 20 V analog signal range and with power supply voltage

changes. Operation from a single positive power supply voltage

is possible. With V+ = 36 V, V– = 0 V, the analog signal range

will extend from ground to +32 V.

PNP logic inputs are TTL and CMOS compatible to allow the

SW06 to upgrade existing designs. The logic “0” and logic “1”

input currents are at microampere levels reducing loading on

CMOS and TTL logic.

REV. A

–2–

SW06–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

SW06B SW06F SW06G

Parameter Symbol Conditions Min Typ Max Min Typ Max Min Typ Max Units

“ON” RESISTANCE R

= 0 V, I

= 1 mA 60 80 60 100 100 150 Ω

= ±10 V, I

= 1 mA 65 80 65 100 100 150

MATCH BETWEEN SWITCHES R

Match V

= 0 V, I

= 100 µA

5 10 5 20 20 %

ANALOG VOLTAGE RANGE V

= 1 mA

+10 +11 +10 +11 +10 +11 V

= 1 mA

–10 –15 –10 –15 –10 –15

ANALOG CURRENT RANGE I

= ±10 V 10 15 7 12 5 10 mA

∆R

VS. APPLIED VOLTAGE ∆R

–10 V ≤ V

≤ 10 V, I

= 1.0 mA 5 15 10 20 10 20 %

SOURCE CURRENT IN

“OFF” CONDITION I

S(OFF)

= 10 V, V

= –10 V

0.3 2.0 0.3 2.0 0.3 10 nA

DRAIN CURRENT IN

“OFF” CONDITION I

D(OFF)

= 10 V, V

= –10 V

0.3 2.0 0.3 2.0 0.3 10 nA

SOURCE CURRENT IN I

S(ON)+

= V

= ±10 V

0.3 2.0 0.3 2.0 0.3 10 nA

“ON” CONDITION I

D(ON)

LOGICAL “1” INPUT VOLTAGE V

INH

Full Temperature Range

2, 4

2.0 2.0 2.0 V

LOGICAL “0” INPUT VOLTAGE V

INL

Full Temperature Range

2, 4

0.8 0.8 0.8 V

LOGICAL “1” INPUT CURRENT I

INH

= 2.0 V to 15.0 V

55 10µA

LOGICAL “0” INPUT I

INL

= 0.8 V 1.5 5.0 1.5 5.0 1.5 10.0 µA

TURN-ON TIME t

See Switching Time 340 500 340 600 340 700 ns

Test Circuit

4, 6

TURN-OFF TIME t

OFF

See Switching Time 200 400 200 400 200 500 ns

Test Circuit

4, 6

BREAK-BEFORE-MAKE TIME t

–t

OFF

Note 7 50 140 50 140 50 140 ns

SOURCE CAPACITANCE C

S(OFF)

= 0 V

7.0 7.0 7.0 pF

DRAIN CAPACITANCE C

D(OFF)

= 0 V

5.5 5.5 5.5 pF

CHANNEL “ON” CAPACITANCE C

D(ON)+

= V

= 0 V

15 15 15 pF

S(ON)

“OFF” ISOLATION I

SO(OFF)

= 5 V rms, R

= 680 Ω,58 58 58dB

= 7 pF, f = 500 kHz

CROSSTALK C

= 5 V rms, R

= 680 Ω,70 70 70dB

= 7 pF, f = 500 kHz

POSITIVE SUPPLY CURRENT I+ All Channels “OFF”, 5.0 6.0 5.0 9.0 6.0 9.0 mA

DIS = “0”

NEGATIVE SUPPLY CURRENT I– All Channels “OFF”, 3.0 5.0 4.0 7.0 4.0 7.0 mA

DIS = “0”

GROUND CURRENT I

All Channels “ON” or 3.0 4.0 3.0 4.0 3.0 5.0 mA

“OFF”

(@ V+ = +15 V, V– = –15 V and TA = +258C, unless otherwise noted)

SW06

REV. A –3–

ELECTRICAL CHARACTERISTICS

SW06B SW06F SW06G

Parameter Symbol Conditions Min Typ Max Min Typ Max Min Typ Max Units

TEMPERATURE RANGE T

Operating –55 +125 –25 +85 0 70 °C

“ON” RESISTANCE R

= 0 V, I

= 1.0 mA 75 110 75 125 75 175 Ω

= ±10 V, I

= 1.0 mA 80 110 80 125 80 175

∆R

MATCH BETWEEN SWITCHES R

Match V

= 0 V, I

= 100 µA

6 20 6 25 10 %

ANALOG VOLTAGE RANGE V

= 1.0 mA

+10 +11 +10 +11 +10 +11 V

= 1.0 mA

–10 –15 –10 –15 –10 –15

ANALOG CURRENT RANGE I

= ±10 V 7 12 5 11 11 mA

∆R

WITH APPLIED VOLTAGE ∆R

–10 V ≤ V

≤ 10 V, I

= 1.0 mA 10 12 15 %

SOURCE CURRENT IN V

= 10 V, V

= –10 V

“OFF” CONDITION I

S(OFF)

= Max Operating Temp

3, 9

60 30 60 nA

DRAIN CURRENT IN V

= 10 V, V

= –10 V

“OFF” CONDITION I

D(OFF)

= Max Operating Temp

3, 9

60 30 60 nA

LEAKAGE CURRENT IN I

S(ON)+

= V

= ±10 V 100 30 60 nA

“ON” CONDITION I

D(ON)

= Max Operating Temp

3, 9

LOGICAL “1” INPUT CURRENT I

INH

= 2.0 V to 15.0 V

10 10 15 µA

LOGICAL “0” INPUT CURRENT I

INL

= 0.8 V 4 10 4 10 5 15 µA

TURN-ON TIME t

See Switching Time 440 900 500 900 1000 ns

Test Circuit

4, 8

TURN-OFF TIME t

OFF

See Switching Time 300 500 330 500 500 ns

Test Circuit

4, 8

BREAK-BEFORE-MAKE TIME t

–t

OFF

Note 7 70 70 50 ns

POSITIVE SUPPLY CURRENT I+ All Channels “OFF,” 9.0 13.5 13.5 mA

DIS = “0”

NEGATIVE SUPPLY CURRENT I– All Channels “OFF,” 7.5 10.5 10.5 mA

DIS = “0”

GROUND CURRENT I

All Channels “ON” or 6.0 7.5 7.5 mA

“OFF”

NOTES

(@ V+ = +15 V, V– = –15 V, –558C ≤ TA ≤ +1258C for SW06BQ, –408C ≤ TA ≤ +858C for

SW06FQ and –408C ≤ TA ≤ +858C for SW06GP/GS, unless otherwise noted)

= 0 V, I

= 100 µA. Specified as a percentage of R

AVERAGE

where: R

AVERAGE

ON1

ON2

ON3

ON4

Guaranteed by R

and leakage tests. For normal operation maximum analog signal voltages should be restricted to less than (V+) –4 V.

Switch being tested ON or OFF as indicated, V

INH

= 2.0 V or V

INL

= 0.8 V, per logic truth table.

Also applies to disable pin.

Current tested at V

= 2.0 V. This is worst case condition.

Sample tested.

Switch is guaranteed by design to provide break-before-make operation.

Guaranteed by design.

Parameter tested only at T

= +125°C for military grade device.

Specifications subject to change without notice.

SW06

REV. A

–4–

WAFER TEST LIMITS

SW06N SW06G

Parameter Symbol Conditions Limit Limit Units

“ON” RESISTANCE R

–10 V ≤ V

≤ 10 V, I

≤ 1 mA 80 100 Ω max

MATCH BETWEEN SWITCHES R

Match V

= 0 V, I

≤ 100 µA 15 20 % max

∆R

VS. V

∆R

–10 V ≤ V

≤ 10 V, I

≤ 1 mA 10 20 % max

POSITIVE SUPPLY CURRENT I+ Note 1 6.0 9.0 mA max

NEGATIVE SUPPLY CURRENT I– Note 1 5.0 7.0 mA max

GROUND CURRENT I

Note 1 4.0 4.0 mA max

ANALOG VOLTAGE RANGE V

= 1 mA ±10.0 ±10.0 V min

LOGIC “1” INPUT VOLTAGE V

INH

Note 2 2.0 2.0 V min

LOGIC “0” INPUT VOLTAGE V

INL

Note 2 0.8 0.8 V max

LOGIC “0” INPUT CURRENT I

INL

0 V ≤ V

≤ 0.8 V 5.0 5.0 µA max

LOGIC “1” INPUT CURRENT I

INH

2.0 V ≤ V

≤ 15 V

55µA max

ANALOG CURRENT RANGE I

= ±10 mV 10 7 mA min

NOTE

Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed

for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.

TYPICAL ELECTRICAL CHARACTERISTICS

SW06N SW06G

Parameter Symbol Conditions Typical Typical Units

“ON” RESISTANCE R

–10 V ≤ V

≤ 10 V, I

≤ 1 mA 60 60 Ω

TURN-ON TIME t

340 340 ns

TURN-OFF TIME t

OFF

200 200 ns

DRAIN CURRENT IN

“OFF” CONDITION I

D(OFF)

= 10 V, V

= –10 V 0.3 0.3 nA

“OFF” ISOLATION I

SO(OFF)

f = 500 kHz, R

= 680 Ω58 58 dB

CROSSTALK C

f = 500 kHz, R

= 680 Ω70 70 dB

NOTES

Power supply and ground current specified for switch “ON” or “OFF.”

Guaranteed by R

and leakage tests.

Current tested at V

= 2.0 V. This is worst case condition.

(@ V+ = +15 V, V– = –15 V, TA = +258C, unless otherwise noted)

SW06

REV. A –5–

ORDERING GUIDE

Temperature Package Package

Model Range Description Option

SW06BQ –55°C to +125°C Cerdip Q-16

SW06BRC –55°C to +125°C LCC E-20A

SW06FQ –40°C to +85°C Cerdip Q-16

SW06GP –40°C to +85°C Plastic DIP N-16

SW06GS –40°C to +85°C SOL R-16

TRUTH TABLE

Switch State

Disable Logic Channels Channels

Input Input 1 & 2 3 & 4

0 X OFF OFF

1 or NC 0 OFF ON

1 or NC 1 ON OFF

ABSOLUTE MAXIMUM RATINGS

Operating Temperature Range

SW06BQ, BRC . . . . . . . . . . . . . . . . . . . –55°C to +125°C

SW06FQ . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

SW06GP, GS . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . +300°C

Maximum Junction Temperature . . . . . . . . . . . . . . . . +150°C

V+ Supply to V– Supply . . . . . . . . . . . . . . . . . . . . . . . +36 V

V+ Supply to Ground . . . . . . . . . . . . . . . . . . . . . . . . . +36 V

Logic Input Voltage . . . . . . . . . . . (–4 V or V–) to V+ Supply

Analog Input Voltage Range

Continuous . . . . . . . . . . . . . V– Supply to V+ Supply +20 V

Maximum Current Through

Any Pin Including Switch . . . . . . . . . . . . . . . . . . . . . 30 mA

Package Type u

JA2

Units

16-Pin Hermetic DIP (Q) 100 16 °C/W

16-Pin Plastic DIP (P) 82 39 °C/W

20-Contact LCC (RC) 98 38 °C/W

16-Pin SOL (S) 98 30 °C/W

NOTES

Absolute maximum ratings apply to both DICE and packaged parts, unless

otherwise noted.

is specified for worst case mounting conditions, i.e., θ

is specified for device

in socket for Cerdip, P-DIP, and LCC packages; θ

is specified for device soldered

to printed circuit board for SO package.

DICE CHARACTERISTICS

Die Size 0.101 × 0.097 inch, 9797 sq. mils

(2.565 × 2.464 mm, 6320 sq. mm)

PIN CONNECTIONS

16-Pin DIP (Q or P-Suffix)

16-Pin SOL (S-Suffix)

SW06BRC/883

LCC Package

(RC-Suffix)

SW06–Typical Performance Characteristics

REV. A

–6–

“ON” Resistance vs. Analog Voltage

Leakage Current vs. Analog Voltage

Supply Current vs. Supply Voltage

vs. Temperature

Leakage Current vs. Temperature

Switch Capacitance vs. Analog

Voltage

“ON” Resistance vs. Power Supply

Voltage

Switch Current vs. Voltage

Supply Current vs. Temperature

SW06

REV. A –7–

OFF

Switching Response

Insertion Loss vs. Frequency

Switching Time vs. Analog Voltage

Crosstalk and “OFF” Isolation vs.

Frequency

Switching Time vs. Temperature

Total Harmonic Distortion

Power Supply Rejection vs.

Frequency Overvoltage Characteristics

SW06–Typical Performance Characteristics (Operating and Single Supply)

REV. A

–8–

Leakage Current vs. V

ANALOG

Supply Current vs. Supply Voltage

Switching Time vs. Supply Voltage

Simplified Schematic Diagram (Typical Switch)

NOTE

These single-supply-operation characteristic curves are valid

when the negative power supply V– is tied to the logic ground

reference pin “GND.” TTL input compatibility is still main-

tained when “GND” is the same potential as the TTL ground.

OFF

is measured from 50% of logic input waveform to 0.9 V

The analog voltage range extends from 0 V to V+ –4 V; the

switch will no longer respond to logic control when V

is within

4 volts of V+.

“On” Resistance vs. Analog Voltage

SW06

REV. A –9–

“Off” Isolation Test Circuit

Crosstalk Test Circuit

Switching Time Test Circuit

SW06

REV. A

–10–

APPLICATIONS INFORMATION

The single analog switch product configures, by appropriate pin

connections, into four switch applications. As shown in Figure

1, the SW06 connects as a QUAD SPST, a DUAL SPDT, a

DUAL DPST, or a DPDT analog switch. This versatility in-

creases further when taking advantage of the disable input (DIS)

which turns all switches OFF when taken active low.

Ion-implantation of the JFET analog switch achieves low ON

resistance and tight channel-to-channel matching. Combining

the low ON resistance and low leakage currents results in a

worst case voltage error figure V

ERROR

@ +125°C = I

D(ON)

SD(ON)

= 100 nA × 100 Ω = 11 microvolts. This amount of er-

ror is negligible considering dissimilar-metal thermally-induced

offsets will be in the 5 to 15 microvolt range.

LOGIC INPUTS

The logic inputs (IN

) and disable input (DIS) are referenced

to a TTL logic threshold value of two forward diode drops (1.4 V

at +25°C) above the GND terminal. These inputs use PNP

transistors which draw maximum current at a logic “0” level and

drops to a leakage current of a reverse biased diode as the logic

input voltage raises above 1.4 volts. Any logic input voltage

greater than 2.0 volts becomes logic “1,” less than 0.8 volts be-

comes logic “0” resulting in full TTL noise immunity not avail-

able from similar CMOS input analog switches. The PNP

transistor inputs require such low input current that the SW06

approaches fan-ins of CMOS input devices. These bipolar logic

inputs exceed any CMOS input circuit in resistance to static

voltage and radiation susceptibility. No damage will occur to the

SW06 if logic high voltages are present when the SW06 power

supplies are OFF. When the V+ and V– supplies are OFF, the

logic inputs present a reverse bias diode loading to active logic

inputs. Input logic thresholds are independent of V+ and V–

supplies making single V+ supply operation possible by simply

connecting GND and V– together to the logic ground supply.

ANALOG VOLTAGE AND CURRENT

ANALOG VOLTAGE

These switches have constant ON resistance for analog voltages

from the negative power supply (V–) to within 4 volts of the

positive power supply. This characteristic shown in the plots re-

sults in good total harmonic distortion, especially when com-

pared to CMOS analog switches that have a 20 to 30 percent

variation in ON resistance versus analog voltage. Positive analog

input voltage should be restricted to 4 volts less than V+ assur-

ing the switch remains open circuit in the OFF state. No in-

crease in switch ON resistance occurs when operating at supply

voltages less than ±15 volts (see plot). Small signals have a 3 dB

down frequency of 70 MHz (see insertion loss versus frequency

plot).

ANALOG CURRENT

The analog switches in the ON state are JFETs biased in their

triode region and act as switches for analog current up to the I

specification (see plot of I

vs V

). Some applications require

pulsed currents exceeding the I

spec. For example, an integra-

tor reset switch discharging a shunt capacitor will produce a

peak current of I

A(PEAK)

= V

CAP

DS(ON)

. In this application, it is

best to connect the source to the most positive end of the ca-

pacitor, thereby achieving the lowest switch resistance and

Figure 1. Functional Applications of SW06

SW06

REV. A –11–

fastest reset times. The switch can easily handle any amount of

capacitor discharge current subject only to the maximum heat

dissipation of the package and the maximum operating junction

temperature from which repetition can be established.

SWITCHING

Switching time t

and t

OFF

characteristics are plotted versus

ANALOG

and temperature. In all cases, t

OFF

is designed faster

than t

to ensure a break-before-make interval for SPDT and

DPDT applications. The disable input (DIS) has the same

switching times (t

and t

OFF

) as the logic inputs (IN

Switching transients occurring at the source and drain contacts

results from ac coupling of the switching FETs gate-to-source

and gate-to-drain coupling capacitance. The switch turn ON

will cause a negative going spike to occur and the turn OFF will

cause a positive spike to occur. These spikes can be reduced by

additional capacitance loading, lower values of R

, or switching

an additional switch (with its extra contact floating) to the op-

posite state connected to the spike sensitive node.

DISABLE NODE

This TTL compatible node is similar to the logic inputs IN

but

has an internal 2 µA current source pull-up. If disable is left un-

connected, it will assume the logic “1” state, then the state of

the switches is controlled only by the logic inputs IN

POWER SUPPLIES

This product operates with power supply voltages ranging from

±12 to ±18 volts; however, the specifications only guarantee

device parameters with ±15 volt ±5% power supplies. The

power supply sensitive parameters have plots to indicate effects

of supply voltages other than ±15 volts.

Typical Applications

Operation from Single Positive Power Supply

High Off Isolation Selector Switch (Shunt-Series Switch)

4-Channel Sample Hold Amplifier

SW06

REV. A

–12–

Single Pole Double Throw Selector Switch with Break-Before-Make Interval

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

20-Terminal Leadless Chip Carrier

(RC-Suffix)

E-20A

20 4

BOTTOM

VIEW

0.028 (0.71)

0.022 (0.56)

45° TYP

0.015 (0.38)

MIN

0.055 (1.40)

0.045 (1.14)

0.050 (1.27)

BSC

0.075 (1.91)

REF

0.011 (0.28)

0.007 (0.18)

R TYP

0.095 (2.41)

0.075 (1.90)

0.100 (2.54) BSC

0.200 (5.08)

BSC

0.150 (3.81)

BSC

0.075

(1.91)

REF

0.358 (9.09)

0.342 (8.69)

0.358

(9.09)

MAX

0.100 (2.54)

0.064 (1.63)

0.088 (2.24)

0.054 (1.37)

16-Lead Plastic DIP

(P-Suffix)

N-16

0.840 (21.33)

0.745 (18.93)

0.280 (7.11)

0.240 (6.10)

PIN 1

SEATING

PLANE

0.022 (0.558)

0.014 (0.356)

0.060 (1.52)

0.015 (0.38)

0.210 (5.33)

MAX 0.130

(3.30)

MIN

0.070 (1.77)

0.045 (1.15)

0.100

(2.54)

BSC

0.160 (4.06)

0.115 (2.93)

0.325 (8.25)

0.300 (7.62)

0.015 (0.381)

0.008 (0.204)

0.195 (4.95)

0.115 (2.93)

16-Lead Cerdip

(Q-Suffix)

Q-16

0.320 (8.13)

0.290 (7.37)

0.015 (0.38)

0.008 (0.20)

15°

0°

0.840 (21.34) MAX

0.200

(5.08)

MAX

0.023 (0.58)

0.014 (0.36)

0.200 (5.08)

0.125 (3.18)

0.100

(2.54)

BSC SEATING

PLANE

0.070 (1.78)

0.030 (0.76)

0.060 (1.52)

0.015 (0.38)

0.150

(3.81)

MIN

0.005 (0.13) MIN

PIN 1

0.080 (2.03) MAX

0.310 (7.87)

0.220 (5.59)

16-Lead Wide Body SOL

(S-Suffix)

R-16/SOL-16

16 9

0.4133 (10.50)

0.3977 (10.00)

0.4193 (10.65)

0.3937 (10.00)

0.2992 (7.60)

0.2914 (7.40)

PIN 1

SEATING

PLANE

0.0118 (0.30)

0.0040 (0.10)

0.0192 (0.49)

0.0138 (0.35)

0.1043 (2.65)

0.0926 (2.35)

0.0500

(1.27)

BSC 0.0125 (0.32)

0.0091 (0.23)

0.0500 (1.27)

0.0157 (0.40)

8°

0°

0.0291 (0.74)

0.0098 (0.25) x 45°