OKI semiconductor MSC230B136D-xxBS4/DS4 1,048,576 Word By 36 Bit DYNAMIC RAM MODULE : FAST PAGE MODE GENERAL DESCRIPTION The Oki MSC23B136D-xxBS4/DS4 is a fully decoded, 1,048,576 word X 36 bit CMOS dynamic random access memory composed of two 16Mb(1Mx16) DRAMs and two 2Mb(1Mx2) DRAMs in SOJ. The mounting of four DRAMs together with decoupling capacitors on a 72-pin glass epoxy Single-in-Line Package supports any application where high density and large capacity of storage memory are required. FEATURES . 1,048,576 word X 36 bit organization 72-pin socket insertable module MSC23B136D-xxBS4 : Gold tab MSC23B136D-xxDS4 : Solder tab * Single +5 V supply +10 % tolerance e Input : TTL compatible * Output : TTL compatible, tristate, nonlatch * Refresh : 1024 cycles/16 ms TAS before RAS refresh, CAS before RAS hidden refresh, FAS only refresh capability FAMILY ORGANIZATION ACCESS TIME Cycle Power Dissipation FAMILY (MAX) Time Operating Standby trac | taa | tcac | (MAX) (MAX) (Max) MSC23B136D-60BS4/DS4 60ns | 30ns | 15ns [ 110ns 2256mW 22mWw MSC23B136D-70BS4/DS4 70ns |} 35ns | 20ns | 130ns 2036mWSOF SB payloads st wwi'Z] AAoge an[RA ayy, 7'OF SB paljloods ST IY Soy $I JO WUG'Z | YIPLA preog OY] JO FIUSIOTJIP IZIS VOWS BY], [x _ ~t S7S6 dALSE'9 200" tZ'1 a eine dALPOT || | ~ | orez < LOFLT'I QALGOZ Ista ' 72 TOUCHE I S9 Aorol 4 aan yf he y AL fo 0 O o Lo + o] + + |g + of X E lo Q jo Oo SLES 4 uo or o a 1 wo dXL6T 101 | XVW8Z'S eal ZOFS6LOL vSC/pSdkx-9ce TAECOSIN TOFR SeFUNCTIONAL BLOCK DIAGRAM MSC23B136D-xxBS4/DS4 A0-AQ CASO WE @ A0-a9 paQi - bao paz - pai pa3 - Daz RAST > RAS DQ4 - Da3 l oe Ee K 005 CCAS bpQq7 f Dpa6 bas fF DQ? UCAS pag /- pas pa10 FR Dai0 bait -> part e WE pai2 F Da12 pais P dais 14 P Dat14 OE DQ15 F- pats pate - pare Vss Veo @ 40-49 DQ1 - vas s DQI7 CAST Dae TASZ @ WE OE Vss Veo @ Ao-a9 Dai Fo 0018 paz fF Dag _ DQ3 F Daz20 RASS 0Q4 - Da21 Das fF 0az2 pes Fp 0023 CCAS Da7 -F Daz4 Das F pass UCAS pag - 0a27 DQ10 - 0a28 pa11 fF paz WE DQ12 - 0Q30 pa13 F bas! pai4 -> 0as2z OE DaiS - pasa pate - pasa Vss Vee L naz6 P passPIN CONFIGURATION MSC23B136D-xxBS4/DS4 Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name 1 Vass 19 NC 37 DQ17 55 DQ12 2 DQo 20 DQ4 38 DQ35 56 DQ30 3 DQ18 21 DQ22 39 Vss 57 DQ13 4 DQ1 22 DQ5 40 CASO 58 DQ31 5 DQ19 23 DQ23 41 TAS2 59 Vcc 6 DQ2 24 DQ6 42 CASS 60 DQ32 7 DQ20 25 DQ24 43 CAST 61 DQ14 8 DQ3 26 DQ7 44 RASO 62 DQ33 9 DQ2a1 or DQ25 45 NC 63 DQ15 10 Vcc 28 A7 46 NC 64 DQ34 11 NC 29 NC 47 WE 65 DQI6 12 AO 30 Vcc 48 NC 66 NC 13 Al 31 A8 49 DQ9 67 PD1 14 A2 32 AQ 50 DQ27 68 PD2 15 A3 33 NC 51 DQi0 69 PD3 16 A4 34 RAS2 52 DQ28 70 PD4 17 A5 35 DQ26 53 DQ11 71 NC 18 A6 36 DQ8 54 DQ29 72 Vss PRESENCE DETECT PINS Pin No. Pin name -60 -70 67 PD1 Vss Vss 68 PD2 Vss Vss 69 PD3 NC Vss 70 PD4 NC NCELECTRICAL CHARACTERISTICS ABSOLUTE _MAXIMUM RATINGS Rating Symbol Value Unit Voltage on any pin relative to Vss Vin: Vout -1.0~+7.0 Vv Voltage Vcc supply relative to Vss Voc -10~+7.0 Vv Short circuit output current los 50 mA Power dissipation Pp 4 Ww Operating temperature Topr -0~+70 C Storage temperature Tstg -40 ~+125 C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted within the limits as specified in this data sheet. Exposure to absolute maximum rating conditions for extended period may affect device reliabity. RECOMMENDED OPERATING CONDITIONS Parameter Symbol MIN TYPE MAX UNIT | Operating temperature Supply Voltage Voc 4.5 5.0 5.5 Vv Vss 0 0 0 Vv 0C~+70C Input high voltage Vi 2.4 - 6.5 Vv Input low voltage Vit -1.0 - 0.8 Vv CAPACITANCE Parameter A0-AQ Capacitance measured with Boonton Meter.DC CHARACTERISTICS (Vec = 5Vt 10%, Ta = 0 ~ +70 C) sg: MSG23B136D- | MSC23B136D- Parameter Symbol Condition 60BS4/DS4 7OBS4/DS4 Unit | Note Min Max Min Max OVSVins6.5V: Input Leakage Current Ii All other pins not -40 40 -40 40 | HA under test = OV Data out is disable Output Leakage Current ILo -10 10 -10 10 A OVEVoutS5.5V H Output High Voltage Vou lou = -5.0mA 2.4 | Vcc 2.4 Vec Vv Output Low Voltage VoL lo. = 4.2mA G 0.4 0 0.4 Vv RAS cycling, Average power suppl 98 Power SUPP'Y oct | TAS cycling - | 410] - | 370 | malt2 current (Operating) tacemin Power supply current lece RAS=Viy | TTL . 8 - 8 mA (Standby) TAS =ViIH MOS - 4 - 4 mA Average power supply RAS cycling, current lec3 TAS =VIL - 410 - 370 | mA |1 (RAS only refresh) trc=min Average power supply current loce tro = min. - 410 - 370 | mA |1 (CAS before RAS refresh) . Average power supply RAS = Vi, current lec? ~- | TKS cycling : 370 - 340 | mA 11,3 (Fast page) tpc = min. NOTE: 1. {cc is dependent on output loading and cycles rates. Specified values are obtained with the output open. 2. Address can be changed once or less while RAS = Vi_ 3. Address can be changed once or less while TAS = ViyqAC CHARACTERISTIC (Voc = 5V+ 10%, Ta = 0 ~70 C) __ NOTE 1.2.3 MSC23B136D- MSC23B136D- Parameter Symbol 60BS4/D84 70BS4/DS4 UNIT | NOTE MIN MAX MIN MAX Random read or write cycle time tac 110 - 130 - ns Fast page mode cycle time {pc 40 - 45 - ns Access time from RAS. trac : 60 : 70 ns | 4,5,6 Access time from TAS. tcac : 15 - 20 ns | 4,5 Access time from column address taa : 30 - 35 ns 14,6 Access time from CAS precharge tcPA - 35 - 40 ns [4,11 TAS to output in Low-Z tcoLz 0 - 0 - ns |4 Output buffer turn-off delay tOFF 0 15 0 20 ns |7 Transition time tr 3 50 3 50 ns {3 Refresh period tREF . 16 : 16 ms RAS precharge time tRP 40 - 50 - ns RAS pulse width tras 60 10K 70 10K ns BAS pulse width (Fast page mode) | tRASP 60 | 100K} 70 | 100K ns RAS hold time tRSH 15 - 20 - ns TAS precharge time tcp 10 - 10 - ns 13 TAS pulse width tcas 15 10K 20 10K ns CAS hold time tCSH 60 : 70 - ns TAS to RAS precharge time tcRP 5 - 5 - ns |11 RAS hold time from TAS precharge | tAHCP 35 - 40 - ns | 11 RAS to CAS delay time treo 20 45 20 50 ns [5 RAS to column address delay time | tRaD 15 30 15 35 ns |6 Row address set-up time tASR 0 - 0 - ns Row address hold time tRAH 10 - 10 : ns Column address set-up time tasc 0 - 0 - ns 10 Column address hold time ICAH 15 : 15 - ns 10 Column address to RAS lead time _| tRAL 30 - 85 - nsAC CHARACTERISTICS (Continued) (Vec = 5V + 10%, Ta = 0 ~70 C) MSC23B136D- | MSC23B136D- Parameter Symbol 60BS4/DS4 70BS4/DS4 UNIT | NOTE MIN MAX MIN MAX Read command set-up time tacs 0 - oO - ns 10 Read command hold time tRCH 0 - Oo - ns 8,10 fieag command hold time reference taRH 0 . 0 _ ns 18 Write command set-up time twos 0 - 0 - ns 10 Write command hold time twoH 10 - 15 : ns 10 Write command pulse width twp 10 - 10 - ns Write command to RAS read time tRWL 16 - 20 - ns Write command to CAS read time tCWL 15 - 20 - ns |12 Data-in set-up time tps 0 - 0 - ns [9,10 Data-in hold time DH 15 - 15 - ns [9,10 TAS precharge WE delay time tcpwD 60 - 70 - ns TAS active delay time from RAS tAPC 5 . 5 . ns 10 precharge RAS to CAS set-up time tesA 10 . 10 . ns |10 (CAS before RAS) TAS hold time (CAS before RAS) tour 10 . 10 . ns 141NOTES: 1) 2) 3) 7) 8) 9) 10) 11) 12) 13) An initial pause of 200 us is required after power-up followed by aminimum of 8 initializatin cycles (examples: RAS only refresh or CAS before RAS refresh) before proper device operation is achieved. The AC measurements assume the transition time (tt) = 5 ns. Vin (min.) and Vi, (max.) are reference levels for measuring the timing of the input signals. Transition times are measured between Viy and ViL. Measured by using an eqivalent load circuit of 2 TTL loads and 100 pF. Operation within the tacp (max) limit ensures that trac (max) can be met. tacp(max) is specified as a reference point only: if tacp is greater than the specified tacp(max) limit, then access time is controlled by tcac. Operation within the trap (max) limit ensures that trac (max) can be met. taap(max) is specified as a reference point only: if taap is greater than the specified trap (max) limit, then access time is controlled by taa. The torr (max.) spec. defines at which time the output data achieves a high impedance state and is not referenced to output voltage levels. Either the tary or the tacH spec. must be satisfied for proper read cycle. These parameters are referenced to UCAS and CCAS leading edge in an early write cycle. These parameters are determined by the earlier falling edge of UCAS or [CAS. These parameters are determined by the later rising edge of UCAS or LCAS. tcwL should be satisfied by both UCAS or [TAS. tcp is determined by the time of both UCAS or CCAS are high.