Standard Pr oducts
June 1997
1 Megabit (64K x16) CMOS Mask-Programmable ROM
1
.Features
•Fast Read Access Time - 70ns
•Low Power CMOS Operation
– 30
µ
A max. Standby
– 35mA max. Active at 5MHz
•Wide Selection of JEDEC Standard Packages
– 40-Lead 600-mil PDIP
– 44-Pad PLCC
– 40-Lead TSOP
– 48-Lead TSOP
•3.0V–5.5V Supply
•High Reliability CMOS Technology
– 2000V ESD Protection
– 200mA Latchup Immunity
•Two-line Control
•CMOS and TTL Compatible Inputs and Outputs
•Full Commercial and Industrial Temperature Ranges
•Designed for Battery to 5V Supplies
Description
The S63LV1024 is a low-power, high performance
1,048,576 bit Mask Programmable Read Only Memory
(ROM) organized 64K x 16. It requires only one power
supply in normal operation. An y w ord can be accessed in
less than 70ns, eliminating the need for speed reducing
WAIT states. The by-16 organization make this par t ideal
for high-performance 16 and 32 bit microprocessor
systems.
The S63LV1024 typically consumes 24mA. Standby
mode supply current is typically less than 20
µ
A.
The S63LV1024 is av ailab le in industry standard JEDEC-
approved packages including: plastic PDIP, PLCC, and
TSOP. The device features two-line control (CE, OE) to
eliminate bus contention in high-speed systems.
With high density 64K word storage capability, the
S63LV1024 allows firmware to be stored reliably and to
be accessed by the system without the delays of mass
storage media.
AMI’s S63LV1024 has additional features to ensure high
quality and efficient production use.
Block Diagram
Absolute Maximum Ratings
1
NOTE:1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent danger
to the device. This is a stress rating only and functional operation of the device at these or any
other conditions beyond those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
2. Minimum voltage is -0.6V DC which may undershoot to -2.0V for pulses less than 20 ns.
Maximum pin voltage is V
CC
+0.6V DC which may overshoot to +6.0V for pulses of less than 20 ns.
Pin Configurations
NOTE: Both GND pins must be connected.
Pin Capacitance
(f = 1 MHz T = 25
°
C)
NOTE: Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
Temperature Under Bias -55
°
C to +125
°
C
Storage Temperature -65
°
C to +150
°
C
Voltage on Any Pin with Respect
to Ground -2.0V to +6V
2
PIN NAME FUNCTION
A0-A15 Addresses
O0-O15 Outputs
CE Chip Enable
OE Output Enable
NC No Connect
TYPICAL MAXIMUM UNITS CONDITIONS
C
IN
410pFV
IN
= 0V
C
OUT
812pFV
OUT
= 0V
VCC
GND
OE
CE
A0-A15
ADDRESS
INPUTS
OE, CE
Y DECODER
OUTPUT
BUFFERS
DATA OUTPUTS
O0 - O15
X DECODER
Y-GATING
CELL MATRIX
S63LV1024
LOW VOL T AGE