Standard Products June 1997 S63LV1024 LOW VOLTAGE 1 Megabit (64K x16) CMOS Mask-Programmable ROM .Features Block Diagram * Fast Read Access Time - 70ns * Low Power CMOS Operation - 30A max. Standby - 35mA max. Active at 5MHz * Wide Selection of JEDEC Standard Packages - 40-Lead 600-mil PDIP - 44-Pad PLCC - 40-Lead TSOP - 48-Lead TSOP * 3.0V-5.5V Supply * High Reliability CMOS Technology - 2000V ESD Protection - 200mA Latchup Immunity * Two-line Control VCC GND DATA OUTPUTS O0 - O15 OE CE OUTPUT BUFFERS OE, CE A0-A15 ADDRESS INPUTS Y-GATING Y DECODER CELL MATRIX X DECODER Absolute Maximum Ratings1 Temperature Under Bias -55C to +125C Storage Temperature -65C to +150C Voltage on Any Pin with Respect to Ground -2.0V to +6V2 NOTE: 1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent danger to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Minimum voltage is -0.6V DC which may undershoot to -2.0V for pulses less than 20 ns. Maximum pin voltage is VCC+0.6V DC which may overshoot to +6.0V for pulses of less than 20 ns. * CMOS and TTL Compatible Inputs and Outputs * Full Commercial and Industrial Temperature Ranges * Designed for Battery to 5V Supplies Description Pin Configurations The S63LV1024 is a low-power, high performance 1,048,576 bit Mask Programmable Read Only Memory (ROM) organized 64K x 16. It requires only one power supply in normal operation. Any word can be accessed in less than 70ns, eliminating the need for speed reducing WAIT states. The by-16 organization make this part ideal for high-performance 16 and 32 bit microprocessor systems. The S63LV1024 typically consumes 24mA. Standby mode supply current is typically less than 20A. PIN NAME The S63LV1024 is available in industry standard JEDECapproved packages including: plastic PDIP, PLCC, and TSOP. The device features two-line control (CE, OE) to eliminate bus contention in high-speed systems. With high density 64K word storage capability, the S63LV1024 allows firmware to be stored reliably and to be accessed by the system without the delays of mass storage media. AMI's S63LV1024 has additional features to ensure high quality and efficient production use. FUNCTION A0-A15 Addresses O0-O15 Outputs CE Chip Enable OE Output Enable NC No Connect NOTE: Both GND pins must be connected. Pin Capacitance (f = 1 MHz T = 25C) TYPICAL MAXIMUM UNITS CONDITIONS CIN 4 10 pF VIN = 0V COUT 8 12 pF VOUT = 0V NOTE: Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. 1 S63LV1024 Standard Products 1 Megabit (64K x16) CMOS Mask-Programmable ROM June 1997 Operating Modes MODE/PIN Read CE OE Ai VCC OUTPUTS VIL VIL Ai VCC DOUT X VIH X VCC High Z VIH X X VCC High Z -70 -90 -120 0C - 70C 0C - 70C 0C - 70C -40C - 85C -40C - 85C -40C - 85C 3.0V - 5.5V 3.0V - 5.5V 3.0V - 5.5V Output Disable Standby DC and AC Operating Conditions S63LV1024 Operating Temperature Commercial Industrial Vdd Power Supply DC and Operating Characteristics 3.0V to 5.5V SYMBOL PARAMETER CONDITION ILI Input Load Current VIN = 0V to VCC ILO Output Leakage Current VOUT = 0V to VCC ISB VCC Standby Current CE = VCC 0.3V ICC VCC Active Current f = 5MHz, IOUT = 0mA, CE = VIL ,VCC = 5.5V VIL Input Low Voltage VIH Input High Voltage VOL Output Low Voltage VOH Output High Voltage APP. MIN MAX UNITS Com., Ind. 1 A Com., Ind. 5 A 30 A Com. 35 mA Ind. 40 mA 0.6 V 2.2 V 2mA 0.4 V 100A 0.2 V -1mA -100A 2 2.2 V VCC - 0.2 V S63LV1024 Standard Products 1 Megabit (64K x16) CMOS Mask-Programmable ROM June 1997 AC Characteristics for Read Operations 3.0V - 5.5V S63LV1024 SYMBOL 3 tACC PARAMETER CONDITION -70 Min. -90 Max. Min. -120 Max. Min. Max. Address to Output Delay CE=OE=VIL 70ns 90ns 120ns 2 CE to Output Delay OE=VIL 70ns 90ns 120ns 2,3 OE to Output Delay CE=VIL 30ns 35ns 35ns 4,5 tDF OE or CE High to Output Float 25ns 25ns 30ns tOH Output Hold from Addresses, CE or OE whichever occurred first tCE tOE 0ns 0ns 0ns AC Waveforms1 ADDRESS ADDRESS VALID CE tCE tOE OE tDF tACC tOH OUTPUT Notes:1. 2. 3. 4. 5. HIGH Z OUTPUT VALID Timing measurement references are 1.5V. Input AC driving levels are 0V and 3.0V, unless otherwise specified. OE may be delayed up to tCE-tOE after the falling edge of CE without impact on tCE. OE may be delayed up to tACC-tOE after the address is valid without impact on t ACC. This parameter is only sampled and is not 100% tested. Output float is defined as the point when data is no longer driven. 3 S63LV1024 Standard Products 1 Megabit (64K x16) CMOS Mask-Programmable ROM June 1997 Input Test Waveforms and Measurement Levels 3.0V AC DRIVING LEVELS AC MEASUREMENT LEVEL 1.5V 0.0V tR, tF < 5 ns (10% to 90%) Output Test Load TEST COMPARATOR OUT VL = 1.92V RL = 476 CL = 30pF Typical Normalized IDD vs. Frequency 3.000 5.5V 2.500 5.0V Normalized IDD 2.000 4.5V 4.0V 1.500 3.6V 3.3V 3.0V 1.000 0.500 0.000 1.00 1.11 1.25 1.43 1.67 2.00 2.50 Frequency (MHz) 4 3.33 5.00 10.00 20.00 S63LV1024 Standard Products 1 Megabit (64K x16) CMOS Mask-Programmable ROM June 1997 40-Pin PDIP Specifications Pin Configuration NC CE O15 O14 O13 O12 O11 O10 O9 O8 GND O7 O6 O5 O4 O3 O2 O1 O0 OE Description The Plastic Dual-In-Line Package (PDIP) meets widely accepted industry standard for MOS/VLSI applications. The package consists of a plastic body, transfer-molded around the leadframe and die. The leadframe is copper alloy, with external pins solder plated. Internally, there is 125 inch silver spot plating on the die attach pad and on each bonding fingertip. These fingers are electrically connected to the die by thermosonic gold ball bonding techniques. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VCC NC NC A15 A14 A13 A12 A11 A10 A9 GND A8 A7 A6 A5 A4 A3 A2 A1 A0 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 Package Description and Outline Dimensions LOW STRESS MOLDING COMPOUND CONDUCTIVE DIE ATTACH MATERIAL DIE GOLD BONDING WIRE E1 LEAD 1 E 1 LEAD COUNT DIRECTION eA C eB A D A1 SPOT SILVER PLATING L COPPER ALLOY LEAD FRAME B1 B e SOLDER PLATING PDIP Specifications SYMBOL A A1 MAX 0.200 - MIN - B B1 C D E E1 e eA eB L 0.020 0.060 0.012 2.455 0.610 0.560 0.100 0.686 0.100 MIN 0.015 0.015 0.040 0.008 1.980 0.580 0.520 TYP 0.580 - NOTE: 1. All measurements in inches. 2. Data is subject to change. Contact the factory for most current specifications. 5 B2 S - - - - S63LV1024 Standard Products 1 Megabit (64K x16) CMOS Mask-Programmable ROM June 1997 44-Pin PLCC Specifications Pin Configuration O13 O14 O15 CE NC NC VCC NC NC A15 A14 Description 6 The PLCC is transfer molded and thermosonic wire bonded. Die is mounted on a copper alloy leadframe and external leads are solder plated to provide improved solderability. 5 4 3 2 1 44 43 42 41 40 O12 7 39 A13 O11 8 38 A12 O10 9 37 A11 O9 10 36 A10 O8 11 35 A9 GND 12 34 GND NC 13 33 NC O7 14 32 A8 O6 15 31 A7 O5 16 30 A6 O4 17 29 A5 18 19 20 21 22 23 24 25 26 27 28 O3 O2 O1 O0 OE NC A0 A1 A2 A3 A4 NOTE: PLCC package pins 1 and 23 are DON'T CONNECT Package Description LOW STRESS MOLDING COMPOUND GOLD WIRE BOND COPPER ALLOY LEADFRAME DIE SILVER PLATING SOLDER PLATING Package Outline Dimensions 1.22/1.07 2 PLCS PIN 1 IDENTIFIER & ZONE D D1 .81/.66 A1 A SEATING PLANE E1 E E3 .10 e .51 MIN. R 1.14/.64 .53/.33 D2/E2 SIDE VIEW D3 TOP VIEW BOTTOM VIEW PLCC Specifications SYMBOL A A1 D1 D2 D3 E1 E2 E3 e D E MAX 4.57 3.04 16.66 16.00 16.66 16.00 2.29 16.51 14.99 16.51 14.99 1.27 BSC 17.65 4.20 12.70 BSC 17.65 MIN 12.70 BSC 17.40 17.40 NOTE: 1. All measurements in millimeters. 2. Data is subject to change. Contact the factory for most current specifications. 6 S63LV1024 Standard Products 1 Megabit (64K x16) CMOS Mask-Programmable ROM June 1997 40-Pin TSOP Specifications Pin Configuration Description A9 A10 A11 A12 A13 A14 A15 NC NC VCC NC CE O15 O14 O13 O12 O11 O10 O9 O8 The Type I Thin Small Outline Package (TSOP) is a thin ends only package. This package is constructed using the latest low stress molding compounds and bonding technology to provide a package with total body thickness of less than 1.90mm. This package is popular for ROM applications in memory cards and other thin card applications. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 GND A8 A7 A6 A5 A4 A3 A2 A1 A0 OE O0 O1 O2 O3 O4 O5 O6 O7 GND Package Description and Outline Dimensions H E 0.90 (.035) LOW STRESS MOLDING COMPOUND A1 40 1 2 3 0.90 (.035) SEATING PLANE A e 1.00 (.039) DIA PIN #1 I.D. (SPHERICAL) DIE GOLD WIRE BOND D B TOP VIEW A2 L c TSOP Specifications SYMBOL A A1 A2 B D E H e c L MAX 1.20 0.15 1.10 0.30 10.10 18.50 20.20 0.16 0.70 5 MIN - 0 0.95 0.15 9.90 18.30 19.80 0.50 BSC 0.10 0.50 0 NOTE: 1. All measurements in millimeters. 2. Data is subject to change. Contact the factory for most current specifications. 7 S63LV1024 Standard Products 1 Megabit (64K x16) CMOS Mask-Programmable ROM June 1997 48-Pin TSOP Specifications Pin Configuration NC A0 A1 A2 A3 A4 A5 NC A6 A7 A8 VSS A9 A10 A11 NC A12 A13 A14 A15 NC NC VDD NC Description The Type I Thin Small Outline Package (TSOP) is a thin ends only package. This package is constructed using the latest low stress molding compounds and bonding technology to provide a package with total body thickness of less than 1.90mm. This package is popular for ROM applications in memory cards and other thin card applications. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 NC OE O0 O1 O2 O3 O4 NC O5 O6 O7 VSS O8 O9 O10 NC O11 O12 O13 O14 O15 CE NC NC 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 Package Description and Outline Dimensions H E 0.90 (.035) 1.10 (.043) LOW STRESS MOLDING COMPOUND e 1.00 (.039) DIA PIN #1 I.D. (SPHERICAL) 1.10 (.043) GOLD WIRE BOND DIE A1 48 1 2 3 0.90 (.035) SEATING PLANE A D B TOP VIEW A2 c L TSOP Specifications SYMBOL A A1 A2 B D E H e c L MAX 1.20 0.15 1.05 0.25 12.20 18.50 20.20 0.20 0.60 5 MIN - 0.00 0.95 0.15 11.80 18.30 19.80 0.50 BSC 0.10 0.40 0 NOTE: 1. All measurements in millimeters. 2. Data is subject to change. Contact the factory for most current specifications. Copyright(R)1997, American Microsystems, Inc. Devices sold by AMI are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMI makes no warranty, express, statutory implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. AMI makes no warranty of merchantability or fitness for any purposes. AMI reserves the right to discontinue production and change specifications and prices at any time and without notice. AMI's products are intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or lifesustaining equipment, are specifically not recommended without additional processing by AMI for such applications. American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, ID 83201, (208) 233-4690, FAX (208) 234-6796 8