Standard Pr oducts
June 1997
1 Megabit (64K x16) CMOS Mask-Programmable ROM
1
.Features
•Fast Read Access Time - 70ns
•Low Power CMOS Operation
– 30
µ
A max. Standby
– 35mA max. Active at 5MHz
•Wide Selection of JEDEC Standard Packages
– 40-Lead 600-mil PDIP
– 44-Pad PLCC
– 40-Lead TSOP
– 48-Lead TSOP
•3.0V–5.5V Supply
•High Reliability CMOS Technology
– 2000V ESD Protection
– 200mA Latchup Immunity
•Two-line Control
•CMOS and TTL Compatible Inputs and Outputs
•Full Commercial and Industrial Temperature Ranges
•Designed for Battery to 5V Supplies
Description
The S63LV1024 is a low-power, high performance
1,048,576 bit Mask Programmable Read Only Memory
(ROM) organized 64K x 16. It requires only one power
supply in normal operation. An y w ord can be accessed in
less than 70ns, eliminating the need for speed reducing
WAIT states. The by-16 organization make this par t ideal
for high-performance 16 and 32 bit microprocessor
systems.
The S63LV1024 typically consumes 24mA. Standby
mode supply current is typically less than 20
µ
A.
The S63LV1024 is av ailab le in industry standard JEDEC-
approved packages including: plastic PDIP, PLCC, and
TSOP. The device features two-line control (CE, OE) to
eliminate bus contention in high-speed systems.
With high density 64K word storage capability, the
S63LV1024 allows firmware to be stored reliably and to
be accessed by the system without the delays of mass
storage media.
AMI’s S63LV1024 has additional features to ensure high
quality and efficient production use.
Block Diagram
Absolute Maximum Ratings
1
NOTE:1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent danger
to the device. This is a stress rating only and functional operation of the device at these or any
other conditions beyond those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
2. Minimum voltage is -0.6V DC which may undershoot to -2.0V for pulses less than 20 ns.
Maximum pin voltage is V
CC
+0.6V DC which may overshoot to +6.0V for pulses of less than 20 ns.
Pin Configurations
NOTE: Both GND pins must be connected.
Pin Capacitance
(f = 1 MHz T = 25
°
C)
NOTE: Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
Temperature Under Bias -55
°
C to +125
°
C
Storage Temperature -65
°
C to +150
°
C
Voltage on Any Pin with Respect
to Ground -2.0V to +6V
2
PIN NAME FUNCTION
A0-A15 Addresses
O0-O15 Outputs
CE Chip Enable
OE Output Enable
NC No Connect
TYPICAL MAXIMUM UNITS CONDITIONS
C
IN
410pFV
IN
= 0V
C
OUT
812pFV
OUT
= 0V
VCC
GND
OE
CE
A0-A15
ADDRESS
INPUTS
OE, CE
Y DECODER
OUTPUT
BUFFERS
DATA OUTPUTS
O0 - O15
X DECODER
Y-GATING
CELL MATRIX
S63LV1024
LOW VOL T AGE
Standard Pr oducts
1 Megabit (64K x16) CMOS Mask-Programmable ROM
June 1997
2
Operating Modes
DC and AC Operating Conditions
DC and Operating Characteristics
3.0V to 5.5V
MODE/PIN CE OE Ai V
CC
OUTPUTS
Read V
IL
V
IL
Ai V
CC
D
OUT
Output Disable X V
IH
XV
CC
High Z
Standby V
IH
XXV
CC
High Z
S63LV1024
-70 -90 -120
Operating Temperature Commercial 0
°
C - 70
°
C0
°
C - 70
°
C0
°
C - 70
°
C
Industrial -40
°
C - 85
°
C -40
°
C - 85
°
C -40
°
C - 85
°
C
V
dd
Power Supply 3.0V – 5.5V 3.0V – 5.5V 3.0V – 5.5V
SYMBOL PARAMETER CONDITION APP. MIN MAX UNITS
I
LI
Input Load Current V
IN
= 0V to V
CC
Com., Ind.
±
1
µ
A
I
LO
Output Leakage Current V
OUT
= 0V to V
CC
Com., Ind.
±
5
µ
A
I
SB
V
CC
Standby Current CE = V
CC
±
0.3V 30
µ
A
I
CC
V
CC
Active Current f = 5MHz, I
OUT
= 0mA,
CE = V
IL
,V
CC
= 5.5V Com. 35 mA
Ind. 40 mA
V
IL
Input Low Voltage 0.6 V
V
IH
Input High Voltage 2.2 V
V
OL
Output Low Voltage 2mA 0.4 V
100
µ
A 0.2 V
V
OH
Output High Voltage -1mA 2.2 V
-100
µ
AV
CC
– 0.2 V
S63LV1024
Standard Pr oducts
June 1997
1 Megabit (64K x16) CMOS Mask-Programmable ROM
3
AC Characteristics for Read Operations
3.0V - 5.5V
AC Waveforms
1
Notes:1. Timing measurement references are 1.5V. Input AC driving levels are 0V and 3.0V, unless otherwise specified.
2. OE may be delayed up to t
CE
-t
OE
after the falling edge of CE without impact on t
CE
.
3. OE may be delayed up to t
ACC
-t
OE
after the address is valid without impact on t
ACC
.
4. This parameter is only sampled and is not 100% tested.
5. Output float is defined as the point when data is no longer driven.
S63LV1024
SYMBOL PARAMETER CONDITION -70 -90 -120
Min. Max. Min. Max. Min. Max.
t
ACC
3
Address to Output Delay CE=OE=V
IL
70ns 90ns 120ns
t
CE
2
CE to Output Delay OE=V
IL
70ns 90ns 120ns
t
OE
2,3
OE to Output Delay CE=V
IL
30ns 35ns 35ns
t
DF
4,5
OE or CE High to Output Float 25ns 25ns 30ns
t
OH
Output Hold from Addresses, CE or OE whichever
occurred first 0ns 0ns 0ns
ADDRESS VALID
OUTPUT
VALID
ADDRESS
CE
tCE
OE
OUTPUT HIGH Z
tOE
tDF
tOH
tACC
S63LV1024
Standard Pr oducts
1 Megabit (64K x16) CMOS Mask-Programmable ROM
June 1997
4
Input Test Waveforms and Measurement Levels
Output Test Load
Typical Normalized IDD vs. Frequency
3.0V
0.0V
1.5V
tR, tF < 5 ns (10% to 90%)
AC
MEASUREMENT
LEVEL
AC
DRIVING
LEVELS
TEST COMPARATOR
OUT VL = 1.92V
CL = 30pF
RL = 476Ω
1.00
0.000
0.500
1.000
1.500
2.000
2.500
3.000
1.11 1.25 1.43 1.67 2.00
Frequency (MHz)
Normalized IDD
2.50 3.33 5.00 10.00 20.00
5.5V
5.0V
4.5V
4.0V
3.6V
3.3V
3.0V
S63LV1024
Standard Pr oducts
June 1997
1 Megabit (64K x16) CMOS Mask-Programmable ROM
5
40-Pin PDIP Specifications
Description
The Plastic Dual-In-Line Package (PDIP) meets widely
accepted industry standard for MOS/VLSI applications.
The package consists of a plastic body, transfer-molded
around the leadframe and die. The leadframe is copper
alloy, with external pins solder plated.
Internally, there is 125µ inch silver spot plating on the die
attach pad and on each bonding finger tip. These fingers
are electrically connected to the die by thermosonic gold
ball bonding techniques.
Pin Configuration
NC
CE
O15
O14
O13
O12
O11
O10
O9
O8
GND
O7
O6
O5
O4
O3
O2
O1
O0
OE
VCC
NC
NC
A15
A14
A13
A12
A11
A10
A9
GND
A8
A7
A6
A5
A4
A3
A2
A1
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
Package Description and Outline Dimensions
PDIP Specifications
NOTE:1. All measurements in inches.
2. Data is subject to change. Contact the factory for most current specifications.
SYMBOL
AA1BB1C D EE1eeAeBLB2S
MAX 0.200 - 0.020 0.060 0.012 2.455 0.610 0.560 0.100
TYP - 0.686 0.100
MIN --
MIN - 0.015 0.015 0.040 0.008 1.980 0.580 0.520 0.580 - - -
LOW STRESS
MOLDING
COMPOUND
SOLDER PLATING
COPPER ALLOY
LEAD FRAME
CONDUCTIVE
DIE ATTACH
MATERIAL
SPOT SILVER
PLATING
GOLD
BONDING
WIRE
DIE
E1 E
1eA C
LEAD COUNT DIRECTION
LEAD 1
L
B1 e
A
DA1 eB
B
S63LV1024
Standard Pr oducts
1 Megabit (64K x16) CMOS Mask-Programmable ROM June 1997
6
44-Pin PLCC Specifications
Description
The PLCC is transfer molded and thermosonic wire
bonded. Die is mounted on a copper alloy leadframe and
external leads are solder plated to provide improved
solderability.
Pin Configuration
NOTE: PLCC package pins 1 and 23 are DON’T CONNECT
O12
O11
O10
O9
O8
GND
NC
O7
O6
O5
A13
A12
A11
A10
A9
GND
NC
A8
A7
A6
A5
O4
7
8
9
10
11
12
13
14
15
16
17 18 19 20 21 22 23 24 25 26 27 28
O3 O2 O1 O0 OE NC A0 A1 A2 A3 A4
O13 O14 O15 CE NC NC VCC NC NC A15 A14
6543214443424140
39
38
37
36
35
34
33
32
31
30
29
Package Description
Package Outline Dimensions
PLCC Specifications
NOTE:1. All measurements in millimeters.
2. Data is subject to change. Contact the factory for most current specifications.
SYMBOL
A A1D1D2D3E1E2E3 e D E
MAX 4.57 3.04 16.66 16.00 12.70
BSC 16.66 16.00 12.70
BSC 1.27
BSC 17.65 17.65
MIN 4.20 2.29 16.51 14.99 16.51 14.99 17.40 17.40
SOLDER
PLATING
LOW STRESS
MOLDING COMPOUND
DIE
COPPER ALLOY
LEADFRAME
GOLD
WIRE
BOND
SILVER
PLATING
D1
1.22/1.07
2 PLCS
PIN 1
IDENTIFIER & ZONE
TOP VIEW
SIDE VIEW
BOTTOM VIEW
.51 MIN.
SEATING PLANE
.10
R 1.14/.64
D3
E3
D
E 1
E
A
e
D2/E2
.53/.33
.81/.66
A1
S63LV1024
Standard Pr oducts
June 1997 1 Megabit (64K x16) CMOS Mask-Programmable ROM
7
40-Pin TSOP Specifications
Description
The Type I Thin Small Outline Package (TSOP) is a thin
ends only package. This package is constructed using
the latest low stress molding compounds and bonding
technology to provide a pac kage with total body thickness
of less than 1.90mm.
This package is popular for ROM applications in memory
cards and other thin card applications.
Pin Configuration
A9
A10
A11
A12
A13
A14
A15
NC
NC
VCC
NC
CE
O15
O14
O13
O12
O11
O10
O9
O8
GND
A8
A7
A6
A5
A4
A3
A2
A1
A0
OE
O0
O1
O2
O3
O4
O5
O6
O7
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
Package Description and Outline Dimensions
TSOP Specifications
NOTE:1. All measurements in millimeters.
2. Data is subject to change. Contact the factory for most current specifications.
SYMBOL
AA1A2B D E H e c Lα°
MAX 1.20 0.15 1.10 0.30 10.10 18.50 20.20 0.50
BSC 0.16 0.70 5
MIN - 0 0.95 0.15 9.90 18.30 19.80 0.10 0.50 0
A2 cL
TOP VIEW
0.90 (.035)
1
3
2
(SPHERICAL)
B
e
40
E
0.90 (.035)
PIN #1 I.D.
1.00 (.039) DIA
HPLANE
SEATING
A1
A
D
α°
DIE
LOW STRESS
MOLDING
COMPOUND GOLD WIRE BOND
S63LV1024
Standard Pr oducts
1 Megabit (64K x16) CMOS Mask-Programmable ROM
June 1997
8
48-Pin TSOP Specifications
Description
The Type
I
Thin Small Outline Package (TSOP) is a thin
ends only package. This package is constructed using
the latest low stress molding compounds and bonding
technology to provide a pac kage with total body thickness
of less than 1.90mm.
This package is popular for ROM applications in memory
cards and other thin card applications.
Pin Configuration
NC
A0
A1
A2
A3
A4
A5
NC
A6
A7
A8
VSS
A9
A10
A11
NC
A12
A13
A14
A15
NC
OE
O0
O1
O2
O3
O4
NC
O5
O6
O7
VSS
O8
O9
O10
NC
O11
O12
O13
O14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
NC 21
NC 22
VDD 23
NC 24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29 O1528 CE27 NC26 NC25
Package Description and Outline Dimensions
TSOP Specifications
NOTE:1. All measurements in millimeters.
2. Data is subject to change. Contact the factory for most current specifications.
Copyright®1997, American Microsystems, Inc.
Devices sold by AMI are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMI makes no w arranty,
express , statutory implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from patent
infringement. AMI makes no warranty of merchantability or fitness for any purposes. AMI reser ves the right to discontinue production and change
specifications and prices at any time and without notice. AMI's products are intended for use in commercial applications. Applications requiring
extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-
sustaining equipment, are specifically not recommended without additional processing by AMI for such applications.
American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, ID 83201, (208) 233-4690, FAX (208) 234-6796
SYMBOL
AA1A2B D E H e c L
α
°
MAX
1.20 0.15 1.05 0.25 12.20 18.50 20.20 0.50
BSC 0.20 0.60 5
MIN
- 0.00 0.95 0.15 11.80 18.30 19.80 0.10 0.40 0
A2 c
TOP VIEW
0.90 (.035)
1.10 (.043)
1
3
2
(SPHERICAL)
B
e
48
E
0.90 (.035)
1.10 (.043)
PIN #1 I.D.
1.00 (.039) DIA
HPLANE
SEATING
A1
A
D
L
α°
DIE
LOW STRESS
MOLDING
COMPOUND GOLD WIRE BOND
S63LV1024
