S2E D MH 2929237 OO3822b bb MESGTH TH-23-13 keyg SGS-THOMSO Sf. MIGROELESTHOMS SoG S=-THOMSON MK62486 VERY FAST CMOS 32K x 9 CACHE BRAM = 32K x 9 CMOS SYNCHRONOUS BURSTSRAM = FAST CYCLE TIMES: 25, 30ns = FAST ACCESS: 19, 24ns Max = ON-BOARD BURST COUNTER = INPUT REGISTERS (ADDR.,DATA,CTRL) = SELF-TIMED WRITE CYCLE THREE STATE COMMON I/O = HIGH OUTPUT DRIVE CAPABILITY = ASYNCHRONOUS OUTPUT ENABLE (G) = BURST CONTROL INPUTS: ADSP, ADSC, ADV a DUAL CHIP SELECTS FOR EASY DEPTH EXPANSION PIN NAMES AO-A14 Address Inputs DQo - DAs Data Inputs/Outputs K Clock Ww Write Enable G Output Enable So Chip Select, Active High sT Chip Select, Active Low ADSP Address Status Processor ADSC Address Status Cache Ctrl. ADV Burst Address Advance RES Reserve, Tied Low Vcc, GND 5 Volts, Ground February 1992 ADVANCE DATA PLCC44 (Q) Figure 1. Pin Connection Ojo | 2 B oO oO = OVOA/O|[A Om ORD tdticdickt yxy > tact < A2 O At Ag MO A12 A4 ) A13 AS O A14 A6 O GND GND 12 MK62486 34 0 DQ7 DOO Tj 13 33 0 DOG DQ1 q 14 32 Q GND GND J 15 nD Vcc Voc 16 so D DAS QD2 d 17 29 ff DQ4 18 19 20 21 22 23 24 25 26 27 28 a Zz oO VA00623 W2 This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 745mK62486 See D MB 7929237 O038ee?7 STY MBSGTH S- THOMSON 1-46-23-13 Figure 2. Block Diagram 8 6 Aw _ e. ADDRESS REGISTERS A2-A14 32K x 9 MEMORY ARRAY By es Bg ee Al (294,912 BITS) P ) > BINARY ai COUNTER K a0 ADV CLR ) Ao ADS ADS p > z ENABLE 9 9 $s = So 4 to REGISTER INPUT REGISTER WRITE LT} w at REGISTER <| _5>5 G aA 9 Da.- Da vroo1076 & DESCRIPTION DEVICE OPERATIONS The MK62486 BRAM is a 288K (294,912-bit) CMOS Burst SRAM, organized as 32,768 words x 9 bits. It is fabricated using SGS-Thomsons low power, high performance, CMOS technology. The device integrates a 2-bit burst counter, input regis- ters, high output drive capability, and high speed synchronous SRAM onto a single chip. The syn-chron- ous design provides precise control using an exter- nal clock (K) input. The MK62486 is specifically adapted to provide a burstable, high performance secondary cache for the i486 microprocessor. The MK62486 is available in a 44 pin plastic leaded chip-carrier (PLCC). The device provides multiple power and ground pins to reduce effects induced by output noise for high performance applications. Separate power and ground pins (Vcca and GNDa) have been employed for DQo-8 to allow output levels referenced to 5 Volts or 3.3 Volts. The main Burst SRAM power requires a single 5V + 5% supply, and ail inputs and outputs are TTL compat- Iple. 22 57 S&S-THOMSON 746 o MICROELECTRONICS Addresses (A0-A14), data inputs (DQ0-DQ8), and control signals, with exception of Output Enable (G), are clock controlled inputs through non-invert- ing, pos-itive edge triggered registers. A cache burst_address sequence can be initiated by either ADSP (Address Status Processor) or ADSC (Ad- dress Sta-tus Cache Controller) inputs, with sub- sequent burst addresses being internally generated by the Burst SRAM. The ADV input (burst address advance) provides control of the burst sequence, which imitates the i486 cache burst address sequence. Once a cache burst cycle begins, the subsequent burst address is generated internally each time the ADV input is asserted at the rising edge of the clock (K) input. The burst counter operates in the same manner for either cache burst write or read cycles. The ADSP and the ADSC inputs control the start and the duration of the burst sequence respec- tively. Each time either address status input is asserted low, a new external base address is reg- istered on the positive going edge of the clock (K).52E D Wl 7929237 0038228 430 MBSGTH MK62486 ASYNCHRONOUS TRUTH TABLE BURST COUNT SEQUENCE T-46-23-1 3 Mode G DQ Status External Address A14-A2 At AO Read L Data Out _ 1st Burst Address A14-A2 Al AO Read H High-Z Write) x Data In (High-Z) 2nd Burst Address A14-A2 Al AO Deselect x High-Z 3rd Burst Address | A14-A2 Ai AO Notes : Note : The burst count sequence wraps around to the initial address 1. X= Don't Care. after a full count is completed. 2. For acache write cycle following a read operation, G must be high before the input data required set-up time, and be held high through the input data hold time. S$ G S-THOMSON SYNCHRONOUS TRUTH TABLE so S1 | ADSP | ADSC | ADV Ww K Address Operation L x L xX X N/A Deselected Xx H H L x xX Tt N/A Deselected H L L x x X tT External Base Address nead Cycle - Begin urst H L H L x L tT Extemal Base Address ine Cycle - Extend urst H L H L x H T External Base Address aod Cycle - Extend urst Write Cycle - Continue xX x H H L L T Advance Burst Address Burst Sequence Read Cycle - Continue x x H H L H tT Advance Burst Address | 514 Sequence Hold Current Burst Write Cycle - Suspend x x H H H L t Address Burst Sequence Hold Current Burst Read Cycle - Suspend x x H H H H t Address Burst Sequence Notes : 1. X= Don't Care. 2. Allinputs except G require set-up and hold times to the rising edge (low to high transition) of the external clock (K). 3. All read and write timings are referenced from G or K. 4 Aread cycle is defined by W high or ADSP low for the required set-up and hold times. A write cycle is defined by W being asserted low for the set-up and hold times. Gis a don't care when W is registered low from the previous rising clock edge. 6. Chip Selects must be true (S0 = high, $1 = low)_at gach rising of the clock while ADSP or ADSC is asserted for the device to remain enabled; Chip Selects are registered whenever ADSP or ADSC is asserted low at the rising edge of the clock. a k7_ SGS-THOMSON 3/2 vf. MICROELECTRONICS 747MK62986 __ sae D Wl 7929237 0038229 377 MMSGTH - ABSOLUTE MAXIMUM RATINGS S G S-THOMSON : T-46-23-1 3 Symbol Parameter Value Unit Vi Voltage on any Pin Relative to Ground ~0.5 to 6 Vv Ta Ambient Operating Temperature 0 to 70 C Tsta Storage Temperature . 65 to 150 C Pp Power Dissipation 1.2 Ww lout Output Current 20 mA Notes : 1. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is nat implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. 2. Output current absolute maximum rating is specified for one output at a time, not to exceed a duration of t secand. RECOMMENDED DC OPERATING CONDITIONS (0 C < Tas +70 C) . Symbol Parameter Min. Typ. Max. Unit Veco Supply Voltage 4.75 5 5.25 Vv GND Ground 0 0 0 Vv Vin Logic 1 All Inputs 2.2 3 Vee + 0.3 v Vir Logic 0 All Inputs 0.3 0.2 0.8 Vv DC ELECTRICAL CHARACTERISTICS (0 C < Tas +70 C; Voc = 5V + 5%) Symbol Parameter Min. Max. Unit Note cor_| fyerageAC Rover Suny Cunt (G = 80 Vin ST eo | om | 4 Isp TTL Standby Current (SO = Vit, ST = Vin) 40 mA 5 \spi CMOS Standby Current (SO < 0.2V, S17 > Voc 0.2V) 30 mA 6 tu Input Leakage Current (Any Input) -1 1 pA 2 ILo Output Leakage Current -1 1 pA 2 Vou Quiput Logic 1 Voltage (lou = 4.0mA) 2.4 Vv 1 VoL | Output Logic 0 Voltage (lo: = 8mA) 04 Vv 1 = Ay7, SSanssroses 7485eE D MM 7929237 0038250 099 MBSGTH MK62486 CAPACITANCE S G S-THOMSON 46-23 (Ta = 25 C, f = 1MHz) Symbol Parameter Typ. Max. Unit Notes C; Input Capacitance on all pins (except DQ) 4 5 pF 7 Co Output Capacitance 8 10 pF 3,7 Notes : 1, All voltages referenced to GND. 6. All other inputs 2 Voc 0.2 or < GND +0.2, f = 0, Voc max. 2, Measured with GND < V < Vcc and outputs deselects. 7. Capacitances are sampled and not 100% tested. 3. Output buffers are deselected. 8. For proper operation the RES input should be tied ta ground. 4. Icc1 measured as average AC current, with outputs open, Voc max, trukH min duty cycle 100%. 5. All other inputs at Vit or Vin, f = 0, Vee max. AC TEST CONDITIONS Parameter Value Unit Input Levels Oto3 v Transition Time 1.5 ns Input and Output Signal Timing Reference Level 1.5 v Ambient Temperature 0 to 70 c Supply Voltage 5+15 % Figure 3. Equivalent Output Load Circuits +5.0 V +5.0 V 480 ohms DEVICE DEVICE UNDER UNDER TEST TEST 255 ohms 85 pF % 255 chms _ 5 pF * = (A) = (B) 3 INCLUDES SCOPE AND TEST JIG *K INCLUDES SCOPE AND TEST vIG yaooro76 INCL Al J vaooio77 {7 SGS-THOMSON 5/12 Tf. menomecrnonics 749MK62486 0 S2E D6 67929237 00382351 T25 MBSGTH READ/WRITE CYCLE TIMING - AC OPERATING CONDITIONS AND CHARACTERISTICS Yer - 9 (0C < Ta s 70C; Vcc = 5V + 5%) S G S-THOMSON _T-46-23-13_ Symbol Parameter 9 4 Unit Note Min. Max. Min. Max. {KHKH Cycle Time 25 30 ns tkKHaV Clock Access Time 19 24 ns 1 tkKHKL Clock High Pulse Width 9.5 11 ns {KLKH Clock Low Pulse Width 9.5 11 ns teLav Output Enable Access Time 8 9 ns 1 tKHOX Clock High to Output Active 3 3 ns 1 toLax Output Enable to Output Active 0 0 ns 2 tkHax2 | Clock High to Q Active (Low-Z) 3 3 ns 2 tkHaz Clock High to Q High-Z 12 15 ns 2 taHaz Output Disable to Q High-Z : 8 9 ns 2 tavKH Address Set-up Time 3 3 ns 3 tapsvkH | Address Status Set-up Time 3 3 ns 3 tovKH Data In Set-up Time 3 3 ns 3 twvKH Write/Read Set-up Time 3 3 ns 3 taovvkH | Address Advance Set-up Time 3 3 ns 3 tsovKH Chip Select 0 (SO) Set-up Time 3 3 ns 3 tsivcn | Chip Select 1 (ST) Set-up Time 3 3 ns 3 tkyax | Address Hold Time 2 2 : ns 3 tkHapsx | Address Status Hold Time 2 2 ns 3 tKHDX Data In Hold Time 2 2 ns 3 tkHwx | Write/Read Hold Time 2 2 ns 3 tkHapvx | Address Advance Hold Time 2 2 , ns 3 tkHsox | Chip Select 0 (SO) Hold Time 2 2 ns 3 tkusix | Chip Select 1 (S1) Hold Time 2 2 ns 3 Notes : 1. Measured with load as shown in Figure 3A. 2. Transition is measured + 500 mV from steady-stage voltage with load as shown in Figure 3B. This parameter is sampled and not 100 % tested 3. Thisisa synchronous device requiring that all inputs must meet the specified set-up and hold times with stable logic levels for all rising edges of the clock input (K). gle 57 SGS-THOMSON J, MICROELECTRONICS 750-~ 5eE D MM 752923? 0038232 9b) MESGTH DEVICE OPERATIONS (Continued) When ADSP is asserted low, any angoing burst cycle is interrupted, and a read operation (indepen- dent of W and ADSC) is performed at the new registered external base address. Anew burst cycle is initiated each time ADSP is asserted. By assert- ing ADSC low, the present burst cycle (initiated by ADSP) is interrupted and an extended burst read or write (depending upon the logic state of W at the rising edge of K ) is performed at the new registered base address. Chip selects (SO and $1) are only sampled when a new base address is loaded. Therefore, the chip selects are registered when either address status input is asserted low at the rising edge of the clock (K), and remain latched internally until the next assertion of either ADSP or ADSC. The MK62486 Truth Tables and timing dia- grams reference specific device operations. It should be noted that the MK62486 allows a non-burst mode of operation where ADSP is the ADS# of the i486 processor in a 2-2 cycle mode of operation, and ADSC is held high during T2 (see Figure 4). However, the non-burst mode obviously negates the advantage of the internal burst counter for fast cache fill operations. In either mode (burst or non-burst), the write cycles are internally self- Figure 4. General 128K Byte Cache Block Diagram timed, and are initiated by the rising edge of the clock input. Self-timed write cycles eliminate com- plex off-chip write pulse generation providing more flexibility for incoming signals. The ADV input controls subsequent burst data accesses after the first data of the burst cycle is processed. Each time ADV is asserted low for subsequent bursts at the rising edge of the clock input, the burst counter is advanced to the next burst address sequence. The address is advanced before the operation. Wait states can be inserted during burst cycles by holding the ADV pin high during positive clock transitions. Upon completion of the full internal burst count, the address will wrap-around to its initial base address GENERAL APPLICATION The MK62486 is organized using the ninth bit as the parity bit to support byte parity. Since the i486 processor provides on-board parity generation and checking, the ninth bit of the cache Burst SRAM can be passed to one of the DP0-DP3 pins of the microprocessor. Thus the MK62486 provides an architecture for building a 32K x 32-bit burstable data cache SRAM array, with byte parity, by using four devices in a 128K byte cache application. S G S~THOMSON DO-31 DPO-3 t+| GLOBAL A2-21 | || MEMORY 15 32 6 I MK62486 BUS ADDR P ADOR. a SP pa0-74 INTF. TAGRAM |! | {| augo bas . i486 -+ ADV I WRITE READ CONTROL CONTROL ADS # = cLK RDY # BRDY # CACHE CONTROLLER BLAST # LOGIC cLK vroo1078 kz SGS-THOMSON 7, incrosuecracmes TH2 761MK62486_ CoE D6 79292397 0038233 &T8 BBSGTH Figure 5. Non-Burst Read/Write 2-2 Cycles S$ 6G S=<THOMSON T-46-23-13 PROCESSOR TM T2 TH T2 CLK STATE READ WRITE CLK tADSVKH t KHADSX ADS Pp ADS ADDR. w 1 S1VKH tKHS1X st (S0=VIH) t ADWWKH t KHADVX ADV @ t KHDX tOVKH Q Dout Q1(A1) Din D1(A2) Note : Non-Burst 2-2 Bus Cycle K486R01 a2 {7 SGS-THOMSON If, isienomecrromes 752- S2E D MM 7929237 0038234 734 MESGTH MKS2486 igure 6. J-46-23-13 Figure 6. Burst Read Cycle SG S-THOMSON T1 T2 T2 T2 T2 T2 T2 T2 1 Begin Burst tKHKH Extend nt xa Suspend Burst K t ADSVKH tKHADSX ADS p ADSc ADDR. w tS1VKH tkKHS1X s1 + (S0=VIH) tADVVKH tKHADVX ADV : : tKHOQZ G tkKHOX tGHaz tGLax tKHOX! DQ at a2 a3 Q2 a3 (Data OUT) (At) (At) (Al) (At) (A2) (A2 (A2) BRAMBR2 9/2 SGS-THOMSON 4. incnorectRowies 753mK624860 SPE DSO 7929237 00382395 670 MBSGTH Figure 7. Burst Write Cycle SG S-THOMSON T-46-23-13 T1 T2 T2 T2 Te T2 T2 T2 T2 Begin Burst tKHKH Extend Burst Suspend Burst Extend Burst tKHKL tKLKH ADS p tADSVKH tKHADSX ADSC tKHAX ADDR. 1 KHWX w tKHSOX _ 50 (S1=VIL) t ADVVKH tKHADVX ADV : G tDVKH DQ D2 D1 D4 Dt Data IN ( ) (A1) {A1) (A2) {A2) (A2) (A2) (A2) (A3) K4s6Bwo2 10/12 K7 86S-THOMsON TF, mcRosLeciRomes 754S52E D WB 792923? 0038236 SO? MBSGTH Figure 8. Combined Burst Read/Write Cycle T1 T2 Begin Burst T2 T2 T2 Suspend Burst tKHKH tKHKL 'KLKH K SJ \ SG S-THOMSON T2 T2 Continue Burst MK62486 T~46-~23.13 T2 WO \/ \S aw, tKHADVX tADVVKH ++ vk t/ _ ADDR. Koa xX | wi 7ST TT LTT ADV t DVKH tKHDX G tGHaz 00 (CoH) (Al) (A1) (A1) (A1) (At) (Al) Notes: SO = high, $1 = low. BWRK486 E 'g_ SGS-THOMSON 11/12 vf, MICROELECTRONICS 756MK62486_ coe p Mm 7929237 0038237 443 MSGTH - -13 8 G S- _46-23-1 ORDERING INFORMATION 7 S- THOMSON T Example: MK62486 Q 19 Package | | Speed Q PLOC44 19 19ns at 4OMHz 24 24ns at 33MHz For a list of available options of Package and Speed refer to the Selector Guide in this Data Book or the current Memory Shortform that will be periodically up-dated. For further information on any aspect of this device, please contact our Sales Office nearest to you. tee {57 SGS-THOMSON Jf, MICROELECTRONICS 756