© Semiconductor Components Industries, LLC, 2013
October, 2013 − Rev. 9
1Publication Order Number:
CAT93C46R/D
CAT93C46R
1 kb Microwire Serial
EEPROM
Description
The CAT93C46R is a 1 kb CMOS Serial EEPROM device which is
organized as either 64 registers of 16 bits or 128 registers of 8 bits, as
determined by the state of the ORG pin. The CAT93C46R features
sequential read and self−timed internal write with auto−clear. On−chip
Power−On Reset circuitry protects the internal logic against powering
up in the wrong state.
In contrast to the CAT93C46, the CAT93C46R features an internal
instruction clock counter which provides improved noise immunity
for Write/Erase commands.
Features
•High Speed Operation: 4 MHz @ 5 V, 2 MHz @ 1.8 V
•1.8 V to 5.5 V Supply Voltage Range
•Selectable x8 or x16 Memory Organization
•Sequential Read
•Software Write Protection
•Power−up Inadvertant Write Protection
•Low Power CMOS Technology
•1,000,000 Program/Erase Cycles
•100 Year Data Retention
•Industrial Temperature Range
•8−pin PDIP, SOIC, TSSOP and 8−pad TDFN Packages
•This Device is Pb−Free, Halogen Free/BFR Free and RoHS
Compliant*
Figure 1. Functional Symbol
DO
GND
CAT93C46R
VCC
ORG
CS
SK
DI
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
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See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
ORDERING INFORMATION
PIN CONFIGURATION
GND
NC
VCC
DO
DI
SK
CS 1
ORG
PDIP (L), SOIC (V),
TSSOP (Y), TDFN (VP2)**
Chip SelectCS
Clock InputSK
Serial Data InputDI
Serial Data OutputDO
Power SupplyVCC
GroundGND
FunctionPin Name
PIN FUNCTION
Memory OrganizationORG
No ConnectionNC
Note: When the ORG pin is connected to VCC, the
x16 organization is selected. When it is connected
to ground, the x8 pin is selected. If the ORG pin is
left unconnected, then an internal pull−up device will
select the x16 organization.
SOIC−8
V SUFFIX
CASE 751BD
PDIP−8
L SUFFIX
CASE 646AA
TDFN−8**
VP2 SUFFIX
CASE 511AK
TSSOP−8
Y SUFFIX
CASE 948AL
(Top View)
** Not recommended for new designs
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Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter Value Units
Storage Temperature −65 to +150 °C
Voltage on Any Pin with Respect to Ground (Note 1) −0.5 to +6.5 V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol Parameter Min Units
NEND (Note 3) Endurance 1,000,000 Program / Erase Cycles
TDR Data Retention 100 Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Block Mode, VCC = 5 V, TA = 25°C
Table 3. D.C. OPERATING CHARACTERISTICS (VCC = +1.8 V to +5.5 V, unless otherwise specified.)
Symbol Parameter Test Conditions Min Max Units
ICC1 Power Supply Current (Write) fSK = 1 MHz
VCC = 5.0 V
1 mA
ICC2 Power Supply Current (Read) fSK = 1 MHz
VCC = 5.0 V
500 mA
ISB1 Power Supply Current (Standby) (x8 Mode) CS = 0 V
ORG = GND
10 mA
ISB2 Power Supply Current (Standby) (x16 Mode) CS = 0 V
ORG = Float or VCC
10 mA
ILI Input Leakage Current VIN = 0 V to VCC 2mA
ILO Output Leakage Current (Including ORG pin) VOUT = 0 V to VCC,
CS = 0 V
2mA
VIL1 Input Low Voltage 4.5 V v VCC < 5.5 V −0.1 0.8 V
VIH1 Input High Voltage 4.5 V v VCC < 5.5 V 2 VCC + 1 V
VIL2 Input Low Voltage 1.8 V v VCC < 4.5 V 0 VCC x 0.2 V
VIH2 Input High Voltage 1.8 V v VCC < 4.5 V VCC x 0.7 VCC + 1 V
VOL1 Output Low Voltage 4.5 V v VCC < 5.5 V
IOL = 2.1 mA
0.4 V
VOH1 Output High Voltage 4.5 V v VCC < 5.5 V
IOH = −400 mA
2.4 V
VOL2 Output Low Voltage 1.8 V v VCC < 4.5 V
IOL = 1 mA
0.2 V
VOH2 Output High Voltage 1.8 V v VCC < 4.5 V
IOH = −100 mA
VCC − 0.2 V
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Table 4. PIN CAPACITANCE
Symbol Test Conditions Min Typ Max Units
COUT (Note 4) Output Capacitance (DO) VOUT = 0 V 5 pF
CIN (Note 4) Input Capacitance (CS, SK, DI, ORG) VIN = 0 V 5 pF
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
Table 5. A.C. CHARACTERISTICS (Note 5)
Symbol Parameter
VCC = 1.8 V − 5.5 V VCC = 4.5 V − 5.5 V
Units
Min Max Min Max
tCSS CS Setup Time 50 50 ns
tCSH CS Hold Time 0 0 ns
tDIS DI Setup Time 100 50 ns
tDIH DI Hold Time 100 50 ns
tPD1 Output Delay to 1 0.25 0.1 ms
tPD0 Output Delay to 0 0.25 0.1 ms
tHZ (Note 6) Output Delay to High−Z 100 100 ns
tEW Program/Erase Pulse Width 5 5 ms
tCSMIN Minimum CS Low Time 0.25 0.1 ms
tSKHI Minimum SK High Time 0.25 0.1 ms
tSKLOW Minimum SK Low Time 0.25 0.1 ms
tSV Output Delay to Status Valid 0.25 0.1 ms
SKMAX Maximum Clock Frequency DC 2 DC 4 MHz
5. Test conditions according to “A.C. Test Conditions” table.
6. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
Table 6. POWER−UP TIMING (Notes 4 and 7)
Symbol Parameter Max Units
tPUR Power−up to Read Operation 1 ms
tPUW Power−up to Write Operation 1 ms
7. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
Table 7. A.C. TEST CONDITIONS
Input Rise and Fall Times v 50 ns
Input Pulse Voltages 0.4 V to 2.4 V 4.5 V v VCC v 5.5 V
Timing Reference Voltages 0.8 V, 2.0 V 4.5 V v VCC v 5.5 V
Input Pulse Voltages 0.2 VCC to 0.7 VCC 1.8 V v VCC v 4.5 V
Timing Reference Voltages 0.5 VCC 1.8 V v VCC v 4.5 V
Output Load Current Source IOLmax/IOHmax; CL = 100 pF
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Table 8. INSTRUCTION SET
Instruction Start Bit Opcode
Address Data
Comments
x8 x16 x8 x16
READ 1 10 A6−A0 A5−A0 Read Address AN–A0
ERASE 1 11 A6−A0 A5−A0 Clear Address AN–A0
WRITE 1 01 A6−A0 A5−A0 D7−D0 D15−D0 Write Address AN–A0
EWEN 1 00 11XXXXX 11XXXX Write Enable
EWDS 1 00 00XXXXX 00XXXX Write Disable
ERAL 1 00 10XXXXX 10XXXX Clear All Addresses
WRAL 1 00 01XXXXX 01XXXX D7−D0 D15−D0 Write All Addresses
Device Operation
The CAT93C46R is a 1024−bit nonvolatile memory
intended for use with industry standard microprocessors.
The CAT93C46R can be organized as either registers of 16
bits or 8 bits. When organized as X16, seven 9−bit
instructions control the reading, writing and erase
operations of the device. When organized as X8, seven
10−bit instructions control the reading, writing and erase
operations of the device. The CAT93C46R operates on a
single power supply and will generate on chip the high
voltage required during any write operation.
Instructions, addresses, and write data are clocked into the
DI pin on the rising edge of the clock (SK). The DO pin is
normally in a high impedance state except when reading data
from the device, or when checking the ready/busy status
after a write operation.
The ready/busy status can be determined after the start of
a write operation by selecting the device (CS high) and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that the
device is ready for the next instruction. If necessary, the DO
pin may be placed back into a high impedance state during
chip select by shifting a dummy “1” into the DI pin. The DO
pin will enter the high impedance state on the rising edge of
the clock (SK). Placing the DO pin into the high impedance
state is recommended in applications where the DI pin and
the DO pin are to be tied together to form a common DI/O
pin. The Ready/Busy flag can be disabled only in Ready
state; no change is allowed in Busy state.
The format for all instructions sent to the device is a
logical “1” start bit, a 2−bit (or 4−bit) opcode, 6−bit address
(an additional bit when organized X8) and for write
operations a 16−bit data field (8−bit for X8 organization).
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAT93C46R will
come out of the high impedance state and, after sending an
initial dummy zero bit, will begin shifting out the data
addressed (MSB first). The output data bits will toggle on
the rising edge of the SK clock and are stable after the
specified time delay (tPD0 or tPD1).
Sequential Read
After the 1st data word has been shifted out and CS
remains asserted with the SK clock continuing to toggle, the
CAT93C46R will automatically increment to the next
address and shift out the next data word. As long as CS is
continuously asserted and SK continues to toggle, the device
will keep incrementing to the next address automatically
until it reaches the end of the address space, then loops back
to address 0. In the sequential Read mode, only the initial
data word is preceeded by a dummy zero bit; all subsequent
data words will follow without a dummy zero bit.
Erase/Write Enable and Disable
The CAT93C46R powers up in the write disable state.
Any writing after power−up or after an EWDS (write
disable) instruction must first be preceded by the EWEN
(write enable) instruction. Once the write instruction is
enabled, it will remain enabled until power to the device is
removed, or the EWDS instruction is sent. The EWDS
instruction can be used to disable all CAT93C46R write and
erase instructions, and will prevent any accidental writing or
clearing of the device. Data can be read normally from the
device regardless of the write enable/disable status.
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Figure 2. Synchronous Data Timing
SK
DI
CS
DO
VALID
DATA VALID
tCSH
tDIH
tCSMIN
tDIS tPD0, tPD1
VALID
tDIS
tCSS
tSKHI tSKLOW
Figure 3. Read Instruction Timing
SK
CS
DI
DO
STANDBY
HIGH−ZHIGH−Z
11 0
0
ANAN−1A0
tPD0
tHZ
tCSMIN
D0
D1
DNDN−1
Figure 4. Sequential Read Instruction Timing
SK
CS
DI
DO HIGH−Z
11 0
ANAN−1A0
Address + 1
D15...D0
or
D7...D0
1111111111111 11
Dummy 0
Don’t Care
Address + 2
D15...D0
or
D7...D0
Address + n
D15...
or
D7...
D15...D0
or
D7...D0
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Figure 5. EWEN/EWDS Instruction Timing
CS
DI
STANDBY
0*
* ENABLE = 11
DISABLE = 00
SK
01
Write
After receiving a WRITE command, address and the data,
the CS (Chip Select) pin must be deselected for a minimum
of tCSMIN (See Design Note for details). The falling edge of
CS will start the self clocking clear and data store cycle of
the memory location specified in the instruction. The
clocking of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of the
CAT93C46R can be determined by selecting the device and
polling the DO pin. Since this device features Auto−Clear
before write, it is NOT necessary to erase a memory location
before it is written into.
Erase
Upon receiving an ERASE command and address, the CS
(Chip Select) pin must be deasserted for a minimum of
tCSMIN after the proper number of clock pulses (See Design
Note). The falling edge of CS will start the self clocking
clear cycle of the selected memory location. The clocking of
the SK pin is not necessary after the device has entered the
self clocking mode. The ready/busy status of the
CAT93C46R can be determined by selecting the device and
polling the DO pin. Once cleared, the content of a cleared
location returns to a logical “1” state.
Erase All
Upon receiving an ERAL command, the CS (Chip Select)
pin must be deselected for a minimum of tCSMIN. The falling
edge of CS will start the self clocking clear cycle of all
memory locations in the device. The clocking of the SK pin
is not necessary after the device has entered the self clocking
mode. The ready/busy status of the CAT93C46R can be
determined by selecting the device and polling the DO pin.
Once cleared, the contents of all memory bits return to a
logical “1” state.
Write All
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
tCSMIN. The falling edge of CS will start the self clocking
data write to all memory locations in the device. The
clocking of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of the
CAT93C46R can be determined by selecting the device and
polling the DO pin. It is not necessary for all memory
locations to be cleared before the WRAL command is
executed.
Design Note
With CAT93C46R, after the last data bit has been
sampled, Chip Select (CS) must be brought Low before the
next rising edge of the clock (SK) in order to start the
self−timed high voltage cycle. This is important because if
the CS is brought low before or after this specific frame
window, the addressed location will not be programmed or
erased.
Figure 6. Write Instruction Timing
SK
CS
DI
DO
STANDBY
HIGH−Z
HIGH−Z
101
BUSY
READY
STATUS
VERIFY
ANAN−1A0DND0
tCS MIN
tSV tHZ
tEW
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Figure 7. Erase Instruction Timing
SK
CS
DI
DO
STANDBY
HIGH−Z
HIGH−Z
1
BUSY READY
STATUS VERIFY
11
ANAN−1A0
tCS MIN
tSV tHZ
tEW
Figure 8. ERAL Instruction Timing
SK
CS
DI
DO
STANDBY
HIGH−Z
HIGH−Z
10 1
BUSY READY
STATUS VERIFY
00
tCS MIN
tHZ
tSV
tEW
Figure 9. WRAL Instruction Timing
STATUS VERIFY
SK
CS
DI
DO
STANDBY
HIGH−Z
10 1
BUSY READY
00 DND0
tCS MIN
tSV tHZ
tEW
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PACKAGE DIMENSIONS
PDIP−8, 300 mils
CASE 646AA−01
ISSUE A
E1
D
A
L
eb
b2
A1
A2
E
eB
c
TOP VIEW
SIDE VIEW END VIEW
PIN # 1
IDENTIFICATION
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-001.
SYMBOL MIN NOM MAX
A
A1
A2
b
b2
c
D
e
E1
L
0.38
2.92
0.36
6.10
1.14
0.20
9.02
2.54 BSC
3.30
5.33
4.95
0.56
7.11
1.78
0.36
10.16
eB 7.87 10.92
E 7.62 8.25
2.92 3.80
3.30
0.46
6.35
1.52
0.25
9.27
7.87
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PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD−01
ISSUE O
E1 E
A
A1
h
θ
L
c
eb
D
PIN # 1
IDENTIFICATION
TOP VIEW
SIDE VIEW END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
SYMBOL MIN NOM MAX
θ
A
A1
b
c
D
E
E1
e
h
0º 8º
0.10
0.33
0.19
0.25
4.80
5.80
3.80
1.27 BSC
1.75
0.25
0.51
0.25
0.50
5.00
6.20
4.00
L0.40 1.27
1.35
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PACKAGE DIMENSIONS
TSSOP8, 4.4x3
CASE 948AL−01
ISSUE O
E1 E
A2
A1
e
b
D
c
A
TOP VIEW
SIDE VIEW END VIEW
q1
L1 L
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
SYMBOL
θ
MIN NOM MAX
A
A1
A2
b
c
D
E
E1
e
L1
0º 8º
L
0.05
0.80
0.19
0.09
0.50
2.90
6.30
4.30
0.65 BSC
1.00 REF
1.20
0.15
1.05
0.30
0.20
0.75
3.10
6.50
4.50
0.90
0.60
3.00
6.40
4.40
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PACKAGE DIMENSIONS
TDFN8, 2x3
CASE 511AK−01
ISSUE A
PIN#1
IDENTIFICATION
E2
E
A3
ebD
A2
TOP VIEW SIDE VIEW BOTTOM VIEW
PIN#1 INDEX AREA
FRONT VIEW
A1
A
L
D2
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MO-229.
SYMBOL MIN NOM MAX
A 0.70 0.75 0.80
A1 0.00 0.02 0.05
A3 0.20 REF
b 0.20 0.25 0.30
D 1.90 2.00 2.10
D2 1.30 1.40 1.50
E 3.00
E2 1.20 1.30 1.40
e
2.90
0.50 TYP
3.10
L 0.20 0.30 0.40
A2 0.45 0.55 0.65
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Ordering Information
OPN
Specific
Device
Marking Pkg Type Temperature Range
Lead
Finish Shipping
CAT93C46RLI−G 93C46RL PDIP−8I = Industrial
(−40°C to +85°C)
NiPdAu Tube, 50 Units / Tube
CAT93C46RVI−G 93C46RV SOIC−8, JEDEC I = Industrial
(−40°C to +85°C)
NiPdAu Tube, 100 Units / Tube
CAT93C46RVI−GT3 93C46RV SOIC−8, JEDEC I = Industrial
(−40°C to +85°C)
NiPdAu Tape & Reel,
3000 Units / Reel
CAT93C46RVP2IGT3
(Note 8)
EL TDFN−8I = Industrial
(−40°C to +85°C)
NiPdAu Tape & Reel,
3000 Units / Reel
CAT93C46RYI−G 46R TSSOP−8I = Industrial
(−40°C to +85°C)
NiPdAu Tube, 100 Units / Tube
CAT93C46RYI−GT3 46R TSSOP−8I = Industrial
(−40°C to +85°C)
NiPdAu Tape & Reel,
3000 Units / Reel
8. Not recommended for new designs.
9. All packages are RoHS−compliant (Lead−free, Halogen−free).
10.The standard lead finish is NiPdAu.
11. For additional package and temperature options, please contact your nearest ON Semiconductor Sales office.
12.For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
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any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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Europe, Middle East and Africa Technical Support:
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CAT93C46R/D
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