ADSP-BF531SBST-300 - Analog Devices

Embedded Processor

Preliminary Technical Data

This information applies to a product under development. Its characteristics

and specifications are subject to change without notice. Analog Devices

assumes no obligation regarding future manufacturing unless otherwise

agreed to in writing.

One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel:781/329-4700 www.analog.com

Fax:781/326-8703 ©Analog Devices,Inc., 2003

REV. PrA

PRELIMINARY TECHNICAL DATA

ADSP-BF531/BF532/BF533

FEATURES

Up to 600 MHz High-Performance Blackfin Processor

Two 16-Bit MACs, Two 40-Bit ALUs, Four 8-Bit Video

ALUs, 40-Bit Shifter

RISC-Like Register and Instruction Model for Ease of

Programming and Compiler-Friendly Support

Advanced Debug, Trace, and Performance- Monitoring

0.7 V to 1.2 V Core V

with On-chip Voltage Regulation

3.3 V-Tolerant I/O

160-Ball Mini-BGA and 176-Lead LQFP Packages

MEMORY

Up to 148K Bytes of On-Chip Memory:

16K Bytes of Instruction SRAM/Cache

64K Bytes of Instruction SRAM

32K Bytes of Instruction ROM

32K Bytes of Data SRAM/Cache

32K Bytes of Data SRAM

4K Bytes of Scratchpad SRAM

Two Dual-Channel Memory DMA Controllers

Memory Management Unit Providing Memory

Protection

External Memory Controller with Glueless Support for

SDRAM, SRAM, FLASH, and ROM

Flexible Memory Booting Options From SPI, External

Memory, or Internal ROM

PERIPHERALS

Parallel Peripheral Interface (PPI)/GPIO,

Supporting ITU-R 656 Video Data Formats

Two Dual-Channel, Full-Duplex Synchronous Serial

Ports, Supporting Eight Stereo I

S Channels

12 Channel DMA Controller

SPI-compatible Port

Three Timer/Counters with PWM Support

UART with Support for IrDA®

Event Handler

Real-Time Clock

Watchdog Timer

Debug/JTAG Interface

On-Chip PLL Capable of 1x To 63x Frequency

Multiplication

FUNCTIONAL BLOCK DIAGRAM

VOLTAGE

REGULATOR

DMA

CONTROLLER

EVENT

CONTROLLER/

CORE TIMER

REAL TIME CLOCK

UART PORT

IrDA

TIMER0, TIMER1,

TIMER2

PPI / GPIO

SERIAL PORTS (2)

SPI PORT

EXTERNAL PORT

FLASH, SDRAM

CONTROL

BOOT ROM

JTAG TEST AND

EMULATION WATCHDOG TIMER

INSTRUCTION

MEMORY

DATA

MEMORY

MMU

CORE / SYSTEM BUS INTERFACE

For current information contact Analog Devices at 800/262-5643

ADSP-BF53x March 2003

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

2REV. PrA

PRELIMINARY TECHNICAL DATA

GENERAL NOTE

This data sheet provides preliminary information for the Black-

fin

processors.

GENERAL DESCRIPTION

The ADSP-BF53x Processors are members of the Blackfin family

of products, incorporating the Analog Devices/Intel Micro Signal

Architecture (MSA). Blackfin processors combine a dual-MAC

state-of-the-art signal processing engine, the advantages of a

clean, orthogonal RISC-like microprocessor instruction set, and

single-instruction, multiple-data (SIMD) multimedia capabili-

ties into a single instruction-set architecture.

The ADSP-BF53x Processors are completely code and pin com-

patible, differing only with respect to their performance and on-

chip memory. Specific performance and memory configurations

are shown in Table 1.

By integrating a rich set of industry-leading system peripherals

and memory, Blackfin processors are the platform of choice for

next-generation applications that require RISC-like programma-

bility, multimedia support and leading-edge signal processing in

one integrated package.

Portable Low-Power Architecture

Blackfin processors provide world-class power management and

performance. Blackfin processors are designed in a low power

and low voltage design methodology and feature Dynamic Power

Management, the ability to vary both the voltage and frequency

of operation to significantly lower overall power consumption.

Varying the voltage and frequency can result in a substantial

reduction in power consumption, compared with just varying the

frequency of operation. This translates into longer battery life for

portable appliances.

System Integration

The ADSP-BF53x Processors are highly integrated system-on-

a-chip solutions for the next generation of digital communication

and consumer multimedia applications. By combining industry-

standard interfaces with a high performance signal processing

core, users can develop cost-effective solutions quickly without

the need for costly external components. The system peripherals

include a UART port, an SPI port, two serial ports (SPORTs),

four general purpose timers (three with PWM capability), a real-

time clock, a watchdog timer, and a Parallel Peripheral Interface.

ADSP-BF53x Processor Peripherals

The ADSP-BF53x Processor contains a rich set of peripherals

connected to the core via several high bandwidth buses, providing

flexibility in system configuration as well as excellent overall

system performance (see the block diagram on Page 1). The

general-purpose peripherals include functions such as UART,

Timers with PWM (Pulse Width Modulation) and pulse mea-

surement capability, general purpose flag I/O pins, a Real-Time

Clock, and a Watchdog Timer. This set of functions satisfies a

wide variety of typical system support needs and is augmented

by the system expansion capabilities of the part. In addition to

these general-purpose peripherals, the ADSP-BF53x Processor

contains high-speed serial and parallel ports for interfacing to a

variety of audio, video, and modem codec functions; an interrupt

controller for flexible management of interrupts from the on-chip

peripherals or external sources; and power management control

functions to tailor the performance and power characteristics of

the processor and system to many application scenarios.

All of the peripherals, except for general-purpose I/O, Real-Time

Clock, and timers, are supported by a flexible DMA structure.

There is also a separate memory DMA channel dedicated to data

transfers between the processor's various memory spaces,

including external SDRAM and asynchronous memory.

Multiple on-chip buses running at up to 133 MHz provide

enough bandwidth to keep the processor core running along with

activity on all of the on-chip and external peripherals.

The ADSP-BF53x Processor includes an on-chip voltage

regulator in support of the ADSP-BF53x Processor Dynamic

Power Management capability. The voltage regulator provides a

range of core voltage levels from a single 2.25 V to 3.6 V input.

The voltage regulator can be bypassed at the user's discretion.

Blackfin Processor Core

As shown in Figure 1 on page 3, the Blackfin processor core

contains two 16-bit multipliers, two 40-bit accumulators, two 40-

bit ALUs, four video ALUs, and a 40-bit shifter. The computa-

tion units process 8-bit, 16-bit, or 32-bit data from the register

file.

The compute register file contains eight 32-bit registers. When

performing compute operations on 16-bit operand data, the

operands for compute operations come from the multiported

Table 1. Processor Comparison

ADSP-BF531 ADSP-BF532 ADSP-BF533

Maximum performance 400 MHz/ 800 MMACs 400 MHz/ 800 MMACs 600 MHz/ 1200 MMACs

Instruction SRAM/Cache 16K bytes 16K bytes 16K bytes

Instruction SRAM 16K bytes 32K bytes 64K bytes

Instruction ROM 32K bytes 32K bytes

Data SRAM/Cache 16K bytes 32K bytes 32K bytes

Data SRAM 32K bytes

Scratchpad 4K bytes 4K bytes 4K bytes

Blackfin is a trademark of Analog Devices, Inc.

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

3REV. PrA

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PRELIMINARY TECHNICAL DATA

Each MAC can perform a 16-bit by 16-bit multiply in each cycle,

accumulating the results into the 40-bit accumulators. Signed

and unsigned formats, rounding, and saturation are supported.

The ALUs perform a traditional set of arithmetic and logical

operations on 16-bit or 32-bit data. In addition, many special

instructions are included to accelerate various signal processing

tasks. These include bit operations such as field extract and pop-

ulation count, modulo 2

multiply, divide primitives, saturation

and rounding, and sign/exponent detection. The set of video

instructions include byte alignment and packing operations, 16-

bit and 8-bit adds with clipping, 8-bit average operations, and 8-

bit subtract/absolute value/accumulate (SAA) operations. Also

provided are the compare/select and vector search instructions.

For certain instructions, two 16-bit ALU operations can be

performed simultaneously on register pairs (a 16-bit high half and

16-bit low half of a compute register). By also using the second

ALU, quad 16-bit operations are possible.

The 40-bit shifter can perform shifts and rotates and is used to

support normalization, field extract, and field deposit

instructions.

The program sequencer controls the flow of instruction execu-

tion, including instruction alignment and decoding. For program

flow control, the sequencer supports PC relative and indirect

conditional jumps (with static branch prediction), and subrou-

tine calls. Hardware is provided to support zero-overhead

looping. The architecture is fully interlocked, meaning that the

programmer need not manage the pipeline when executing

instructions with data dependencies.

The address arithmetic unit provides two addresses for simulta-

neous dual fetches from memory. It contains a multiported

Length, and Base registers (for circular buffering), and eight

additional 32-bit pointer registers (for C-style indexed stack

manipulation).

Blackfin processors support a modified Harvard architecture in

combination with a hierarchical memory structure. Level 1 (L1)

memories are those that typically operate at the full processor

speed with little or no latency. At the L1 level, the instruction

memory holds instructions only. The two data memories hold

data, and a dedicated scratchpad data memory stores stack and

local variable information.

In addition, multiple L1 memory blocks are provided, offering a

configurable mix of SRAM and cache. The Memory Manage-

ment Unit (MMU) provides memory protection for individual

tasks that may be operating on the core and can protect system

registers from unintended access.

Figure 1. Blackfin Processor Core

SEQUENCER

ALIGN

DECODE

LOOP BUFFER

DAG0 DAG1

16 16

88 8 8

40 40

A0 A1

BARREL

SHIFTER

DATA ARITHMETIC UNIT

CONTROL

UNIT

ADDRESS ARITHMETIC UNIT

For current information contact Analog Devices at 800/262-5643

ADSP-BF53x March 2003

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

4REV. PrA

PRELIMINARY TECHNICAL DATA

The architecture provides three modes of operation: User mode,

Supervisor mode, and Emulation mode. User mode has

restricted access to certain system resources, thus providing a

protected software environment, while Supervisor mode has

unrestricted access to the system and core resources.

The Blackfin processor instruction set has been optimized so that

16-bit opcodes represent the most frequently used instructions,

resulting in excellent compiled code density. Complex DSP

instructions are encoded into 32-bit opcodes, representing fully

featured multifunction instructions. Blackfin processors support

a limited multi-issue capability, where a 32-bit instruction can be

issued in parallel with two 16-bit instructions, allowing the pro-

grammer to use many of the core resources in a single instruction

cycle.

The Blackfin processor assembly language uses an algebraic

syntax for ease of coding and readability. The architecture has

been optimized for use in conjunction with the C/C++ compiler,

resulting in fast and efficient software implementations.

Memory Architecture

The ADSP-BF53x Processor views memory as a single unified

4G byte address space, using 32-bit addresses. All resources,

including internal memory, external memory, and I/O control

registers, occupy separate sections of this common address space.

The memory portions of this address space are arranged in a

hierarchical structure to provide a good cost/performance

balance of some very fast, low-latency on-chip memory as cache

or SRAM, and larger, lower-cost and performance off-chip

memory systems. See Figure 2 on page 4, Figure 3 on page 5,

and Figure 4 on page 5.

The L1 memory system is the primary highest-performance

memory available to the Blackfin processor. The off-chip

memory system, accessed through the External Bus Interface

Unit (EBIU), provides expansion with SDRAM, flash memory,

and SRAM, optionally accessing up to 132M bytes of physical

memory.

The memory DMA controller provides high-bandwidth data-

movement capability. It can perform block transfers of code or

data between the internal memory and the external memory

spaces.

Internal (On-chip) Memory

The ADSP-BF53x Processor has three blocks of on-chip memory

providing high-bandwidth access to the core.

The first is the L1 instruction memory, consisting of up to

80K bytes SRAM, of which 16K bytes can be configured as a

four-way set-associative cache. This memory is accessed at full

processor speed.

The second on-chip memory block is the L1 data memory, con-

sisting of up to two banks of up to 32K bytes each. Each memory

bank is configurable, offering both Cache and SRAM function-

ality. This memory block is accessed at full processor speed.

The third memory block is a 4K byte scratchpad SRAM which

runs at the same speed as the L1 memories, but is only accessible

as data SRAM and cannot be configured as cache memory.

External (Off-Chip) Memory

External memory is accessed via the EBIU. This 16-bit interface

provides a glueless connection to a bank of synchronous DRAM

(SDRAM) as well as up to four banks of asynchronous memory

devices including FLASH, EPROM, ROM, SRAM, and

memory mapped I/O devices.

The PC133-compliant SDRAM controller can be programmed

to interface to up to 128M bytes of SDRAM.

The asynchronous memory controller can be programmed to

control up to four banks of devices with very flexible timing

parameters for a wide variety of devices. Each bank occupies a

1M byte segment regardless of the size of the devices used, so

that these banks will only be contiguous if each is fully populated

with 1M byte of memory.

I/O Memory Space

Blackfin processors do not define a separate I/O space. All

resources are mapped through the flat 32-bit address space. On-

chip I/O devices have their control registers mapped into

memory-mapped registers (MMRs) at addresses near the top of

the 4G byte address space. These are separated into two smaller

blocks, one which contains the control MMRs for all core func-

tions, and the other which contains the registers needed for setup

Figure 2. ADSP-BF533 Internal/External Memory Map

RESERVED

CORE MMR REGISTERS (2M BYTE)

RESERVED

SCRATCHPAD SRAM (4K BYTE)

INSTRUCTION SRAM (64K BYTE)

SYSTEM MMR REGISTERS (2M BYTE)

RESERVED

DATA BANK B SRAM / CACHE (16K BYTE)

DATA BANK B SRAM (16K BYTE)

DATA BANK A SRAM / CACHE (16K BYTE)

ASYNC MEMORY BANK 3 (1M BYTE)

ASYNC MEMORY BANK 2 (1M BYTE)

ASYNC MEMORY BANK 1 (1M BYTE)

ASYNC MEMORY BANK 0 (1M BYTE)

SDRAM MEMORY (16M BYTE - 128M BYTE)

INSTRUCTION SRAM / CACHE (16K BYTE)

INTERNALMEMORYMAP

EXTERNALMEMORYMAP

0xFFFF FFFF

0xFFE0 0000

0xFFB0 0000

0xFFA1 4000

0xFFA1 0000

0xFF90 8000

0xFF90 4000

0xFF80 8000

0xFF80 4000

0xEF00 0000

0x2040 0000

0x2030 0000

0x2020 0000

0x2010 0000

0x2000 0000

0x0800 0000

0x0000 0000

0xFFC0 0000

0xFFB0 1000

0xFFA0 0000

RESERVED

DATA BANK A SRAM (16K BYTE)

0xFF90 0000

0xFF80 0000

RESERVED

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

5REV. PrA

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ADSP-BF53xMarch 2003

PRELIMINARY TECHNICAL DATA

and control of the on-chip peripherals outside of the core. The

MMRs are accessible only in supervisor mode and appear as

reserved space to on-chip peripherals.

Booting

The ADSP-BF53x Processor contains a small boot kernel, which

configures the appropriate peripheral for booting. If the ADSP-

BF53x Processor is configured to boot from boot ROM memory

space, the processor starts executing from the on-chip boot

ROM. For more information, see Booting Modes on Page 13.

Event Handling

The event controller on the ADSP-BF53x Processor handles all

asynchronous and synchronous events to the processor. The

ADSP-BF53x Processor provides event handling that supports

both nesting and prioritization. Nesting allows multiple event

service routines to be active simultaneously. Prioritization

ensures that servicing of a higher-priority event takes precedence

over servicing of a lower-priority event. The controller provides

support for five different types of events:

•Emulation – An emulation event causes the processor to

enter emulation mode, allowing command and control of

the processor via the JTAG interface.

•Reset – This event resets the processor.

•Non-Maskable Interrupt (NMI) – The NMI event can be

generated by the software watchdog timer or by the NMI

input signal to the processor. The NMI event is frequently

used as a power-down indicator to initiate an orderly

shutdown of the system.

•Exceptions – Events that occur synchronously to program

flow (i.e., the exception will be taken before the instruc-

tion is allowed to complete). Conditions such as data

alignment violations and undefined instructions cause

exceptions.

•Interrupts – Events that occur asynchronously to program

flow. They are caused by input pins, timers, and other

peripherals, as well as by an explicit software instruction.

Each event type has an associated register to hold the return

address and an associated return-from-event instruction. When

an event is triggered, the state of the processor is saved on the

supervisor stack.

The ADSP-BF53x Processor Event Controller consists of two

stages, the Core Event Controller (CEC) and the System

Interrupt Controller (SIC). The Core Event Controller works

with the System Interrupt Controller to prioritize and control all

system events. Conceptually, interrupts from the peripherals

enter into the SIC, and are then routed directly into the general-

purpose interrupts of the CEC.

Figure 3. ADSP-BF532 Internal/External Memory Map

CORE MMR REGISTERS (2M BYTE)

RESERVED

SCRATCHPAD SRAM (4K BYTE)

INSTRUCTION ROM (32K BYTE)

SYSTEM MMR REGISTERS (2M BYTE)

RESERVED

DATA BANK B SRAM / CACHE (16K BYTE)

RESERVED

DATA BANK A SRAM / CACHE (16K BYTE)

ASYNC MEMORY BANK 3 (1M BYTE)

ASYNC MEMORY BANK 2 (1M BYTE)

ASYNC MEMORY BANK 1 (1M BYTE)

ASYNC MEMORY BANK 0 (1M BYTE)

SDRAM MEMORY (16M BYTE - 128M BYTE)

INSTRUCTION SRAM / CACHE (16K BYTE)

INTERNALMEMORYMAP

EXTERNALMEMORYMAP

0xFFFF FFFF

0xFFE0 0000

0xFFB0 0000

0xFFA1 4000

0xFFA0 8000

0xFF90 8000

0xFF90 4000

0xFF80 8000

0xFF80 4000

0xEF00 0000

0x2040 0000

0x2030 0000

0x2020 0000

0x2010 0000

0x2000 0000

0x0800 0000

0x0000 0000

0xFFC0 0000

0xFFB0 1000

0xFFA0 0000

RESERVED

0xFFA1 0000 INSTRUCTION SRAM (32K BYTE)

Figure 4. ADSP-BF531 Internal/External Memory Map

CORE MMR REGISTERS (2M BYTE)

RESERVED

SCRATCHPAD SRAM (4K BYTE)

INSTRUCTION ROM (32K BYTE)

SYSTEM MMR REGISTERS (2M BYTE)

RESERVED

DATA BANK A SRAM / CACHE (16K BYTE)

ASYNC MEMORY BANK 3 (1M BYTE)

ASYNC MEMORY BANK 2 (1M BYTE)

ASYNC MEMORY BANK 1 (1M BYTE)

ASYNC MEMORY BANK 0 (1M BYTE)

SDRAM MEMORY (16M BYTE - 128M BYTE)

INSTRUCTION SRAM / CACHE (16K BYTE)

INTERNALMEMORYMAP

EXTERNALMEMORYMAP

0xFFFF FFFF

0xFFE0 0000

0xFFB0 0000

0xFFA1 4000

0xFFA0 8000

0xFF90 8000

0xFF90 4000

0xFF80 8000

0xFF80 4000

0xEF00 0000

0x2040 0000

0x2030 0000

0x2020 0000

0x2010 0000

0x2000 0000

0x0800 0000

0x0000 0000

0xFFC0 0000

0xFFB0 1000

0xFFA0 0000

RESERVED

0xFFA1 0000

INSTRUCTION SRAM (16K BYTE)

RESERVED

0xFFA0 C000

For current information contact Analog Devices at 800/262-5643

ADSP-BF53x March 2003

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

6REV. PrA

PRELIMINARY TECHNICAL DATA

Core Event Controller (CEC)

The CEC supports nine general-purpose interrupts (IVG15–7),

in addition to the dedicated interrupt and exception events. Of

these general-purpose interrupts, the two lowest-priority inter-

rupts (IVG15–14) are recommended to be reserved for software

interrupt handlers, leaving seven prioritized interrupt inputs to

support the peripherals of the ADSP-BF53x Processor. Table 2

describes the inputs to the CEC, identifies their names in the

Event Vector Table (EVT), and lists their priorities.

System Interrupt Controller (SIC)

The System Interrupt Controller provides the mapping and

routing of events from the many peripheral interrupt sources to

the prioritized general-purpose interrupt inputs of the CEC.

Although the ADSP-BF53x Processor provides a default

mapping, the user can alter the mappings and priorities of

interrupt events by writing the appropriate values into the

Interrupt Assignment Registers (IAR). Table 3 describes the

inputs into the SIC and the default mappings into the CEC.

Event Control

The ADSP-BF53x Processor provides the user with a very

flexible mechanism to control the processing of events. In the

CEC, three registers are used to coordinate and control events.

Each register is 16 bits wide:

•CEC Interrupt Latch Register (ILAT) – The ILAT

appropriate bit is set when the processor has latched the

event and cleared when the event has been accepted into

the system. This register is updated automatically by the

controller, but it may be written only when its correspond-

ing IMASK bit is cleared.

•CEC Interrupt Mask Register (IMASK) – The IMASK

events. When a bit is set in the IMASK register, that event

is unmasked and will be processed by the CEC when

asserted. A cleared bit in the IMASK register masks the

event, preventing the processor from servicing the event

even though the event may be latched in the ILAT register.

This register may be read or written while in supervisor

mode. (Note that general-purpose interrupts can be

globally enabled and disabled with the STI and CLI

instructions, respectively.)

•CEC Interrupt Pending Register (IPEND) – The IPEND

IPEND register indicates the event is currently active or

nested at some level. This register is updated automati-

cally by the controller but may be read while in supervisor

mode.

Table 2. Core Event Controller (CEC)

Priority

(0 is Highest) Event Class EVT Entry

0 Emulation/Test

Control

EMU

1 Reset RST

2 Non-Maskable

Interrupt

NMI

3 Exception EVX

4 Reserved -

5Hardware ErrorIVHW

6Core TimerIVTMR

7 General Interrupt 7 IVG7

8 General Interrupt 8 IVG8

9 General Interrupt 9 IVG9

10 General Interrupt 10 IVG10

11 General Interrupt 11 IVG11

12 General Interrupt 12 IVG12

13 General Interrupt 13 IVG13

14 General Interrupt 14 IVG14

15 General Interrupt 15 IVG15

Table 3. System Interrupt Controller (SIC)

Peripheral Interrupt Event Default Mapping

PLL Wakeup IVG7

DMA Error IVG7

PPI Error IVG7

SPORT 0 Error IVG7

SPORT 1 Error IVG7

SPI Error IVG7

UART Error IVG7

Real-Time Clock IVG8

DMA Channel 0 (PPI) IVG8

DMA Channel 1 (SPORT 0 RX) IVG9

DMA Channel 2 (SPORT 0 TX) IVG9

DMA Channel 3 (SPORT 1 RX) IVG9

DMA Channel 4 (SPORT 1 TX) IVG9

DMA Channel 5 (SPI) IVG10

DMA Channel 6 (UART RX) IVG10

DMA Channel 7 (UART TX) IVG10

Timer 0 IVG11

Timer 1 IVG11

Timer 2 IVG11

PF Interrupt A IVG12

PF Interrupt B IVG12

DMA Channels 8 and 9

(Memory DMA Stream 1)

IVG13

DMA Channels 10 and 11

(Memory DMA Stream 0)

IVG13

Software Watchdog Timer IVG13

Table 3. System Interrupt Controller (SIC) (Continued)

Peripheral Interrupt Event Default Mapping

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PRELIMINARY TECHNICAL DATA

The SIC allows further control of event processing by providing

three 32-bit interrupt control and status registers. Each register

contains a bit corresponding to each of the peripheral interrupt

events shown in Table 3 on Page 6.

•SIC Interrupt Mask Register (SIC_IMASK)– This

peripheral interrupt event. When a bit is set in the register,

that peripheral event is unmasked and will be processed

by the system when asserted. A cleared bit in the register

masks the peripheral event, preventing the processor from

servicing the event.

•SIC Interrupt Status Register (SIC_ISR) – As multiple

peripherals can be mapped to a single event, this register

allows the software to determine which peripheral event

source triggered the interrupt. A set bit indicates the

peripheral is asserting the interrupt, and a cleared bit

indicates the peripheral is not asserting the event.

•SIC Interrupt Wakeup Enable Register (SIC_IWR) – By

enabling the corresponding bit in this register, a periph-

eral can be configured to wake up the processor, should

the core be idled when the event is generated. (see

Dynamic Power Management on Page 10.)

Because multiple interrupt sources can map to a single general-

purpose interrupt, multiple pulse assertions can occur simulta-

neously, before or during interrupt processing for an interrupt

event already detected on this interrupt input. The IPEND

acknowledgement.

The appropriate ILAT register bit is set when an interrupt rising

edge is detected (detection requires two core clock cycles). The

bit is cleared when the respective IPEND register bit is set. The

IPEND bit indicates that the event has entered into the processor

pipeline. At this point the CEC will recognize and queue the next

rising edge event on the corresponding event input. The

minimum latency from the rising edge transition of the general-

purpose interrupt to the IPEND output asserted is three core

clock cycles; however, the latency can be much higher, depending

on the activity within and the state of the processor.

DMA Controllers

The ADSP-BF53x Processor has multiple, independent DMA

controllers that support automated data transfers with minimal

overhead for the processor core. DMA transfers can occur

between the ADSP-BF53x Processor's internal memories and

any of its DMA-capable peripherals. Additionally, DMA

transfers can be accomplished between any of the DMA-capable

peripherals and external devices connected to the external

memory interfaces, including the SDRAM controller and the

asynchronous memory controller. DMA-capable peripherals

include the SPORTs, SPI port, UART, and PPI. Each individual

DMA-capable peripheral has at least one dedicated DMA

channel.

The ADSP-BF53x Processor DMA controller supports both 1-

dimensional (1D) and 2-dimensional (2D) DMA transfers.

DMA transfer initialization can be implemented from registers

or from sets of parameters called descriptor blocks.

The 2D DMA capability supports arbitrary row and column sizes

up to 64K elements by 64K elements, and arbitrary row and

column step sizes up to +/- 32K elements. Furthermore, the

column step size can be less than the row step size, allowing

implementation of interleaved data streams. This feature is espe-

cially useful in video applications where data can be de-

interleaved on the fly.

Examples of DMA types supported by the ADSP-BF53x

Processor DMA controller include:

•A single, linear buffer that stops upon completion

•A circular, auto-refreshing buffer that interrupts on each

full or fractionally full buffer

•1-D or 2-D DMA using a linked list of descriptors

•2-D DMA using an array of descriptors, specifying only

the base DMA address within a common page

In addition to the dedicated peripheral DMA channels, there are

two memory DMA channels provided for transfers between the

various memories of the ADSP-BF53x Processor system. This

enables transfers of blocks of data between any of the memories—

including external SDRAM, ROM, SRAM, and flash memory—

with minimal processor intervention. Memory DMA transfers

can be controlled by a very flexible descriptor-based methodology

or by a standard register-based autobuffer mechanism.

Real-Time Clock

The ADSP-BF53x Processor Real-Time Clock (RTC) provides

a robust set of digital watch features, including current time,

stopwatch, and alarm. The RTC is clocked by a 32.768 KHz

crystal external to the ADSP-BF53x Processor. The RTC

peripheral has dedicated power supply pins so that it can remain

powered up and clocked even when the rest of the processor is in

a low-power state. The RTC provides several programmable

interrupt options, including interrupt per second, minute, hour,

or day clock ticks, interrupt on programmable stopwatch count-

down, or interrupt at a programmed alarm time.

The 32.768 KHz input clock frequency is divided down to a 1 Hz

signal by a prescaler. The counter function of the timer consists

of four counters: a 60-second counter, a 60-minute counter, a

24-hour counter, and an 32,768-day counter.

When enabled, the alarm function generates an interrupt when

the output of the timer matches the programmed value in the

alarm control register. There are two alarms: The first alarm is

for a time of day. The second alarm is for a day and time of that

day.

The stopwatch function counts down from a programmed value,

with one-second resolution. When the stopwatch is enabled and

the counter underflows, an interrupt is generated.

For current information contact Analog Devices at 800/262-5643

ADSP-BF53x March 2003

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

8REV. PrA

PRELIMINARY TECHNICAL DATA

Like the other peripherals, the RTC can wake up the ADSP-

BF53x Processor from a low-power state upon generation of any

RTC wakeup event.

Connect RTC pins RTXI and RTXO with external components

as shown in Figure 5.

Watchdog Timer

The ADSP-BF53x Processor includes a 32-bit timer that can be

used to implement a software watchdog function. A software

watchdog can improve system availability by forcing the

processor to a known state through generation of a hardware

reset, non-maskable interrupt (NMI), or general-purpose inter-

rupt, if the timer expires before being reset by software. The

programmer initializes the count value of the timer, enables the

appropriate interrupt, then enables the timer. Thereafter, the

software must reload the counter before it counts to zero from

the programmed value. This protects the system from remaining

in an unknown state where software, which would normally reset

the timer, has stopped running due to an external noise condition

or software error.

If configured to generate a hardware reset, the watchdog timer

resets both the core and the ADSP-BF53x Processor peripherals.

After a reset, software can determine if the watchdog was the

source of the hardware reset by interrogating a status bit in the

watchdog timer control register.

The timer is clocked by the system clock (SCLK), at a maximum

frequency of f

SCLK

Timers

There are four general-purpose programmable timer units in the

ADSP-BF53x Processor. Three timers have an external pin that

can be configured either as a Pulse Width Modulator (PWM) or

timer output, as an input to clock the timer, or as a mechanism

for measuring pulse widths and periods of external events. These

timers can be synchronized to an external clock input to the PF1

pin, an external clock input to the PPI_CLK pin, or to the internal

SCLK.

The timer units can be used in conjunction with the UART to

measure the width of the pulses in the data stream to provide an

auto-baud detect function for a serial channel.

The timers can generate interrupts to the processor core

providing periodic events for synchronization, either to the

system clock or to a count of external signals.

In addition to the three general-purpose programmable timers,

a fourth timer is also provided. This extra timer is clocked by the

internal processor clock and is typically used as a system tick clock

for generation of operating system periodic interrupts.

Serial Ports (SPORTs)

The ADSP-BF53x Processor incorporates two dual-channel syn-

chronous serial ports (SPORT0 and SPORT1) for serial and

multiprocessor communications. The SPORTs support the

following features:

•I

S capable operation.

•Bidirectional operation – Each SPORT has two sets of

independent transmit and receive pins, enabling eight

channels of I

S stereo audio.

•Buffered (8-deep) transmit and receive ports – Each port

has a data register for transferring data words to and from

other processor components and shift registers for shifting

data in and out of the data registers.

•Clocking – Each transmit and receive port can either use

an external serial clock or generate its own, in frequencies

ranging from (f

SCLK

/131,070) Hz to (f

SCLK

/2) Hz.

•Word length – Each SPORT supports serial data words

from 3 to 32 bits in length, transferred most-significant-

bit first or least-significant-bit first.

•Framing – Each transmit and receive port can run with

or without frame sync signals for each data word. Frame

sync signals can be generated internally or externally,

active high or low, and with either of two pulsewidths and

early or late frame sync.

•Companding in hardware – Each SPORT can perform

A-law or µ-law companding according to ITU recommen-

dation G.711. Companding can be selected on the

transmit and/or receive channel of the SPORT without

additional latencies.

•DMA operations with single-cycle overhead – Each

SPORT can automatically receive and transmit multiple

buffers of memory data. The processor can link or chain

sequences of DMA transfers between a SPORT and

memory.

•Interrupts – Each transmit and receive port generates an

interrupt upon completing the transfer of a data word or

after transferring an entire data buffer or buffers through

DMA.

•Multichannel capability – Each SPORT supports 128

channels out of a 1024-channel window and is compatible

with the H.100, H.110, MVIP-90, and HMVIP

standards.

Figure 5. External Components for RTC

RTXO

C1 C2

SUGGESTED COMPONENTS:

ECLIPTEK EC38J (THROUGH-HOLE PACKAGE)

EPSON MC405 12 pF LOAD (SURFACE MOUNT PACKAGE)

C1 = 22 pF

C2 = 22 pF

R1 = 10MV

NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.

CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2

SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 pF.

RTXI

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

9REV. PrA

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PRELIMINARY TECHNICAL DATA

Serial Peripheral Interface (SPI) Port

The ADSP-BF53x Processor has an SPI-compatible port that

enables the processor to communicate with multiple SPI-com-

patible devices.

The SPI interface uses three pins for transferring data: two data

pins (Master Output-Slave Input, MOSI, and Master Input-

Slave Output, MISO) and a clock pin (Serial Clock, SCK). An

SPI chip select input pin (

SPISS

) lets other SPI devices select the

processor, and seven SPI chip select output pins (

SPISEL7–1

)

let the processor select other SPI devices. The SPI select pins are

reconfigured Programmable Flag pins. Using these pins, the SPI

port provides a full-duplex, synchronous serial interface, which

supports both master/slave modes and multimaster

environments.

The SPI port’s baud rate and clock phase/polarities are program-

mable (see Figure 6), and it has an integrated DMA controller,

configurable to support transmit or receive data streams. The

SPI’s DMA controller can only service unidirectional accesses at

any given time.

During transfers, the SPI port simultaneously transmits and

receives by serially shifting data in and out on its two serial data

lines. The serial clock line synchronizes the shifting and sampling

of data on the two serial data lines.

UART Port

The ADSP-BF53x Processor provides a full-duplex Universal

Asynchronous Receiver/Transmitter (UART) port, which is fully

compatible with PC-standard UARTs. The UART port provides

a simplified UART interface to other peripherals or hosts, sup-

porting full-duplex, DMA-supported, asynchronous transfers of

serial data. The UART port includes support for 5 to 8 data bits,

1 or 2 stop bits, and none, even, or odd parity. The UART port

supports two modes of operation:

•PIO (Programmed I/O) – The processor sends or receives

data by writing or reading I/O-mapped UART registers.

The data is double-buffered on both transmit and receive.

•DMA (Direct Memory Access) – The DMA controller

transfers both transmit and receive data. This reduces the

number and frequency of interrupts required to transfer

data to and from memory. The UART has two dedicated

DMA channels, one for transmit and one for receive.

These DMA channels have lower default priority than

most DMA channels because of their relatively low service

rates.

The UART port's baud rate (see Figure 7), serial data format,

error code generation and status, and interrupts are

programmable:

•Supporting bit rates ranging from (f

SCLK

/ 1,048,576) to

SCLK

/16) bits per second.

•Supporting data formats from 7 to12 bits per frame.

•Both transmit and receive operations can be configured

to generate maskable interrupts to the processor.

In conjunction with the general-purpose timer functions,

autobaud detection is supported.

The capabilities of the UART are further extended with support

for the Infrared Data Association (IrDA®) Serial Infrared

Physical Layer Link Specification (SIR) protocol.

Programmable Flags (PFx)

The ADSP-BF53x Processor has 16 bi-directional, general-

purpose Programmable Flag (PF15–0) pins. Each programma-

ble flag can be individually controlled by manipulation of the flag

control, status and interrupt registers:

•Flag Direction Control Register – Specifies the direction

of each individual PFx pin as input or output.

•Flag Control and Status Registers – The ADSP-BF53x

Processor employs a “write one to modify” mechanism

that allows any combination of individual flags to be

modified in a single instruction, without affecting the level

of any other flags. Four control registers are provided.

One register is written in order to set flag values, one

is written in order to toggle flag values, and one register

is written in order to specify a flag value. Reading the flag

status register allows software to interrogate the sense of

the flags.

•Flag Interrupt Mask Registers – The two Flag Interrupt

Mask Registers allow each individual PFx pin to function

as an interrupt to the processor. Similar to the two Flag

Control Registers that are used to set and clear individual

flag values, one Flag Interrupt Mask Register sets bits to

enable interrupt function, and the other Flag Interrupt

Mask register clears bits to disable interrupt function.

Figure 6. SPI Clock Rate Calculation

SPI Clock Rate f

SCLK

2SPIBAUD×

--------------------------------------

where SPIBAUD = 2 to 65,535

Figure 7. UART Clock Rate Calculation

UART Clock Rate f

SCLK

16 D×

----------------

where D = 1 to 65,536

For current information contact Analog Devices at 800/262-5643

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out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

10 REV. PrA

PRELIMINARY TECHNICAL DATA

PFx pins defined as inputs can be configured to generate

hardware interrupts, while output PFx pins can be

triggered by software interrupts.

•Flag Interrupt Sensitivity Registers – The two Flag

Interrupt Sensitivity Registers specify whether individual

PFx pins are level- or edge-sensitive and specify—if edge-

sensitive—whether just the rising edge or both the rising

and falling edges of the signal are significant. One register

selects the type of sensitivity, and one register selects

which edges are significant for edge-sensitivity.

Parallel Peripheral Interface

The ADSP-BF53x Processor provides a Parallel Peripheral

Interface (PPI) that can connect directly to parallel A/D and D/A

converters, video encoders and decoders, and other general

purpose peripherals. The PPI consists of a dedicated input clock

pin, up to 3 frame synchronization pins, and up to 16 data pins.

The input clock supports parallel data rates up to f

SCLK

/2 MHz,

and the synchronization signals can be configured as either inputs

or outputs.

The PPI supports a variety of general purpose and ITU-R 656

modes of operation. In general purpose mode, the PPI provides

half-duplex, bi-directional data transfer with up to 16 bits of data.

Up to 3 frame synchronization signals are also provided. In ITU-

R 656 mode, the PPI provides half-duplex, bi-directional transfer

of 8- or 10-bit video data. Additionally, on-chip decode of

embedded start-of-line (SOL) and start-of-field (SOF) preamble

packets is supported.

General Purpose Mode Descriptions

The GP modes of the PPI are intended to suit a wide variety of

data capture and transmission applications. Three distinct sub-

modes are supported:

•Input Mode - Frame Syncs and data are inputs into the

PPI.

•Frame Capture Mode - Frame Syncs are outputs from the

PPI, but data are inputs.

•Output Mode - Frame Syncs and data are outputs from

the PPI.

Input Mode

This mode is intended for ADC applications, as well as video

communication with hardware signaling. In its simplest form,

PPI_FS1 is an external frame sync input that controls when to

read data. The PPI_DELAY MMR allows for a delay (in

PPI_CLK cycles) between reception of this frame sync and the

initiation of data reads. The number of input data samples is user-

programmable and defined by the contents of the PPI_Count

supported, as programmed by the PPI_CONTROL register.

Frame Capture Mode

This mode allows the video source(s) to act as a slave (e.g., for

frame capture). The ADSP-BF53x Processor controls when to

read from the video source(s). PPI_FS1 is an HSYNC output

and PPI_FS2 is a VSYNC output.

Output Mode

This mode is used for transmitting video or other data with up to

three output frame syncs. Typically, a single frame sync is appro-

priate for data converter applications, whereas two or three frame

syncs could be used for sending video with hardware signaling.

ITU -R 656 Mode Descriptions

The ITU-R 656 modes of the PPI are intended to suit a wide

variety of video capture, processing, and transmission applica-

tions. Three distinct sub-modes are supported:

•Active Video Only Mode

•Vertical Blanking Only Mode

•Entire Field Mode

Active Video Only Mode

This mode is used when only the active video portion of a field

is of interest and not any of the blanking intervals. The PPI will

not read in any data between the End of Active Video (EAV) and

Start of Active Video (SAV) preamble symbols, or any data

present during the vertical blanking intervals. In this mode, the

control byte sequences are not stored to memory; they are filtered

by the PPI. After synchronizing to the start of Field 1, the PPI

will ignore incoming samples until it sees an SAV code. The user

specifies the number of active video lines per frame (in

PPI_Count register).

Vertical Blanking Interval Mode

In this mode, the PPI only transfers vertical blanking interval

(VBI) data.

Entire Field Mode

In this mode, the entire incoming bit stream is read in through

the PPI. This includes active video, control preamble sequences,

and ancillary data that may be embedded in horizontal and

vertical blanking intervals. Data transfer starts immediately after

synchronization to Field 1.

Dynamic Power Management

The ADSP-BF53x Processor provides four operating modes,

each with a different performance/power profile. In addition,

Dynamic Power Management provides the control functions to

dynamically alter the processor core supply voltage, further

reducing power dissipation. Control of clocking to each of the

ADSP-BF53x Processor peripherals also reduces power con-

sumption. See Table 4 for a summary of the power settings for

each mode.

Full-On Operating Mode – Maximum Performance

In the Full-On mode, the PLL is enabled and is not bypassed,

providing capability for maximum operational frequency. This is

the power-up default execution state in which maximum perfor-

mance can be achieved. The processor core and all enabled

peripherals run at full speed.

Active Operating Mode – Moderate Power Savings

In the Active mode, the PLL is enabled but bypassed. Because

the PLL is bypassed, the processor’s core clock (CCLK) and

system clock (SCLK) run at the input clock (CLKIN) frequency.

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11REV. PrA

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PRELIMINARY TECHNICAL DATA

In this mode, the CLKIN to CCLK multiplier ratio can be

changed, although the changes are not realized until the Full-On

mode is entered. DMA access is available to appropriately con-

figured L1 memories.

In the Active mode, it is possible to disable the PLL through the

PLL Control register (PLL_CTL). If disabled, the PLL must be

re-enabled before transitioning to the Full-On or Sleep modes.

Sleep Operating Mode – High Power Savings

The Sleep mode reduces power dissipation by disabling the clock

to the processor core (CCLK). The PLL and system clock

(SCLK), however, continue to operate in this mode. Typically an

external event or RTC activity will wake up the processor. When

in the Sleep mode, assertion of wakeup will cause the processor

to sense the value of the BYPASS bit in the PLL Control register

(PLL_CTL). If BYPASS is disabled, the processor will transition

to the Full On mode. If BYPASS is enabled, the processor will

transition to the Active mode.

When in the Sleep mode, system DMA access to L1 memory is

not supported.

Deep Sleep Operating Mode – Maximum Power Savings

The Deep Sleep mode maximizes power savings by disabling the

clocks to the processor core (CCLK) and to all synchronous

peripherals (SCLK). Asynchronous peripherals, such as the

RTC, may still be running but will not be able to access internal

resources or external memory. This powered-down mode can

only be exited by assertion of the reset interrupt (

RESET

) or by

an asynchronous interrupt generated by the RTC. When in Deep

Sleep mode, assertion of

RESET

or the RTC asynchronous

interrupt causes the processor to transition to the Full On mode.

Power Savings

As shown in Table 5, the ADSP-BF53x Processor supports three

different power domains. The use of multiple power domains

maximizes flexibility, while maintaining compliance with

industry standards and conventions. By isolating the internal

logic of the ADSP-BF53x Processor into its own power domain,

separate from the RTC and other I/O, the processor can take

advantage of Dynamic Power Management, without affecting the

RTC or other I/O devices.

The power dissipated by a processor is largely a function of the

clock frequency of the processor and the square of the operating

voltage. For example, reducing the clock frequency by 25%

results in a 25% reduction in power dissipation, while reducing

the voltage by 25% reduces power dissipation by more than 40%.

Further, these power savings are additive, in that if the clock

frequency and supply voltage are both reduced, the power savings

can be dramatic.

The Dynamic Power Management feature of the ADSP-BF53x

Processor allows both the processor’s input voltage (V

DDINT

) and

clock frequency (f

CCLK

) to be dynamically controlled.

As explained above, the savings in power dissipation can be

modeled by the following equations:

where the variables in the equations are:

•f

CCLKNOM

is the nominal core clock frequency

•f

CCLKRED

is the reduced core clock frequency

•V

DDINTNOM

is the nominal internal supply voltage

•V

DDINTRED

is the reduced internal supply voltage

•T

NOM

is the duration running at f

CCLKNOM

•T

RED

is the duration running at f

CCLKRED

Voltage Regulation

The ADSP-BF53x Processor provides an on-chip voltage

regulator that can generate processor core voltage levels (0.7V to

1.2V) from an external 2.25 V to 3.6 V supply. Figure 8 shows

the typical external components required to complete the power

management system. The regulator controls the internal logic

voltage levels and is programmable with the Voltage Regulator

Control Register (VR_CTL) in increments of 50 mV. The

regulator can also be disabled and bypassed at the user’s

discretion.

Table 4. Power Settings

Mode

PLL

Bypassed

Core

Clock

(CCLK)

System

Clock

(SCLK)

Full On Enabled No Enabled Enabled

Active Enabled/Disabled Yes Enabled Enabled

Sleep Enabled – Disabled Enabled

Deep Sleep Disabled – Disabled Disabled

Table 5. Power Domains

Power Domain VDD Range

All internal logic, except RTC V

DDINT

RTC internal logic and crystal I/O V

DDRTC

All other I/O V

DDEXT

Power Savings Factor

CCLKRED

CCLKNOM

-----------------------------V

DDINTRED

DDINTNOM

-----------------------------------





×T

RED

NOM

-----------------





×



% Power Savings 1 Power Savings Factor–()100%×=

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12 REV. PrA

PRELIMINARY TECHNICAL DATA

Clock Signals

The ADSP-BF53x Processor can be clocked by an external

crystal, a sine wave input, or a buffered, shaped clock derived

from an external clock oscillator.

If an external clock is used, it should be a TTL compatible signal

and must not be halted, changed, or operated below the specified

frequency during normal operation. This signal is connected to

the processor’s CLKIN pin. When an external clock is used, the

XTAL pin must be left unconnected.

Alternatively, because the ADSP-BF53x Processor includes an

on-chip oscillator circuit, an external crystal may be used. The

crystal should be connected across the CLKIN and XTAL pins,

with two capacitors connected as shown in Figure 9. Capacitor

values are dependent on crystal type and should be specified by

the crystal manufacturer. A parallel-

resonant, fundamental frequency, microprocessor-grade crystal

should be used.

As shown in Figure 10 on page 12, the core clock (CCLK) and

system peripheral clock (SCLK) are derived from the input clock

(CLKIN) signal. An on-chip PLL is capable of multiplying the

CLKIN signal by a user programmable 1x to 63x multiplication

factor (bounded by specified minimum and maximum VCO fre-

quencies). The default multiplier is 10x, but it can be modified

by a software instruction sequence. On-the-fly frequency changes

can be effected by simply writing to the PLL_DIV register.

All on-chip peripherals are clocked by the system clock (SCLK).

The system clock frequency is programmable by means of the

SSEL3–0 bits of the PLL_DIV register. The values programmed

into the SSEL fields define a divide ratio between the PLL output

(VCO) and the system clock. SCLK divider values are 1 through

15. Table 6 illustrates typical system clock ratios:

The maximum frequency of the system clock is f

SCLK

. Note that

the divisor ratio must be chosen to limit the system clock

frequency to its maximum of f

SCLK

. The SSEL value can be

changed dynamically without any PLL lock latencies by writing

the appropriate values to the PLL divisor register (PLL_DIV).

The core clock (CCLK) frequency can also be dynamically

changed by means of the CSEL1–0 bits of the PLL_DIV register.

Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in

Table 7. This programmable core clock capability is useful for

fast core frequency modifications.

Figure 8. Voltage Regulator Circuit

Figure 9. External Crystal Connections

DDEXT

DDINT

OUT

1-0

EXTERNAL COMPONENTS

2.25V - 3.6V

INPUT VOLTAGE

RANGE

NDS8434

ZHCS1000

100 µF 1µF

10 µH

0.1 µF

NOTE: VR

OUT

1-0 SHOULD BE TIED TOGETHER EXTERNALLY

CLKIN CLKOUTXTAL

DSP

Figure 10. Frequency Modification Methods

Table 6. Example System Clock Ratios

Signal

Name

SSEL3–0

Divider

Ratio

VCO/SCLK

Example Frequency

Ratios (MHz)

VCO SCLK

0001 1:1 100 100

0110 6:1 300 50

1010 10:1 500 50

Table 7. Core Clock Ratios

Signal

Name

CSEL1–0

Divider

Ratio

VCO/CCLK

Example Frequency

Ratios

VCO CCLK

00 1:1 300 300

01 2:1 300 150

10 4:1 500 125

11 8:1 200 25

PLL

1×-63×

÷1:15

÷1, 2, 4, 8

VCO

SCLK ≤CCLK

SCLK ≤133 MHZ

CLKIN

DYNAMIC MODIFICATION

REQUIRES PLL SEQUENCING DYNAMIC MODIFICATION

ON-THE-FLY

CCLK

SCLK

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13REV. PrA

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PRELIMINARY TECHNICAL DATA

Booting Modes

The ADSP-BF53x Processor has three mechanisms (listed in

Table 8) for automatically loading internal L1 instruction

memory after a reset. A fourth mode is provided to execute from

external memory, bypassing the boot sequence.

The BMODE pins of the Reset Configuration Register, sampled

during power-on resets and software-initiated resets, implement

the following modes:

•Execute from 16-bit external memory – Execution

starts from address 0x2000 0000 with 16-bit packing.

The boot ROM is bypassed in this mode. All configu-

ration settings are set for the slowest device possible

(3-cycle hold time; 15-cycle R/W access times; 4-cycle

setup).

•Boot from 8-bit external FLASH memory – The 8-bit

FLASH boot routine located in boot ROM memory

space is set up using Asynchronous Memory Bank 0.

All configuration settings are set for the slowest device

possible (3-cycle hold time; 15-cycle R/W access times;

4-cycle setup).

•Boot from SPI serial EEPROM (8-bit addressable) –

The SPI uses the PF2 output pin to select a single SPI

EPROM device, submits a read command at address

0x00, and begins clocking data into the beginning of L1

instruction memory. An 8-bit addressable SPI-compat-

ible EPROM must be used.

•Boot from SPI serial EEPROM (16-bit addressable) –

The SPI uses the PF2 output pin to select a single SPI

EPROM device, submits a read command at address

0x0000, and begins clocking data into the beginning of

L1 instruction memory. A 16-bit addressable SPI-com-

patible EPROM must be used.

For each of the boot modes, an 10-byte header is first read from

an external memory device. The header specifies the number of

bytes to be transferred and the memory destination address.

Multiple memory blocks may be loaded by any boot sequence.

Once all blocks are loaded, program execution commences from

the start of L1 instruction SRAM.

In addition, bit 4 of the Reset Configuration Register can be set

by application code to bypass the normal boot sequence during

a software reset. For this case, the processor jumps directly to the

beginning of L1 instruction memory.

To augment the boot modes, a secondary software loader is

provided that adds additional booting mechanisms. This

secondary loader provides the capability to boot from 16-bit

FLASH memory, fast FLASH, variable baud rate, and other

sources.

Instruction Set Description

The Blackfin processor family assembly language instruction set

employs an algebraic syntax designed for ease of coding and read-

ability. The instructions have been specifically tuned to provide

a flexible, densely encoded instruction set that compiles to a very

small final memory size. The instruction set also provides fully

featured multifunction instructions that allow the programmer

to use many of the processor core resources in a single instruction.

Coupled with many features more often seen on microcontrol-

lers, this instruction set is very efficient when compiling C and

C++ source code. In addition, the architecture supports both

user (algorithm/application code) and supervisor (O/S kernel,

device drivers, debuggers, ISRs) modes of operation, allowing

multiple levels of access to core processor resources.

The assembly language, which takes advantage of the processor’s

unique architecture, offers the following advantages:

•Seamlessly integrated DSP/CPU features are optimized

for both 8-bit and 16-bit operations.

•A multi-issue load/store modified-Harvard architecture,

which supports two 16-bit MAC or four 8-bit ALU + two

load/store + two pointer updates per cycle.

•All registers, I/O, and memory are mapped into a unified

4G byte memory space, providing a simplified program-

ming model.

•Microcontroller features, such as arbitrary bit and bit-

field manipulation, insertion, and extraction; integer

operations on 8-, 16-, and 32-bit data-types; and separate

user and supervisor stack pointers.

•Code density enhancements, which include intermixing

of 16- and 32-bit instructions (no mode switching, no

code segregation). Frequently used instructions are

encoded in 16 bits.

Development Tools

The ADSP-BF53x Processor is supported with a complete set of

CROSSCORE™ software and hardware development tools,

including Analog Devices emulators and VisualDSP++™ devel-

opment environment. The same emulator hardware that

supports other Blackfin DSPs also fully emulates the ADSP-

BF53x Processor.

The VisualDSP++ project management environment lets pro-

grammers develop and debug an application. This environment

includes an easy to use assembler (which is based on an algebraic

syntax), an archiver (librarian/library builder), a linker, a loader,

a cycle-accurate instruction-level simulator, a C/C++ compiler,

and a C/C++ runtime library that includes DSP and mathemat-

ical functions. A key point for these tools is C/C++ code

efficiency. The compiler has been developed for efficient transla-

Table 8. Booting Modes

BMODE1–0 Description

00 Execute from 16-bit external memory

(Bypass Boot ROM)

01 Boot from 8-bit flash

10 Boot from SPI serial ROM (8-bit

address range)

11 Boot from SPI serial ROM (16-bit

address range)

For current information contact Analog Devices at 800/262-5643

ADSP-BF53x March 2003

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

14 REV. PrA

PRELIMINARY TECHNICAL DATA

tion of C/C++ code to processor assembly. The processor has

architectural features that improve the efficiency of compiled

C/C++ code.

The VisualDSP++ debugger has a number of important features.

Data visualization is enhanced by a plotting package that offers

a significant level of flexibility. This graphical representation of

user data enables the programmer to quickly determine the per-

formance of an algorithm. As algorithms grow in complexity, this

capability can have increasing significance on the designer’s

development schedule, increasing productivity. Statistical

profiling enables the programmer to non intrusively poll the

processor as it is running the program. This feature, unique to

VisualDSP++, enables the software developer to passively gather

important code execution metrics without interrupting the real-

time characteristics of the program. Essentially, the developer can

identify bottlenecks in software quickly and efficiently. By using

the profiler, the programmer can focus on those areas in the

program that impact performance and take corrective action.

Debugging both C/C++ and assembly programs with the

VisualDSP++ debugger, programmers can:

•View mixed C/C++ and assembly code (interleaved

source and object information).

•Insert breakpoints.

•Set conditional breakpoints on registers, memory,

and stacks.

•Trace instruction execution.

•Perform linear or statistical profiling of program

execution.

•Fill, dump, and graphically plot the contents of memory.

•Perform source level debugging.

•Create custom debugger windows.

The VisualDSP++ IDDE lets programmers define and manage

software development. Its dialog boxes and property pages let

programmers configure and manage all of the Blackfin develop-

ment tools, including the color syntax highlighting in the

VisualDSP++ editor. This capability permits programmers to:

•Control how the development tools process inputs and

generate outputs.

•Maintain a one-to-one correspondence with the tool’s

command line switches.

The VisualDSP++ Kernel (VDK) incorporates scheduling and

resource management tailored specifically to address the memory

and timing constraints of DSP programming. These capabilities

enable engineers to develop code more effectively, eliminating the

need to start from the very beginning, when developing new

application code. The VDK features include Threads, Critical

and Unscheduled regions, Semaphores, Events, and Device flags.

The VDK also supports Priority-based, Preemptive, Coopera-

tive, and Time-Sliced scheduling approaches. In addition, the

VDK was designed to be scalable. If the application does not use

a specific feature, the support code for that feature is excluded

from the target system.

Because the VDK is a library, a developer can decide whether to

use it or not. The VDK is integrated into the VisualDSP++ devel-

opment environment, but can also be used via standard

command line tools. When the VDK is used, the development

environment assists the developer with many error-prone tasks

and assists in managing system resources, automating the gener-

ation of various VDK based objects, and visualizing the system

state, when debugging an application that uses the VDK.

VCSE is Analog Devices technology for creating, using, and

reusing software components (independent modules of substan-

tial functionality) to quickly and reliably assemble software

applications. Download components from the Web and drop

them into the application. Publish component archives from

within VisualDSP++. VCSE supports component implementa-

tion in C/C++ or assembly language.

Use the Expert Linker to visually manipulate the placement of

code and data on the embedded system. View memory utilization

in a color-coded graphical form, easily move code and data to

different areas of the processor or external memory with the drag

of the mouse, examine run time stack and heap usage. The Expert

Linker is fully compatible with existing Linker Definition File

(LDF), allowing the developer to move between the graphical

and textual environments.

Analog Devices emulators use the IEEE 1149.1 JTAG Test

Access Port of the ADSP-BF53x Processor processor to monitor

and control the target board processor during emulation. The

emulator provides full speed emulation, allowing inspection and

modification of memory, registers, and processor stacks. Non

intrusive in-circuit emulation is assured by the use of the proces-

sor’s JTAG interface—the emulator does not affect target system

loading or timing.

In addition to the software and hardware development tools

available from Analog Devices, third parties provide a wide range

of tools supporting the Blackfin processor family. Hardware tools

include Blackfin processor PC plug-in cards. Third party

software tools include DSP libraries, real-time operating systems,

and block diagram design tools.

Designing an Emulator-Compatible Processor

Board (Target)

The Analog Devices family of emulators are tools that every

system developer needs to test and debug hardware and software

systems. Analog Devices has supplied an IEEE 1149.1 JTAG Test

Access Port (TAP) on each JTAG processor. The emulator uses

the TAP to access the internal features of the processor, allowing

the developer to load code, set breakpoints, observe variables,

observe memory, and examine registers. The processor must be

halted to send data and commands, but once an operation has

been completed by the emulator, the processor system is set

running at full speed with no impact on system timing.

To use these emulators, the target board must include a header

that connects the processor’s JTAG port to the emulator.

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

15REV. PrA

For current information contact Analog Devices at 800/262-5643

ADSP-BF53xMarch 2003

PRELIMINARY TECHNICAL DATA

For details on target board design issues including mechanical

layout, single processor connections, multiprocessor scan chains,

signal buffering, signal termination, and emulator pod logic, see

the

EE-68: Analog Devices

TAG Emulation Technical Reference

the Analog Devices web site (www.analog.com)—use site search

on “EE-68.” This document is updated regularly to keep pace

with improvements to emulator support.

PIN DESCRIPTIONS

ADSP-BF53x Processor pin definitions are listed in Table 9.

In order to maintain maximum functionality and reduce package

size and pin count, some pins have dual, multiplexed functional-

ity. In cases where pin functionality is reconfigurable, the default

state is shown in plain text, while alternate functionality is shown

in italics.

Table 9. Pin Descriptions

Pin Name I/O Function

Memory Interface

ADDR19–1 O Address Bus for Async/Sync Access

DATA15–0 I/O Data Bus for Async/Sync Access

ABE1–0/SDQM1–0 O Byte Enables/Data Masks for Async/Sync Access

IBus Request

BG OBus Grant

BGH O Bus Grant Hang

Asynchronous Memory Control

AMS3–0 O Bank Select

ARDY

I Hardware Ready Control

AOE OOutput Enable

ARE ORead Enable

AWE OWrite Enable

Synchronous Memory Control

SRAS ORow Address Strobe

SCAS O Column Address Strobe

SWE OWrite Enable

SCKE O Clock Enable

CLKOUT O Clock Output

SA10 O A10 Pin

SMS O Bank Select

Timers

TMR0 I/O Timer 0

TMR1/PPI_FS1 I/O Timer 1/PPI Frame Sync1

TMR2/PPI_FS2 I/O Timer 2/PPI Frame Sync2

Parallel Peripheral Interface Port/GPIO

PF0/SPISS I/O Programmable Flag 0/SPI Slave Select Input

PF1/SPISEL1/TMRCLK I/O Programmable Flag 1/SPI Slave Select Enable 1/External Timer Reference

PF2/SPISEL2 I/O Programmable Flag 2/SPI Slave Select Enable 2

PF3/SPISEL3/PPI_FS3 I/O Programmable Flag 3/SPI Slave Select Enable 3/PPI Frame Sync 3

PF4/SPISEL4/PPI15 I/O Programmable Flag 4/SPI Slave Select Enable 4 / PPI 15

PF5/SPISEL5/PPI14 I/O Programmable Flag 5/SPI Slave Select Enable 5 / PPI 14

PF6/SPISEL6/PPI13 I/O Programmable Flag 6/SPI Slave Select Enable 6 / PPI 13

PF7/SPISEL7/PPI12 I/O Programmable Flag 7/SPI Slave Select Enable 7 / PPI 12

PF8/PPI11 I/O Programmable Flag 8/PPI 11

PF9/PPI10 I/O Programmable Flag 9/PPI 10

PF10/PPI9 I/O Programmable Flag 10/PPI 9

PF11/PPI8 I/O Programmable Flag 11/PPI 8

PF12/PPI7 I/O Programmable Flag 12/PPI 7

PF13/PPI6 I/O Programmable Flag 13/PPI 6

PF14/PPI5 I/O Programmable Flag 14/PPI 5

PF15/PPI4 I/O Programmable Flag 15/PPI 4

For current information contact Analog Devices at 800/262-5643

ADSP-BF53x March 2003

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

16 REV. PrA

PRELIMINARY TECHNICAL DATA

PPI3–0 I/O PPI3–0

PPI_CLK I PPI Clock

Serial Ports

RSCLK0 I/O SPORT0 Receive Serial Clock

RFS0 I/O SPORT0 Receive Frame Sync

DR0PRI I SPORT0 Receive Data Primary

DR0SEC I SPORT0 Receive Data Secondary

TSCLK0 I/O SPORT0 Transmit Serial Clock

TFS0 I/O SPORT0 Transmit Frame Sync

DT0PRI O SPORT0 Transmit Data Primary

DT0SEC O SPORT0 Transmit Data Secondary

RSCLK1 I/O SPORT1 Receive Serial Clock

RFS1 I/O SPORT1 Receive Frame Sync

DR1PRI I SPORT1 Receive Data Primary

DR1SEC I SPORT1 Receive Data Secondary

TSCLK1 I/O SPORT1 Transmit Serial Clock

TFS1 I/O SPORT1 Transmit Frame Sync

DT1PRI O SPORT1 Transmit Data Primary

DT1SEC O SPORT1 Transmit Data Secondary

SPI Port

MOSI I/O Master Out Slave In

MISO I/O Master In Slave Out

SCK I/O SPI Clock

UART Port

RX I UART Receive

TX O UART Transmit

Real Time Clock

RTXI

IRTC Crystal Input

RTXO O RTC Crystal Output

JTAG Por t

TCK I JTAG Clock

TDO O JTAG Serial Data Out

TDI I JTAG Serial Data In

TMS I JTAG Mode Select

TRST IJTAG Reset

EMU OEmulation Output

Clock

CLKIN I Clock/Crystal Input

XTAL O Crystal Output

Mode Controls

RESET I Reset

NMI

INon-maskable Interrupt

BMODE1–0 I Boot Mode Strap

Voltage Regulator

VROUT1-0 O External FET Drive

Table 9. Pin Descriptions (Continued)

Pin Name I/O Function

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

17REV. PrA

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PRELIMINARY TECHNICAL DATA

Supplies

DDEXT

PI/O Power Supply

DDINT

PCore Power Supply

DDRTC

PReal Time Clock Power Supply

GND G External Ground

This pin should always be pulled HIGH when not used.

This pin should always be pulled LOW when not used.

Table 9. Pin Descriptions (Continued)

Pin Name I/O Function

For current information contact Analog Devices at 800/262-5643

ADSP-BF53x March 2003

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

18 REV. PrA

PRELIMINARY TECHNICAL DATA

SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

Parameter

Specifications subject to change without notice.

Parameter Minimum Nominal Maximum Unit

DDINT

Internal Supply Voltage 0.7 1.2 1.26 V

DDEXT

External Supply Voltage 2.25 2.5 or 3.3 3.6 V

DDRTC

Real Time Clock Power Supply Voltage 2.25 3.6 V

High Level Input Voltage

, @ V

DDEXT

=maximum

The ADSP-BF53x Processor is 3.3 V tolerant (always accepts up to 3.6 V maximum V

), but voltage compliance (on outputs, V

) depends on the input

DDEXT

, because V

(maximum) approximately equals V

DDEXT

(maximum). This 3.3 V tolerance applies to bi-directional pins (DATA15-0, TMR2-0,

PF15-0, PPI3-0, RSCLK1-0, TSCLK1-0, RFS1-0, TFS1-0, MOSI, MISO, SCK) and input only pins (BR, ARDY, PPI_CLK, DR0PRI, DR0SEC,

DR1PRI, DR1SEC, RX, RTXI, TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, and BMODE1-0).

2.0 3.6 V

Low Level Input Voltage

, @ V

DDEXT

=minimum –0.3 0.6 V

AMBIENT

Ambient Operating Temperature

Industrial -40 85 ºC

Commercial 0 70 ºC

ELECTRICAL CHARACTERISTICS

Parameter

Specifications subject to change without notice.

Test Conditions Minimum Maximum Unit

High Level Output Voltage

Applies to output and bidirectional pins.

@ V

DDEXT

=3.0V,

= –0.5 mA

2.4 V

Low Level Output Voltage

@ V

DDEXT

=3.0V,

= 2.0 mA

0.4 V

High Level Input Current

Applies to input pins.

@ V

DDEXT

=maximum,

= V

maximum

TBD µA

Low Level Input Current

@ V

DDEXT

=maximum,

= 0 V

TBD µA

OZH

Three-State Leakage Current

Applies to three-statable pins.

@ V

DDEXT

= maximum,

= V

maximum

TBD µA

OZL

Three-State Leakage Current

@ V

DDEXT

= maximum,

= 0 V

TBD µA

Input Capacitance

5, 6

Applies to all signal pins.

Guaranteed, but not tested.

= 1 MHz,

CASE

= 25°C,

= 2.5 V

TBD pF

PRELIMINARY TECHNICAL DATA

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

19REV. PrA

For current information contact Analog Devices at 800/262-5643

ADSP-BF53xMarch 2003

ESD SENSITIVITY

ABSOLUTE MAXIMUM RATINGS

Internal (Core) Supply Voltage

DDINT

) . . . . . . –0.3 V to +1.5 V

Stresses greater than those listed above may cause permanent damage to the device.

These are stress ratings only. Functional operation of the device at these or any other

conditions greater than those indicated in the operational sections of this specification

is not implied. Exposure to absolute maximum rating conditions for extended periods

may affect device reliability.

External (I/O) Supply Voltage

DDEXT

) . . . . . . . –0.3 V to +4.0 V

Input Voltage

. . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V

Output Voltage Swing

. . . . . . . . . . . . . . –0.5 V to V

DDEXT

+0.5 V

Load Capacitance

1,2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 pF

For proper SDRAM controller operation, the maximum load capacitance is 50 pF (at

3.3V) or 30 pF (at 2.5V) for ADDR, DATA, ABE/SDQM, CLKOUT, SCKE, SA10,

SRAS, SCAS, SWE, and SMS.

Core Clock (CCLK)

ADSP-BF533 . . . . . . . . . . . . . . . . . . . . . . . . .600 MHz

ADSP-BF532/BF531. . . . . . . . . . . . . . . . . . . .400 MHz

Peripheral Clock (SCLK)

. . . . . . . . . . . . . . . . . . . . . .133 MHz

Storage Temperature Range

. . . . . . . . . . . . . . –65ºC to +150ºC

Lead Temperature (5 seconds)

. . . . . . . . . . . . . . . . . . . . . 185ºC

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V

readily accumulate on the human body and test equipment and can discharge without

detection. Although the ADSP-BF53x Processor features proprietary ESD protection

circuitry, permanent damage may occur on devices subjected to high energy electrostatic

discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

For current information contact Analog Devices at 800/262-5643

ADSP-BF53x March 2003

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

20 REV. PrA

PRELIMINARY TECHNICAL DATA

TIMING SPECIFICATIONS

Table 10 and Table 12 describe the timing requirements for the ADSP-BF53x Processor clocks. Take care in selecting MSEL, SSEL,

and CSEL ratios so as not to exceed the maximum core clock, system clock and Voltage Controlled Oscillator (VCO) operating

frequencies, as described in

ABSOLUTE MAXIMUM RATINGS

. Table 12 describes Phase-Locked Loop operating conditions.

Table 10. Core and System Clock Requirements—ADSP-BF533

Parameter Minimum Maximum Unit

CCLK1.2

Core Cycle Period (V

DDINT

=1.2 V–5%) 1.67 ns

CCLK1.1

Core Cycle Period (V

DDINT

=1.1 V–5%) TBD ns

CCLK1.0

Core Cycle Period (V

DDINT

=1.0 V–5%) TBD ns

CCLK0.9

Core Cycle Period (V

DDINT

=0.9 V–5%) TBD ns

CCLK0.8

Core Cycle Period (V

DDINT

=0.8 V–5%) TBD ns

CCLK0.7

Core Cycle Period (V

DDINT

=0.7 V–5%) TBD ns

SCLK

System Clock Period Maximum of (7.5 or t

CCLKNN

)ns

Table 11. Core and System Clock Requirements—ADSP-BF532/531

Parameter Minimum Maximum Unit

CCLK1.2

Core Cycle Period (V

DDINT

=1.2 V–5%) 2.5 ns

CCLK1.1

Core Cycle Period (V

DDINT

=1.1 V–5%) TBD ns

CCLK1.0

Core Cycle Period (V

DDINT

=1.0 V–5%) TBD ns

CCLK0.9

Core Cycle Period (V

DDINT

=0.9 V–5%) TBD ns

CCLK0.8

Core Cycle Period (V

DDINT

=0.8 V–5%) TBD ns

CCLK0.7

Core Cycle Period (V

DDINT

=0.7 V–5%) TBD ns

SCLK

System Clock Period Maximum of (7.5 or t

CCLKNN

)ns

Table 12. Phase-Locked Loop Operating Conditions

Parameter Minimum Maximum Unit

Voltage Controlled Oscillator (VCO) Frequency 50 Maximum CCLK MHz

PRELIMINARY TECHNICAL DATA

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

21REV. PrA

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ADSP-BF53xMarch 2003

Clock and Reset Timing

Table 13 and Figure 11 describe clock and reset operations. Per ABSOLUTE MAXIMUM RATINGS on Page 19, combinations of

CLKIN and clock multipliers must not select core/peripheral clocks in excess of 600/133 MHz.

Table 13. Clock and Reset Timing

Parameter Minimum Maximum Unit

Timing Requirements

CKIN

CLKIN Period 30.0 100.0 ns

CKINL

CLKIN Low Pulse

Applies to bypass mode and non-bypass mode.

10.0 ns

CKINH

CLKIN High Pulse

10.0 ns

WRST

RESET Asserted Pulsewidth Low

Applies after power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2000 CLKIN cycles, while

RESET is asserted, assuming stable power supplies and CLKIN (not including start-up time of external clock oscillator).

11 t

CKIN

Switching Characteristics

SCLK

CLKOUT Period

The figure below shows a x2 ratio between t

CKIN

and t

SCLK

, but the ratio has many programmable options. For more information, see the System Design

chapter of the ADSP-BF533 Processor Hardware Reference.

7.5 ns

Figure 11. Clock and Reset Timing

SCLKD

CLKOUT

RESET

CLKIN

CKINH

CKIN

CKINL

SCLK

WRST

For current information contact Analog Devices at 800/262-5643

ADSP-BF53x March 2003

This information applies to a product under development. Its characteristics and specifications are subject to change with-

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22 REV. PrA

PRELIMINARY TECHNICAL DATA

Asynchronous Memory Read Cycle Timing

Table 14. Asynchronous Memory Read Cycle Timing

Parameter Minimum Maximum Unit

Timing Requirements

SDAT

DATA15– 0 Setup Before CLKOUT 2.1 ns

HDAT

DATA15– 0 Hold After CLKOUT 0.8 ns

SARDY

ARDY Setup Before CLKOUT 5.5 ns

HARDY

ARDY Hold After CLKOUT 0.0 ns

Switching Characteristic

Output Delay After CLKOUT

Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, ARE.

6.0 ns

Output Hold After CLKOUT

0.8 ns

Figure 12. Asynchronous Memory Read Cycle Timing

tDO

tSDAT

CLKOUT

AMSx

ABE1–0

tHO

BE, ADDRESS

READ

tHDAT

DATA15–0

AOE

tDO

tSARDY

tHARDY

ACCESS EXTENDED

3CYCLES

HOLD

1CYCLE

ARE

tHARDY

ARDY

ADDR19–1

SETUP

2CYCLES

PROGRAMMED READ ACCESS

4CYCLES

PRELIMINARY TECHNICAL DATA

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

23REV. PrA

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Asynchronous Memory Write Cycle Timing

Table 15. Asynchronous Memory Write Cycle Timing

Parameter Minimum Maximum Unit

Timing Requirements

SARDY

ARDY Setup Before CLKOUT 5.5 ns

HARDY

ARDY Hold After CLKOUT 0.0 ns

DDAT

DATA15–0 Disable After CLKOUT 6.0 ns

ENDAT

DATA15–0 Enable After CLKOUT 1.0 ns

Switching Characteristic

Output Delay After CLKOUT

Output pins include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, AWE.

6.0 ns

Output Hold After CLKOUT

0.8 ns

Figure 13. Asynchronous Memory Write Cycle Timing

ENDAT

CLKOUT

AMSx

ABE1–0

BE, ADDRESS

WRITE DATA

DDAT

DATA15–0

AWE

SARDY

HARDY

SETUP

2CYCLES PROGRAMMED WRITE

ACCESS 2 CYCLES

ACCESS

EXTENDED

1CYCLE

HOLD

1CYCLE

ARDY

ADDR19–1

For current information contact Analog Devices at 800/262-5643

ADSP-BF53x March 2003

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

24 REV. PrA

PRELIMINARY TECHNICAL DATA

SDRAM Interface Timing

Table 16. SDRAM Interface Timing

Parameter Minimum Maximum Unit

Timing Requirement

SSDAT

DATA Setup Before CLKOUT 2.1 ns

HSDAT

DATA Hold After CLKOUT 0.8 ns

Switching Characteristic

SCLK

CLKOUT Period 7.5 ns

SCLKH

CLKOUT Width High 2.5 ns

SCLKL

CLKOUT Width Low 2.5 ns

DCAD

Command, ADDR, Data Delay After CLKOUT

Command pins include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.

6.0 ns

HCAD

Command, ADDR, Data Hold After CLKOUT

0.8 ns

DSDAT

Data Disable After CLKOUT 6.0 ns

ENSDAT

Data Enable After CLKOUT 1.0 ns

Figure 14. SDRAM Interface Timing

HCAD

DSDAT

DCAD

SSDAT

DCAD

ENSDAT

HSDAT

SCLKL

SCLKH

SCLK

CLKOUT

DATA (IN)

DATA(OUT)

CMND ADDR

(OUT)

NOTE: COMMAND = SRAS,SCAS,SWE,SDQM,SMS, SA10, SCKE.

PRELIMINARY TECHNICAL DATA

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

25REV. PrA

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ADSP-BF53xMarch 2003

External Port Bus Request and Grant Cycle Timing

Table 17 and Figure 15 describe external port bus request and bus grant operations.

Table 17. External Port Bus Request and Grant Cycle Timing

Parameter

, 1, 2

These are preliminary timing parameters that are based on worst-case operating conditions.

The pad loads for these timing parameters are 20 pF.

Minimum Maximum Unit

Timing Requirements

BR asserted to CLKOUT high setup 4.6 ns

CLKOUT high to BR de-asserted hold time 0.0 ns

Switching Characteristics

CLKOUT high to xMS, address, and RD/WR disable 4.3 ns

CLKOUT low to xMS, address, and RD/WR enable 4.0 ns

DBG

CLKOUT high to BG asserted setup 2.2 ns

EBG

CLKOUT high to BG de-asserted hold time 2.2 ns

DBH

CLKOUT high to BGH asserted setup 2.4 ns

EBH

CLKOUT high to BGH de-asserted hold time 2.4 ns

Figure 15. External Port Bus Request and Grant Cycle Timing

ADDR19-1

AMSx

CLKOUT

DBG

DBH

EBG

EBH

AWE

BGH

ARE

ABE1-0

For current information contact Analog Devices at 800/262-5643

ADSP-BF53x March 2003

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26 REV. PrA

PRELIMINARY TECHNICAL DATA

Parallel Peripheral Interface Timing

Table 18 and Figure 16 on page 26, Figure 17 on page 27, and Figure 18 on page 27 describe Parallel Peripheral Interface operations.

Table 18. Parallel Peripheral Interface Timing

Parameter Minimum Maximum Unit

Timing Requirements

PCLKW

PPI_CLK Width

GP Frame Capture and GP Input Modes 6.0 ns

GP Output Mode 10.0 ns

PCLK

PPI_CLK Period

PPI_CLK frequency cannot exceed f

SCLK

GP Frame Capture and GP Input Modes 15.0 ns

GP Output Mode 25.0 ns

Timing Requirements - GP Input and Frame Capture Modes

SDRE

Receive Data Setup Before PPI_CLK

Referenced to sample edge.

3.0 ns

HDRE

Receive Data Hold After PPI_CLK

3.0 ns

IDFSE

FS Input Delay After PPI_CLK 3.0 ns

IFS1D

Delay Between FS1 Assertion and Valid Data (Input Mode) 0 65535 PPI_CLK periods

Switching Characteristics - GP Output and Frame Capture Modes

ODFSE

Output FS Delay After PPI_CLK

Referenced to drive edge.

12.0 ns

DDTE

Transmit Data Delay After PPI_CLK

(GP Output Mode)

12.0 ns

HDTE

Transmit Data Hold After PPI_CLK

5.0 ns

OFS1D

Delay Between FS1 Assertion and Valid Data 1 65536 PPI_CLK periods

FS12

Delay Between FS2 and FS1 Assertion

FS2 period must be an integer multiple of FS1 period.

0 PPI_CLK periods

Figure 16. GP Output Mode and Frame Capture Timing

PPI_CLK

PPI_FS1

PPIX

ODFSE

PCLK W

PCLK

ELEMENT N-1 ELE MENT N ELEMENT 1

DDTE

HD TE

OF S1D

NOTES: CLOCK AND FRAME SYNC POLARITIES ARE PROGRAMMABLE. PPI_DELAY = 0 IN THIS FIGURE.

ELEMENT 1 IS THE FIRST DATA WORD FRAMED BY THE P PI_FS 1 E DGE SHOWN. E LEMENT N BELONGS

TO T H E PR E VIO U S F RA M E.

PRELIMINARY TECHNICAL DATA

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

27REV. PrA

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ADSP-BF53xMarch 2003

Figure 17. GP Input Timing

Figure 18. General Purpose Frame Capture and Output Mode Timing

PPI_CLK

PPI_FS1

PPIX

IDFSE

IF S 1 D

ELEMENT N ELEMENT 1 ELEMENT 2

SDRE

HDRE

NOTES: CLOCK AND FRAME SYNC POLARITIES ARE PROGRAMMABLE. PPI_DELAY = 0 IN THIS FIGURE.

ELEMENT 1 IS THE FIRST DATA WORD FRAMED BY THE PPI_FS1 EDGE SHOWN. ELEMENT N BELONGS

TO T H E P R E VIOU S F RA M E.

PPI_CLK

PPI_FS1

PPI_FS2

PPI_FS3

FS12

PCLKW

PCLK

For current information contact Analog Devices at 800/262-5643

ADSP-BF53x March 2003

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

28 REV. PrA

PRELIMINARY TECHNICAL DATA

Serial Ports

Table 19. Serial Ports—External Clock

Parameter Minimum Maximum Unit

Timing Requirements

SFSE

TFS/RFS Setup Before TSCLK/RSCLK

Referenced to sample edge.

3.0 ns

HFSE

TFS/RFS Hold After TSCLK/RSCLK

3.0 ns

SDRE

Receive Data Setup Before RSCLK

3.0 ns

HDRE

Receive Data Hold After RSCLK

3.0 ns

SCLKEW

TSCLK/RSCLK Width 4.5 ns

SCLKE

TSCLK/RSCLK Period 15.0 ns

Table 20. Serial Ports—Internal Clock

Parameter Minimum Maximum Unit

Timing Requirements

SFSI

TFS/RFS Setup Before TSCLK/RSCLK

Referenced to sample edge.

6.0 ns

HFSI

TFS/RFS Hold After TSCLK/RSCLK

0.0 ns

SDRI

Receive Data Setup Before RSCLK

6.0 ns

HDRI

Receive Data Hold After RSCLK

0.0 ns

SCLKEW

TSCLK/RSCLK Width 4.5 ns

SCLKE

TSCLK/RSCLK Period 15.0 ns

Table 21. Serial Ports—External Clock

Parameter Minimum Maximum Unit

Switching Characteristics

DFSE

TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)

Referenced to drive edge.

10.0 ns

HOFSE

TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS)

0.0 ns

DDTE

Transmit Data Delay After TSCLK

10.0 ns

HDTE

Transmit Data Hold After TSCLK

0.0 ns

Table 22. Serial Ports—Internal Clock

Parameter Minimum Maximum Unit

Switching Characteristics

DFS

TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)

Referenced to drive edge.

4.0 ns

HOFS

TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS)

0.0 ns

DDT

Transmit Data Delay After TSCLK

4.0 ns

HDT

Transmit Data Hold After TSCLK

0.0 ns

SCLKIW

TSCLK/RSCLK Width 4.5 ns

PRELIMINARY TECHNICAL DATA

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

29REV. PrA

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ADSP-BF53xMarch 2003

Table 23. Serial Ports—Enable and Three-State

Parameter Minimum Maximum Unit

Switching Characteristics

DTENE

Data Enable Delay from External TSCLK

5.0 ns

DDTTE

Data Disable Delay from External TSCLK

12.0 ns

DTENI

Data Enable Delay from Internal TSCLK 2.0 ns

DDTTI

Data Disable Delay from Internal TSCLK

5.0 ns

Referenced to drive edge.

Table 24. External Late Frame Sync

Parameter Minimum Maximum Unit

Switching Characteristics

DDTLFSE

Data Delay from Late External TFS or External RFS with MCE = 1, MFD = 0

1,2

10.5 ns

DTENLFSE

Data Enable from late FS or MCE = 1, MFD = 0

1,2

3.5 ns

MCE = 1, TFS enable and TFS valid follow t

DDTENFS

and t

DDTLFSE

If external RFS/TFS setup to RSCLK/TSCLK > t

SCLKE

/2 then t

DDTLSCK

and t

DTENLSCK

apply, otherwise t

DDTLFSE

and t

DTENLFS

apply.

For current information contact Analog Devices at 800/262-5643

ADSP-BF53x March 2003

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

30 REV. PrA

PRELIMINARY TECHNICAL DATA

Figure 19. Serial Ports

DDTTE

DDTEN

DDTTI

DDTIN

DRIVE

EDGE DRIVE

EDGE

DRIVE

EDGE

DRIVE

EDGE

TSCLK / RSCLK

TSCLK (EXT)

TFS ("LATE", EXT.)

TSCLK (INT)

TFS ("LATE", INT.)

SDRI

RSCLK

RFS

DRIVE

EDGE

SAMPLE

EDGE

HDRI

SFSI

HFSI

DFSE

HOFSE

SCLKIW

DATA RECEIVE- INTERNAL CLOCK

SDRE

DATA RECEIVE- EXTERNAL CLOCK

RSCLK

RFS

DRIVE

EDGE

SAMPLE

EDGE

HDRE

SFSE

HFSE

DFSE

SCLKEW

HOFSE

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DDTI

HDTI

TSCLK

TFS

DRIVE

EDGE SAMPLE

EDGE

SFSI

HFSI

SCLKIW

DFSI

HOFSI

DATA TRANSMIT- INTERNAL CLOCK

DDTE

HDTE

TSCLK

TFS

DRIVE

EDGE SAMPLE

EDGE

SFSE

HFSE

DFSE

SCLKEW

HOFSE

DATA TRANSMIT- EXTERNAL CLOCK

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.

PRELIMINARY TECHNICAL DATA

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

31REV. PrA

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ADSP-BF53xMarch 2003

Figure 20. External Late Frame Sync (Frame Sync Setup < t

SCLKE

/2)

tDDTLFSE

tSFSE/I

tHDTE/I

RSCLK

DRIVE DRIVESAMPLE

RFS

DT 2ND BIT1ST BIT

tDDTENFS

tDDTE/I

tHOFSE/I

tDDTENFS

tSFSE/I

tHDTE/I

DRIVE DRIVESAMPLE

TSCLK

TFS

2ND BIT1ST BIT

tDDTLFSE

tDDTE/I

tHOFSE/I

EXTERNAL RFS WITH MCE = 1, MFD = 0

LATE EXTERNAL TFS

For current information contact Analog Devices at 800/262-5643

ADSP-BF53x March 2003

This information applies to a product under development. Its characteristics and specifications are subject to change with-

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32 REV. PrA

PRELIMINARY TECHNICAL DATA

Figure 21. External Late Frame Sync (Frame Sync Setup > t

SCLKE

/2)

RSCLK

RFS

SFSE/I

HOFSE/I

DTENLSCK

DDTE/I

HDTE/I

DDTLSCK

DRIVE SAMPLE

1ST BIT 2ND BIT

DRIVE

TSCLK

TFS

SFSE/I

HOFSE/I

DTENLSCK

DDTE/I

HDTE/I

DDTLSCK

DRIVE SAMPLE

1ST BIT 2ND BIT

DRIVE

LATE EXTERNAL TFS

EXTERNAL RFS WITH MCE=1, MFD=0

PRELIMINARY TECHNICAL DATA

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

33REV. PrA

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ADSP-BF53xMarch 2003

Serial Peripheral Interface (SPI) Port—Master Timing

Table 25 and Figure 22 describe SPI port master operations.

Table 25. Serial Peripheral Interface (SPI) Port—Master Timing

Parameter Minimum Maximum Unit

Timing Requirements

SSPID

Data input valid to SCK edge (data input setup) 6.0 ns

HSPID

SCK sampling edge to data input invalid 0 ns

Switching Characteristics

SDSCIM

SPISELx low to first SCK edge (x=0 or 1) 2t

SCLK

-1.5 ns

SPICHM

Serial clock high period 2t

SCLK

-1.5 ns

SPICLM

Serial clock low period 2t

SCLK

-1.5 ns

SPICLK

Serial clock period 4t

SCLK

-1.5 ns

HDSM

Last SCK edge to SPISELx high (x=0 or 1) 2t

SCLK

-1.5 ns

SPITDM

Sequential transfer delay 2t

SCLK

-1.5 ns

DDSPID

SCK edge to data out valid (data out delay) 0 6 ns

HDSPID

SCK edge to data out invalid (data out hold) 0 5 ns

Figure 22. Serial Peripheral Interface (SPI) Port—Master Timing

SSPID

HSPID

HDSPID

LSBMSB

HSPID

DDSPID

MOSI

(OUTPUT)

MISO

(INPUT)

SPISELx

(OUTPUT)

SCK

(CPOL = 0)

(OUTPUT)

SCK

(CPOL = 1)

(OUTPUT)

SPICHM

SPICLM

SPICLK

SPICHM

HDSM

SPITDM

HDSPID

LSB VALID

LSBMSB

MSB VALID

HSPID

DDSPID

MOSI

(OUTPUT)

MISO

(INPUT)

SSPID

CPHA=1

CPHA=0

MSB VALID

SDSCIM

SSPID

LSB VALID

For current information contact Analog Devices at 800/262-5643

ADSP-BF53x March 2003

This information applies to a product under development. Its characteristics and specifications are subject to change with-

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34 REV. PrA

PRELIMINARY TECHNICAL DATA

Serial Peripheral Interface (SPI) Port—Slave Timing

Table 26 and Figure 23 describe SPI port slave operations.

Table 26. Serial Peripheral Interface (SPI) Port—Slave Timing

Parameter Minimum Maximum Unit

Timing Requirements

SPICHS

Serial clock high period 2t

SCLK

-1.5 ns

SPICLS

Serial clock low period 2t

SCLK

-1.5 ns

SPICLK

Serial clock period 4t

SCLK

-1.5 ns

HDS

Last SCK edge to SPISS not asserted 2t

SCLK

-1.5 ns

SPITDS

Sequential Transfer Delay 2t

SCLK

-1.5 ns

SDSCI

SPISS assertion to first SCK edge 2t

SCLK

-1.5 ns

SSPID

Data input valid to SCK edge (data input setup) 1.6 ns

HSPID

SCK sampling edge to data input invalid 1.6 ns

Switching Characteristics

DSOE

SPISS assertion to data out active 08 ns

DSDHI

SPISS deassertion to data high impedance 08 ns

DDSPID

SCK edge to data out valid (data out delay) 0 10 ns

HDSPID

SCK edge to data out invalid (data out hold) 0 10 ns

Figure 23. Serial Peripheral Interface (SPI) Port—Slave Timing

HSPID

DDSPID

DSDHI

LSBMSB

MSB VALID

HSPID

DSOE

DDSPID

HDSPID

MISO

(OUTPUT)

MOSI

(INPUT)

SSPID

SPISS

(INPUT)

SCK

(CPOL = 0)

(INPUT)

SCK

(CPOL = 1)

(INPUT)

SDSCI

SPICHS

SPICLS

SPICLK

HDS

SPICHS

SSPID

HSPID

DSDHI

LSB VALID

MSB

MSB VALID

DSOE

DDSPID

MISO

(OUTPUT)

MOSI

(INPUT)

SSPID

LSB VALID

LSB

CPHA=1

CPHA=0

SPITDS

PRELIMINARY TECHNICAL DATA

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

35REV. PrA

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ADSP-BF53xMarch 2003

Universal Asynchronous Receiver-Transmitter (UART) Port—Receive and Transmit Timing

Figure 24 describes UART port receive and transmit operations. The maximum baud rate is SCLK/16. As shown in Figure 24 there

is some latency between the generation internal UART interrupts and the external data operations. These latencies are negligible at

the data transmission rates for the UART.

Figure 24. UART Port—Receive and Transmit Timing

RXD DATA(5–8)

INTERNAL

UART RECEIVE

INTERRUPT

UART RECEIVE BIT SET BY DATA STOP;

CLEARED BY FIFO READ

CLKOUT

(SAMPLE CLOCK)

TXD DATA(5–8) STOP (1–2)

INTERNAL

UART TRANSMIT

INTERRUPT

UART TRANSMIT BIT SET BY PROGRAM;

CLEARED BY WRITE TO TRANSMIT

START

STOP

TRANSMIT

RECEIVE

For current information contact Analog Devices at 800/262-5643

ADSP-BF53x March 2003

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

36 REV. PrA

PRELIMINARY TECHNICAL DATA

Timer Cycle Timing

Table 27 and Figure 25 describe timer expired operations. The input signal is asynchronous in “width capture mode” and “external

clock mode” and has an absolute maximum input frequency of f

SCLK

/2 MHz.

Table 27. Timer Cycle Timing

Parameter Minimum Maximum Unit

Timing Characteristics

Timer Pulsewidth Input Low

The minimum pulsewidths apply for TMRx input pins in width capture and external clock modes. They also apply to the PF1 or PPI_CLK input pins in

PWM output mode.

1 SCLK cycles

Timer Pulsewidth Input High

1 SCLK cycles

Switching Characteristic

HTO

Timer Pulsewidth Output

The minimum time for t

HTO

is one cycle, and the maximum time for t

HTO

equals (2

–1) cycles.

1(2

–1) SCLK cycles

Figure 25. Timer PWM_OUT Cycle Timing

CLKOUT

TMRx

(PWM OUTPUT MODE)

HTO

TMRx

(WIDTH CAPTURE AND

EXTERNAL CLOCK MODES)

PRELIMINARY TECHNICAL DATA

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

37REV. PrA

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ADSP-BF53xMarch 2003

Programmable Flags Cycle Timing

Table 28 and Figure 26 describe programmable flag operations.

Table 28. Programmable Flags Cycle Timing

Parameter Minimum Maximum Unit

Timing Requirement

WFI

Flag input pulsewidth t

SCLK

+ 1 ns

Switching Characteristic

DFO

Flag output delay from CLKOUT low 6 ns

Figure 26. Programmable Flags Cycle Timing

FLAG INPUT

PF (INPUT)

WFI

PF (OUTPUT)

CLKOUT

FLAG OUTPUT

DFO

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ADSP-BF53x March 2003

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

38 REV. PrA

PRELIMINARY TECHNICAL DATA

JTAG Test And Emulation Port Timing

Table 29 and Figure 27 describe JTAG port operations.

Table 29. JTAG Port Timing

Parameter Minimum Maximum Unit

Timing Parameters

TCK

TCK Period 20 ns

STAP

TDI, TMS Setup Before TCK High 4 ns

HTAP

TDI, TMS Hold After TCK High 4 ns

SSYS

System Inputs Setup Before TCK Low

System Inputs=DATA15-0, ARDY, TMR2-0, PF15-0, PPI_CLK, RSCLK0-1, RFS0-1, DR0PRI, DR0SEC, TSCLK0-1, TFS0-1, DR1PRI, DR1SEC,

MOSI, MISO, SCK, RX, RESET, NMI, BMODE1-0, BR, PP3-0.

4ns

HSYS

System Inputs Hold After TCK Low

5ns

TRSTW

TRST Pulsewidth

50 MHz Maximum

4 TCK cycles

Switching Characteristics

DTDO

TDO Delay from TCK Low 10 ns

DSYS

System Outputs Delay After TCK Low

System Outputs=DATA15-0, ADDR19-1, ABE1-0, AOE, ARE, AWE, AMS3-0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS, TMR2-0, PF15-

0, RSCLK0-1, RFS0-1, TSCLK0-1, TFS0-1, DT0PRI, DT0SEC, DT1PRI, DT1SEC, MOSI, MISO, SCK, TX, BG, BGH, PPI3-0.

012ns

Figure 27. JTAG Port Timing

TMS

TDI

TDO

SYSTEM

INPUTS

SYSTEM

OUTPUTS

TCK

HTAP

STAP

DTDO

SSYS

HSYS

DSYS

PRELIMINARY TECHNICAL DATA

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

39REV. PrA

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ADSP-BF53xMarch 2003

160-LEAD BGA PINOUT

Table 30 lists the BGA pinout by signal name. Table 31 on Page 40 lists the pinout by lead number.

Table 30. 160-Lead BGA Lead Assignment (Alphabetically by Signal)

Signal

Lead

Number Signal

Lead

Number Signal

Lead

Number Signal

Lead

Number

ABE0 H13 DATA12 M5 GND L6 SCK D1

ABE1 H12 DATA13 N5 GND L8 SCKE B13

ADDR1 J14 DATA14 P5 GND L10 SMS C13

ADDR10 M13 DATA15 P4 GND M4 SRAS D13

ADDR11 M14 DATA2 P9 GND M10 SWE D12

ADDR12 N14 DATA3 M8 GND P14 TCK P2

ADDR13 N13 DATA4 N8 MISO E2 TDI M3

ADDR14 N12 DATA5 P8 MOSI D3 TDO N3

ADDR15 M11 DATA6 M7 NMI B10 TFS0 H3

ADDR16 N11 DATA7 N7 PF0 D2 TFS1 E1

ADDR17 P13 DATA8 P7 PF1 C1 TMR0 L2

ADDR18 P12 DATA9 M6 PF10 A4 TMR1 M1

ADDR19 P11 DR0PRI K1 PF11 A5 TMR2 K2

ADDR2 K14 DR0SEC J2 PF12 B5 TMS N2

ADDR3 L14 DR1PRI G3 PF13 B6 TRST N1

ADDR4 J13 DR1SEC F3 PF14 A6 TSCLK0 J1

ADDR5 K13 DT0PRI H1 PF15 C6 TSCLK1 F1

ADDR6 L13 DT0SEC H2 PF2 C2 TX K3

ADDR7 K12 DT1PRI F2 PF3 C3 VDDEXT A1

ADDR8 L12 DT1SEC E3 PF4 B1 VDDEXT C7

ADDR9 M12 EMU M2 PF5 B2 VDDEXT C12

AMS0 E14 GND A10 PF6 B3 VDDEXT D5

AMS1 F14 GND A14 PF7 B4 VDDEXT D9

AMS2 F13 GND B11 PF8 A2 VDDEXT F12

AMS3 G12 GND C4 PF9 A3 VDDEXT G4

AOE G13 GND C5 PPI0 C8 VDDEXT J4

ARDY E13 GND C11 PPI1 B8 VDDEXT J12

ARE G14 GND D4 PPI2 A7 VDDEXT L7

AWE H14 GND D7 PPI3 B7 VDDEXT L11

BG P10 GND D8 PPI_CLK C9 VDDEXT P1

BGH N10 GND D10 RESET C10 VDDINT D6

BMODE0 N4 GND D11 RFS0 J3 VDDINT E4

BMODE1 P3 GND F4 RFS1 G2 VDDINT E11

BR D14 GND F11 RSCLK0 L1 VDDINT J11

CLKIN A12 GND G11 RSCLK1 G1 VDDINT L4

CLKOUT B14 GND H4 RTXI A9 VDDINT L9

DATA0 M9 GND H11 RTXO A8 VDDRTC B9

DATA1 N9 GND K4 RX L3 VROUT0 A13

DATA10 N6 GND K11 SA10 E12 VROUT1 B12

DATA11 P6 GND L5 SCAS C14 XTAL A11

For current information contact Analog Devices at 800/262-5643

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40 REV. PrA

PRELIMINARY TECHNICAL DATA

Table 31. 160-Lead BGA Lead Assignment (Numerically by Lead Number)

Lead

Number Signal

Lead

Number Signal

Lead

Number Signal

Lead

Number Signal

A1 VDDEXT C13 SMS H1 DT0PRI M3 TDI

A2 PF8 C14 SCAS H2 DT0SEC M4 GND

A3 PF9 D1 SCK H3 TFS0 M5 DATA12

A4 PF10 D2 PF0 H4 GND M6 DATA9

A5 PF11 D3 MOSI H11 GND M7 DATA6

A6 PF14 D4 GND H12 ABE1 M8 DATA3

A7 PPI2 D5 VDDEXT H13 ABE0 M9 DATA0

A8 RTXO D6 VDDINT H14 AWE M10 GND

A9 RTXI D7 GND J1 TSCLK0 M11 ADDR15

A10 GND D8 GND J2 DR0SEC M12 ADDR9

A11 XTAL D9 VDDEXT J3 RFS0 M13 ADDR10

A12 CLKIN D10 GND J4 VDDEXT M14 ADDR11

A13 VROUT0 D11 GND J11 VDDINT N1 TRST

A14 GND D12 SWE J12 VDDEXT N2 TMS

B1 PF4 D13 SRAS J13 ADDR4 N3 TDO

B2 PF5 D14 BR J14 ADDR1 N4 BMODE0

B3 PF6 E1 TFS1 K1 DR0PRI N5 DATA13

B4 PF7 E2 MISO K2 TMR2 N6 DATA10

B5 PF12 E3 DT1SEC K3 TX N7 DATA7

B6 PF13 E4 VDDINT K4 GND N8 DATA4

B7 PPI3 E11 VDDINT K11 GND N9 DATA1

B8 PPI1 E12 SA10 K12 ADDR7 N10 BGH

B9 VDDRTC E13 ARDY K13 ADDR5 N11 ADDR16

B10 NMI E14 AMS0 K14 ADDR2 N12 ADDR14

B11 GND F1 TSCLK1 L1 RSCLK0 N13 ADDR13

B12 VROUT1 F2 DT1PRI L2 TMR0 N14 ADDR12

B13 SCKE F3 DR1SEC L3 RX P1 VDDEXT

B14 CLKOUT F4 GND L4 VDDINT P2 TCK

C1 PF1 F11 GND L5 GND P3 BMODE1

C2 PF2 F12 VDDEXT L6 GND P4 DATA15

C3 PF3 F13 AMS2 L7 VDDEXT P5 DATA14

C4 GND F14 AMS1 L8 GND P6 DATA11

C5 GND G1 RSCLK1 L9 VDDINT P7 DATA8

C6 PF15 G2 RFS1 L10 GND P8 DATA5

C7 VDDEXT G3 DR1PRI L11 VDDEXT P9 DATA2

C8 PPI0 G4 VDDEXT L12 ADDR8 P10 BG

C9 PPI_CLK G11 GND L13 ADDR6 P11 ADDR19

C10 RESET G12 AMS3 L14 ADDR3 P12 ADDR18

C11 GND G13 AOE M1 TMR1 P13 ADDR17

C12 VDDEXT G14 ARE M2 EMU P14 GND

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

41REV. PrA

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ADSP-BF53xMarch 2003

PRELIMINARY TECHNICAL DATA

Figure 28. 160-Ball Metric BGA Pin Configuration (Top

View)

Figure 29. 160-Ball Metric BGA Pin Configuration (Bottom

View)

1234567891011121314

DDINT

DDEXT

GND

I/O

KEY:

ROUT

DDRTC

1234567891011121314

DDINT

DDEXT

GND

I/O

KEY:

ROUT

DDRTC

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

42REV. PrA

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ADSP-BF53xMarch 2003

PRELIMINARY TECHNICAL DATA

OUTLINE DIMENSIONS

Dimensions in the outline dimension figure on Page 42 are

shown in millimeters.

160-Lead Metric Plastic Ball Grid Array (mini-BGA)

(BC-160)

176-LEAD LQFP (ST-176-1)

TOP VIEW

12.00 BSC SQ

BALL A1

INDICATOR

DETAIL A

SEATING

PLANE

1.70

MAX

0.40 NOM

(NOTE 3)

0.55

0.50

0.45

BALL DIAMETER

DETAIL A

BOTTOM VIEW

13 11 9 7 5 3 1

14 12 10 8 6 4 2

0.80 BSC

BALL PITCH

10.40

BSC

NOTES

1. DIMENSIONS ARE IN MILLIMETERS.

2. COMPLIES WITH JEDEC REGISTERED OUTLINE

MO-205, VARIATION AE.

3. MINIMUM BALL HEIGHT 0.25.

A1 CORNER

INDEX AREA

0.12

MAX

COPLANARITY

0.85 MIN

TOP VIEW (PINS DOWN)

PIN 1

133

1132

176

26.00 BSC SQ

24.00 BSC SQ

0.27

0.22 TYP

0.17

0.50 BSC

LEAD PITCH

0.75

0.60

0.45

SEATING

PLANE

1.60 MAX

0.15

0.05

0.08 MAX LEAD

COPLANARITY

1.45

1.40

1.35

DETAIL A

NOTES:

1. DIMENSIONS IN MILLIMETERS.

2. ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 OF ITS

IDEAL POSITION, WHEN MEASURED IN THE LATERAL DIRECTION.

3. CENTER DIMENSIONS ARE NOMINAL.

DETAIL A

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

43REV. PrA

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PRELIMINARY TECHNICAL DATA

ORDERING GUIDE

Table 32.

Part Number

Ambient Temperature

Range

Maximum

Instruction Rate Operating Voltage

ADSP-BF533SKBC-600 0ºC to 70ºC 600 MHz 0.7 V to 1.2 V internal, 2.5 V or 3.3 V I/O

ADSP-BF533SBBC-500 -40ºC to 85ºC 500 MHz 0.7 V to 1.2 V internal, 2.5 V or 3.3 V I/O

ADSP-BF532SBBC-400 -40ºC to 85ºC 400 MHz 0.7 V to 1.2 V internal, 2.5 V or 3.3 V I/O

ADSP-BF532SBST-300 -40ºC to 85ºC 300 MHz 0.7 V to 1.2 V internal, 2.5 V or 3.3 V I/O

ADSP-BF531SBBC-400 -40ºC to 85ºC 400 MHz 0.7 V to 1.2 V internal, 2.5 V or 3.3 V I/O

ADSP-BF531SBST-300 -40ºC to 85ºC 300 MHz 0.7 V to 1.2 V internal, 2.5 V or 3.3 V I/O

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

44REV. PrA

For current information contact Analog Devices at 800/262-5643

ADSP-BF53xMarch 2003

PRELIMINARY TECHNICAL DATA