CM74CB2 LSB 2x8 Preliminary Low-Voltage Low-Skew Dual 1-to-8 Buffer FEATURES PMC-Sierra's CM74CB218 is a monolithic CMOS high-speed clock buffer. It contains two matched 1-to-8 fan-out buffers, designed for low outputto-output skews. The inputs can be connected together to form a single 1-to16 fan-out buffer. The CM74CB218 is packaged in a space-saving 28-pin SSOP package. PMC-Sierra's CM74CB218 is pincompatible with many industry-standard `218 buffers. Due to PMC-Sierra's extensive success in rigorous telecom applications of PLL technology, our clock management products are superior in performance, semiconductor process, and pricing to existing solutions from other vendors. BUFFERING POWER SUPPLY * Dual 1-to-8 fan-out buffering functionality. * Clock speeds up to 200 MHz. * Less than 250 ps output-to-output skew, including between banks. * Shared output-enable for all outputs. * 3.3V operation, with 5V-tolerant inputs ( 5V-tolerance requires device to be powered up; therefore it is important to ensure that the system 3.3V supply is sequenced to come up in advance of the 5V supply.) * Outputs can operate at 2.5V (i.e. for voltage translator applications) * 3.3V 5% * 2.5V 5% for 2.5V outputs TEMPERATURE RANGE * 0 C to 70 C ("Commercial") PACKAGING * 28-pin SSOP * Lead-free packaging available upon request ESD PROTECTION * 2 kV HBM * 500V CDM Contact PMC-Sierra's authorized sales representative in your area to obtain samples for qualification. See PMCSierra's Web site (www.pmc-sierra.com) for a list of sales representatives by area. BLOCK DIAGRAM 8 INA QA7, QA6, ...QA1, QA0 x8 OE 8 INB QB7, QB6, ...QB1, QB0 x8 PMC-2031577 Issue 1 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE (c) Copyright PMC-Sierra, Inc. 2003 All rights reserved.