CM74CB2
Preliminary
Low-Voltage Low-Skew Dual 1-to-8 Buffer
LSB 2x8
PMC-2031577 PROPRIET ARY AND CONFIDENTIAL TO PMC-SIERRA, INC., © Copyright PMC-Sierra, Inc. 2003
Issue 1 AND FOR ITS CUSTOMERS’ INTERNAL USE All rights reserved.
FEATURES
PMC-Sierra’s CM74CB218 is a
monolithic CMOS high-speed clock
buffer. It contains two matched 1-to-8
fan-out buffers, designed for low output-
to-output skews. The inputs can be
connected together to form a single 1-to-
16 fan-out buffer.
The CM74CB218 is packaged in a
space-saving 28-pin SSOP package.
PMC-Sierra’s CM74CB218 is pin-
compatible with many industry-standard
‘218 buffers. Due to PMC-Sierra’s
extensive success in rigorous telecom
applications of PLL technolog y, our clock
management products are superior in
performance, semiconductor process,
and pricing to existing solutions from
other vendors.
Contact PMC-Sierra’s authorized sales
representative in your area to obtain
samples for qualification. See PMC-
Sierra’s Web site (www.pmc-sierra.com)
for a list of sales representatives by
area.
BUFFERING
• Dual 1-to-8 fan-out buffering
functionality.
• Clock speeds up to 200 MHz.
• Less than 250 ps output-to-output
skew, including between banks.
• Shared output-enable for all outputs.
• 3.3V operation, with 5V-tolerant inputs
( 5V-tolerance requires device to be
powered u p; there fore it i s importan t to
ensure that the system 3.3V supply is
sequenced to come up in advance of
the 5V supply.)
• Outputs can operate at 2.5V (i.e. for
voltage translator applications)
POWER SUPPLY
•3.3V ± 5%
• 2.5V ± 5% for 2.5V outputs
TEMPERATURE RANGE
• 0 C to 70 C (“Commercial”)
PACKAGING
• 28-pin SSOP
• Lead-free packaging available upon
request
ESD PROTECTION
•2 kV HBM
• 500V CDM
B
LOCK DIAGRAM
8
8
INA
INB
OE
QA7, QA6, ...QA1, QA0
x8
x8
QB7, QB6, ...QB1, QB0
