DSs1312 DALLAS SEMICONDUCTOR DS1312 Nonvolatile Controller with Lithium Battery Monitor FEATURES Converts CMOS SRAM into nonvolatile memory Unconditionally write-protects SRAM when Vcc is out of tolerance Automatically switches to battery backup supply when Vcc power failure occurs Monitors voltage of a lithium cell and provides advanced warning of impending battery failure Signals lowbattery condition on active low Battery Warning output signal Optional -5% or 10% power fail detection Space-saving 8pin DIP and SOIC packages Optional 16pin SOIC and 20-pin TSSOP versions reset processor when power failure occurs and hold processor in reset during system powerup |ndustrial temperature range of -40C to +85C DESCRIPTION The DS1312 Nonvolatile Controller with Battery Monitor isa CMOS circuit which solves the application problem of converting CMOS RAM into nonvolatile memory. Incoming power is monitored for an out-ofHolerance condition. When such a condition is detected, chip enable is inhibited to accomplish write protection and the battery is switched on to supply the RAM with unin- terrupted power. Special circuitry uses a low-leakage CMOS process which affords precise voltage detection at extremely low battery consumption. PIN ASSIGNMENT Veco] 1 2 Veo Veco OH | 1 ~ 810 Vcei Veer C 2 7 Bw Vear OO | 2 70 Bw ToL[] 3 6 CEO ToL OH | 3 6f0 CEO @npd CJ 4 5 CEI GND O | 4 510 CEI DS1312 8-PIN DIP 3 | DS13128-2 8-PIN SOIC (300 MIL) (150 MIL) y nce T] 1 20] Nc ne Of} 1 1600 NC Veco | 2 191) Veer Veco OH | 2 15M Veo. nc 3 18] RST ne 00 }3 140 RST yo. Ol 4 17 ne Vear HL | 4 13M NC nc (] 5 i6(] Nc Nc OO |5 1200 Bw nce 6 is] BW ToL OI] |6 1110 CEO Ne O01 }7 iof nc = TOU? 14] Ne GND O | 8 emo cer = NC 8 13] CEO nc (] 9 121] ne DS13128 16-PIN SOIC (300 MIL) @ND [] 10 411 CEI DS1312E 20-PIN TSSOP PIN DESCRIPTION Vecl +5V Power Supply Input Veco SRAM Power Supply Output Veat Backup Battery Input CEI Chip Enable Input CEO Chip Enable Output TOL - Vcc Tolerance Select BW Battery Warning Output (Open Drain) RST Reset Output (Open Drain) GND Ground NG No Connection 022598 1/10DS1312 In addition to batterybackup support, the DS1312 per- forms the important function of monitoring the remaining capacity of the lithium battery and providing a warning before the battery reaches end-of-life. Because the open-circuit voltage of a lithium backup battery remains relatively constant over the majority of its life, accurate battery monitoring requires loadedbattery voltage measurement. The DS1312 performs such measure- ment by periodically comparing the voltage of the bat- tery as it supports an internal resistive load with a care- fully selected reference voltage. If the battery voltage falls below the reference voltage under such conditions, the battery will soon reach end-of-life. As a result, the Battery Warning pin is activated to signal the need for battery replacement. MEMORY BACKUP The DS1312 performs all the circuit functions required to provide batterybackup for an SRAM. First, the device provides a switch to direct power from the bat- tery or the system power supply (Vcc)). Whenever Vcoc| is less than the switch point Vew and Vcc, is less than the battery voltage Vpart, the battery is switched in to provide backup power to the SRAM. This switch has voltage drop of less than 0.2 volts. Second, the DS1312 handles power failure detection and SRAM write-protection. Voc is constantly moni- tored, and when the supply goes out of tolerance, a pre- cision comparator detects power failure and inhibits chip enable output (CEO) in order to writeprotect the SRAM. This is accomplished by holding CEO to within 0.2 volts of Vago when V is out of tolerance. If CET is (active) low at the time that power failure is detected, the CEO signal is kept low until CEI is brought high again. Once CEI is brought high, CEO is taken high and held high until after Voc) has returned to its nominal voltage level. If CElis not brought high by 1.5 us after power fail- ure is detected, CEO is forced high at that time. This specific scheme for delaying write protection for up to 1.5 us guarantees that any memory access in progress when power failure occurs will complete properly. Power failure detection occurs in the range of 4.7510 4.5 volts (5% tolerance) when the TOL pin is wired to GND or in the range of 4.5 to 4.25 volts (10% tolerance) when TOL is connected to Veco. BATTERY VOLTAGE MONITORING The DS1312 automatically performs periodic battery voltage monitoring at a factoryprogrammed time inter- val of 24 hours. Such monitoring begins within tpec after Voc) rises above Vcctp, and is suspended when power failure occurs. After each 24 hour period (tgtcn) has elapsed, the DS1312 connects Vpaz to an internal 1.2 MQ test resis- tor (Rint) for one second (tptpw). During this one second, if VpatT falls below the factory-programmed battery voltage trip point (Vptp), the battery warning output BWis asserted. While BWis active battery test- ing will be performed with period tgrcw to detect battery removal and replacement. Once asserted, BW remains active until the battery is physically removed and replaced by a fresh cell. The battery is still retested after each Vcc power-up, however, even if BW was active on powerdown. If the battery is found to be higher than Vptp during such testing, BW is deasserted and regular 24-hour testing resumes. BW has an open-drain out- put driver. Battery replacement following BW activation is normally done with Voc) nominal so that SRAM data is not lost. During battery replacement, the minimum time duration between old battery detachment and new battery attachment (tgppa) must be met or BW will not deacti- vate following attachment of the new battery. Should BW not deactivate for this reason, the new battery can be detached for tgppa and then reattached to clear BW. NOTE: The DS1312 cannot constantly monitor an attached battery because such monitoring would drasti- cally reduce the life of the battery. As a result, the DS1312 only tests the battery for one second out of every 24 hours and does not monitor the battery in any way between tests. If a good battery (one that has not been previously flagged with BW) is removed between battery tests, the DS1312 may not immediately sense the removal and may not activate BW until the next scheduled battery test. If a battery is then reattached to the DS1312, the battery may not be tested until the next scheduled test. NOTE: Battery monitoring is only an useful technique when testing can be done regularly over the entire life of a lithium battery. Because the DS1312 only performs battery monitoring when Vcc _ is nominal, systems which are powereddown for excessively long periods can completely drain their lithium cells without receiving any advanced warning. To prevent such an occurrence, systems using the DS1312 battery monitoring feature should be poweredup periodically (at least once every few months) in order to perform battery testing. Further- 022598 2/10DSs1312 more, anytime BW is activated on the first battery test after a power-up, data integrity should be checked via checksum or other technique. POWER MONITORING DS1312S and DS1312E varieties have an additional reset pin. These varieties detect out-oftolerance power supply conditions and warn a processorbased system of impending power failure. When Vcc, falls below the trip point level defined by the TOL pin (Vectp), the Vcc; comparator activates the reset signal RST. Reset occurs in the range of 4.75 to 4.5 volts (5% tolerance) when the TOL pin is connected to GND or in the range of 4.5 to 4.25 volts (10% tolerance) when TOL is connected to Veco. RST also serves as a power-on reset during power-up. After Voc) exceeds Voctp, RST will be held active for FUNCTIONAL BLOCK DIAGRAM Figure 1 CEI e 200 ms nominal (tppy). This reset period is sufficiently long to prevent system operation during power-on tran- sients and to allow tpec to expire. RST has an open drain output driver. FRESHNESS SEAL MODE When the battery is first attached to the DS1312 without Voc power applied, the device does not immediately provide battery-backup power on Vcco. Only after Voc) exceeds Voctp and later falls below both Vew and Veat will the DS1312 leave Freshness Seal Mode and provide batterybackup power. This mode allows a bat- tery to be attached during manufacturing but not used until after the system has been activated for the first time. As a result, no battery energy is drained during storage and shipping. CIRCUITRY T DELAY TIMING | TOL | >> = | J 4 RST [Yorn > Veci [ Veco 7 est Vew REF = ) >So______++ th >" VY ' ' \ ' 1 ; ke I I Vear AW TT ' CURRENT-LIMITING REDUNDANT ' BATTERY CHARGING/SHORTING ' RESISTOR SERIES FET * - - - PROTECTION CIRCUITRY Tr se 1 (U.L. RECONGNIZED) Vetp REF 1.2 MQ BATTERY WARNING __ CONTROL CIRCUITRY BW -| 022598 3/10DS1312 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground 0.5V to +7.0V Operating Temperature 40C to +85C Storage Temperature 55C to +125C Soldering Temperature 260C for 10 seconds * This is astress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is notimplied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS (-40C to +85C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Supply Voltage TOL=GND Vecl 4.75 5.0 5.5 Vv 1 Supply Voltage TOL=Vcoco Vecl 4.5 5.0 5.5 Vv 1 Battery Supply Voltage VBaT 2.0 6.0 Vv 1 Logic 1 Input Vin 2.0 Vec!+0.3 Vv 1,12 Logic 0 Input VIL 0.3 +0.8 Vv 1,12 DC ELECTRICAL CHARACTERISTICS (-40C to +85C; Veci >Vcctp) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Operating Current (TTL inputs) lect 200 400 HA 2 Operating Current (CMOS inputs) loce 50 100 HA 2,5 RAM Supply Current leco1 140 mA 3 (Veco 2 Veci -0.2V) RAM Supply Current leco1 200 mA 4 (Veco 2 Veci -0.3V) Voc Trip Point (TOL=GND) VoctTp 4.50 4.62 4.75 Vv 1 Voc Trip Point (TOL=Vecq) VoctTp 4.25 4.37 4.50 Vv 1 Veat Trip Point VeTp 2.5 2.6 2.7 Vv 1 Voc/VBat Switch Point Vow 2.6 2.7 2.8 Vv 1 Output Current @ 2.4V lou -1 mA 7,10 Output Current @ 0.4V lo 4 mA 7,10 Input Leakage lit -1.0 +1.0 HA Output Leakage ILo -1.0 +1.0 pA Battery Monitoring Test Load RINT 0.8 1.2 1.5 MQ 022598 4/10DSs1312 DC ELECTRICAL CHARACTERISTICS (-40C to +85C; Voc! < VBat; Veci < Vsw) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Battery Current IBAT 100 nA 2 Battery Backup Current locoe 500 HA 6 Supply Voltage Veco VeatT0.2 1 CEO Output VoHL Vpat0.2 1,8 CAPACITANCE (ta=25C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Capacitance (CEI, TOL) Cin 7 pF Output Capacitance Court 7 pF (CEO, BW, RST) AC ELECTRICAL CHARACTERISTICS (-40C to +85C; Voc = Vectp) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES CEI to CEO Propagation Delay tpp 5 10 ns CE Pulse Width tcE 1.5 is 11 Vec Valid to End of Write tREC 12 125 ms 9 Protection Voc Valid to CEI Inactive tpu 2 ms Voc Valid to RST Inactive tReU 150 200 350 ms 10 Voc Valid to BW Valid tppu 1 s 10 AC ELECTRICAL CHARACTERISTICS (-40C to +85C; Vec! < Vectp) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Vcc Slew Rate te 150 ps Voc Fail Detect to RST Active tReD 5 15 us 10 Vcc Slew Rate tr 150 ps AC ELECTRICAL CHARACTERISTICS (-40C to +85C; Voc = Vectp) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Battery Test to BW Active taw 1 s 10 Battery Test CycleNormal tBTCN 24 hr Battery Test Cycle-Warning tBTcw 5 s Battery Test Pulse Width tBTPW 1 s Battery Detach to Battery Attach tBDBA 7 s Battery Attach to BW Inactive tBaBW 1 s 10 022598 5/10DS1312 TIMING DIAGRAM: POWER UP CEI CEO Veci Veco tapu SLEWS UP WITH Voc trPu Vat RST Vsw Vin NOTE: lf Veat < Vsw. Veco will begin to slew with Voc) when Vocl = VBat. \ SLEWS UP WITH Voc vit 4 022598 6/10DSs1312 TIMING DIAGRAM: POWER DOWN toe cs CSSAION CEO Veci Vcco SLEWS DOWN ? WITH Voc VpaT Vsw RST X Vit SLEWS DOWN WITH Voc BW NOTE: If Veat < Vsw: Veco will slew down with Vecy until Voc! = VBat-. 022598 7/10DS1312 TIMING DIAGRAM: BATTERY WARNING DETECTION Voctp V, / ce tapu Ye Vaart __,, \ \ | _ JI \ VBTP tetcn >| t tatpw w__ BICW - BATTERY TEST L i ACTIVE ] ee Y. t BW NOTE: tgw is measured from the expiration of the internal timer to the activation of the battery warning output BW. TIMING DIAGRAM: BATTERY REPLACEMENT cc BATTERY BATTERY \ DETACH vt BAT BTP FLOATING 'BaBw ke ' p84 022598 8/10DSs1312 NOTES: 1. All voltages referenced to ground. . Measured with outputs open circuited. . lecor is the maximum average load which the DS1312 can supply to attached memories at Veco > Veci-0.2V. 2 3 4. Ieco1 is the maximum average load which the DS1312 can supply to attached memories at Veco = Veci-0.3V. 5. All inputs within 0.3V of ground or Voc). 6 . leco2 is the maximum average load current which the DS1312 can supply to the memories in the battery backup mode. 7. Measured with a load as shown in Figure 1. 8. Chip Enable Output CEO can only sustain leakage current in the batterybackup mode. 9. CEO will be held high for a time equal to tpe after Voc) crosses VocTp on powerup. 10. BW and RST are open drain outputs and, as such, cannot source current. External pull-up resistors should be connected to these pins for proper operation. Both BW and RST can sink 10 mA. 11. t maximum must be met to ensure data integrity on powerdown. 12. In battery-backup mode, inputs must never be below ground or above Voco. 13. The DS1312 is recognized by Underwriters Laboratory (U.L. ) under file E99151. DC TEST CONDITIONS AC TEST CONDITIONS Outputs Open Output Load: See below All voltages are referenced to ground Input Pulse Levels: 0 3.0V Timing Measurement Reference Levels Input: 1.5V Output: 1.5V Input pulse Rise and Fall Times: 5 ns OUTPUT LOAD Figure 1 +5 VOLTS 1.1KQ D.U.T. 30 pF* 680KQ * INCLUDING SCOPE AND JIG CAPACITANCE 022598 9/10DS1312 DATA SHEET REVISION SUMMARY The following represent the key differences between 12/16/96 and 06/12/97 version of the DS1312 data sheet. Please review this summary carefully. 1. Changed Vpat max to 6V 2. Changed tpapw from 75 to 1s max 3. Changed block diagram to show UL compliance The following represent the key differences between 06/12/97 and 08/29/97 version of the DS1312 data sheet. Please review this summary carefully. 1. Changed AC test conditions The following represent the key differences between 08/29/97 and 12/16/97 version of the DS1312 data sheet. Please review this summary carefully. 1. Specified Input Capacitance as being only for CEI, TOL and output capacitance as being only for CEO, B and RST. This is not a change but rather a clarification. 2. Add note 13 describing UL recognition. 022598 10/10