Functional Description
The EQ50F100 6.25Gbps Backplane Equalizer is a fixed,
receive-end backplane equalizer. It enables serial transmis-
sion over FR-4 backplane with trace length of at least 30" at
6.25Gbps. It consists of an equalizer filter, limiting amplifier,
offset driver, and offset cancellation circuit. The equalizer
block compensates for the high frequency attenuation
caused by the bandwidth-limited transmission channel found
in backplane system. The limiting amplifier boost the signal
at the output of the equalizer block. The offset cancellation
circuit corrects for internal mis-match and offset from the
previous stage to minimize duty-cycle distortion.
Input and Output
The input and output stage of the EQ50F100 is implemented
using current mode logic (CML). The input stage has an
equivalent DC differential input resistance of 100Ω. The
positive and negative output channels are internally termi-
nated with a 50Ωpull-up to VDD. AC coupling is recom-
mended for both input and output.
Application Information
PCB LAYOUT AND POWER SYSTEM
CONSIDERATIONS
Power system performance may be greatly improved by
using thin dielectrics (2 to 4 mils) for power / ground sand-
wiches. This arrangement provides plane capacitance for
the PCB power system with low-inductance parasitic. Exter-
nal bypass capacitors should include both RF ceramic and
tantalum electrolytic types. RF capacitors may use values in
the range of 0.1nF to 10nF. Tantalum capacitors may be in
the 2.2uF to 10uF range. Voltage rating of the tantalum
capacitors should be at least 5X the power supply voltage
being used.
It is a recommended practice to use two vias at each power
pin as well as at all RF bypass capacitor terminals. Dual vias
reduce the interconnect inductance by up to half, thereby
reducing interconnect inductance and extending the effec-
tive frequency range of the bypass components. Locate RF
capacitors as close as possible to the supply pins, and use
wide low impedance traces (not 50 Ohm traces). Surface
mount capacitors are recommended due to their smaller
parasitics. It is recommended to connect power and ground
pins directly to the power and ground planes with bypass
capacitors connected to the plane with via on both ends of
the capacitor. Connecting power or ground pins to an exter-
nal bypass capacitor will increase the inductance of the path.
A small body size X7R chip capacitor, such as 0603 or 0402,
is recommended for external bypass. Its small body size
reduces the parasitic inductance of the capacitor. The user
must pay attention to the resonance frequency of these
external bypass capacitors, usually in the range of 20-30
MHz range. To provide effective bypassing, multiple capaci-
tors are often used to achieve low impedance between the
supply rails over the frequency of interest. At high frequency,
it is also a common practice to use two vias from power and
ground pins to the planes, reducing the impedance at high
frequency.
See AN-1187 for additional information on LLP package.
AC COUPLING
For multi-giga bit design, the smallest available package
should be used for the AC coupling capacitor. This will help
minimize degradation of signal quality due to package para-
sitics. The most common used capacitor value for the
EQ50F100 interface is 0.1uF capacitor.
EQ50F100
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