USB334x Enhanced Single Supply Hi-Speed USB ULPI Transceiver Product Features * USB-IF Battery Charging 1.2 Specification Compliant * Link Power Management (LPM) Specification Compliant * Integrated ESD protection circuits - Up to 25kV IEC Air Discharge without external devices * Over-Voltage Protection circuit (OVP) protects the VBUS pin from continuous DC voltages up to 30V * Integrated USB Switch (USB3341, USB3346, and USB3347) - Allows single USB port of connection by providing switching function for: -Battery charging -Stereo and mono/mic audio -USB Full-Speed/Low-Speed data * RapidCharge AnywhereTM Provides: - 3-times the charging current through a USB port over traditional solutions - USB-IF Battery Charging 1.2 compliance to any portable device - Charging current up to 1.5Amps via compatible USB host or dedicated charger - Dedicated Charging Port (DCP), Charging (CDP) & Standard (SDP) Downstream Port support * flexPWR(R) Technology - Extremely low current design ideal for battery powered applications - "Sleep" mode tri-states all ULPI pins and places the part in a low current state - 1.8V to 3.3V IO Voltage (USB3343) * Single Power Supply Operation - Integrated 1.8V regulator - Integrated 3.3V regulator -100mV dropout voltage * PHYBoost - Programmable USB transceiver drive strength for recovering signal integrity * VariSenseTM - Programmable USB receiver sensitivity * "Wrapper-less" design for optimal timing performance and design ease - Low Latency Hi-Speed Receiver (43 HiSpeed clocks Max) allows use of legacy UTMI Links with a ULPI bridge 2009-2018 Microchip Technology Inc. * External Reference Clock operation available - ULPI Clock Input Mode (60 MHz sourced by Link) - 0 to 3.6V input drive tolerant - Able to accept "noisy" clock sources as reference to internal, low-jitter PLL - Crystal support available (USB3343) * Smart detection circuits allow identification of USB charger, headset, or data cable insertion * Includes full support for the optional On-The-Go (OTG) protocol detailed in the On-The-Go Supplement Revision 2.0 specification * Supports the OTG Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) * UART mode for non-USB serial data transfers * Internal 5V cable short-circuit protection of ID, DP and DM lines to VBUS or ground * Industrial Operating Temperature -40C to +85C * 24 pin, QFN RoHS Compliant package (4 x 4 x 0.90 mm height) Applications The USB334x is the solution of choice for any application where a Hi-Speed USB connection is desired and when board space, power, and interface pins must be minimized. * * * * * * * * * * * * * * Cell Phones PDAs MP3 Players GPS Personal Navigation Scanners External Hard Drives Digital Still and Video Cameras Portable Media Players Entertainment Devices Printers Set Top Boxes Video Record/Playback Systems IP and Video Phones Gaming Consoles DS00002646A-page 1 USB334x TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS00002646A-page 2 2009-2018 Microchip Technology Inc. USB334x Table of Contents 1.0 General Description ........................................................................................................................................................................ 4 2.0 Pin Locations and Definitions .......................................................................................................................................................... 7 3.0 Limiting Values .............................................................................................................................................................................. 13 4.0 Electrical Characteristics ............................................................................................................................................................... 15 5.0 Architecture Overview ................................................................................................................................................................... 24 6.0 ULPI Operation ............................................................................................................................................................................. 42 7.0 ULPI Register Map ........................................................................................................................................................................ 63 8.0 Application Notes .......................................................................................................................................................................... 77 9.0 Package Outline ............................................................................................................................................................................ 82 Appendix A: Data sheet Revision History ........................................................................................................................................... 88 2009-2018 Microchip Technology Inc. DS00002646A-page 3 USB334x 1.0 GENERAL DESCRIPTION Microchip's USB334x is a family of Hi-Speed USB 2.0 Transceivers that provide a physical layer (PHY) solution wellsuited for portable electronic devices. Both commercial and industrial temperature applications are supported. Each model in the USB334x family may use a 60MHz reference clock or the model-number specific reference clock shown on the Product Identification System page. Several advanced features make the USB334x the transceiver of choice by reducing both eBOM part count and printed circuit board (PCB) area. Outstanding ESD robustness eliminates the need for external ESD protection devices in typical applications. The internal Over-Voltage Protection circuit (OVP) protects the USB334x from voltages up to 30V on the VBUS pin. By using a reference clock from the Link, the USB334x removes the cost of a dedicated crystal reference from the design. The USB334x includes integrated 3.3V and 1.8V regulators, making it possible to operate the device from a single power supply. The USB334x is optimized for use in portable applications where a low operating current and standby currents are essential. The USB334x operates from a single supply and includes integrated regulators for its supplies. The USB334x also supports the USB Link Power Management protocol (LPM) to further reduce USB operating currents. The USB334x family is enabled with RapidCharge Anywhere which supports USB-IF Battery Charging 1.2 for any portable device. RapidCharge Anywhere provides three times the charging current through a USB port over traditional solutions which translate up to 1.5Amps via compatible USB host or dedicated charger. In addition, this provides a complete USB charging ecosystem between device and host ports such as Dedicated Charging Port (DCP), Charging (CDP) and Standard (SDP) Downstream Ports. Section 5.9, "USB Charger Detection Support," on page 38 describes this is further detail. The USB334x meets all of the electrical requirements for a Hi-Speed USB Host, Device, or an On-the-Go (OTG) transceiver. In addition to the supporting USB signaling, the USB334x also provides USB UART mode and, in versions with the integrated USB switch, USB Audio mode. USB334x uses the industry standard UTMI+ Low Pin Interface (ULPI) to connect the USB transceiver to the Link. ULPI uses a method of in-band signaling and status byte transfers between the Link and PHY to facilitate a USB session with only twelve pins. The USB334x uses "wrapper-less" technology to implement the ULPI interface. This "wrapper-less" technology allows the PHY to achieve a low latency transmit and receive time. Microchip's low latency transceiver allows an existing UTMI Link to be reused by adding a UTMI to ULPI bridge. By adding a bridge to the ASIC the existing and proven UTMI Link IP can be reused. Versions of the USB334x with the integrated USB switch enable a single USB port of connection. DS00002646A-page 4 2009-2018 Microchip Technology Inc. USB334x FIGURE 1-1: BLOCK DIAGRAM (USB3341, USB3346, AND USB3347) REFCLK OVP ID DP DM ESD Protection VBUS OTG BC 1.1 Hi-Speed USB Transceiver SPK_L SPK_R USB DP/DM Switch Low Jitter Integrated PLL ULPI Registers and State Machine BIAS RBIAS Integrated Power Management RESETB VBAT VDD33 VDD18 ULPI Interface STP NXT DIR CLKOUT DATA[7:0] In USB audio mode, a switch connects the DP pin to the SPK_R pin, and another switch connects he DM pin to the SPK_L pin. These switches are shown in the lower left-hand corner of .The USB334x can be configured to enter USB audio mode as described in Section 6.7.2, "USB Audio Mode (USB3341 and USB3346)," on page 61. In addition, these switches are on when the RESETB pin of the USB334x is asserted. The USB audio mode enables audio signaling from a single USB port of connection, and the switches may also be used to connect Full Speed USB from another transceiver to the USB connector. 2009-2018 Microchip Technology Inc. DS00002646A-page 5 USB334x OVP ID DP ESD Protection VBUS DM OTG Hi-Speed USB Transceiver XO BLOCK DIAGRAM (USB3343) REFCLK / XI FIGURE 1-2: Low Jitter Integrated PLL ULPI Registers and State Machine BIAS Integrated Power Management RBIAS RESETB VBAT VDD33 VDD18 VDDIO ULPI Interface STP NXT DIR CLKOUT DATA[7:0] The USB334x includes an integrated 3.3V LDO regulator that is used to generate 3.3V from power applied to the VBAT pin. The voltage on the VBAT pin can range from 3.0 to 5.5V. The regulator dropout voltage is less than 100mV which allows the PHY to continue USB signaling when the voltage on VBAT drops to 3.0V. The USB transceiver will continue to operate at lower voltages, although some parameters may be outside the limits of the USB specifications. The VBAT and VDD33 pins should never be connected together. In USB UART mode, the USB334x DP and DM pins are redefined to enable pass-through of asynchronous serial data. The USB334x will enter UART mode when programmed, as described in Section 6.7.1, "Entering USB UART Mode," on page 60. 1.1 Reference Documents UTMI+ Low Pin Interface (ULPI) Specification, Revision 1.1 Universal Serial Bus Specification, Revision 2.0 On-The-Go Supplement to the USB 2.0 Specification, Revision 1.3 On-The-Go Supplement to the USB 2.0 Specification, Revision 2.0 USB Battery Charging Specification, Revision 1.2 DS00002646A-page 6 2009-2018 Microchip Technology Inc. USB334x 2.0 PIN LOCATIONS AND DEFINITIONS 2.1 USB334x Pin Locations and Descriptions 2.1.1 USB3341, USB3346, AND USB3347 PIN DIAGRAM AND PIN DEFINITIONS The illustration below is viewed from the top of the package. DIR STP VDD18 RESETB REFCLK RBIAS 24 23 22 21 20 19 USB3341, USB3346, AND USB3347 PIN LOCATIONS - TOP VIEW CLKOUT 1 18 ID NXT 2 17 VBUS DATA0 3 16 VBAT DATA1 4 15 VDD33 DATA2 5 14 DM DATA3 6 13 DP 7 8 9 10 11 12 DATA5 DATA6 DATA7 SPK_L SPK_R 24Pin QFN 4x4mm DATA4 FIGURE 2-1: The following table details the pin definitions for the figure above. TABLE 2-1: USB3341, USB3346, AND USB3347 PIN DESCRIPTIONS Pin Name Direction/ Type Active Level 1 CLKOUT Output, CMOS N/A ULPI Clock Output Mode: 60MHz ULPI Clock Outputput. All ULPI signals are driven synchronous to the rising edge of this clock. ULPI Clock Input Mode: Connect this pin to VDD18 to configure 60MHz ULPI Clock Input mode as described in Section 5.5.1. 2 NXT Output, CMOS High The PHY asserts NXT to throttle the data. When the Link is sending data to the PHY, NXT indicates when the current byte has been accepted by the PHY. 3 DATA[0] I/O, CMOS N/A ULPI bi-directional data bus. DATA[0] is the LSB. 4 DATA[1] I/O, CMOS N/A ULPI bi-directional data bus. 2009-2018 Microchip Technology Inc. Description DS00002646A-page 7 USB334x TABLE 2-1: USB3341, USB3346, AND USB3347 PIN DESCRIPTIONS (CONTINUED) Pin Name Direction/ Type Active Level 5 DATA[2] I/O, CMOS N/A ULPI bi-directional data bus. 6 DATA[3] I/O, CMOS N/A ULPI bi-directional data bus. 7 DATA[4] I/O, CMOS N/A ULPI bi-directional data bus. 8 DATA[5] I/O, CMOS N/A ULPI bi-directional data bus. 9 DATA[6] I/O, CMOS N/A ULPI bi-directional data bus. 10 DATA[7] I/O, CMOS N/A ULPI bi-directional data bus. DATA[7] is the MSB. 11 SPK_L I/O, Analog N/A USB switch in/out for DM signals. 12 SPK_R I/O, Analog N/A USB switch in/out for DP signals. 13 DP I/O, Analog N/A D+ pin of the USB cable. 14 DM I/O, Analog N/A D- pin of the USB cable. 15 VDD33 Power N/A 3.3V Regulator Output. A 1.0uF (<1 ohm ESR) bypass capacitor to ground is required for regulator stability. The bypass capacitor should be placed as close as possible to the USB334x. 16 VBAT Power N/A Regulator input. The regulator supply can be from 5.5V to 3.0V. 17 VBUS I/O, Analog N/A This pin is used for the VBUS comparator inputs and for VBUS pulsing during session request protocol. An external resistor, RVBUS, is required between this pin and the USB connector. 18 ID Input, Analog N/A For device applications the ID pin is connected to VDD33. For Host applications ID is grounded. For OTG applications the ID pin is connected to the USB connector. 19 RBIAS Analog, CMOS N/A Bias Resistor pin. This pin requires an 8.06k (1%) resistor to ground, placed as close as possible to the USB334x. Nominal voltage during ULPI operation is 0.8V. 20 REFCLK Input, CMOS N/A ULPI Clock Output Mode: Model-specific reference clock pin. See Product Identification System, Note 1. Clock Input Mode: 60MHz ULPI Clock Input. DS00002646A-page 8 Description 2009-2018 Microchip Technology Inc. USB334x TABLE 2-1: USB3341, USB3346, AND USB3347 PIN DESCRIPTIONS (CONTINUED) Pin Name Direction/ Type Active Level 21 RESETB Input, CMOS, Low When low, the part is suspended and the 3.3V and 1.8V regulators are disabled. When high, the USB334x will operate as a normal ULPI device, as described in Section 5.6.2. The state of this pin may be changed asynchronously to the clock signals. When asserted for a minimum of 1 microsecond and then de-asserted, the ULPI registers are reset to their default state and all internal state machines are reset. 22 VDD18 Power N/A 1.8V Regulator Output. A 1.0uF (<1 ohm ESR) bypass capacitor to ground is required for regulator stability. The bypass capacitor should be placed as close as possible to the USB334x. 23 STP Input, CMOS High The Link asserts STP for one clock cycle to stop the data stream currently on the bus. If the Link is sending data to the PHY, STP indicates the last byte of data was on the bus in the previous cycle. 24 DIR Output, CMOS N/A Controls the direction of the data bus. When the PHY has data to transfer to the Link, it drives DIR high to take ownership of the bus. When the PHY has no data to transfer it drives DIR low and monitors the bus for commands from the Link. FLAG GND Ground N/A Ground. 2009-2018 Microchip Technology Inc. Description DS00002646A-page 9 USB334x 2.2 USB3343 Diagram and Pin Definitions The illustration below is viewed from the top of the package. STP VDD18 RESETB REFCLK / XI XO RBIAS 24 23 22 21 20 19 USB3343 PIN LOCATIONS - TOP VIEW DIR 1 18 ID CLKOUT 2 17 VBUS NXT 3 16 VBAT DATA0 4 15 VDD33 DATA1 5 14 DM DATA2 6 13 DP 7 8 9 10 11 12 DATA4 VDDIO DATA5 DATA6 DATA7 24Pin QFN 4x4mm DATA3 FIGURE 2-2: The following table details the pin definitions for the figure above. TABLE 2-2: USB3343 PIN DESCRIPTIONS Pin Name Direction/ Type Active Level 1 DIR Output, CMOS N/A Controls the direction of the data bus. When the PHY has data to transfer to the Link, it drives DIR high to take ownership of the bus. When the PHY has no data to transfer it drives DIR low and monitors the bus for commands from the Link. 2 CLKOUT Output, CMOS N/A ULPI Clock Out Mode: 60MHz ULPI clock output. All ULPI signals are driven synchronous to the rising edge of this clock. ULPI Clock In Mode: Connect this pin to VDDIO to configure 60MHz ULPI Clock IN mode as described in Section 5.5.1. 3 NXT Output, CMOS High The PHY asserts NXT to throttle the data. When the Link is sending data to the PHY, NXT indicates when the current byte has been accepted by the PHY. 4 DATA[0] I/O, CMOS N/A ULPI bi-directional data bus. DATA[0] is the LSB. 5 DATA[1] I/O, CMOS N/A ULPI bi-directional data bus. DS00002646A-page 10 Description 2009-2018 Microchip Technology Inc. USB334x TABLE 2-2: USB3343 PIN DESCRIPTIONS (CONTINUED) Pin Name Direction/ Type Active Level 6 DATA[2] I/O, CMOS N/A ULPI bi-directional data bus. 7 DATA[3] I/O, CMOS N/A ULPI bi-directional data bus. 8 DATA[4] I/O, CMOS N/A ULPI bi-directional data bus. Power N/A ULPI interface supply voltage. When RESETB is low and VDDIO is powered on, ULPI pins will tri-state. 9 VDDIO Description 10 DATA[5] I/O, CMOS N/A ULPI bi-directional data bus. 11 DATA[6] I/O, CMOS N/A ULPI bi-directional data bus. 12 DATA[7] I/O, CMOS N/A ULPI bi-directional data bus. DATA[7] is the MSB. 13 DP I/O, Analog N/A D+ pin of the USB cable. 14 DM I/O, Analog N/A D- pin of the USB cable. 15 VDD33 Power N/A 3.3V Regulator Output. A 1.0uF (<1 ohm ESR) bypass capacitor to ground is required for regulator stability. The bypass capacitor should be placed as close as possible to the USB334x. 16 VBAT Power N/A Regulator input. The regulator supply can be from 5.5V to 3.0V. 17 VBUS I/O, Analog N/A This pin is used for the VBUS comparator inputs and for VBUS pulsing during session request protocol. An external resistor, RVBUS, is required between this pin and the USB connector. 18 ID Input, Analog N/A For device applications the ID pin is connected to VDD33. For Host applications ID is grounded. For OTG applications the ID pin is connected to the USB connector. 19 RBIAS Analog, CMOS N/A Bias Resistor pin. This pin requires an 8.06k (1%) resistor to ground, placed as close as possible to the USB334x. Nominal voltage during ULPI operation is 0.8V. 20 XO Output, CMOS N/A Crystal pin. If using an external clock on REFCLK / XI, this pin should be floated. 21 REFCLK/XI Input, CMOS N/A ULPI Clock Out Mode: Model-specific reference clock or XI (crystal in) pin. See Product Identification System, Note 1. ULPI Clock In Mode: 60MHz ULPI clock input. 2009-2018 Microchip Technology Inc. DS00002646A-page 11 USB334x TABLE 2-2: USB3343 PIN DESCRIPTIONS (CONTINUED) Pin Name Direction/ Type Active Level 22 RESETB Input, CMOS, Low When low, the part is suspended and the 3.3V and 1.8V regulators are disabled. When high, the USB334x will operate as a normal ULPI device, as described in Section 5.6.2. The state of this pin may be changed asynchronously to the clock signals. When asserted for a minimum of 1 microsecond and then de-asserted, the ULPI registers are reset to their default state and all internal state machines are reset. 23 VDD18 Power N/A 1.8V Regulator Output. A 1.0uF (<1 ohm ESR) bypass capacitor to ground is required for regulator stability. The bypass capacitor should be placed as close as possible to the USB334x. 24 STP Input, CMOS High The Link asserts STP for one clock cycle to stop the data stream currently on the bus. If the Link is sending data to the PHY, STP indicates the last byte of data was on the bus in the previous cycle. FLAG GND Ground N/A Ground. DS00002646A-page 12 Description 2009-2018 Microchip Technology Inc. USB334x 3.0 LIMITING VALUES 3.1 Absolute Maximum Ratings TABLE 3-1: ABSOLUTE MAXIMUM RATINGS Parameter Symbol VBUS, VBAT, ID, DP, DM, SPK_L, and SPK_R voltage to GND VMAX_5V Maximum VDD18 voltage to Ground Conditions TYP MAX Units -0.5 +6.0 V VMAX_18V -0.5 2.5 V Maximum VDD33 voltage to Ground VMAX_33V -0.5 4.0 V Maximum VDDIO voltage to Ground (USB3343) VMAX_IOV -0.5 4.0 V Maximum I/O voltage to Ground (USB3341, USB3346, and USB3347) VMAX_IN -0.5 2.5 V Maximum I/O voltage to Ground (USB3343) VMAX_IN -0.5 VDDIO + 0.7 Operating Temperature TMAX_OP -40 85 C Storage Temperature TMAX_STG -55 150 C Note: 3.2 Voltage measured at pin. VBUS tolerant to 30V with external RVBUS. MIN Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Recommended Operating Conditions TABLE 3-2: RECOMMENDED OPERATING CONDITIONS Parameter Symbol Conditions MIN VBAT to GND VBAT 3.0 VDD33 to GND VDD33 3.0 VDD18 to GND VDD18 VDDIO to GND Input Voltage on Digital Pins (RESETB, STP, DIR, NXT, DATA[7:0]) (USB3341, USB3346, and USB3347) TYP MAX Units 5.5 V 3.3 3.6 V 1.6 1.8 2.0 V VDDIO 1.6 1.8-3.3 3.6 V VI 0.0 VDD18 V 2009-2018 Microchip Technology Inc. DS00002646A-page 13 USB334x TABLE 3-2: RECOMMENDED OPERATING CONDITIONS (CONTINUED) Parameter Symbol Conditions MIN TYP MAX Units Input Voltage on Digital Pins (RESETB, STP, DIR, NXT, DATA[7:0]) (USB3343) VI 0.0 VDDIO V Voltage on Analog I/O Pins (DP, DM, ID, SPK_L, SPK_R) VI(I/O) 0.0 VDD33 V VBUS to GND VVMAX 0.0 5.5 V Ambient Temperature TA -40 85 C 3.3 Package Thermal Specifications TABLE 3-3: PACKAGE THERMAL PARAMETERS Symbol JA JT JC Note: C/W Velocity (Meter/s) 56 0 49 1 1 0 1 1 10 0 10 1 Thermal parameters are measured or estimated for devices in a multi-layer 2S2P PCB per JESDN51. DS00002646A-page 14 2009-2018 Microchip Technology Inc. USB334x 4.0 ELECTRICAL CHARACTERISTICS The following conditions are assumed unless otherwise specified: VDD33 = 3.0 to 3.6V; VDD18 = 1.6 to 2.0V; VSS = 0V; TA = -40C to +85C 4.1 Operating Current TABLE 4-1: OPERATING CURRENT (USB3341, USB3346, AND USB3347) Parameter Symbol Conditions MIN TYP MAX Units Synchronous Mode Current (Default Configuration) IVBAT(SYNC) USB Idle 22 23 25 mA Synchronous Mode Current (HS USB operation) IVBAT(HS) Active USB Transfer 38 40 52 mA Synchronous Mode Current (FS/LS USB operation) IVBAT(FS) Active USB Transfer 29 34 43 mA Serial Mode Current (FS/LS USB) Note 4-1 IVBAT(FS_S) 6 8 9 mA USB UART Current Note 4-1 IVBAT(UART) 6 8 9 mA USB Audio Mode Note 4-2 IVBAT(AUDIO) VVBAT = 4.2V 63 71 117 uA Low Power Mode Note 4-2 IVBAT(SUSPEND) VVBAT = 4.2V 29 36 81 uA RESET Mode IVBAT(RSTB) RESETB = 0 VVBAT = 4.2V 0 1 11 uA MIN TYP MAX 18 22 24 mA 1 2 5 mA 33 35 37 mA 5 6 14 mA 25 28.5 30 mA IVIO(FS) 4 5 13 mA IVBAT(FS_S) 7 8 9 mA IVIO(FS_S) 0 0.1 0.7 mA IVBAT(UART) 7 8 9 mA IVIO(UART) 0 0.1 0.7 mA 29 32 83 uA 0 0 2 uA TABLE 4-2: OPERATING CURRENT (USB3343) Parameter Synchronous Mode Current (Default Configuration) Synchronous Mode Current (HS USB operation) Synchronous Mode Current (FS/LS USB operation) Serial Mode Current (FS/LS USB) Note 4-1 USB UART Current Note 4-1 Low Power Mode Note 4-2 Note 4-3 Symbol IVBAT(SYNC) Conditions USB Idle IVIO(SYNC) IVBAT(HS) Active USB Transfer IVIO(HS) IVBAT(FS) IVBAT(SUSPEND) IVIO(SUSPEND) 2009-2018 Microchip Technology Inc. Active USB Transfer VVBAT = 4.2V VVDDIO = 1.8V Units DS00002646A-page 15 USB334x TABLE 4-2: OPERATING CURRENT (USB3343) (CONTINUED) Parameter RESET Mode Note 4-3 Symbol Conditions IVBAT(RSTB) RESETB = 0 VVBAT = 4.2V VVDDIO = 1.8V IVIO(RSTB) MIN TYP MAX 0.1 1 12 uA 0 0 7 uA Note 4-1 ClockSuspendM bit = 0. Note 4-2 SessEnd, VbusVld, and IdFloat comparators disabled. STP Interface protection disabled. Note 4-3 REFCLK is OFF 4.2 Units Clock Specifications The model number for each frequency of REFCLK is provided in "Product Identification System", Example a. TABLE 4-3: CLOCK SPECIFICATIONS Parameter Suspend Recovery Time Symbol Conditions MIN TYP MAX Units 1.1 1.2 ms 150 uS 1.2 ms TSTART LPM Enable = 0 1.0 TSTART_LPM LPM Enable = 1 125 PHY Preparation Time 60 MHz REFCLK TPREP LPM Enable = 0 1.0 TPREP_LPM LPM Enable = 1 125 150 uS CLKOUT Duty Cycle DCCLKOUT ULPI Clock Input Mode 45 55 % REFCLK Duty Cycle DCREFCLK 20 80 % REFCLK Frequency Accuracy FREFCLK -500 +500 1.1 PPM Note: * TSTART and TPREP are measured from the time when REFCLK and RESETB are both valid to when the USB334x de-asserts DIR. * The USB334x uses the AutoResume feature, Section 6.4.1.4, "Host Resume K," on page 53, to allow a host start-up time of less than 1ms. 4.3 ULPI Interface Timing TABLE 4-4: ULPI INTERFACE TIMING Parameter Symbol Conditions MIN MAX Units Setup time (STP, data in) TSC, TSD Model-specific REFCLK 5.0 ns Hold time (STP, data in) THC, THD Model-specific REFCLK 0.0 ns Output delay (control out, 8-bit data out) TDC, TDD Model-specific REFCLK 1.5 Setup time (STP, data in) TSC, TSD 60 MHz REFCLK 3 ns Hold time (STP, data in) THC, THD 60 MHz REFCLK 0 ns Output delay (control out, 8-bit data out) TDC, TDD 60 MHz REFCLK 0.5 60 MHz ULPI Output Clock Note 4-4 6 ns 60 MHz ULPI Input Clock DS00002646A-page 16 6.0 ns 2009-2018 Microchip Technology Inc. USB334x Note: CLoad = 10pF Note 4-4 4.4 REFCLK does not need to be aligned in any way to the ULPI signals. Digital IO Pins TABLE 4-5: DIGITAL IO CHARACTERISTICS: RESETB, STP, DIR, NXT, DATA[7:0], AND REFCLK PINS Parameter Symbol Conditions MIN TYP MAX Units Low-Level Input Voltage (USB3341, USB3346, and USB3347) VIL VSS 0.4 * VDD18 V Low-Level Input Voltage (USB3343) VIL VSS 0.8 V High-Level Input Voltage (USB3341, USB3346, and USB3347) VIH 0.68 * VDD18 VDD18 V High-Level Input Voltage (USB3343) VIH 0.68 * VDDIO VDDIO V High-Level Input Voltage REFCLK and RESETB (USB3341, USB3346, and USB3347) VIH_REF 0.68 * VDD18 VDD33 V High-Level Input Voltage REFCLK and RESETB (USB3343) VIH_REF 0.68 * VDDIO VDD33 V Low-Level Output Voltage VOL IOL = 8mA 0.4 V High-Level Output Voltage (USB3341, USB3346, and USB3347) VOH IOH = -8mA VDD18 - 0.4 V High-Level Output Voltage (USB3343) VOH IOH = -8mA VDDIO 0.4 V Output rise time TIORISE CLOAD = 10pF 1.19 nS Output fall time TIOFALL CLOAD = 10pF 1.56 nS Input Leakage Current ILI Pin Capacitance Cpin STP pull-up resistance RSTP InterfaceProtectDisable = 0 55 DATA[7:0] pull-down resistance RDATA_PD ULPI Synchronous Mode 55 CLKOUT External Drive (USB3341, USB3346, and USB3347) VIH_ED CLKOUT External (USB3343) VIH_ED Drive 2009-2018 Microchip Technology Inc. 10 uA 4 pF 67 80 k 67 77 k At start-up or following reset 0.4 * VDD18 V At start-up or following reset 0.4 * VDDIO V DS00002646A-page 17 USB334x 4.5 DC Characteristics: Analog I/O Pins TABLE 4-6: DC CHARACTERISTICS: ANALOG I/O PINS (DP/DM) Parameter Symbol Conditions MIN TYP MAX Units LS/FS FUNCTIONALITY Input levels Differential Receiver Input Sensitivity VDIFS Differential Receiver Common-Mode Voltage VCMFS Single-Ended Receiver Low Level Input Voltage VILSE Note 4-6 Single-Ended Receiver High Level Input Voltage VIHSE Note 4-6 Single-Ended Receiver Hysteresis VHYSSE | V(DP) - V(DM) | 0.2 V 0.8 2.5 V 0.8 V 2.0 V 0.050 0.150 V 0.3 V 3.6 V 49.5 Output Levels Low Level Output Voltage VFSOL Pull-up resistor on DP; RL = 1.5k to VDD33 High Level Output Voltage VFSOH Pull-down resistor on DP, DM; Note 4-6 RL = 15k to GND 2.8 Driver Output Impedance for HS ZHSDRV Steady state drive 40.5 Input Impedance ZINP RX, RPU, RPD disabled 1.0 Pull-up Resistor Impedance RPU Bus Idle, Note 4-5 0.900 1.24 1.575 k Pull-up Resistor Impedance RPU Device Receiving, Note 45 1.425 2.26 3.09 k Pull-dn Resistor Impedance RPD Note 4-5 14.25 16.9 20 k HS Differential Input Sensitivity VDIHS | V(DP) - V(DM) | 100 HS Data Signaling Common Mode Voltage Range VCMHS HS Squelch Detection Threshold (Differential) VHSSQ HS Disconnect Threshold VHSDSC Termination 45 M HS FUNCTIONALITY Input levels VariSense[1:0] = 00b Note 4-7 mV -50 500 mV 100 150 mV 525 625 mV -10 10 mV Output Levels High Speed Low Level Output Voltage (DP/DM referenced to GND) DS00002646A-page 18 VHSOL 45 load 2009-2018 Microchip Technology Inc. USB334x TABLE 4-6: DC CHARACTERISTICS: ANALOG I/O PINS (DP/DM) (CONTINUED) Parameter Symbol Conditions MIN TYP MAX Units High Speed High Level Output Voltage (DP/DM referenced to GND) VHSOH 45 load 360 440 mV High Speed IDLE Level Output Voltage (DP/DM referenced to GND) VOLHS 45 load -10 10 mV Chirp-J Output Voltage (Differential) VCHIRPJ HS termination resistor disabled, pull-up resistor connected. 45 load. 700 1100 mV Chirp-K Output Voltage (Differential) VCHIRPK HS termination resistor disabled, pull-up resistor connected. 45 load. -900 -500 mV 10 uA 10 pF Leakage Current OFF-State Leakage Current ILZ Port Capacitance Transceiver Input Capacitance CIN Pin to GND 5 Note 4-5 The resistor value follows the 27% Resistor ECN published by the USB-IF. Note 4-6 The values shown are valid when the USB RegOutput bits in the USB IO & Power Management register are set to the default value. Note 4-7 An automatic waiver up to 200mV is granted to accommodate system-level elements such as measurement/test fixtures, captive cables, EMI components, and ESD suppression. This parameter can be tuned using VariSense technology, as defined in Section 7.1.3.1, "HS Compensation Register," on page 72 of Section 7.0, ULPI Register Map. 4.6 Dynamic Characteristics: Analog I/O Pins TABLE 4-7: DYNAMIC CHARACTERISTICS: ANALOG I/O PINS (DP/DM) Parameter Symbol Conditions MIN TYP MAX Units FS Output Driver Timing FS Rise Time TFR CL = 50pF; 10 to 90% of |VOH - VOL| 4 20 ns FS Fall Time TFF CL = 50pF; 10 to 90% of |VOH - VOL| 4 20 ns Output Signal Crossover Voltage VCRS Excluding the first transition from IDLE state 1.3 2.0 V Differential Rise/Fall Time Matching TFRFM Excluding the first transition from IDLE state 90 111.1 % TLR CL = 50-600pF; 10 to 90% of |VOH - VOL| 75 300 ns LS Output Driver Timing LS Rise Time 2009-2018 Microchip Technology Inc. DS00002646A-page 19 USB334x TABLE 4-7: DYNAMIC CHARACTERISTICS: ANALOG I/O PINS (DP/DM) (CONTINUED) Parameter Symbol Conditions MIN TYP MAX Units LS Fall Time TLF CL = 50-600pF; 10 to 90% of |VOH - VOL| 75 300 ns Differential Rise/Fall Time Matching TLRFM Excluding the first transition from IDLE state 80 125 % HS Output Driver Timing Differential Rise Time THSR 500 ps Differential Fall Time THSF 500 ps Driver Waveform Requirements Eye pattern of Template 1 in USB 2.0 specification High Speed Mode Timing Receiver Waveform Requirements Eye pattern of Template 4 in USB 2.0 specification Data Source Jitter and Receiver Jitter Tolerance Eye pattern of Template 4 in USB 2.0 specification 4.7 VBUS Electrical Characteristics TABLE 4-8: VBUS ELECTRICAL CHARACTERISTICS Parameter Symbol Conditions MIN TYP MAX Units SessEnd trip point VSessEnd 0.2 0.5 0.8 V SessVld trip point VSessVld 0.8 1.4 2.0 V VbusVld trip point VVbusVld 4.4 4.58 4.75 V VBUS Pull-Up RVPU VBUS to VDD33 Note 4-8 (ChargeVbus = 1) 1.29 1.34 1.45 k VBUS Pull-down RVPD VBUS to GND Note 4-8 (DisChargeVbus = 1) 1.55 1.7 1.85 k VBUS Impedance RVB VBUS to GND 40 75 100 k A-Device Impedance to ground RIdGnd Maximum Impedance to ground on ID pin 100 k Note 4-8 The RVPD and RVPU values include the required 1k external RVBUS resistor. DS00002646A-page 20 2009-2018 Microchip Technology Inc. USB334x 4.8 ID Electrical Characteristics TABLE 4-9: ID ELECTRICAL CHARACTERISTICS Parameter Symbol Conditions MIN TYP MAX Units ID Ground Trip Point VIdGnd 0.4 0.7 0.9 V ID Float Trip Point VIdFloat 1.6 2.2 2.5 V ID pull-up resistance RID IdPullup = 1 80 100 120 k ID weak pull-up resistance RIDW IdPullup = 0 1 ID pull-dn resistance RIDPD IdGndDrv = 1 4.9 M 1000 USB Audio Switch Characteristics TABLE 4-10: USB AUDIO SWITCH CHARACTERISTICS Parameter Symbol Conditions MIN TYP MAX Units Minimum "ON" Resistance RON_Min 0 < Vswitch < VDD33 2.7 5 5.8 Maximum "ON" Resistance RON_Max 0 < Vswitch < VDD33 4.5 7 13 Minimum "OFF" Resistance ROFF_Min 0 < Vswitch < VDD33 1 4.10 M USB Charger Detection Characteristics TABLE 4-11: USB CHARGER DETECTION CHARACTERISTICS Parameter Symbol Data Source Voltage VDAT_SRC Data Detect Voltage Conditions TYP MAX Units 0.5 0.7 V VDAT_REF 0.25 0.4 V Data Source Current IDAT_SRC 250 Data Sink Current IDAT_SINK 50 150 uA Data Connect Current IDP_SRC 7 13 uA Weak Pull-up Resistor Impedance RCD 2009-2018 Microchip Technology Inc. IDAT_SRC < 250uA MIN Configured by bits 4 and 5 in USB IO & Power Management register. 128 uA 170 212 k DS00002646A-page 21 USB334x 4.11 Regulator Output Voltages and Capacitor Requirement TABLE 4-12: REGULATOR OUTPUT VOLTAGES AND CAPACITOR REQUIREMENT Parameter Regulator Output Voltage Symbol VDD33 Regulator Bypass Capacitor COUT33 Bypass Capacitor ESR CESR33 Regulator Output Voltage VDD18 Regulator Bypass Capacitor COUT18 Bypass Capacitor ESR CESR18 4.12 Conditions MIN TYP MAX 5.5V > VBAT > 3.0V 2.8 3.3 3.6 V USB UART Mode & UART RegOutput[1:0] = 01 6V > VBAT > 3.0V 2.7 3.0 3.3 V USB UART Mode & UART RegOutput[1:0] = 10 6V > VBAT > 3.0V 2.47 2.75 3.03 V USB UART Mode & UART RegOutput[1:0] = 11 6V > VBAT > 3.0V 2.25 2.5 2.75 V 1.0 3.6V > VDD33 > 2.25V Units F 1.6 1.8 1 2.0 V 1.0 F 1 Piezoelectric Resonator for Internal Oscillator The internal oscillator may be used with an external quartz crystal or ceramic resonator as described in Section 5.4, "Crystal Reference Support (USB3343 only)," on page 28. See Table 4-13 for the recommended crystal specifications. TABLE 4-13: USB334X QUARTZ CRYSTAL SPECIFICATIONS Parameter Symbol MIN Crystal Cut NOM MAX Units Notes AT, typ Crystal Oscillation Mode Fundamental Mode Crystal Calibration Mode Parallel Resonant Mode Frequency Ffund Total Allowable PPM Budget - See Example a on page 79 - MHz - - 500 PPM Note 4-9 Shunt Capacitance CO - 7 typ - pF Load Capacitance CL - 20 typ - pF Drive Level PW 0.1 - - W Equivalent Series Resistance R1 - - 30 USB334x REFCLK Pin Capacitance - 3 typ - pF Note 4-10 USB334x XO Pin Capacitance - 3 typ - pF Note 4-10 Note 4-9 The required bit rate accuracy for Hi-Speed USB applications is 500 ppm as provided in the USB 2.0 Specification. This takes into account the effect of voltage, temperature, aging, etc. DS00002646A-page 22 2009-2018 Microchip Technology Inc. USB334x Note 4-10 4.13 This number includes the pad, the bond wire and the lead frame. Printed Circuit Board (PCB) capacitance is not included in this value. The PCB capacitance value and the capacitance value of the XO and REFCLK pins are required to accurately calculate the value of the two external load capacitors. ESD and Latch-Up Performance TABLE 4-14: Parameter ESD AND LATCH-UP PERFORMANCE Conditions MIN TYP MAX Units Comments ESD PERFORMANCE Note 4-11 Human Body Model 8 kV Device System EN/IEC 61000-4-2 Contact Discharge 25 kV 3rd party system test System EN/IEC 61000-4-2 Air-gap Discharge 25 kV 3rd party system test LATCH-UP PERFORMANCE All Pins Note 4-11 EIA/JESD 78, Class II 150 mA REFCLK, XO (USB3343 only), ID, RESETB, SPK_L (USB3341, USB3346, and USB3347 only) and SPK_R (USB3341, USB3346, and USB3347 only) pins: 5kV Human Body Model. 2009-2018 Microchip Technology Inc. DS00002646A-page 23 USB334x 5.0 ARCHITECTURE OVERVIEW The USB334x consists of the blocks shown in the diagrams below. FIGURE 5-1: USB334X SYSTEM DIAGRAM (USB3341, USB3346, AND USB3347) VDD18 Digital IO VDD33 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 STP NXT DIR CLKOUT RESETB HS/FS/LS TX Encoding Integrated Low Jitter PLL REFCLK HS/FS/LS RX Decoding BIAS RID IdFloat Rid Value VDD33 SessValid RVPD LDO ULPI Digitial VbusValid Charger Detection RPU VDD33 RPU RCD VDD33 RCD VDD18 ESD Protection LDO RVB VBAT VDD33 SessEnd RX Data RVPU OVP VBUS TX Data ID OTG Module RIDW IdGnd TX DP RPD SPK_L RPD DM RX RBIAS SPK_R DS00002646A-page 24 2009-2018 Microchip Technology Inc. USB334x FIGURE 5-2: USB334X SYSTEM DIAGRAM (USB3343) VDD33 RID Rid Value VDD33 SessValid RVPD LDO ULPI Digitial VbusValid Charger Detection RPU VDD33 RPU RCD VDD33 RCD VDD18 ESD Protection LDO RVB VBAT VDD33 SessEnd VDDIO DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 STP NXT DIR CLKOUT RESETB RX Data RVPU OVP TX Data VBUS Digital IO IdFloat ID OTG Module RIDW IdGnd TX DP HS/FS/LS TX Encoding Integrated Low Jitter PLL HS/FS/LS RX Decoding BIAS REFCLK / XI XO 5.1 RPD RPD DM RX RBIAS ULPI Digital Operation and Interface This section of the USB334x is covered in detail in Section 6.0, "ULPI Operation". 5.2 USB 2.0 Hi-Speed Transceiver The blocks in the lower left-hand corner of interface to the DP/DM pins. 5.2.1 USB TRANSCEIVER The USB334x transceiver includes a Universal Serial Bus Specification Rev 2.0 compliant receiver and transmitter. The DP/DM signals in the USB cable connect directly to the receivers and transmitters. The receiver consists of receivers for HS and FS/LS mode. Depending on the mode, the selected receiver provides the serial data stream through the multiplexer to the RX Logic block. For HS mode support, the HS RX block contains a squelch circuit to insure that noise is not interpreted as data. The RX block also includes a single-ended receiver on each of the data lines to determine the correct FS linestate. Data from the Link is encoded, bit stuffed, serialized and transmitted onto the USB cable by the transmitter. Separate differential FS/LS and HS transmitters are included to support all modes. The USB334x TX block meets the HS signaling level requirements in the USB 2.0 Specification when the PCB traces from the DP and DM pins to the USB connector are correctly designed. In some systems the proper 90 differential impedance can not be maintained and it may be desirable to compensate for loss by adjusting the HS transmitter amplitude and this HS squelch threshold. The PHYBoost bits in the HS Compensation Register may be configured to adjust the HS transmitter amplitude at the DP and DM pins. The VariSense bits in the HS Compensation Register can also be used to lower the squelch threshold to compensate for losses on the PCB. To ensure proper operation of the USB transceiver the settings of Table 5-1 must be followed. 2009-2018 Microchip Technology Inc. DS00002646A-page 25 USB334x 5.2.2 TERMINATION RESISTORS The USB334x transceiver fully integrates all of the USB termination resistors on both DP and DM. This includes 1.5k pull-up resistors, 15k pull-down resistors and the 45 High Speed termination resistors. These resistors require no tuning or trimming by the Link. The state of the resistors is determined by the operating mode of the transceiver when operating in synchronous mode. The XcvrSelect[1:0], TermSelect and OpMode[1:0] bits in the Function Control register, and the DpPulldown and DmPulldown bits in the OTG Control register control the configuration of the termination resistors. All possible valid resistor combinations are shown in Table 5-1, and operation is supported in only the configurations shown. If a ULPI Register Setting is configured that does not match a setting in the table, the transceiver operation is not maintained and the settings in the last row of Table 5-1 will be used. * * * * * RPU_DP_EN activates the 1.5k DP pull-up resistor RPU_DM_EN activates the 1.5k DM pull-up resistor RPD_DP_EN activates the 15k DP pull-down resistor RPD_DM_EN activates the 15k DM pull-down resistor HSTERM_EN activates the 45 DP and DM High Speed termination resistors TABLE 5-1: DP/DM TERMINATION VS. SIGNALING MODE USB334x Termination Resistor Settings RPU_DM_EN RPD_DP_EN RPD_DM_EN HSTERM_EN 01b Xb Xb 0b 0b 0b 0b 0b Power-up or VBUS < VSESSEND 01b 0b 00b 1b 1b 0b 0b 1b 1b 0b Host Chirp 00b 0b 10b 1b 1b 0b 0b 1b 1b 1b Host High Speed 00b 0b 00b 1b 1b 0b 0b 1b 1b 1b Host Full Speed X1b 1b 00b 1b 1b 0b 0b 1b 1b 0b Host HS/FS Suspend 01b 1b 00b 1b 1b 0b 0b 1b 1b 0b Host HS/FS Resume 01b 1b 10b 1b 1b 0b 0b 1b 1b 0b Host Low Speed 10b 1b 00b 1b 1b 0b 0b 1b 1b 0b Host LS Suspend 10b 1b 00b 1b 1b 0b 0b 1b 1b 0b Host LS Resume 10b 1b 10b 1b 1b 0b 0b 1b 1b 0b Host Test J/Test_K 00b 0b 10b 1b 1b 0b 0b 1b 1b 1b Peripheral Chirp 00b 1b 10b 0b 0b 1b 0b 0b 0b 0b Peripheral HS 00b 0b 00b 0b 0b 0b 0b 0b 0b 1b Peripheral FS 01b 1b 00b 0b 0b 1b 0b 0b 0b 0b DmPulldown Xb DpPulldown XXb OpMode[1:0] Tri-State Drivers, Note 5-1 Signaling Mode TermSelect RPU_DP_EN XcvrSelect[1:0] ULPI Register Settings General Settings Host Settings Peripheral Settings DS00002646A-page 26 2009-2018 Microchip Technology Inc. USB334x TABLE 5-1: DP/DM TERMINATION VS. SIGNALING MODE (CONTINUED) USB334x Termination Resistor Settings RPU_DM_EN RPD_DP_EN RPD_DM_EN HSTERM_EN 00b 0b 0b 1b 0b 0b 0b 0b Peripheral HS/FS Resume 01b 1b 10b 0b 0b 1b 0b 0b 0b 0b Peripheral LS 10b 1b 00b 0b 0b 0b 1b 0b 0b 0b Peripheral LS Suspend 10b 1b 00b 0b 0b 0b 1b 0b 0b 0b Peripheral LS Resume 10b 1b 10b 0b 0b 0b 1b 0b 0b 0b Peripheral Test J/Test K 00b 0b 10b 0b 0b 0b 0b 0b 0b 1b OTG device, Peripheral Chirp 00b 1b 10b 0b 1b 1b 0b 0b 1b 0b OTG device, Peripheral HS 00b 0b 00b 0b 1b 0b 0b 0b 1b 1b OTG device, Peripheral FS 01b 1b 00b 0b 1b 1b 0b 0b 1b 0b OTG device, Peripheral HS/FS Suspend 01b 1b 00b 0b 1b 1b 0b 0b 1b 0b OTG device, Peripheral HS/FS Resume 01b 1b 10b 0b 1b 1b 0b 0b 1b 0b OTG device, Peripheral Test J/Test K 00b 0b 10b 0b 1b 0b 0b 0b 1b 1b 01b 0b 00b 0b 1b 0b 0b 0b 1b 0b 0b 0b 1b 1b 0b DmPulldown 1b DpPulldown 01b OpMode[1:0] Peripheral HS/FS Suspend Signaling Mode TermSelect RPU_DP_EN XcvrSelect[1:0] ULPI Register Settings Charger Detection Connect Detect Any combination not defined above, Note 5-2 Note: * This is equivalent to Table 40, Section 4.4 of the ULPI 1.1 specification. * USB334x does not support operation as an upstream hub port. See Section 6.4.1.3, "UTMI+ Level 3," on page 53. Note 5-1 When RESETB = 0 The HS termination will tri-state the USB drivers Note 5-2 The transceiver operation is not maintained in a combination that is not defined. The USB334x uses the 27% resistor ECN resistor tolerances. The resistor values are shown in Table 4-6. 5.3 Bias Generator This block consists of an internal bandgap reference circuit used for generating the driver current and the biasing of the analog circuits. This block requires an external 8.06K,1% tolerance, reference resistor connected from RBIAS to ground. This resistor should be placed as close as possible to the USB334x to minimize the trace length. The nominal voltage at RBIAS is 0.8V +/- 10% and therefore the resistor will dissipate approximately 80 W of power. 2009-2018 Microchip Technology Inc. DS00002646A-page 27 USB334x 5.4 Crystal Reference Support (USB3343 only) The USB3343 provide support for a 26 MHz crystal to provide the reference frequency required by the device in place of a clock oscillator. The crystal should be connected to the REFCLK/XI and XO pins as shown in Figure 8-2. If a 26 MHz clock oscillator is used in place of a crystal, it should be driven into the REFCLK/XI pin, and the XO pin should be left floating. Proper care should be taken to ensure that a crystal is selected with appropriate power dissipation characteristics. 5.5 Integrated Low Jitter PLL The USB334x uses an integrated low jitter phase locked loop (PLL) to provide a clean 480 MHz clock required for HS USB signal quality. This clock is used by the PHY during both transmit and receive. The USB334x PLL requires an accurate frequency reference to be driven on the REFCLK pin. 5.5.1 REFCLK FREQUENCY SELECTION The USB334x PLL is designed to operate in one of two reference clock modes. In the first mode, the 60 MHz ULPI clock is driven on the REFCLK pin. In the second mode a reference clock is driven on the REFCLK pin. The Link is driving the ULPI clock, in the first mode, and this is referred to as ULPI Clock Input Mode. In the second mode, the USB334x generates the ULPI clock, and this is referred to as ULPI Clock Output Mode. During start-up, the USB334x monitors the CLKOUT pin. If a connection to VDD18 (USB3341, USB3346, and USB3347) or VDDIO (USB3343) is detected, the USB334x is configured for a 60 MHz ULPI reference clock driven on the REFCLK pin. Section 5.5.1.1, "ULPI Clock Input Mode (60 MHz REFCLK Mode)," on page 28 and Section 5.5.1.2, "ULPI Clock Output Mode," on page 29 describe how to configure the USB334x for either ULPI Clock Input Mode or ULPI Clock Output Mode. 5.5.1.1 ULPI Clock Input Mode (60 MHz REFCLK Mode) When using ULPI Clock Input Mode, the Link must supply the 60 MHz ULPI clock to the USB334x. In this mode the 60 MHz ULPI Clock is connected to the REFCLK pin, and the CLKOUT pin is tied high to VDD18 (USB3341, USB3346, and USB3347) or VDDIO(USB3343). After the PLL has locked to the correct frequency, the USB334x will de-assert DIR and the Link can begin using the ULPI interface. The USB334x will start the clock within the time specified in Table 4-3. For Host applications, the ULPI AutoResume bit should be enabled. This is described in Section 6.4.1.4, "Host Resume K," on page 53. FIGURE 5-3: CONFIGURING THE USB334X FOR ULPI CLOCK INPUT MODE (60 MHZ) VDD18/ VDDIO ~~ CLKOUT ULPI Clk Out REFCLK To PLL Link Reference Clk In DS00002646A-page 28 ~~ Clock Source SMSC PHY 2009-2018 Microchip Technology Inc. USB334x 5.5.1.2 ULPI Clock Output Mode When using ULPI Clock Output Mode, the USB334x generates the 60 MHz ULPI clock used by the Link. In this mode, the REFCLK pin must be driven with the model-specific frequency, and the CLKOUT pin sources the 60 MHz ULPI clock to the Link. When using ULPI Clock Output Mode, the system must not drive the CLKOUT pin following POR or hardware reset with a voltage that exceeds the value of VIH_ED provided in Table 4-4. An example of ULPI Clock Output Mode is shown in Figure 8-1 After the PLL has locked to the correct frequency, the USB334x generates the 60 MHz ULPI clock on the CLKOUT pin, and de-asserts DIR to indicate that the PLL is locked. The USB334x will start the clock within the time specified in Table 4-3, and it will be accurate to within 500ppm. For Host applications the ULPI AutoResume bit should be enabled. This is described in Section 6.4.1.4, "Host Resume K," on page 53. When using ULPI Clock Output Mode, the edges of the reference clock do not need to be aligned in any way to the ULPI interface signals. There is no need to align the phase of the REFCLK and the CLKOUT. For the USB3341, USB3343, USB3346, and USB3347, the reference clock frequency required is shown in the Product Identification System section. FIGURE 5-4: CONFIGURING THE USB334X FOR ULPI CLOCK OUTPUT MODE ~~ ULPI Clk In CLKOUT From PLL Link Clock Source REFCLK To PLL ~~ 5.5.2 MCHP PHY REFCLK AMPLITUDE The reference clock should be connected to the REFCLK pin as shown in the application diagrams, . The REFCLK pin is designed to be driven with a square wave from 0V to VDD18 (USB3341, USB3346, and USB3347) or VDDIO (USB3343), but can be driven with a square wave from 0V to as high as 3.6V. The USB334x uses only the positive edge of the REFCLK. If a digital reference is not available, the REFCLK pin can be driven by an analog sine wave that is AC coupled into the REFCLK pin. If using an analog clock the DC bias should be set at the mid-point of the VDD18 supply using a bias circuit as shown in Figure 5-5. The amplitude must be greater than 300mV peak to peak. The component values provided in Figure 5-5 are for example only. The actual values should be selected to satisfy system requirements. The REFCLK amplitude must comply with the signal amplitudes shown in Table 4-5 and the duty cycle in Table 4-3. 2009-2018 Microchip Technology Inc. DS00002646A-page 29 USB334x FIGURE 5-5: EXAMPLE OF CIRCUIT USED TO SHIFT A REFERENCE CLOCK COMMONMODE VOLTAGE LEVEL 47k 1.8V Supply To REFCLK pin 0.1uF 5.5.3 47k Clock REFCLK JITTER The USB334x is tolerant to jitter on the reference clock. The REFCLK jitter should be limited to a peak to peak jitter of less than 1nS over a 10uS time interval. If this level of jitter is exceeded when configured for either ULPI Clock Input Mode or ULPI Clock Output Mode, the USB334x High Speed eye diagram may be degraded. The frequency accuracy of the REFCLK must meet the +/- 500ppm requirement as shown in Table 4-3. 5.5.4 REFCLK ENABLE/DISABLE The REFCLK should be enabled when the RESETB pin is brought high. The ULPI interface will start running after the time specified in Table 4-3. If the reference clock enable is delayed relative to the RESETB pin, the ULPI interface will start operation delayed by the same amount. The reference clock can be run at anytime the RESETB pin is low without causing the USB334x to start-up or draw current. When the USB334x is placed in Low Power Mode or Carkit Mode, the reference clock can be stopped after the final ULPI register write is complete. The STP pin is asserted to bring the USB334x out of Low Power Mode. The reference clock should be started at the same time STP is asserted to minimize the USB334x start-up time. If the reference clock is stopped while in ULPI Synchronous mode the PLL will come out of lock and the frequency of oscillation will decrease to the minimum allowed by the PLL design. If the reference clock is stopped during a USB session, the session may drop. 5.6 Internal Regulators and POR The USB334x includes integrated power management functions, including a Low-Dropout regulator that can be used to generate the 3.3V USB supply, an integrated 1.8V regulator, and a POR generator described in Section 5.6.2, "Power On Reset (POR)," on page 31. 5.6.1 INTEGRATED LOW DROPOUT REGULATORS The USB334x includes two integrated linear regulators. Power sourced at the VBAT pin is regulated to 3.3V and 1.8V output on the VDD33 and VDD18 pins. To ensure stability, both regulators require an external bypass capacitor as specified in Table 4-12 placed as close to the pin as possible. The USB334x regulators are designed to generate the 3.3 Volt and 1.8 Volt supplies for the USB334x only. Using the regulators to provide current for other circuits is not recommended and Microchip does not ensure USB performance or regulator stability. During USB UART mode the 3.3V regulator output voltage can be changed to allow the USB334x to work with UARTs operating at different operating voltages. The 3.3V regulator output is configured to the voltages shown in Table 4-12 with the UART RegOutput[1:0] bits in the USB IO & Power Management register. The regulators are enabled by the RESETB pin. When RESETB pin is low both regulators are disabled and the regulator outputs are pulled low by weak pull-down. The RESETB pin must be brought high to enable the regulators. DS00002646A-page 30 2009-2018 Microchip Technology Inc. USB334x For peripheral-only or host-only bus-powered applications, the input to VBAT may be derived from the VBUS pin of the USB connector. In this configuration, the supply must be capable of withstanding any transient voltage present at the VBUS pin of the USB connector. Microchip does not recommend connecting the VBAT pin to the VBUS terminal of the USB connector. 5.6.2 POWER ON RESET (POR) The USB334x provides a POR circuit that generates an internal reset pulse after the VDD18 supply is stable. After the internal POR goes high the USB334x will release from reset and begin normal ULPI operation as described in Note 5-3. The ULPI registers will power up in their default state summarized in Table 7-1 when the 1.8V supply comes up. Cycling the RESETB pin can also be used to reset the ULPI registers to their default state (and reset all internal state machines) by bringing the pin low for a minimum of 1 microsecond and then high. It is not necessary to wait for the VDD33 and VDD18 pins to discharge to 0 volts to reset the part. The RESETB pin must be pulled high to enable the 3.3V and 1.8V regulators. A pull-down resistor is not present on the RESETB pin and therefore the system should drive the RESETB pin to the desired state at all times. If the system does not need to place the USB334x into reset mode the RESETB pin can be connected to a supply between 1.8V and 3.3V. 5.6.3 RECOMMENDED POWER SUPPLY SEQUENCE For USB operation, the USB334x requires a valid voltage on the VBAT and VDDIO pins. The VDD33 and VDD18 regulators are automatically enabled when the RESETB pin is brought high. Table 5-2 presents the power supply configurations in more detail. The RESETB pin can be held low until the VBAT supply is stable. If the Link is not ready to interface the USB334x, the Link may choose to hold the RESETB pin low until it is ready to control the ULPI interface. TABLE 5-2: OPERATING MODE VS. POWER SUPPLY CONFIGURATION VBAT VDDIO (Note 5-4) RESETB 0 0 0 Powered Off 1 X 0 RESET Mode. (Note 5-3) 1 1 1 Full USB operation as described in Section 6.0, "ULPI Operation," on page 42. Operating Modes Available Note 5-3 VDDIO must be present for ULPI pins to tri-state. Note 5-4 USB3343 only. 5.6.4 START-UP The power on default state of the USB334x is ULPI Synchronous mode. The USB334x requires the following conditions to begin operation: the power supplies must be stable, the REFCLK must be present and the RESETB pin must be high. After these conditions are met, the USB334x will begin ULPI operation that is described in Section 6.0, "ULPI Operation," on page 42. Figure 5-6 below shows a timing diagram to illustrate the start-up of the USB334x. At T0, the supplies are stable and the USB334x is held in reset mode. At T1, the Link drives RESETB high after the REFCLK has started. The RESETB pin may be brought high asynchronously to REFCLK. Once, the 3.3V and 1.8V internal supplies become stable the USB334x will apply the 15 K pull downs to the data bus and assert DIR until the internal PLL has locked. After the PLL has locked, the USB334x will check that the Link has de-asserted STP and at T2 it will de-assert DIR and begin ULPI operation. The ULPI bus will be available as shown in Figure 5-6 in the time defined as TSTART given in Table 4-3. If the REFCLK signal starts after the RESETB pin is brought high, then time T0 will begin when REFCLK starts. TSTART also assumes that the Link has de-asserted STP. If the Link has held STP high the USB334x will hold DIR high until STP is deasserted. When the LINK de-asserts STP, it must be ready drive the ULPI data bus to idle (00h) for a minimum of one clock cycle after DIR de-asserts. 2009-2018 Microchip Technology Inc. DS00002646A-page 31 USB334x FIGURE 5-6: ULPI START-UP TIMING T0 SUPPLIES STABLE T1 REFCLK T2 REFCLK valid RESETB DATA[7:0] PHY Tri-States PHY Drives Idle DIR PHY Tri-States PHY Drives High STP IDLE RXCMD IDLE LINK Drives Low TSTART 5.7 USB On-The-Go (OTG) The USB334x provides support for the USB OTG protocol. OTG allows the USB334x to be dynamically configured as a host or peripheral depending on the type of cable inserted into the Micro-AB receptacle. When the Micro-A plug of a cable is inserted into the Micro-AB receptacle, the USB device becomes the A-device. When a Micro-B plug is inserted, the device becomes the B-device. The OTG A-device behaves similar to a Host while the B-device behaves similar to a peripheral. The differences are covered in the "On-The-Go Supplement to the USB 2.0 Specification". In applications where only USB Host or USB Peripheral is required, the OTG Module is unused. 5.7.1 ID RESISTOR DETECTION The ID pin of the USB connector is monitored by the ID pin of the USB334x to detect the attachment of different types of USB devices and cables. For device only applications that do not use the ID signal the ID pin should be connected to VDD33. The block diagram of the ID detection circuitry is shown in Figure 5-7 and the related parameters are given in Table 4-9. DS00002646A-page 32 2009-2018 Microchip Technology Inc. USB334x FIGURE 5-7: USB334X ID RESISTOR DETECTION CIRCUITRY ~~ VDD33 ID RID=100K RIDW>1M IdPullup To USB Con. IdGnd Vref IdGnd en IdGndDrv IdFloat Vref IdFloat en Rid ADC ~~ 5.7.1.1 IdGnd Rise or IdGnd Fall IdFloatRise or IdFloatFall RidValue OTG Module USB OTG Operation The USB334x can detect ID grounded and ID floating to determine if an A or B cable has been inserted. The A plug will ground the ID pin while the B plug will float the ID pin. These are the only two valid states allowed in the OTG Protocol. To monitor the status of the ID pin, the Link activates the IdPullup bit in the OTG Control register, waits 50mS and then reads the status of the IdGnd bit in the USB Interrupt Status register. If an A cable has been inserted the IdGnd bit will read 0. If a B cable is inserted, the ID pin is floating and the IdGnd bit will read 1. The USB334x provides an integrated weak pull-up resistor on the ID pin, RIDW. This resistor is present to keep the ID pin in a known state when the IdPullup bit is disabled and the ID pin is floated. In addition to keeping the ID pin in a known state, it enables the USB334x to generate an interrupt to inform the link when a cable with a resistor to ground has been attached to the ID pin. The weak pull-up is small enough that the largest valid RID resistor pulls the ID pin low and causes the IdGnd comparator to go low. After the link has detected an ID pin state change, the RID converter can be used to determine the resistor value as described in Section 5.7.1.2, "Measuring ID Resistance to Ground," on page 33. 5.7.1.2 Measuring ID Resistance to Ground The Link can use the integrated resistance measurement capabilities of the USB334x to determine the value of an ID resistance to ground. The following table details the valid values of resistance to ground that the USB334x can detect. 2009-2018 Microchip Technology Inc. DS00002646A-page 33 USB334x TABLE 5-3: Note: VALID VALUES OF ID RESISTANCE TO GROUND ID Resistance to Ground Rid Value Ground 000 75 +/-1% 001 102k +/-1% 010 200k+/-1% 011 Floating 101 IdPullUp = 0 The ID resistance to ground can be read while the USB334x is in Synchronous Mode. When a resistor to ground is attached to the ID pin, the state of the IdGnd comparator will change. After the Link has detected ID transition to ground, it can use the methods described in Section 6.8, "RID Converter Operation," on page 61 to operate the Rid converter. 5.7.1.3 Note: Using IdFloat Comparator (not recommended) The ULPI specification details a method to detect a 102 k resistance to ground using the IdFloat comparator. This method can only detect 0, 102 k, and floating terminations of the ID pin. Due to this limitation it is recommended to use the RID Converter as described in Section 5.7.1.2, "Measuring ID Resistance to Ground," on page 33. The ID pin can be either grounded, floated, or connected to ground with a 102 k external resistor. To detect the 102K resistor, set the idPullup bit in the OTG Control register, causing the USB334x to apply the 100K internal pull-up connected between the ID pin and VDD33. Set the idFloatRise and idFloatFall bits in the Carkit Interrupt Enable register to enable the IdFloat comparator to generate an RXCMD to the Link when the state of the IdFloat changes. As described in Figure 6-3, the alt_int bit of the RXCMD will be set. The values of IdGnd and IdFloat are shown for the three types cables that can attach to the USB Connector in Table 5-4. TABLE 5-4: Note: IDGND AND IDFLOAT VS. ID RESISTANCE TO GROUND ID Resistance IDGND IDFLOAT Float 1 1 102K 1 0 GND 0 0 The ULPI register bits IdPullUp, IdFloatRise, and IdFloatFall should be enabled. To save current when an A Plug is inserted, the internal 102k pull-up resistor can be disabled by clearing the IdPullUp bit in the OTG Control register and the IdFloatRise and IdFloatFall bits in both the USB Interrupt Enable Rising and USB Interrupt Enable Falling registers. If the cable is removed the weak RIDW will pull the ID pin high. The IdGnd value can be read using the ULPI USB Interrupt Status register, bit 4. In host mode, it can be set to generate an interrupt when IdGnd changes by setting the appropriate bits in the USB Interrupt Enable Rising and USB Interrupt Enable Falling registers. The IdFloat value can be read by reading the ULPI Carkit Interrupt Status register bit 0. DS00002646A-page 34 2009-2018 Microchip Technology Inc. USB334x Note: 5.7.2 The IdGnd switch has been provided to ground the ID pin for future applications. VBUS MONITORING AND VBUS PULSING The USB334x includes all of the VBUS comparators required for OTG. The VBUSVld, SessVld, and SessEnd comparators shown in Figure 5-8 are fully integrated into the USB334x. These comparators are used to monitor changes in the VBUS voltage, and the state of each comparator can be read from the USB Interrupt Status register. The VbusVld comparator is used by the Link, when configured as an A device, to ensure that the VBUS voltage on the cable is valid. The SessVld comparator is used by the Link when configured as both an A or B device to indicate a session is requested or valid. Finally the SessEnd comparator is used by the B-device to indicate a USB session has ended. Also included in the VBUS Monitor and Pulsing block are the resistors used for VBUS pulsing in SRP. The resistors used for VBUS pulsing include a pull-down to ground and a pull-up to VDD33. In some applications, voltages much greater than 5.5V may be present at the VBUS pin of the USB connector. The USB334x includes an over voltage protection circuit that protects the VBUS pin of the USB334x from excessive voltages as shown in Figure 5-8. FIGURE 5-8: USB334X OTG VBUS BLOCK ~~ VDD33 ChrgVbus 0.5V SessEnd RVPU en RVPD RVBUS 1.4V RVB To USB Con. SessValid VBUS Overvoltage Protection VBUS SessEnd Rise or SessEnd Fall VbusValid 4.575V DischrgVbus en VbusValid Rise or VbusValid Fall [0, X] [1, 0] EXTVBUS (logic 1) IndicatorComplement RXCMD VbusValid [1, 1] [UseExternalVbusindicator, IndicatorPassThru] ~~ 5.7.2.1 MCHP PHY SessEnd Comparator The SessEnd comparator is used during the Session Request Protocol (SRP). The comparator is used by the B-device to detect when a USB session has ended and it is safe to start Vbus Pulsing to request a USB session from the A-device. When VBUS goes below the threshold in Table 4-8, the USB session is considered to be ended, and SessEnd will transition from 0 to 1. The SessEnd comparator can be disabled by clearing this bit in both the USB Interrupt Enable Rising and USB Interrupt Enable Falling registers. When disabled, the SessEnd bit in the USB Interrupt Status register will read 0. 2009-2018 Microchip Technology Inc. DS00002646A-page 35 USB334x The SessEnd Comparator is only used when configured as an OTG device. If the USB334x is used as a Host or Device only the SessEnd Comparator should be disabled, using the method described above. 5.7.2.2 SessVld Comparator The SessVld comparator is used when the PHY is configured as both an A and B device. When configured as an A device, the SessVld is used to detect Session Request protocol (SRP). When configured as a B device, SessVld is used to detect the presence of VBUS. The SessVld comparator output can also be read from the USB Interrupt Status register. The SessVld comparator will also generate an RX CMD, as detailed in Section 6.3.1, "ULPI Receive Command (RX CMD)," on page 48, anytime the comparator changes state. The SessVld interrupts can be disabled by clearing this bit in both the USB Interrupt Enable Rising and USB Interrupt Enable Falling registers. When the interrupts are disabled, the SessVld comparator is still operational and will generate RX CMD's. The SessVld comparator trip point is detailed in Table 4-9. Note: The OTG Supplement specifies a voltage range for A-Device Session Valid and B-Device Session Valid comparator. The USB334x PHY combines the two comparators into one and uses the narrower threshold range. 5.7.2.3 VbusVld Comparator The VbusVld comparator is only used when the USB334x is configured as a host that can supply less than 100mA VBUS current. In the USB protocol, the A-device supplies the VBUS voltage and is responsible to ensure it remains within a specified voltage range. The VbusVld comparator can be disabled by clearing this bit in both the USB Interrupt Enable Rising and USB Interrupt Enable Falling registers. When disabled, bit 1 of the USB Interrupt Status register will return a 0. The VbusVld comparator threshold values are detailed in Table 4-9. If the USB334x is used as a Device only the VbusValid Comparator should be disabled, using the method described above. The USB334x includes the external VbusVld indicator logic as detailed in the ULPI Specification. The external VbusVld indicator is tied to a logic one. The decoding of this logic is shown in Table 5-5 below. By default this logic is disabled. TABLE 5-5: EXTERNAL VBUS INDICATOR LOGIC Typical Application Use External Vbus Indicator Indicator Pass Thru Indicator Complement OTG Device 0 X X Internal VbusVld comparator (Default) 1 1 0 Fixed 1 1 1 1 Fixed 0 1 0 0 Internal VbusVld comparator. 1 0 1 Fixed 0 1 1 0 Fixed 1 1 1 1 Fixed 0 0 X X Internal VbusVld comparator. This information should not be used by the Link. (Note 5-5) Standard Host Standard Peripheral Note 5-5 RXCMD Vbus Valid Encoding Source A peripheral should not use VbusVld to begin operation. The peripheral should use SessVld to detect the presence of VBUS on the USB connector. VbusVld should only be used for USB Host and OTG A-device applications. DS00002646A-page 36 2009-2018 Microchip Technology Inc. USB334x 5.7.2.4 VBUS Pulsing with Pull-up and Pull-down Resistors In addition to the internal VBUS comparators, the USB334x also includes the integrated VBUS pull-up and pull-down resistors used for VBUS Pulsing during OTG Session Request Protocol. To discharge the VBUS voltage so that a Session Request can begin, the USB334x provides a pull-down resistor from VBUS to GND. This resistor is controlled by the DischargeVbus bit 3 of the OTG Control register. The pull-up resistor is connected between VBUS and VDD33. This resistor is used to pull VBUS above 2.1 volts so that the A-Device knows that a USB session has been requested. The state of the pull-up resistor is controlled by the bit 4 ChargeVbus of the OTG Control register. The Pull-Up and Pull-Down resistor values are detailed in Table 4-9. The internal VBUS Pull-up and Pull-down resistors are designed to include the RVBUS external resistor in series. This external resistor is used by the VBUS Over voltage protection described below. 5.7.2.5 VBUS Input Impedance The OTG Supplement requires an A-Device that supports Session Request Protocol to have a VBUS input impedance less than 100k and greater the 40k to ground. The USB334x provides a 75k resistance to ground, RVB. The RVB resistor tolerance is detailed in Table 4-9. 5.7.2.6 VBUS Over Voltage Protection (OVP) The USB334x provides an integrated over voltage protection circuit to protect the VBUS pin from excessive voltages that may be present at the USB connector. The over voltage protection circuit works with an external resistor (RVBUS) by drawing current across the resistor to reduce the voltage at the VBUS pin. When voltage at the VBUS pin exceeds 5.5V, the Over voltage Protection block will sink current to ground until VBUS is below 5.5V. The current drops the excess voltage across RVBUS and protects the USB334x VBUS pin. The required RVBUS value is dependent on the operating mode of the USB334x as shown in Table 5-6. TABLE 5-6: REQUIRED RVBUS RESISTOR VALUE Operating Mode RVBUS Device only 20k 5% OTG Host Capable of less than 100mA of current on VBUS 1k 5% Host or OTG Host capable of >100mA UseExternalVbusIndicator = 1 20k 5% The Over voltage Protection circuit is designed to protect the USB334x from continuous voltages up to 30V on the RVBUS resistor. The RVBUS resistor must be sized to handle the power dissipated across the resistor. The resistor power can be found using the equation below: 2 Vprotect - 5.0 P RVBUS = -------------------------------------------R VBUS Where: * Vprotect is the VBUS protection required. * RVBUS is the resistor value, 1k or 20k. * PRVBUS is the required power rating of RVBUS. For example, protecting a peripheral or device only application to 15V would require a 20k RVBUS resistor with a power rating of 0.05W. To protect an OTG product to 15V would require a 1k RVBUS resistor with a power rating of 0.1W. 2009-2018 Microchip Technology Inc. DS00002646A-page 37 USB334x 5.7.3 DRIVING EXTERNAL VBUS The USB334x monitors VBUS as described in VBUS Monitoring and VBUS Pulsing. The USB334x does not provide an external output for the DrvVbusExternal ULPI register. For OTG and Host applications, the external VBUS supply or power switch must be controlled by the Link. 5.8 USB UART Support The USB334x provides support for the USB UART interface as detailed in the ULPI specification and the former CEA936A specification. The USB334x can be placed in UART Mode using the method described in Section 6.7, "Carkit Mode," on page 59, and the regulator output will automatically switch to the value configured by the UART RegOutput bits in the USB IO & Power Management register. While in UART mode, the Linestate signals cannot be monitored on the DATA[0] and DATA[1] pins. 5.9 USB Charger Detection Support The following blocks allow the USB334x to detect when a Battery Charger, Charging Host Port, or a USB Host is attached to the USB connector. The USB334x can also be configured to appear as a Charging Host Port, all according to the USB-IF Battery Charging 1.2 specification. The charger detection circuitry should be disabled during USB operation. FIGURE 5-9: USB CHARGER DETECTION BLOCK DIAGRAM ~~ VDD33 C hargerP ullupE nD P RCD RCD C hargerP ullupE nD M C ontactD etectE n en I D P _S R C DP V D A T_S R C T o U S B C on . V D atS rcE n H ostC hrgE n DM V D A T_R E F RPD RPD T o U S B C on . V datD et en ID atS inkE n en I D A T_S IN K D pP ulldow n D m P ulldow n ~~ Note: MCHP PHY The italic names in the Figure 5-9 correspond to bits in the ULPI register set. DS00002646A-page 38 2009-2018 Microchip Technology Inc. USB334x The charger detection circuitry runs from the VDD33 supply and requires that the VDD33 supply to be present to run the charger detection circuitry. The VDD33 supply is present anytime the RESETB pin is pulled high and VBAT is present. The charger detection circuits are fully functional while in Low Power Mode (Suspendm = 0). The status of the VdatDet can be relayed back to the Link through the ULPI interrupts in both Synchronous mode and Low Power Mode. 5.9.1 ACTIVE ANALOG CHARGER DETECTION (USB-IF BATTERY CHARGING 1.2) The USB334x includes the active analog charger detection specified in the USB-IF Battery Charging Specification. The additional analog circuitry will allow the USB334x to: 1. 2. 3. 4. Detect a Dedicated Charging Port (DCP) with the DP and DM pins shorted together. Detect a Standard Downstream Port (SDP) which has no battery charging circuitry. Detect a Charging Downstream Port (CDP) which actively supplies voltage to the DM pin when connected to a USB-IF BC 1.2 compatible device. Behave as a Charging Downstream Port by enabling the voltage source on the DM pin. The charger detection circuitry is shown in Figure 5-9. The VdatDet output is qualified with the Linestate[1:0] value. If the Linestate is not equal to 00 the VdatDet signal will not assert. The proper detection process flows through different modes of detection and uses the linestate and VdatDet signals values to determine the connection. Table 5-7 describes the bit values that need to be set to enter each mode. DMPULLDOWN DPPULLDOWN HOSTCHRGEN CONTACTDETE N Charger Detection Modes IDATSINKEN USB CHARGER SETTING VS. MODES VDATSRCEN TABLE 5-7: Device Connect Detect (The Connect Detect setting in Table 5-1 must be followed) 0 0 1 0 0 1 Device Charger Detection 1 1 0 0 0 0 Device Enhanced Charger Detection 1 1 0 1 0 0 Device USB Operation 0 0 0 0 0 0 Charging Host Port, no charging device attached and SE0 (VdatDet = 0) 0 1 0 1 1 1 Charging Host Port, charging device attached (VdatDet = 1) 1 1 0 1 1 1 Charging Host Port USB Operation 0 0 0 1 1 1 5.9.1.1 Example Charger Detection Flow - Dedicated Charging Port The USB-IF Battery Charging 1.2 specification describes in detail the flow for each charger type, but below is an example of the flow used to detect a Dedicated Charger (DCP). 1. 2. Device detects Vbus voltage is present from RXCMD, (SESS_VLD is 1) Device enters the Device Connect Detect mode. If the linestate still equals 10 after a specified timeout, the charger is an unknown charger and there will be no attempted USB enumeration. If the linestate equals 00 or 11, the device will go to the next mode: 2009-2018 Microchip Technology Inc. DS00002646A-page 39 USB334x 3. Device enters Device Charger Detection mode. If the VdatDet bit is 0 then the host is a Standard Downstream Port (SDP) and the device will draw the standard 500mA of current and enter the Device USB Operation mode. If the VdatDet bit is 1 then the host is a charger that can supply at least 1.5A of current, the device will go to the next mode. 4. Device enters Device Enhanced Charger Detection mode. If the VdatDet bit is 0 then the device is connected to a Charging Downstream Port (CDP) and the device will enter the Device USB Operation mode. If the VdatDet bit is 1 then the device is connected to a Dedicated Charging Port (DCP) and the device will not try to enumerate. 5. The charger detection is complete. 5.9.2 Note: RESISTIVE CHARGER DETECTION The Resistive Charger Detection has been superseded by the Active Analog Charger Detection (USB-IF Battery Charging 1.2) detailed above. It is recommended that new designs use the Active Analog Charger Detection (USB-IF Battery Charging 1.2). To support the detection and identification of different types of USB chargers the USB334x provides integrated pull-up resistors, RCD, on both DP and DM. These pull-up resistors along with the single ended receivers can be used to determine the type of USB charger attached. Reference information on implementing charger detection is provided in Section 8.2. TABLE 5-8: Note: 5.10 Note: USB WEAK PULL-UP ENABLE RESETB DP Pullup Enable DM Pullup Enable 0 0 0 1 ChargerPullupEnableDP ChargerPullupEnableDM ChargerPullupEnableDP and ChargerPullupEnableDM are enabled in the USB IO & Power Management register. USB Audio Support (USB3341 and USB3346) The USB334x supports "USB Digital Audio" through the USB protocol in ULPI and USB Serial modes described in Section 6.0, "ULPI Operation," on page 42. The USB334x provides two low resistance analog switches that allow analog audio to be multiplexed over the DP and DM terminals of the USB connector. The audio switches are shown in . The electrical characteristics of the USB Audio Switches are provided in Table 4-11. During normal USB operation the switches are off. When USB Audio is desired the switches can be turned "on" by enabling the SpkLeftEn, SpkRightEn, or MicEn bits in the Carkit Control register as described in Section 6.7.2, "USB Audio Mode (USB3341 and USB3346)," on page 61. These bits are disabled by default. The RESETB pin must be high when using the analog switches so that the VDD33 supply is present. If the VDD33 supply is applied externally and RESETB is held low the switches will be off. In addition to USB Audio support the switches could also be used to multiplex a second Full Speed USB transceiver to the USB connector. The signal quality will be degraded slightly due to the "on" resistance of the switches. The USB334x single-ended receivers described in Section 5.2.1, "USB Transceiver," on page 25 are enabled while in synchronous mode and are disabled when Carkit Mode is entered. DS00002646A-page 40 2009-2018 Microchip Technology Inc. USB334x The USB334x does not provide the DC bias for the audio signals. The SPK_R and SPK_L pins should be biased to 1.65V when audio signals are routed through the USB334x. This DC bias is necessary to prevent the audio signal from swinging below ground and being clipped by ESD Diodes. When the system is not using the USB Audio switches, the SPK_R and SPK_L switches should be disabled. 2009-2018 Microchip Technology Inc. DS00002646A-page 41 USB334x 6.0 ULPI OPERATION 6.1 ULPI Introduction The USB334x uses the industry standard ULPI digital interface for communication between the transceiver and Link (device controller). The ULPI interface is designed to reduce the number of pins required to connect a discrete USB transceiver to an ASIC or digital controller. For example, a full UTMI+ Level 3 OTG interface requires 54 signals while a ULPI interface requires only 12 signals. The ULPI interface is documented completely in the "UTMI+ Low Pin Interface (ULPI) Specification Revision 1.1". The following sections describe the operating modes of the USB334x digital interface. Figure 6-1 illustrates the block diagram of the ULPI digital functions. It should be noted that this USB334x does not use a "ULPI wrapper" around a UTMI+ PHY core as the ULPI specification implies. FIGURE 6-1: ULPI DIGITAL BLOCK DIAGRAM USB Transmit and Receive Logic Tx Data Data[7:0] To TX Analog FS/LS Tx Data High Speed Data Recovery Full / Low Speed Data Recovery NOTE: The ULPI interface is a wrapperless design. HS RX Data To OTG Analog To USB Audio Analog Interface Protect Disable UseExternal Vbus Indicator Indicator Complement Indicator Pass Thru DischrgVbus ChrgVbus IdGndDrv IdPullUp SpkLeftEn SpkRightEn/MicEn ChargerPullupEnDP ChargerPullupEnDM RidValue[2:0] RidCon...Start RidCon...Done Rid State Machine VbusValid SessionValid SessionEnd IdGnd IdFloat ULPI Interupt XcvrSelect[1:0] TermSelect OpMode[1:0] Reset DpPulldown DmPulldown SwapDP/DM RegOutput[1:0] TxdEn RxdEn To RX Analog FS/LS Data Transceiver Control Rx Data ULPI Register Access STP HS Tx Data ULPI Protocol Block Linestates[1:0] HostDisconnect NXT SuspendM 6pinSerial Mode 3pinSerial Mode ClockSuspendM AutoResume CarkitMode DIR High Speed TX Full Speed TX Low Speed TX Interrupt Control RESETB POR ULPI Register Array The advantage of a "wrapper-less" architecture is that the USB334x has a lower USB latency than a design which must first register signals into the PHY's wrapper before the transfer to the transceiver core. A low latency PHY allows a wrapper around a UTMI Link to be used and still make the required USB turn-around timing required by the USB 2.0 specification. DS00002646A-page 42 2009-2018 Microchip Technology Inc. USB334x RxEndDelay maximum allowed by the UTMI+/ULPI for 8-bit data is 63 Hi-Speed clocks. USB334x uses a low latency Hi-Speed receiver path to lower the RxEndDelay to 43 Hi-Speed clocks. This low latency design gives the Link more cycles to make decisions and reduces the Link complexity. This is the result of the "wrapper less" architecture of the USB334x. This low RxEndDelay should allow legacy UTMI Links to use a "wrapper" to convert the UTMI+ interface to a ULPI interface. In Figure 6-1, a single ULPI Protocol Block decodes the ULPI 8-bit bi-directional bus when the Link addresses the PHY. The Link must use the DIR output to determine direction of the ULPI data bus. The USB334x is the "bus arbitrator". The ULPI Protocol Block will route data/commands to the transmitter or the ULPI register array. 6.1.1 ULPI INTERFACE SIGNALS The UTMI+ Low Pin Interface (ULPI) uses a 12-pin interface to connect a USB Transceiver to an external Link. The reduction of external pins, relative to UTMI+, is accomplished implementing the relatively static configuration pins (i.e. xcvrselect[1:0], termselect, opmode[1:0], and DpPullDown DmPulldown) as an internal register array. An 8-bit bi-directional data bus clocked at 60 MHz allows the Link to access this internal register array and transfer USB packets to and from the PHY. The remaining 3 pins function to control the data flow and arbitrate the data bus. Direction of the 8-bit data bus is controlled by the DIR output from the PHY. Another output, NXT, is used to control data flow into and out of the device. Finally, STP, which is in input to the PHY, terminates transfers and is used to start up and resume from Low Power Mode. The ULPI Interface signals are described below in Table 6-1. TABLE 6-1: Signal ULPI INTERFACE SIGNALS Direction Description CLK I/O 60 MHz ULPI clock. All ULPI signals are driven synchronous to the rising edge of this clock. This clock can be either driven by the PHY or the Link as described in Section 5.5.1, "REFCLK Frequency Selection," on page 28. DATA[7:0] I/O 8-bit bi-directional data bus. Bus ownership is determined by DIR. The Link and PHY initiate data transfers by driving a non-zero pattern onto the data bus. ULPI defines interface timing for a single-edge data transfers with respect to rising edge of the ULPI clock. DIR OUT Controls the direction of the data bus. When the PHY has data to transfer to the Link, it drives DIR high to take ownership of the bus. When the PHY has no data to transfer it drives DIR low and monitors the bus for commands from the Link. The PHY will pull DIR high whenever the interface cannot accept data from the Link, such as during PLL start-up. STP IN The Link asserts STP for one clock cycle to stop the data stream currently on the bus. If the Link is sending data to the PHY, STP indicates the last byte of data was on the bus in the previous cycle. NXT OUT The PHY asserts NXT to throttle the data. When the Link is sending data to the PHY, NXT indicates when the current byte has been accepted by the PHY. The Link places the next byte on the data bus in the following clock cycle. USB334x implements a Single Data Rate (SDR) ULPI interface with all data transfers happening on the rising edge of the 60 MHz ULPI Clock while operating in Synchronous Mode. The direction of the data bus is determined by the state of DIR. When DIR is high, the PHY is driving DATA[7:0]. When DIR is low, the Link is driving DATA[7:0]. Each time DIR changes, a "turn-around" cycle occurs where neither the Link nor PHY drive the data bus for one clock cycle. During the "turn-around" cycle, the state of DATA[7:0] is unknown and the PHY will not read the data bus. Because USB uses a bit-stuffing encoding, some means of allowing the PHY to throttle the USB transmit data is needed. The ULPI signal NXT is used to request the next byte to be placed on the data bus by the Link. The ULPI interface supports the two basic modes of operation: Synchronous Mode and Asynchronous Mode. Asynchronous Mode includes Low Power Mode, the Serial Modes, and Carkit Mode. In Synchronous Mode, all signals change synchronously with the 60 MHz ULPI clock. In asynchronous modes the clock is off and the ULPI bus is redefined to bring out the signals required for that particular mode of operations. The description of synchronous Mode is described 2009-2018 Microchip Technology Inc. DS00002646A-page 43 USB334x in the following sections while the descriptions of the asynchronous modes are described in Section 6.5, "Low Power Mode," on page 55, Section 6.6, "Full Speed/Low Speed Serial Modes," on page 58, and Section 6.7, "Carkit Mode," on page 59. 6.1.2 ULPI INTERFACE TIMING IN SYNCHRONOUS MODE The control and data timing relationships are given in Figure 6-2 and Table 4-4. All timing is relative to the rising clock edge of the 60 MHz ULPI Clock. FIGURE 6-2: ULPI SINGLE DATA RATE TIMING DIAGRAM IN SYNCHRONOUS MODE 60MHz ULPI CLK TSC THC Control In STP TSD THD Data In DATA[7:0] TDC TDC Control Out DIR, NXT TDD Data Out DATA[7:0] 6.2 ULPI Register Access The following section details the steps required to access registers through the ULPI interface. At any time DIR is low the Link may access the ULPI registers set using the Transmit Command byte. The ULPI registers retain their contents when the PHY is in Low Power Mode, Full Speed/Low Speed Serial Mode, or Carkit Mode. 6.2.1 TRANSMIT COMMAND BYTE (TX CMD) A command from the Link begins a ULPI transfer from the Link to the USB334x. Before reading a ULPI register, the Link must wait until DIR is low, and then send a Transmit Command Byte (TX CMD) byte. The TX CMD byte informs the USB334x of the type of data being sent. The TX CMD is followed by a data transfer to or from the USB334x. Table 6-2 gives the TX command byte (TX CMD) encoding for the USB334x. The upper two bits of the TX CMD instruct the PHY as to what type of packet the Link is transmitting. DS00002646A-page 44 2009-2018 Microchip Technology Inc. USB334x TABLE 6-2: ULPI TX CMD BYTE ENCODING Command Name CMD Bits[7:6] CMD Bits[5:0] Idle 00b 000000b ULPI Idle Transmit 01b 000000b USB Transmit Packet with No Packet Identifier (NOPID) 00XXXXb USB Transmit Packet Identifier (PID) where DATA[3:0] is equal to the 4-bit PID. P3P2P1P0 where P3 is the MSB. XXXXXXb Immediate Register Write Command where: DATA[5:0] = 6-bit register address Register Write 10b 101111b Register Read 11b Extended Register Write Command where the 8-bit register address is available on the next cycle. XXXXXXb Immediate Register Read Command where: DATA[5:0] = 6-bit register address 101111b 6.2.2 Command Description Extended Register Read Command where the 8-bit register address is available on the next cycle. ULPI REGISTER WRITE A ULPI register write operation is given in Figure 6-3. The TX command with a register write DATA[7:6] = 10b is driven by the Link at T0. The register address is encoded into DATA[5:0] of the TX CMD byte. FIGURE 6-3: ULPI REGISTER WRITE IN SYNCHRONOUS MODE T0 T1 T2 T3 T4 T5 T6 CLK DATA[7:0] Idle TXD CMD (reg write) Reg Data[n] Idle DIR STP NXT ULPI Register Reg Data [n-1] Reg Data [n] To write a register, the Link will wait until DIR is low, and at T0, drive the TX CMD on the data bus. At T2 the PHY will drive NXT high. On the next rising clock edge, T3, the Link will write the register data. At T4, the PHY will accept the register data and drive NXT low. The Link will drive an Idle on the bus and drive STP high to signal the end of the data packet. Finally, at T5, the PHY will latch the data into the register and the Link will pull STP low. 2009-2018 Microchip Technology Inc. DS00002646A-page 45 USB334x NXT is used to throttle when the Link drives the register data on the bus. DIR is low throughout this transaction since the PHY is receiving data from the Link. STP is used to end the transaction and data is registered after the de-assertion of STP. After the write operation completes, the Link must drive a ULPI Idle (00h) on the data bus. If the databus is not driven to idle the USB334x may decode the non-zero bus value as an RX Command. A ULPI extended register write operation is shown in Figure 6-4. To write an extended register, the Link will wait until DIR is low, and at T0, drive the TX CMD on the data bus. At T2 the PHY will drive NXT high. On the next clock T3 the Link will drive the extended address. On the next rising clock edge, T4, the Link will write the register data. At T5, the PHY will accept the register data and drive NXT low. The Link will drive an Idle on the bus and drive STP high to signal the end of the data packet. At T5, the PHY will latch the data into the register. Finally, at T6, the Link will drive STP low. FIGURE 6-4: ULPI EXTENDED REGISTER WRITE IN SYNCHRONOUS MODE T0 T1 T2 T3 T4 T5 T6 T7 CLK DATA[7:0] Idle TXD CMD (extended reg write) Extended address Reg Data[n] Idle DIR STP NXT ULPI Register DS00002646A-page 46 Reg Data [n-1] Reg Data [n] 2009-2018 Microchip Technology Inc. USB334x 6.2.3 ULPI REGISTER READ A ULPI register read operation is given in Figure 6-5. The Link drives a TX CMD byte with DATA[7:6] = 11h for a register read. DATA[5:0] of the ULPI TX command bye contain the register address. FIGURE 6-5: ULPI REGISTER READ IN SYNCHRONOUS MODE T0 T1 T2 T3 T4 T5 T6 CLK DATA[7:0] Idle TXD CMD reg read Turn around Reg Data Turn around Idle DIR STP NXT At T0, the Link will place the TX CMD on the data bus. At T2, the PHY will bring NXT high, signaling the Link it is ready to accept the data transfer. At T3, the PHY reads the TX CMD, determines it is a register read, and asserts DIR to gain control of the bus. The PHY will also de-assert NXT. At T4, the bus ownership has transferred back to the PHY and the PHY drives the requested register onto the data bus. At T5, the Link will read the data bus and the PHY will drop DIR low returning control of the bus back to the Link. After the turn around cycle, the Link must drive a ULPI Idle command at T6. A ULPI extended register read operation is shown in Figure 6-6.To read an extended register, the Link writes the TX CMD with the address set to 2Fh. At T2, the PHY will assert NXT, signaling the Link it is ready to accept the extended address. At T3, the Link places the extended register address on the bus. At T4, the PHY reads the extended address, and asserts DIR to gain control of the bus. The PHY will also de-assert NXT. At T5, the bus ownership has transferred back to the PHY and the PHY drives the requested register onto the data bus. At T6, the Link will read the data bus and the PHY will de-assert DIR returning control of the bus back to the Link. After the turn around cycle, the Link must drive a ULPI Idle command at T6. 2009-2018 Microchip Technology Inc. DS00002646A-page 47 USB334x FIGURE 6-6: ULPI EXTENDED REGISTER READ IN SYNCHRONOUS MODE T0 T1 T2 T3 T4 T5 T6 T7 CLK DATA[7:0] Idle TXD CMD extended reg read Extended address Turn around Reg Data Turn around Idle DIR STP NXT 6.3 USB334x Receiver The following section describes how the USB334x uses the ULPI interface to receive USB signaling and transfer status information to the Link. This information is communicated to the Link using RX Commands to relay bus status and received USB packets. 6.3.1 ULPI RECEIVE COMMAND (RX CMD) The ULPI Link needs information which was provided by the following pins in a UTMI implementation: linestate[1:0], rxactive, rxvalid, rxerror, and VbusValid. When implementing the OTG functions, the VBUS and ID pin states must also be transferred to the Link. ULPI defines a Receive Command Byte (RXCMD) that contains this information. An RXCMD can be sent a any time the bus is idle. The RXCMD is initiated when the USB334x asserts DIR to take control of the bus. The timing of RXCMD is shown in the figure below. The USB334x can send single or back to back RXCMD's as required. The Encoding of the RXCMD byte is given in the Table 6-3. DS00002646A-page 48 2009-2018 Microchip Technology Inc. USB334x FIGURE 6-7: ULPI RXCMD TIMING T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK DATA[7:0] Idle Turn around RXCMD Turn around Idle Turn around RXCMD RXCMD Turn around Idle DIR STP NXT Transfer of the RXCMD byte occurs in Synchronous Mode when the PHY has control of the bus. The ULPI Protocol Block shown in Figure 6-1 determines when to send an RXCMD. A RXCMD will occur: * * * * * When a linestate change occurs. When VBUS or ID comparators change state. During a USB receive when NXT is low. After the USB334x deasserts DIR and STP is low during start-up After the USB334x exits Low Power Mode, Serial Modes, or Carkit Mode after detecting that the Link has deasserted STP, and DIR is low. When a USB Receive is occurring, RXCMD's are sent whenever NXT = 0 and DIR = 1. During a USB Transmit, the RXCMD's are returned to the Link after STP is asserted. If an RXCMD event occurs during a Hi-Speed USB transmit, the RXCMD is blocked until STP de-asserts at the end of the transmit. The RXCMD contains the status that is current at the time the RXCMD is sent. 2009-2018 Microchip Technology Inc. DS00002646A-page 49 USB334x TABLE 6-3: ULPI RX CMD ENCODING Data [7:0] Name [1:0] Linestate UTMI Linestate Signals. See Section 6.3.1.1, "Definition of Linestate," on page 50 [3:2] Encoded VBUS State ENCODED VBUS VOLTAGE STATES [5:4] Rx Event Encoding [6] State of ID pin [7] alt_int Description and Value VALUE VBUS VOLTAGE SESSEND SESSVLD VBUSVLD2 00 VVBUS < VSESS_END 1 0 0 01 VSESS_END < VVBUS < VSESS_VLD 0 0 0 10 VSESS_VLD < VVBUS < VVBUS_VLD X 1 0 11 VVBUS_VLD < VVBUS X X 1 ENCODED UTMI EVENT SIGNALS VALUE RXACTIVE RXERROR HOSTDISCONNECT 00 0 0 0 01 1 0 0 11 1 1 0 10 X X 1 Set to the logic state of the ID pin. A logic low indicates an A device. A logic high indicates a B device. Asserted when a non-USB interrupt occurs. This bit is set when an unmasked event occurs on any bit in the Carkit Interrupt Latch register. The Link must read the Carkit Interrupt Latch register to determine the source of the interrupt. Section 6.8, "RID Converter Operation," on page 61 describes how an interrupt can be generated when the RidConversionDone bit is set. Note 1: An `X' is a do not care and can be either a logic 0 or 1. 2: The value of VbusValid is defined in Table 5-5. 6.3.1.1 Definition of Linestate The Linestate information is used to relay information back to the Link on the current status of the USB data lines, DP and DM. The definition of Linestate changes as the USB334x transitions between LS/FS mode, HS mode, and HS Chirp. 6.3.1.1.1 LS/FS Linestate Definitions In LS and FS operating modes the Linestate is defined by the outputs of the LS/FS Single Ended Receivers (SE RX). The logic thresholds for single ended receivers, VILSE and VILSE are shown in Table 4-6. DS00002646A-page 50 2009-2018 Microchip Technology Inc. USB334x TABLE 6-4: USB LINESTATE DECODING IN FS AND LS MODE Linestate[1:0] DP SE RX DM SE RX State 00 SE0 0 0 USB Reset 01 J (FS idle) 1 0 J State 10 K (LS Idle) 0 1 K State 11 SE1 1 1 SE1 Low Speed uses the same Linestate decoding threshold as Full Speed. Low Speed re-defines the Idle state as an inversion of the Full Speed idle to account for the inversion which occurs in the hub repeater path. Linestates are decoded exactly as in Table 6-4 with the idle as a K state. 6.3.1.1.2 HS Linestate Definition In HS mode the data transmission is too fast for Linestate to be transmitted with each transition in the data packet. In HS operation the Linestate is redefined to indicate activity on the USB interface. The Linestate will signal the assertion and de-assertion of squelch in HS mode. TABLE 6-5: USB LINESTATE DECODING IN HS MODE Linestate[1:0] DP SE RX DM SE RX State 00 SE0 0 0 HS Squelch asserted 01 J 1 0 HS Squelch de-asserted 10 K 0 1 Invalid State 11 SE1 1 1 Invalid State 6.3.1.1.3 HS CHIRP Linestate Definition There is also a third use of Linestate in HS Chirp where when the Host and Peripheral negotiate the from FS mode to HS mode. While the transitions from K to J or SE0 are communicated to the Link through the Linestate information. TABLE 6-6: USB LINESTATE DECODING IN HS CHIRP MODE Linestate[1:0] DP SE RX DM SE RX State 00 SE0 0 0 HS Squelch asserted 01 J 1 0 HS Squelch de-asserted & HS differential Receiver = 1 10 K 0 1 HS Squelch de-asserted & HS differential Receiver = 0 11 SE1 1 1 Invalid State 2009-2018 Microchip Technology Inc. DS00002646A-page 51 USB334x 6.3.2 USB RECEIVER The USB334x ULPI receiver fully supports HS, FS, and LS transmit operations. In all three modes the receiver detects the start of packet and synchronizes to the incoming data packet. In the ULPI protocol, a received packet has the priority and will immediately follow register reads and RXCMD transfers. Figure 6-8 shows a basic USB packet received by the USB334x over the ULPI interface. FIGURE 6-8: ULPI RECEIVE IN SYNCHRONOUS MODE CLK DATA[7:0] Idle Turn around Rxd Cmd PID D1 Rxd Cmd D2 Turn around DIR STP NXT In Figure 6-8 the PHY asserts DIR to take control of the data bus from the Link. The assertion of DIR and NXT in the same cycle contains additional information that Rxactive has been asserted. When NXT is de-asserted and DIR is asserted, the RXCMD data is transferred to the Link. After the last byte of the USB receive packet is transferred to the PHY, the linestate will return to idle. The ULPI Full Speed receiver operates according to the UTMI / ULPI specification. In the Full Speed case, the NXT signal will assert only when the Data bus has a valid received data byte. When NXT is low with DIR high, the RXCMD is driven on the data bus. In Full Speed, the USB334x will not issue a Rxactive de-assertion in the RXCMD until the DP/DM linestate transitions to idle. This prevents the Link from violating the two Full Speed bit times minimum turn around time. 6.3.2.1 Disconnect Detection A Hi-Speed host must detect a disconnect by sampling the transmitter outputs during the long EOP transmitted during a SOF packet. The USB334x only looks for a Hi-Speed disconnect during the long EOP where the period is long enough for the disconnect reflection to return to the host PHY. When a Hi-Speed disconnect occurs, the USB334x will return a RXCMD and set the host disconnect bit in the USB Interrupt Status register. When in FS or LS modes, the Link is expected to handle all disconnect detection. 6.3.2.2 Link Power Management (LPM) Token Receive The USB334x is fully capable of receiving the Extended PID in the LPM token. When the LPM 0000b PID is received, this information is passed to the Link as a normal receive packet. If the Link chooses to enter LPM suspend, the procedure detailed in Section 6.5.3, "Link Power Management (LPM)," on page 57 can be followed. 6.4 USB334x Transmitter The USB334x ULPI transmitter fully supports HS, FS, and LS transmit operations. Figure 6-1 shows the Hi-Speed, Full Speed, and Low Speed transmitter block controlled by ULPI Protocol Block. Encoding of the USB packet follows the bitstuffing and NRZI outlined in the USB 2.0 specification. Many of these functions are reused between the HS and FS/LS transmitters. When using the USB334x, Table 5-1 should always be used as a guideline on how to configure for various DS00002646A-page 52 2009-2018 Microchip Technology Inc. USB334x modes of operation. The transmitter decodes the inputs of XcvrSelect[1:0], TermSelect, OpMode[1:0], DpPulldown, and DmPulldown to determine what operation is expected. Users must strictly adhere to the modes of operation given in Table 5-1. Several important functions for a device and host are designed into the transmitter blocks. The USB334x transmitter will transmit a 32-bit long Hi-Speed sync before every Hi-Speed packet. In Full and Low Speed modes a 8-bit sync is transmitted. When the device or host needs to chirp for Hi-Speed port negotiation, the OpMode = 10 setting will turn off the bit-stuffing and NRZI encoding in the transmitter. At the end of a chirp, the USB334x OpMode register bits should be changed only after the RXCMD linestate encoding indicates that the transmitter has completed transmitting. Should the opmode be switched to normal bit-stuffing and NRZI encoding before the transmit pipeline is empty, the remaining data in the pipeline may be transmitted in an bit-stuff encoding format. Please refer to the ULPI specification for a detailed discussion of USB reset and HS chirp. 6.4.1 USB334X HOST FEATURES The USB334x can also support USB Host operation and includes the following features that are required for Host operation. 6.4.1.1 Hi-Speed Long EOP When operating as a Hi-Speed host, the USB334x will automatically generate a 40 bit long End of Packet (EOP) after a SOF PID (A5h). The USB334x determines when to send the 40-bit long EOP by decoding the ULPI TX CMD bits [3:0] for the SOF. The 40-bit long EOP is only transmitted when the DpPulldown and DmPulldown bits in the OTG Control register are asserted. The Hi-Speed 40-bit long EOP is used to detect a disconnect in mode. In device mode, the USB334x will not send a long EOP after a SOF PID. 6.4.1.2 Low Speed Keep-Alive Low Speed keep alive is supported by the USB334x. When in Low Speed mode, the USB334x will send out two Low Speed bit times of SE0 when a SOF PID is received. 6.4.1.3 UTMI+ Level 3 Pre-amble is supported for UTMI+ Level 3 compatibility. When XcvrSelect is set to (11b) in host mode, (DpPulldown and DmPulldown both asserted) the USB334x will pre-pend a Full Speed pre-amble before the Low Speed packet. Full Speed rise and fall times are used in this mode. The pre-amble consists of the following: Full Speed sync, the encoded pre-PID (C3h) and then Full Speed idle (DP=1 and DM = 0). A Low Speed packet follows with a sync, data and a LS EOP. The USB334x will only support UTMI+ Level 3 as a host. The USB334x does not support UTMI+ Level 3 as a peripheral. A UTMI+ Level 3 peripheral is an upstream hub port. The USB334x will not decode a pre-amble packet intended for a LS device when the USB334x is configured as the upstream port of a FS hub, XcvrSelect = 11b, DpPulldown = 0b, DmPulldown =0b. 6.4.1.4 Host Resume K Resume K generation is supported by the USB334x. At the end of a USB Suspend the PHY will drive a K back to the downstream device. When the USB334x exits from Low Power Mode, when operating as a host, it will automatically transmit a Resume K on DP/DM. The transmitters will end the K with SE0 for two Low Speed bit times. If the USB334x was operating in Hi-Speed mode before the suspend, the host must change to Hi-Speed mode before the SE0 ends. SE0 is two Low Speed bit times which is about 1.2 us. For more details please see sections 7.1.77 and 7.9 of the USB Specification. In device mode, the resume K will not append an SE0, but release the bus to the correct idle state, depending upon the operational mode as shown in Table 5-1. The ULPI specification includes a detailed discussion of the resume sequence and the order of operations required. To support Host start-up of less than 1mS the USB334x implements the ULPI AutoResume bit in the Interface Control register. The default AutoResume state is 0 and this bit should be enabled for Host applications. 6.4.1.5 No SYNC and EOP Generation (OpMode = 11) UTMI+ defines OpMode = 11 where no sync and EOP generation occurs in Hi-Speed operation. This is an option to the ULPI specification and not implemented in the USB334x. 2009-2018 Microchip Technology Inc. DS00002646A-page 53 USB334x 6.4.2 TYPICAL USB TRANSMIT WITH ULPI Figure 6-9 shows a typical USB transmit sequence. A transmit sequence starts by the Link sending a TX CMD where DATA[7:6] = 01b, DATA[5:4] = 00b, and Data[3:0] = PID. The TX CMD with the PID is followed by transmit data. FIGURE 6-9: ULPI TRANSMIT IN SYNCHRONOUS MODE CLK DATA[7:0] TXD CMD (USB tx) Idle D0 D1 D2 D3 IDLE Turn Around RXD CMD Turn Around DIR NXT STP DP/DM SE0 !SQUELCH SE0 During transmit the PHY will use NXT to control the rate of data flow into the PHY. If the USB334x pipeline is full or bitstuffing causes the data pipeline to overfill NXT is de-asserted and the Link will hold the value on Data until NXT is asserted. The USB Transmit ends when the Link asserts STP while NXT is asserted. Note: The Link cannot assert STP with NXT de-asserted since the USB334x is expecting to fetch another byte from the Link. After the USB334x completes transmitting, the DP and DM lines return to idle and a RXCMD is returned to the Link so the inter-packet timers may be updated by linestate. While operating in Full Speed or Low Speed, an End-of-Packet (EOP) is defined as SE0 for approximately two bit times, followed by J for one bit time. The transceiver drives a J state for one bit time following the SE0 to complete the EOP. The Link must wait for one bit time following line state indication of the SE0 to J transition to allow the transceiver to complete the one bit time J state. All bit times are relative to the speed of transmission. In the case of Full Speed or Low Speed, after STP is asserted each FS/LS bit transition will generate a RXCMD since the bit times are relatively slow. 6.4.2.1 Link Power Management Token Transmit A Host Link can send a LPM command using the USB334x. When sending the LPM token the normal transmit method is not used. Sending a LPM token requires the USB334x to send a 0000b or `F0' PID. When the ULPI specification was defined the `F0' PID was not defined. The ULPI specification used the "Reserved" `F0' PID to signal chirp and resume signaling while using OpMode 10b. While in OpMode 00b the USB334x is able to generate the `F0' PID as shown below. DS00002646A-page 54 2009-2018 Microchip Technology Inc. USB334x FIGURE 6-10: LPM TOKEN TRANSMIT CLK DATA[7:0] Idle TXD CMD (40h TX NOPID ) PID (F0h) D0 D1 Turn Around IDLE Turn Around RXD CMD IDLE DIR NXT STP DP/DM SE0 !SQUELCH SE0 To send the `F0' PID, the link will be required to use the TX CMD with NOPID to initiate the transmit and then follow up the TX CMD with the `F0' PID. The data bytes follow as in a normal transmit, in OpMode 00b. The key difference is in that the link will have to send the PID the same as it would send a data packet. The USB334x is able to recognize the LPM transmit and correctly send the PID information. 6.5 Low Power Mode Low Power Mode is a power down state to save current when the USB session is suspended. The Link controls when the PHY is placed into or out of Low Power Mode. In Low Power Mode all of the circuits are powered down except the interface pins, Full Speed receiver, VBUS comparators, and IdGnd comparator. The VBUS and ID comparators can optionally be powered down to save current as shown in Section 6.5.5, "Minimizing Current in Low Power Mode," on page 58. Before entering Low Power Mode, the USB334x must be configured to set the desired state of the USB transceiver. The XcvrSelect[1:0], TermSelect and OpMode[1:0] bits in the Function Control register, and the DpPulldown and DmPulldown bits in the OTG Control register control the configuration as shown in Table 5-1. The DP and DM pins are configured to a high impedance state by configuring OpMode[1:0] = 01 as shown in the programming example in Table 6-8. Pull-down resistors with a value of approximately 2M are present on the DP and DM pins to avoid false linestate indications that could result if the pins were allowed to float. 6.5.1 ENTERING LOW POWER/SUSPEND MODE To enter Low Power Mode, the Link will write a 0 or clear the SuspendM bit in the Function Control register. After this write is complete, the PHY will assert DIR high and after a minimum of five rising edges of CLKOUT, drive the clock low. After the clock is stopped, the PHY will enter a low power state to conserve current. Placing the PHY in Suspend Mode is not related to USB Suspend. To clarify this point, USB Suspend is initiated when a USB host stops data transmissions and enters Full-Speed mode with 15K pull-down resistors on DP and DM. The suspended device goes to Full-Speed mode with a pull-up on DP. Both the host and device remain in this state until one of them drives DM high (this is called a resume). 2009-2018 Microchip Technology Inc. DS00002646A-page 55 USB334x FIGURE 6-11: ENTERING LOW POWER MODE FROM SYNCHRONOUS MODE T0 T1 T2 T3 T4 T5 T6 CLK DATA[7:0] Idle TXD CMD (reg write) Reg Data[n] Idle Turn Around ... T10 Low Power Mode DIR STP NXT SUSPENDM (ULPI Register Bit) While in Low Power Mode, the Data interface is redefined so that the Link can monitor Linestate and the VBUS voltage. In Low Power Mode DATA[3:0] are redefined as shown in Table 6-7. Linestate[1:0] is the combinational output of the Single-Ended Receivers. The "int" or interrupt signal indicates an unmasked interrupt has occurred. When an unmasked interrupt or linestate change has occurred, the Link is notified and can determine if it should wake-up the PHY. TABLE 6-7: Signal INTERFACE SIGNAL MAPPING DURING LOW POWER MODE Maps to Direction Description linestate[0] DATA[0] OUT Combinatorial LineState[0] driven directly by the Full-Speed single ended receiver. Note 6-1 linestate[1] DATA[1] OUT Combinatorial LineState[1] driven directly by the Full-Speed single ended receiver. Note 6-1 reserved DATA[2] OUT Driven Low int DATA[3] OUT Active high interrupt indication. Must be asserted whenever any unmasked interrupt occurs. reserved DATA[7:4] OUT Driven Low Note 6-1 LineState: These signals reflect the current state of the Full-Speed single ended receivers. LineState[0] directly reflects the current state of DP. LineState[1] directly reflects the current state of DM. When DP=DM=0 this is called "Single Ended Zero" (SE0). When DP=DM=1, this is called "Single Ended One" (SE1). An unmasked interrupt can be caused by the following comparators changing state: VbusVld, SessVld, SessEnd, and IdGnd. If any of these signals change state during Low Power Mode and the bits are enabled in either the USB Interrupt Enable Rising or USB Interrupt Enable Falling registers, DATA[3] will assert. During Low Power Mode, the VbusVld and SessEnd comparators can have their interrupts masked to lower the suspend current as described in Section 6.5.5, "Minimizing Current in Low Power Mode," on page 58. While in Low Power Mode, the Data bus is driven asynchronously because all of the PHY clocks are stopped during Low Power Mode. DS00002646A-page 56 2009-2018 Microchip Technology Inc. USB334x 6.5.2 EXITING LOW POWER MODE To exit Low Power Mode, the Link will assert STP. Upon the assertion of STP, the USB334x will begin its start-up procedure. After the PHY start-up is complete, the PHY will start the clock on CLKOUT and de-assert DIR. After DIR has been de-asserted, the Link can de-assert STP when ready and start operating in Synchronous Mode. The PHY will automatically set the SuspendM bit to a 1 in the Function Control register. FIGURE 6-12: EXITING LOW POWER MODE T0 ... CLK DATA[7:0] LOW POWER MODE T1 T2 TURN AROUND T3 DATA BUS IGNORED (SLOW LINK) IDLE (FAST LINK) Fast Link Drives Bus Idle and STP low DIR T4 T5 IDLE Slow Link Drives Bus Idle and STP low STP Note: Not to Scale TSTART The value for TSTART is given in Table 4-3. Should the Link de-assert STP before DIR is de-asserted, the USB334x will detect this as a false resume request and return to Low Power Mode. This is detailed in Section 3.9.4 of the UTMI+ Low Pin Interface (ULPI) Specification Revision 1.1. 6.5.3 LINK POWER MANAGEMENT (LPM) When the USB334x is operating with a Link capable of Link Power Management, the Link will place the USB334x in and out of suspend rapidly to conserve power. The USB334x provides a fast suspend recovery that allows the USB334x to meet the suspend recovery time detailed in the Link Power Management ECN to the USB 2.0 specification. When the Link places the USB334x into suspend during Link Power Management, the LPM Enable bit of the HS Compensation Register must be set to 1. This allows the USB334x to start-up in the time specified in Table 4-3. 6.5.4 INTERFACE PROTECTION ULPI protocol assumes that both the Link and PHY will keep the ULPI data bus driven by either the Link when DIR is low or the PHY when DIR is high. The only exception is when DIR has changed state and a turn around cycle occurs for 1 clock period. In the design of a USB system, there can be cases where the Link may not be driving the ULPI bus to a known state while DIR is low. Two examples where this can happen is because of a slow Link start-up or a hardware reset. 6.5.4.1 Start up Protection Upon start-up, when the PHY de-asserts DIR, the Link must be ready to receive commands and drive Idle on the data bus. If the Link is not ready to receive commands or drive Idle, it must assert STP before DIR is de-asserted. The Link can then de-assert STP when it has completed its start-up. If the Link doesn't assert STP before it can receive commands, the PHY may interpret the data bus state as a TX CMD and transmit invalid data onto the USB bus, or make invalid register writes. 2009-2018 Microchip Technology Inc. DS00002646A-page 57 USB334x When the USB334x sends a RXCMD the Link is required to drive the data bus back to idle at the end of the turn around cycle. If the Link does not drive the databus to idle the USB334x may take the information on the data bus as a TXCMD and transmit data on DP and DM until the Link asserts stop. If the ID pin is floated the last RXCMD from the USB334x will remain on the bus after DIR is de-asserted and the USB334x will take this in as a TXCMD. A Link should be designed to have the default POR state of the STP output high and the data bus tri-stated. The USB334x has weak pull-downs on the data bus to prevent these inputs from floating when not driven. These resistors are only used to prevent the ULPI interface from floating during events when the link ULPI pins may be tri-stated. The strength of the pull down resistors can be found in Table 4-5. The pull downs are not strong enough to pull the data bus low after a ULPI RXCMD, the Link must drive the data bus to idle after DIR is de-asserted. In some cases, a Link may be software configured and not have control of its STP pin until after the PHY has started. In this case, the USB334x has in internal pull-up on the STP input pad which will pull STP high while the Link's STP output is tri-stated. The STP pull-up resistor is enabled on POR and can be disabled by setting the InterfaceProtectDisable bit 7 of the Interface Control register. The STP pull-up resistor will pull-up the Link's STP input high until the Link configures and drives STP high. After the Link completes its start-up, STP can be synchronously driven low. A Link design which drives STP high during POR can disable the pull-up resistor on STP by setting InterfaceProtectDisable bit to 1. A motivation for this is to reduce the suspend current. In Low Power Mode, STP is held low, which would draw current through the pull-up resistor on STP. 6.5.4.2 Warm Reset Designers should also consider the case of a warm restart of a Link with a PHY in Low Power Mode. After the PHY enters Low Power Mode, DIR is asserted and the clock is stopped. The USB334x looks for STP to be asserted to restart the clock and then resume normal synchronous operation. Should the USB334x be suspended in Low Power Mode, and the Link receives a hardware reset, the PHY must be able to recover from Low Power Mode and start its clock. If the Link asserts STP on reset, the PHY will exit Low Power Mode and start its clock. If the Link does not assert STP on reset, the interface protection pull-up can be used. When the Link is reset, its STP output will tri-state and the pull-up resistor will pull STP high, signaling the PHY to restart its clock. 6.5.5 MINIMIZING CURRENT IN LOW POWER MODE In order to minimize the suspend current in Low Power Mode, the VBUS and ID comparators can be disabled to reduce suspend current. In Low Power Mode, the VbusVld and SessEnd comparators are not needed and can be disabled by clearing the associated bits in both the USB Interrupt Enable Rising and USB Interrupt Enable Falling registers. By disabling the interrupt in BOTH the rise and fall registers, the SessEnd and VbusVld comparators are turned off. The IdFloatRise and IdFloatFall bits in Carkit Interrupt Enable register should also be disabled if they were set. When exiting Low Power Mode, the Link should immediately re-enable the VbusVld and SessEnd comparators if host or OTG functionality is required. In addition to disabling the OTG comparators in Low Power Mode, the Link may choose to disable the Interface Protect Circuit. By setting the InterfaceProtectDisable bit high in the Interface Control register, the Link can disable the pull-up resistor on STP. When RESETB is low the Interface Protect Circuit will be disabled. 6.6 Full Speed/Low Speed Serial Modes The USB334x includes two serial modes to support legacy Links which use either the 3pin or 6pin serial format. To enter either serial mode, the Link will need to write a 1 to the 6-pin FsLsSerialMode or the 3-pin FsLsSerialMode bits in the Interface control register. Serial Mode may be used to conserve power when attached to a device that is not capable of operating in Hi-Speed. The serial modes are entered in the same manner as the entry into Low Power Mode. The Link writes the Interface Control register bit for the specific serial mode. The USB334x will assert DIR and shut off the clock after at least five clock cycles. Then the data bus goes to the format of the serial mode selected. Before entering Serial Mode the Link must set the ULPI transceiver to the appropriate mode as defined in Table 5-1. In ULPI Clock Output Mode, the PHY will shut off the 60 MHz clock to conserve power. Should the Link need the 60 MHz clock to continue during the serial mode of operation, the ClockSuspendM bit[3] of the Interface Control Register should be set before entering a serial mode. If set, the 60 MHz clock will be present during serial modes. DS00002646A-page 58 2009-2018 Microchip Technology Inc. USB334x In serial mode, interrupts are possible from unmasked sources. The state of each interrupt source is sampled prior to the assertion of DIR and this is compared against the asynchronous level from interrupt source. Exiting the serial modes is the same as exiting Low Power Mode. The Link must assert STP to signal the PHY to exit serial mode. When the PHY can accept a command, DIR is de-asserted and the PHY will wait until the Link de-asserts STP to resume synchronous ULPI operation. The RESETB pin can also be pulsed low to reset the USB334x and return it to Synchronous Mode. 6.6.1 3-PIN FS/LS SERIAL MODE Three pin serial mode utilizes the data bus pins for the serial functions shown in Table 6-8. TABLE 6-8: PIN DEFINITIONS IN 3 PIN SERIAL MODE Signal Connected to Direction tx_enable DATA[0] IN Active High transmit enable. data DATA[1] I/O TX differential data on DP/DM when tx_enable is high. RX differential data from DP/DM when tx_enable is low. SE0 DATA[2] I/O TX SE0 on DP/DM when tx_enable is high. RX SE0_b from DP/DM when tx_enable is low. interrupt DATA[3] OUT Asserted when any unmasked interrupt occurs. Active high. Reserved DATA[7:4] OUT Driven Low. 6.6.2 Description 6-PIN FS/LS SERIAL MODE Six pin serial mode utilizes the data bus pins for the serial functions shown in Table 6-9. TABLE 6-9: PIN DEFINITIONS IN 6 PIN SERIAL MODE Signal Connected to Direction tx_enable DATA[0] IN Active High transmit enable. tx_data DATA[1] IN Tx differential data on DP/DM when tx_enable is high. tx_se0 DATA[2] IN Tx SE0 on DP/DM when tx_enable is high. interrupt DATA[3] OUT Asserted when any unmasked interrupt occurs. Active high. rx_dp DATA[4] OUT Single ended receive data on DP. rx_dm DATA[5] OUT Single ended receive data on DM. rx_rcv DATA[6] OUT Differential receive data from DP and DM. Reserved DATA[7] OUT Driven Low. 6.7 Description Carkit Mode The USB334x includes Carkit Mode to support a USB UART and USB Audio Mode. By entering Carkit Mode, the USB334x current drain is minimized. The internal PLL is disabled and the 60 MHz ULPI CLKOUT will be stopped to conserve power by default. The Link may configure the 60 MHz clock to continue by setting the ClockSuspendM bit of the Interface Control register before entering Carkit Mode. If set, the 60 MHz clock will continue during the Carkit Mode of operation. 2009-2018 Microchip Technology Inc. DS00002646A-page 59 USB334x In Carkit Mode, interrupts are possible if they have been enabled in the Carkit Interrupt Enable register. The state of each interrupt source is sampled prior to the assertion of DIR and this is compared against the asynchronous level from interrupt source. In Carkit Mode, the Linestate signals are not available per the ULPI specification. The ULPI interface is redefined to the following when Carkit Mode is entered. TABLE 6-10: PIN DEFINITIONS IN CARKIT MODE Signal Connected to Direction Description txd DATA[0] IN UART TXD signal that is routed to the DM pin if the TxdEn is set in the Carkit Control register. rxd DATA[1] OUT UART RXD signal that is routed to the DP pin if the RxdEn bit is set in the Carkit Control register. reserved DATA[2] OUT Driven Low (CarkitDataMC = 0, default) IN Tri-state (CarkitDataMC = 1) int DATA[3] OUT Asserted when any unmasked interrupt occurs. Active high. reserved DATA[4:7] OUT Driven Low. Exiting Carkit Mode is the same as exiting Low Power Mode as described in Section 6.5.2, "Exiting Low Power Mode," on page 57. The Link must assert STP to signal the PHY to exit serial mode. When the PHY can accept a command, DIR is de-asserted and the PHY will wait until the Link de-asserts STP to resume synchronous ULPI operation. The RESETB pin can also be pulsed low to reset the USB334x and return it to Synchronous Mode. 6.7.1 ENTERING USB UART MODE The USB334x can be placed into UART Mode by first setting the TxdEn and RxdEn bits in the Carkit Control register. Then the Link can set the CarkitMode bit in the Interface Control register. The TxdEn and RxdEn bits must be written before the CarkitMode bit. TABLE 6-11: ULPI REGISTER PROGRAMMING EXAMPLE TO ENTER UART MODE R/W Address (HEX) Value (HEX) W 04 W Description Result 49 Configure Non-Driving mode Select FS transmit edge rates OpMode=01 XcvrSelect=01 39 00 Set regulator to 3.3V UART RegOutput=00 W 19 0C Enable UART connections RxdEn=1 TxdEn=1 W 07 04 Enable carkit mode CarkitMode=1 After the CarkitMode bit is set, the ULPI interface will become redefined as described in Table 6-10, and the USB334x will transmit data through the DATA[0] to DM of the USB connector and receive data on DP and pass the information the Link on DATA[1]. When entering UART mode, the regulator output will automatically switch to the value configured by the UART RegOutput bits in the USB IO & Power Management register and the RCD pull-up resistors will be applied internally to DP and DM. This will hold the UART in its default operating state. While in UART mode, the transmit edge rates can be set to either the Full Speed USB or Low Speed USB edge rates by using the XcvrSelect[1:0] bits in the Function Control register. DS00002646A-page 60 2009-2018 Microchip Technology Inc. USB334x 6.7.2 USB AUDIO MODE (USB3341 and USB3346) When the USB334x is powered in Synchronous Mode, the Audio switches can be enabled by asserting the SpkLeftEn, or SpkRightEn bits in the Carkit Control register. After the register write is complete, the USB334x will immediately enable or disable the audio switch. Then the Link can set the CarkitMode bit in the Interface Control register. The SpkLeftEn, or SpkRightEn bits must be written before the CarkitMode bit. TABLE 6-12: ULPI REGISTER PROGRAMMING EXAMPLE TO ENTER AUDIO MODE R/W Address (HEX) Value (HEX) Description Result W 04 48 Configure Non-Driving mode OpMode=01 W 19 30 Enable Audio connections SpkrRightEn=1, SpkrLeftEn=1 W 07 04 Enable carkit mode CarkitMode=1 After the CarkitMode bit is set, the ULPI interface will become redefined as described in Table 6-10. 6.8 RID Converter Operation The RID converter is designed to read the value of the ID resistance to ground and report back its value through the ULPI interface. When a resistor to ground is applied to the ID pin the state of the IdGnd comparator will change from a 1 to a 0 as described in Section 5.7.1, "ID Resistor Detection," on page 32. If the USB334x is in ULPI mode, an RXCMD will be generated with bit 6 low. If the USB334x is in Low Power Mode (or one of the other non-ULPI modes), the DATA[3] interrupt signal will go high. After the USB334x has detected the change of state on the ID pin, the RID converter can be used to determine the value of ID resistance. To start a ID resistance measurement, the RidConversionStart bit is set in the Vendor Rid Conversion register. The Link can use one of two methods to determine when the RID Conversion is complete. One method is polling the RidConversionStart bit as described in Section 7.1.3.4, "Vendor Rid Conversion," on page 74. The preferred method is to set the RidIntEn bit in the Vendor Rid Conversion register. When RidIntEn is set, an RXCMD will be generated after the RID conversion is complete. As described in Table 6-3, the alt_int bit of the RXCMD will be set. After the RID Conversion is complete, the Link can read RidValue from the Vendor Rid Conversion register. 6.8.1 HEADSET AUDIO MODE This mode is designed to allow a user to view the status of several signals while using an analog Audio headset with a USB connector. This mode is provided as an alternate mode to the CarKit Mode defined in Section 6.7, "Carkit Mode," on page 59. In the CarKit mode the Link is unable to view the source of the interrupt on ID. For the Link to view the interrupt on ID the PHY must be returned to synchronous mode so the interrupt can be read. This will force the audio switches to be deactivated during the PHY start-up which may glitch the audio signals. In addition the Link can not change the resistance on the ID pin without starting up the PHY to access the ULPI registers. The Headset Audio Mode is entered by writing to the Headset Audio Mode register, and allows the Link access to the state of the VBUS and ID pins during audio without having to break the audio connection. The Headset Audio mode also allows for the Link to change the resistance on the ID pin to change the audio device attached from mono to stereo. 2009-2018 Microchip Technology Inc. DS00002646A-page 61 USB334x TABLE 6-13: Signal PIN DEFINITIONS IN HEADSET AUDIO MODE Connected to Direction Description SessVld DATA[0] OUT Output of SessVld comparator VbusVld DATA[1] OUT Output of VbusVld Comparator (interrupt must be enabled) IdGndDrv DATA[2] IN Drives ID pin to ground when asserted 0b: Not connected 1b: Connects ID to ground. DATA[3] OUT Driven low IdGround DATA[4] OUT Asserted when the ID pin is grounded. 0b: ID pin is grounded 1b: ID pin is floating IdFloat DATA[5] OUT Asserted when the ID pin is floating. IdPullup or Id_pullup330 must be enabled. IdFloatRise and IdFloatFall must be enabled. IdPullup330 DATA[6] IN When enabled a 330k pullup is applied to the ID pin. This bit will also change the trip point of the IdGnd comparator to the value shown in Table 4-9. 0b: Disables the pull-up resistor 1b: Enables the pull-up resistor IdPullup DATA[7] IN Connects the 100k pull-up resistor from the ID pin to VDD3.3 0b: Disables the pull-up resistor 1b: Enables the pull-up resistor Exiting Headset Audio Mode is the same as exiting Low Power Mode as described in Section 6.5.2, "Exiting Low Power Mode," on page 57. The RESETB pin can also be pulsed low to reset the USB334x and return to Synchronous Mode. DS00002646A-page 62 2009-2018 Microchip Technology Inc. USB334x 7.0 ULPI REGISTER MAP 7.1 ULPI Register Array The USB334x PHY implements all of the ULPI registers detailed in the ULPI revision 1.1 specification. The complete USB334x ULPI register set is shown in Table 7-1. All registers are 8 bits. This table also includes the default state of each register upon POR or de-assertion of RESETB, as described in Section 5.6.2, "Power On Reset (POR)," on page 31. The RESET bit in the Function Control Register does not reset the bits of the ULPI register array. The Link should not read or write to any registers not listed in this table. The USB334x supports extended register access. The immediate register set (00-3Fh) can be accessed through either a immediate address or an extended register address. TABLE 7-1: ULPI REGISTER MAP Register Name Default State Address (6bit) Read Write Set Clear Vendor ID Low 24h 00h - - - Vendor ID High 04h 01h - - - Product ID Low 09h 02h - - - Product ID High 00h 03h - - - Function Control 41h 04-06h 04h 05h 06h Interface Control 00h 07-09h 07h 08h 09h OTG Control 06h 0A-0Ch 0Ah 0Bh 0Ch USB Interrupt Enable Rising 1Fh 0D-0Fh 0Dh 0Eh 0Fh USB Interrupt Enable Falling 1Fh 10-12h 10h 11h 12h USB Interrupt Status (Note 7-1) 00h 13h - - - USB Interrupt Latch 00h 14h - - - Debug 00h 15h - - - Scratch Register 00h 16-18h 16h 17h 18h Carkit Control 00h 19-1Bh 19h 1Ah 1Bh Reserved 00h Carkit Interrupt Enable 00h 1D-1Fh 1Dh 1Eh 1Fh Carkit Interrupt Status 00h 20h - - - Carkit Interrupt Latch 00h 21h - - - Reserved 00h HS Compensation Register 00h 31h 31h - - USB-IF Charger Detection 00h 32h 32h - - Headset Audio Mode 00 33 33 - - Reserved 00h 2009-2018 Microchip Technology Inc. 1Ch 22-30h 34-35h DS00002646A-page 63 USB334x TABLE 7-1: ULPI REGISTER MAP (CONTINUED) Default State Register Name Address (6bit) Read Write Set Clear Vendor Rid Conversion 00h 36-38h 36h 37h 38h USB IO & Power Management 04h 39-3Bh 39h 3Ah 3Bh Reserved 00h Note 7-1 7.1.1 3C-3Fh Dynamically updates to reflect current status of interrupt sources. ULPI REGISTER SET The following registers are used for the ULPI interface. 7.1.1.1 Vendor ID Low Address = 00h (read only) Field Name Vendor ID Low 7.1.1.2 Bit Access Default 7:0 rd 24h Bit Access Default 7:0 rd 04h Bit Access Default 7:0 rd 09h Bit Access Default 7:0 rd 00h Description Microchip Vendor ID Vendor ID High Address = 01h (read only) Field Name Vendor ID High 7.1.1.3 Description Microchip Vendor ID Product ID Low Address = 02h (read only) Field Name Product ID Low 7.1.1.4 Description Microchip Product ID Product ID High Address = 03h (read only) Field Name Product ID High DS00002646A-page 64 Description Microchip Product ID 2009-2018 Microchip Technology Inc. USB334x 7.1.1.5 Function Control Address = 04-06h (read), 04h (write), 05h (set), 06h (clear) Field Name Bit Access Default 1:0 rd/w/s/c 01b Selects the required transceiver speed. 00b: Enables HS transceiver 01b: Enables FS transceiver 10b: Enables LS transceiver 11b: Enables FS transceiver for LS packets (FS preamble automatically pre-pended) 2 rd/w/s/c 0b Controls the DP and DM termination depending on XcvrSelect, OpMode, DpPulldown, and DmPulldown. The DP and DM termination is detailed in Table 5-1. 4:3 rd/w/s/c 00b Selects the required bit encoding style during transmit. 00b: Normal Operation 01b: Non-Driving 10b: Disable bit-stuff and NRZI encoding 11b: Reserved Reset 5 rd/w/s/c 0b Active high transceiver reset. This reset does not reset the ULPI interface or register set. Automatically clears after reset is complete. SuspendM 6 rd/w/s/c 1b Active low PHY suspend. When cleared the PHY will enter Low Power Mode as detailed in Section 6.5, "Low Power Mode," on page 55. Automatically set when exiting Low Power Mode. LPM Enable 7 rd/w/s/c 0b When enabled the PLL start-up time is shortened to allow fast start-up for LPM. The reduced PLL start-up time is achieved by bypassing the VCO process compensation which was done on initial start-up. XcvrSelect[1:0] TermSelect OpMode 7.1.1.6 Description Interface Control Address = 07-09h (read), 07h (write), 08h (set), 09h (clear) Field Name Bit Access Default Description 6-pin FsLsSerialMode 0 rd/w/s/c 0b When asserted the ULPI interface is redefined to the 6-pin Serial Mode. The PHY will automatically clear this bit when exiting serial mode. 3-pin FsLsSerialMode 1 rd/w/s/c 0b When asserted the ULPI interface is redefined to the 3-pin Serial Mode. The PHY will automatically clear this bit when exiting serial mode. CarkitMode 2 rd/w/s/c 0b When asserted the ULPI interface is redefined to the Carkit interface. The PHY will automatically clear this bit when exiting Carkit Mode. 2009-2018 Microchip Technology Inc. DS00002646A-page 65 USB334x Field Name Bit Access Default Description ClockSuspendM 3 rd/w/s/c 0b Enables Link to turn on 60 MHz CLKOUT in Serial Mode or Carkit Mode. 0b: Disable clock in serial or Carkit Mode. 1b: Enable clock in serial or Carkit Mode. AutoResume 4 rd/w/s/c 0b Only applicable in Host mode. Enables the PHY to automatically transmit resume signaling. This function is detailed in Section 6.4.1.4, "Host Resume K," on page 53. IndicatorComplement 5 rd/w/s/c 0b Inverts the EXTVBUS signal. This function is detailed in Section 5.7.2, "VBUS Monitoring and VBUS Pulsing," on page 35. Note: IndicatorPassThru 6 rd/w/s/c 0b Disables and'ing the internal VBUS comparator with the EXTVBUS signal when asserted. This function is detailed in Section 5.7.2, "VBUS Monitoring and VBUS Pulsing," on page 35. Note: InterfaceProtectDisable 7.1.1.7 7 rd/w/s/c 0b The EXTVBUS signal is always high on the USB334x. The EXTVBUS signal is always high on the USB334x. Used to disable the integrated STP pull-up resistor used for interface protection. This function is detailed in Section 6.5.4, "Interface Protection," on page 57. OTG Control Address = 0A-0Ch (read), 0Ah (write), 0Bh (set), 0Ch (clear) Field Name Bit Access Default Description IdPullup 0 rd/w/s/c 0b Connects a 100 k pull-up resistor from the ID pin to VDD33 0b: Disables the pull-up resistor 1b: Enables the pull-up resistor DpPulldown 1 rd/w/s/c 1b Enables the 15 k pull-down resistor on DP. 0b: Pull-down resistor not connected 1b: Pull-down resistor connected DmPulldown 2 rd/w/s/c 1b Enables the 15 k pull-down resistor on DM. 0b: Pull-down resistor not connected 1b: Pull-down resistor connected DischrgVbus 3 rd/w/s/c 0b This bit is only used during SRP. Connects a resistor from VBUS to ground to discharge VBUS. 0b: disconnect resistor from VBUS to ground 1b: connect resistor from VBUS to ground ChrgVbus 4 rd/w/s/c 0b This bit is only used during SRP. Connects a resistor from VBUS to VDD33 to charge VBUS above the SessValid threshold. 0b: disconnect resistor from VBUS to VDD33 1b: connect resistor from VBUS to VDD33 DS00002646A-page 66 2009-2018 Microchip Technology Inc. USB334x Field Name Bit Access Default Description DrvVbus 5 rd/w/s/c 0b Enables external 5 volt supply to drive 5 volts on VBUS. This signal is or'ed with DrvVbusExternal. 0b: Do not drive Vbus. 1b: Drive Vbus DrvVbusExternal 6 rd/w/s/c 0b Enables external 5 volt supply to drive 5 volts on VBUS. This signal is or'ed with DrvVbus. 0b: Do not drive Vbus 1b: Drive Vbus UseExternalVbus Indicator 7 rd/w/s/c 0b Tells the PHY to use an external VBUS over-current or voltage indicator. This function is detailed in Section 5.7.2, "VBUS Monitoring and VBUS Pulsing," on page 35. 0b: Use the internal VbusValid comparator 1b: Use the EXTVBUS input as for VbusValid signal. Note: 7.1.1.8 The EXTVBUS signal is always high on the USB334x. USB Interrupt Enable Rising Address = 0D-0Fh (read), 0Dh (write), 0Eh (set), 0Fh (clear) Field Name Bit Access Default Description HostDisconnect Rise 0 rd/w/s/c 1b Generate an interrupt event notification when Hostdisconnect changes from low to high. Applicable only in host mode. VbusValid Rise 1 rd/w/s/c 1b Generate an interrupt event notification when Vbusvalid changes from low to high. SessValid Rise 2 rd/w/s/c 1b Generate an interrupt event notification when SessValid changes from low to high. SessEnd Rise 3 rd/w/s/c 1b Generate an interrupt event notification when SessEnd changes from low to high. IdGnd Rise 4 rd/w/s/c 1b Generate an interrupt event notification when IdGnd changes from low to high. 7:5 rd 0h Read only, 0. Reserved 7.1.1.9 USB Interrupt Enable Falling Address = 10-12h (read), 10h (write), 11h (set), 12h (clear) Field Name Bit Access Default Description HostDisconnect Fall 0 rd/w/s/c 1b Generate an interrupt event notification when Hostdisconnect changes from high to low. Applicable only in host mode. VbusValid Fall 1 rd/w/s/c 1b Generate an interrupt event notification when Vbusvalid changes from high to low. SessValid Fall 2 rd/w/s/c 1b Generate an interrupt event notification when SessValid changes from high to low. 2009-2018 Microchip Technology Inc. DS00002646A-page 67 USB334x Field Name Bit Access Default SessEnd Fall 3 rd/w/s/c 1b Generate an interrupt event notification when SessEnd changes from high to low. IdGnd Fall 4 rd/w/s/c 1b Generate an interrupt event notification when IdGnd changes from high to low. Reserved 7:5 rd 0h Read only, 0. 7.1.1.10 Description USB Interrupt Status Address = 13h (read only) This register dynamically updates to reflect current status of interrupt sources. Field Name Bit Access Default Description HostDisconnect 0 0b Current value of the UTMI+ HS Hostdisconnect output. Applicable only in host mode. VbusValid 1 0b Current value of the UTMI+ Vbusvalid output. If VbusValid Rise and VbusValid Fall are set this register will read 0. SessValid 2 0b Current value of the UTMI+ SessValid output. This register will always read the current status of the Session Valid comparator regardless of the SessValid Rise and SessValid Fall settings. SessEnd 3 0b Current value of the UTMI+ SessEnd output. If SessEnd Rise and SessEnd Fall are set this register will read 0. IdGnd 4 0b Current value of the UTMI+ IdGnd output. 7:5 0h Read only, 0. Reserved Note: rd (read only) The default value is only valid after POR. When the register is read it will match the current status of the comparators at the moment the register is read. DS00002646A-page 68 2009-2018 Microchip Technology Inc. USB334x 7.1.1.11 USB Interrupt Latch Address = 14h (read only with auto clear) Field Name Bit Access Default Description HostDisconnect Latch 0 0b Set to 1b by the PHY when an unmasked event occurs on Hostdisconnect. Cleared when this register is read. Applicable only in host mode. VbusValid Latch 1 0b Set to 1b by the PHY when an unmasked event occurs on VbusValid. Cleared when this register is read. SessValid Latch 2 0b Set to 1b by the PHY when an unmasked event occurs on SessValid. Cleared when this register is read. SessEnd Latch 3 0b Set to 1b by the PHY when an unmasked event occurs on SessEnd. Cleared when this register is read. IdGnd Latch 4 0b Set to 1b by the PHY when an unmasked event occurs on IdGnd. Cleared when this register is read. 0h Read only, 0. rd (Note 7-2) Reserved 7:5 Note 7-2 rd: Read Only with auto clear. 7.1.1.12 rd Debug Address = 15h (read only) Field Name Bit Access Default Linestate[1:0] 1:0 rd 00b Reserved 7:2 rd 000000b 7.1.1.13 Description Contains the current value of Linestate[1:0]. Read only, 0. Scratch Register Address = 16-18h (read), 16h (write), 17h (set), 18h (clear) Field Name Scratch Bit Access Default 7:0 rd/w/s/c 00h 2009-2018 Microchip Technology Inc. Description Empty register byte for testing purposes. Software can read, write, set, and clear this register and the PHY functionality will not be affected. DS00002646A-page 69 USB334x 7.1.2 CARKIT CONTROL REGISTERS The following registers are used to set-up and enable the USB UART and USB Audio functions. 7.1.2.1 Carkit Control Address = 19-1Bh (read), 19h (write), 1Ah (set), 1Bh (clear) This register is used to program the USB334x into and out of the Carkit Mode. When entering the UART mode the Link must first set the desired TxdEn and the RxdEn bits and then transition to Carkit Mode by setting the CarkitMode bit in the Interface Control Register. When RxdEn is not set then the DATA[1] pin is held to a logic high. Field Name Bit Access Default CarkitPwr 0 rd 0b Read only, 0. IdGndDrv 1 rd/w/s/c 0b Drives ID pin to ground TxdEn 2 rd/w/s/c 0b Connects UART TXD (DATA[0]) to DM RxdEn 3 rd/w/s/c 0b Connects UART RXD (DATA[1]) to DP SpkLeftEn 4 rd/w/s/c 0b Connects DM pin to SPK_L pin SpkRightEn 5 rd/w/s/c 0b Connects DP pin to SPK_R pin. See Note below. MicEn 6 rd/w/s/c 0b Connects DP pin to SPK_R pin. See Note below. CarkitDataMC 7 rd/w/s/c 0b When set the UPLI DATA[2] pin is changed from a driven 0 to tri-state, when carkit mode is entered. Note: Description If SpkRightEn or MicEn are asserted the DP pin will be connected to SPK_R. To disconnect the DP pin from the SPK_R pin both SpkrRightEn and MicEn must be set to de-asserted. If using USB UART mode, the UART data will appear at the SPK_L and SPK_R pins if the corresponding SpkLeftEn, SpkRightEn, or MicEn switches are enabled. If using USB Audio the TxdEn and RxdEn bits should not be set when the SpkLeftEn, SpkRightEn, or MicEn switches are enabled. The USB single-ended receivers described in Section 5.2.1, "USB Transceiver," on page 25 are disabled when either SpkLeftEn, SpkRightEn, or MicEn are set. 7.1.2.2 Carkit Interrupt Enable Address = 1D-1Fh (read), 1Dh (write), 1Eh (set), 1Fh (clear) Field Name Bit Access Default Description IdFloatRise 0 rd/w/s/c 0b When enabled an interrupt will be generated on the alt_int of the RXCMD byte when the ID pin transitions from non-floating to floating. The IdPullup bit in the OTG Control register should be set. IdFloatFall 1 rd/w/s/c 0b When enabled an interrupt will be generated on the alt_int of the RXCMD byte when the ID pin transitions from floating to non-floating. The IdPullup bit in the OTG Control register should be set. VdatDetIntEn 2 rd/w/s/c 0b When enabled an interrupt will be generated on the alt_int of the RXCMD byte when the VDAT_DET Comparator changes state. DS00002646A-page 70 2009-2018 Microchip Technology Inc. USB334x Field Name Bit Access Default Description CarDpRise 3 rd 0b Not Implemented. Reads as 0b. CarDpFall 4 rd 0b Not Implemented. Reads as 0b. RidIntEn 5 rd/w/s/c 0b When enabled an interrupt will be generated on the alt_int of the RXCMD byte when RidConversionDone bit is asserted. Note: This register bit is or'ed with the RidIntEn bit of the Vendor Rid Conversion register described in Section 7.1.3.4, "Vendor Rid Conversion," on page 74. Reserved 6 rd/w/s/c 0b Read only, 0. Reserved 7 rd 0b Read only, 0. Bit Access Default Description IdFloat 0 rd 0b Asserted when the ID pin is floating. IdPullup must be enabled. VdatDet 1 rd 0b VDAT_DET Comparator output 0b: No voltage is detected on DP 1b: Voltage detected on DP, IdatSinkEn must be set to 1. 7.1.2.3 Carkit Interrupt Status Address = 20h (read only) Field Name Note: CarDp RidValue VdatDet can also be read from the USB-IF Charger Detection register described in Section 7.1.3.3, "Headset Audio Mode," on page 74. 2 rd 0b Not Implemented. Reads as 0b. 5:3 rd 000b Conversion value of Rid resistor 000: 0 001: 75 010: 102 K 011: 200 K 100: Reserved 101: ID floating 111: Error Note: 2009-2018 Microchip Technology Inc. RidValue can also be read from the Vendor Rid Conversion register described in Section 7.1.3.4, "Vendor Rid Conversion," on page 74. DS00002646A-page 71 USB334x Field Name RidConversionDone Bit Access Default Description 6 rd 0b Automatically asserted by the USB334x when the Rid Conversion is finished. The conversion will take 282uS. This bit will auto clear when the RidValue is read from the Rid Conversion Register. Reading the RidValue from the Carkit Interrupt Status register will not clear either RidConversionDone status bit. Note: Reserved 7.1.2.4 7 rd 0b RidConversionDone can also be read from the Vendor Rid Conversion register described in Section 7.1.3.4, "Vendor Rid Conversion," on page 74. Read only, 0. Carkit Interrupt Latch Address = 21h (read only with auto-clear) Field Name Bit Access Default Description IdFloat Latch 0 rd (Note 7-3) 0b Asserted if the state of the ID pin changes from nonfloating to floating while the IdFloatRise bit is enabled or if the state of the ID pin changes from floating to non-floating while the IdFloatFall bit is enabled. VdatDet Latch 1 rd 0b If VdatDetIntEn is set and the VdatDet bit changes state, this bit will be asserted. CarDp Latch 2 rd 0b Not Implemented. Reads as 0b. RidConversionLatch 3 rd (Note 7-3) 0b If RidIntEn is set and the state of the RidConversionDone bit changes from a 0 to 1 this bit will be asserted. Reserved 7:4 rd 0000b Note 7-3 rd: Read Only with auto clear 7.1.3 Read only, 0. VENDOR REGISTER ACCESS The vendor specific registers include the range from 30h to 3Fh. These can be accessed by the ULPI immediate register read / write. 7.1.3.1 HS Compensation Register Address = 31h (read / write) The USB334x is designed to meet the USB specifications and requirements when the DP and DM signals are properly designed on the PCB. The DP and DM trace impedance should be 45 single ended and 90 differential. In cases where the DP and DM traces are not able to meet these requirements the HS Compensation register can be used to compensate for the losses in signal amplitude. DS00002646A-page 72 2009-2018 Microchip Technology Inc. USB334x Field Name Bit Access Default Description VariSense 1:0 rd/w 00b Used to lower the threshold of the squelch detector. 00: 100% (default) 01: 83% 10: 66.7% 11: 50% Reserved 2 rd 0b Read only, 0. Reserved 3 rd 0b Read only, 0. PHYBoost 6:4 rd/w 000b Reserved 7 rd 0b 7.1.3.2 Used to change the output voltage of the Hi-Speed transmitter 000: Nominal 001: +3.7% 010: +7.4% 011: +11.0% 100: +14.7% 101: +18.3% 110: +22.0% 111: +25.7% Read only, 0. USB-IF Charger Detection Address = 32h (read / write) Field Name Bit Access Default VDatSrcEn 0 rd/w 0 VDAT_SRC voltage enable 0b: Disabled 1b: Enabled IDatSinkEn 1 rd/w 0 IDAT_SINK current sink and VDAT_DET comparator enable 0b: Disabled, VDAT_DET = 0. 1b: Enabled ContactDetectEn 2 rd/w 0 IDP_SRC Enable 0b: Disabled 1b: Enabled HostChrgEn 3 rd/w 0 Enable Charging Host Port Mode. 0b: Portable Device 1b: Charging Host Port. When the charging host port bit is set the connections of VDAT_SRC, IDAT_SINK, IDP_SRC, and VDAT_DET are reversed between DP and DM. 2009-2018 Microchip Technology Inc. Description DS00002646A-page 73 USB334x Field Name VdatDet Bit Access Default Description 4 rd 0 VDAT_DET Comparator output. IdatSinkEn must be set to 1 to enable the comparator. 0b: No voltage is detected on DP or Linestate[1:0] is not equal to 00b. 1b: Voltage detected on DP, and Linestate[1:0] = 00b. Note: Reserved Note: 7.1.3.3 5-7 rd VdatDet can also be read from the Carkit Interrupt Status register described in Section 7.1.2.3, "Carkit Interrupt Status," on page 71. Read only, 0. The charger detection should be turned off before beginning USB operation. USB-IF Charger Detection Bits 2:0 should be set to 000b. Headset Audio Mode Address = 33h (read / write) Field Name Bit Access Default Description HeadsetAudioEn 3:0 rd/w 0000b When this field is set to a value of `1010', the Headset Audio Mode is enabled as described in Section 6.8.1, "Headset Audio Mode," on page 61. Reserved 7:4 rd 0h 7.1.3.4 Read only, 0. Vendor Rid Conversion Address = 36-38h (read), 36h (write), 37h (set), 38h (clear) Field Name RidValue Bit Access Default 2:0 rd/w 000b Description Conversion value of Rid resistor 000: 0 001: 75 010: 100 K 011: 200 K 100: 440 K 101: ID floating 111: Error Note: RidConversionDone 3 rd (Note 7-4) 0b Automatically asserted by the USB334x when the Rid Conversion is finished. The conversion will take 282uS. This bit will auto clear when the RidValue is read from the Rid Conversion Register. Reading the RidValue from the Carkit Interrupt Status Register will not clear either RidConversionDone status bit. Note: DS00002646A-page 74 RidValue can also be read from the Carkit Interrupt Status Register. RidConversionDone can also be read from the Carkit Interrupt Status Register. 2009-2018 Microchip Technology Inc. USB334x Field Name Bit Access Default Description RidConversionStart 4 rd/w/s/c 0b When this bit is asserted either through a register write or set, the Rid converter will read the value of the ID resistor. When the conversion is complete this bit will auto clear. Reserved 5 rd/w/s/c 0b This bit must remain at 0. RidIntEn 6 rd/w/s/c 0b When enabled an interrupt will be generated on the alt_int of the RXCMD byte when RidConversionDone bit is asserted. Note: Reserved 7 Note 7-4 7.1.3.5 rd 0b This register bit is or'ed with the RidIntEn bit of the Carkit Interrupt Status register. Read only, 0. rd: Read Only with auto clear. USB IO & Power Management Address = 39-3Bh (read), 39h (write), 3Ah (set), 3Bh (clear) Field Name Bit Access Default Reserved 0 rd/w/s/c 0b Read only, 0. SwapDP/DM 1 rd/w/s/c 0b When asserted, the DP and DM pins of the USB transceiver are swapped. This bit can be used to prevent crossing the DP/DM traces on the board. In UART mode, it swaps the routing to the DP and DM pins. In USB Audio Mode, it does not affect the SPK_L and SPK_R pins. 3:2 rd/w/s/c 01b Controls the output voltage of the VBAT to VDD33 regulator in UART mode. When the PHY is switched from USB mode to UART mode regulator output will automatically change to the value specified in this register when TxdEn is asserted. 00: 3.3V 01: 3.0V (default) 10: 2.75V 11: 2.5V UART RegOutput Description Note: When in USB Audio Mode the regulator will remain at 3.3V. When using this register it is recommended that the Link exit UART mode by using the RESETB pin. ChargerPullupEnDP 4 rd/w/s/c 0b Enables the RCD Pull-up resistor on the DP pin. (The pull-up is automatically enabled in UART mode) ChargerPullupEnDM 5 rd/w/s/c 0b Enables the RCD Pull-up resistor on the DM pin. (The pull-up is automatically enabled in UART mode) 2009-2018 Microchip Technology Inc. DS00002646A-page 75 USB334x Field Name USB RegOutput DS00002646A-page 76 Bit Access Default Description 7:6 rd/w/s/c 00b Controls the output voltage of the VBAT to VDD33 regulator in USB mode. When the PHY is in Synchronous Mode, Serial Mode, or Low Power Mode, the regulator output will be the value specified in this register. 00: 3.3V (default) 01: 3.0V 10: 2.75V 11: 2.5V 2009-2018 Microchip Technology Inc. USB334x 8.0 APPLICATION NOTES 8.1 Application Diagram The USB334x requires few external components as shown in the application diagrams. The USB 2.0 Specification restricts the voltage at the VBUS pin to a maximum value of 5.25V. In some applications, the voltage will exceed this limit, so the USB334x provides an integrated over voltage protection circuit. The over voltage protection circuit works with an external resistor (RVBUS) to lower the voltage at the VBUS pin. TABLE 8-1: REFERENCE DESIGNATOR COMPONENT VALUES IN APPLICATION DIAGRAMS VALUE DESCRIPTION COUT See Table 4-12 Bypass capacitor to ground (<1 ESR) for regulator stability. Place as close as possible to the PHY. CVBUS See Table 8-2 Capacitor to ground required by the USB Specification. Microchip recommends <1 ESR. Place near the USB connector. CBYP System dependent. Bypass capacitor to ground. Typical values used are 0.1 or 0.01 F. Place as close as possible to the PHY. CDC_LOAD System dependent. The USB connector housing may be ACcoupled to the device ground. Industry convention is to ground only the host side of the cable shield. RVBUS 1k or 20k Series resistor to work with internal over voltage protection. See Section 5.7.2.6, "VBUS Over Voltage Protection (OVP)," on page 37 for information regarding power dissipation. RBIAS 8.06k (1%) Series resistor to establish reference voltage. See Section 5.3, "Bias Generator," on page 27 for information regarding power dissipation. TABLE 8-2: NOTES CAPACITANCE VALUES AT VBUS OF USB CONNECTOR MODE MIN VALUE Host 120F Device 1F 10F OTG 1F 6.5F 2009-2018 Microchip Technology Inc. MAX VALUE DS00002646A-page 77 USB334x FIGURE 8-1: USB3341, USB3346, AND USB3347 APPLICATION DIAGRAM (DEVICE CONFIGURED FOR ULPI CLOCK OUTPUT MODE) RVBUS must be installed to enable overvoltage protection of the VBUS pin. USB3341 / USB3346 RVBUS 17 VBUS 16 VBAT 15 VDD33 3.0-5.5V Supply The capacitor CVBUS must be installed on this side of RVBUS. USB Receptacle CBYP CVBUS COUT Link Controller RESETB 21 RESETB DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 STP NXT DIR CLKOUT 10 9 8 7 6 5 4 3 23 2 24 1 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 STP NXT DIR CLKIN REFCLK 20 VBUS 18 ID DM 14 DM DP 13 DP VDD18 22 11 SPK_L RBIAS 12 SPK_R COUT SHIELD GND REFCLK ULPI Output Clock Mode CDC_BLOCK GND 19 RBIAS 25 Optional Switched Signal to DP/DM DS00002646A-page 78 2009-2018 Microchip Technology Inc. USB334x FIGURE 8-2: USB3343 APPLICATION DIAGRAM (DEVICE CONFIGURED FOR ULPI CLOCK OUTPUT MODE) RVBUS must be installed to enable overvoltage protection of the VBUS pin. USB3343 RESETB 22 RVBUS 17 VBUS 16 VBAT 15 VDD33 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 STP NXT DIR CLKOUT 3.0-5.5V Supply The capacitor CVBUS must be installed on this side of RVBUS. USB Receptacle CBYP CVBUS COUT VBUS ID DM 14 DM DP 13 DP GND CDC_BLOCK XO 20 1M Resonator VDDIO CBYP GND 25 2009-2018 Microchip Technology Inc. ULPI Output Clock Mode DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 STP NXT DIR CLKIN COUT VDDIO Supply 9 RESETB 12 11 10 8 7 6 5 4 24 3 1 2 VDD18 23 18 SHIELD Link Controller REFCLK/XI 21 RBIAS 19 RBIAS CLOAD - or Crystal and Caps DS00002646A-page 79 USB334x FIGURE 8-3: USB3341, USB3346, AND USB3347 APPLICATION DIAGRAM (HOST OR OTG CONFIGURED FOR ULPI CLOCK INPUT MODE) Link Controller CPEN RVBUS must be installed to enable overvoltage protection of the VBUS pin. RVBUS VBUS Switch EN 5V IN USB3341/USB3346 RESETB 21 OUT The capacitor CVBUS must be installed on this side of RVBUS. 17 VBUS 16 VBAT 15 VDD33 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 STP NXT DIR CLKOUT 3.0-5.5V Supply CBYP USB Receptacle CVBUS COUT REFCLK 20 VBUS ID 18 ID DM 14 DM DP 13 DP VDD18 22 11 SPK_L VDDIO 8 12 SPK_R RBIAS 19 SHIELD GND RESETB 10 9 8 7 6 5 4 3 23 2 24 1 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 STP NXT DIR CLKOUT ULPI Clock In Mode COUT GND 25 VDDIO Suppl CBYP Optional Switched Signal to DP/DM 8.2 USB Charger Detection The USB334x provides the hardware described in the USB Battery Charging Specification. Microchip provides an Application Note which describes how to use the USB334x in a battery charging application. 8.3 Reference Designs Microchip has generated reference designs for connecting the USB334x to SoCs with a ULPI port. Please contact the Microchip sales office for more details. 8.4 ESD Performance The USB334x is protected from ESD strikes. By eliminating the requirement for external ESD protection devices, board space is conserved, and the board manufacturer is enabled to reduce cost. The advanced ESD structures integrated into the USB334x protect the device whether or not it is powered up. 8.4.1 HUMAN BODY MODEL (HBM) PERFORMANCE HBM testing verifies the ability to withstand the ESD strikes like those that occur during handling and manufacturing, and is done without power applied to the IC. To pass the test, the device must have no change in operation or performance due to the event. The USB334x HBM performance is detailed in Table 4-14. DS00002646A-page 80 2009-2018 Microchip Technology Inc. USB334x 8.4.2 EN/IEC 61000-4-2 PERFORMANCE The EN/IEC 61000-4-2 ESD specification is an international standard that addresses system-level immunity to ESD strikes while the end equipment is operational. In contrast, the HBM ESD tests are performed at the device level with the device powered down. Microchip contracts with Independent laboratories to test the USB334x to EN/IEC 61000-4-2 in a working system. Reports are available upon request. Please contact your Microchip representative, and request information on 3rd party ESD test results. The reports show that systems designed with the USB334x can safely provide the ESD performance shown in Table 4-14 without additional board level protection. In addition to defining the ESD tests, EN/IEC 61000-4-2 also categorizes the impact to equipment operation when the strike occurs (ESD Result Classification). The USB334x maintains an ESD Result Classification 1 or 2 when subjected to an EN/IEC 61000-4-2 (level 4) ESD strike. Both air discharge and contact discharge test techniques for applying stress conditions are defined by the EN/IEC 61000-4-2 ESD document. 8.4.2.1 Air Discharge To perform this test, a charged electrode is moved close to the system being tested until a spark is generated. This test is difficult to reproduce because the discharge is influenced by such factors as humidity, the speed of approach of the electrode, and construction of the test equipment. 8.4.2.2 Contact Discharge The uncharged electrode first contacts the USB connector to prepare this test, and then the probe tip is energized. This yields more repeatable results, and is the preferred test method. The independent test laboratories contracted by Microchip provide test results for both types of discharge methods. 2009-2018 Microchip Technology Inc. DS00002646A-page 81 USB334x 9.0 PACKAGE OUTLINE 24-Pin Sawn QFN - USB3341 Only FIGURE 9-1: 24-Lead Very Thin Plastic Quad Flat, No Lead Package (MJ) - 4x4x0.9 mm Body [VQFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A B N NOTE 1 1 2 E (DATUM B) (DATUM A) 2X 0.10 C 2X 0.10 C TOP VIEW 0.10 C C A1 A SEATING PLANE 24X (A3) 0.08 C SIDE VIEW 0.10 C A B D2 0.10 C A B E2 e 2 2 1 NOTE 1 K N L 24X b 0.10 0.05 e C A B C BOTTOM VIEW Microchip Technology Drawing C04-143B MJ Sheet 1 of 2 DS00002646A-page 82 2009-2018 Microchip Technology Inc. USB334x 24-Pin Sawn QFN - USB3341 Only (CONTINUED) FIGURE 9-1: 24-Lead Very Thin Plastic Quad Flat, No Lead Package (MJ) - 4x4x0.9 mm Body [VQFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units Dimension Limits Number of Terminals N e Pitch Overall Height A Standoff A1 Terminal Thickness A3 Overall Width E Exposed Pad Width E2 Overall Length D Exposed Pad Length D2 Terminal Width b Terminal Length L Terminal-to-Exposed Pad K MIN 0.80 0.00 2.40 2.40 0.20 0.30 0.20 MILLIMETERS NOM 24 0.50 BSC 0.85 0.02 0.20 REF 4.00 BSC 2.50 4.00 BSC 2.50 0.25 0.40 - MAX 0.90 0.05 2.60 2.60 0.30 0.50 - Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-143B MJ Sheet 2 of 2 2009-2018 Microchip Technology Inc. DS00002646A-page 83 USB334x 24-Pin Sawn QFN - USB3341 Only (CONTINUED) FIGURE 9-1: 24-Lead Very Thin Plastic Quad Flat, No Lead Package (MJ) - 4x4x0.9 mm Body [VQFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging C1 X2 EV 24 1 2 G2 OV C2 Y2 EV G1 Y1 X1 E SILK SCREEN RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Optional Center Pad Width X2 Optional Center Pad Length Y2 Contact Pad Spacing C1 Contact Pad Spacing C2 Contact Pad Width (X24) X1 Contact Pad Length (X24) Y1 Contact Pad to Center Pad (X24) G1 Contact Pad to Contact Pad (X20) G2 Thermal Via Diameter V Thermal Via Pitch EV MIN MILLIMETERS NOM 0.50 BSC MAX 2.60 2.60 3.90 3.90 0.30 0.85 0.23 0.20 0.30 1.00 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. 2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process Microchip Technology Drawing C04-2143A MJ DS00002646A-page 84 2009-2018 Microchip Technology Inc. USB334x FIGURE 9-2: 24-Pin Punched QFN - USB3343, USB3346 & USB3347 Only /HDG9HU\7KLQ3ODVWLF4XDG)ODW1R/HDG3DFNDJH0- [PP%RG\>94)1@ 3XQFK6LQJXODWHG:LWK[([SRVHG3DG 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ ' $ ' ; % 1 & 127( ( ( '$780% '$780$ ; & ; & 7239,(: & & 6($7,1* 3/$1( $ $ ; $ & 6,'(9,(: $ & $ % ' & $ % ( H 127( ;. 1 ;E ;/ H & $ % & %277209,(: 0LFURFKLS7HFKQRORJ\'UDZLQJ&5HY$6KHHWRI 2009-2018 Microchip Technology Inc. DS00002646A-page 85 USB334x 24-Pin Punched QFN - USB3343, USB3346 & USB3347 Only (CONTINUED) FIGURE 9-2: /HDG9HU\7KLQ3ODVWLF4XDG)ODW1R/HDG3DFNDJH0- [PP%RG\>94)1@ 3XQFK6LQJXODWHG:LWK[([SRVHG3DG 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ Notes: 8QLWV 'LPHQVLRQ/LPLWV 1XPEHURI7HUPLQDOV 1 H 3LWFK $ 2YHUDOO+HLJKW 6WDQGRII $ 0ROG&DS7KLFNQHVV $ $ 7HUPLQDO7KLFNQHVV 2YHUDOO/HQJWK ' 0ROG7RS/HQJWK ' ([SRVHG3DG/HQJWK ' 2YHUDOO:LGWK ( 0ROG7RS:LGWK ( ( ([SRVHG3DG:LGWK E 7HUPLQDO:LGWK 7HUPLQDO/HQJWK / 7HUPLQDOWR([SRVHG3DG . 0,1 0,//,0(7(56 120 %6& 5() %6& %6& %6& %6& 0$; 3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD 3DFNDJHLVSXQFKVLQJXODWHG 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0 %6&%DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV 5()5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\ 0LFURFKLS7HFKQRORJ\'UDZLQJ&5HY$6KHHWRI DS00002646A-page 86 2009-2018 Microchip Technology Inc. USB334x 24-Pin Punched QFN - USB3343, USB3346 & USB3347 Only (CONTINUED) FIGURE 9-2: /HDG9HU\7KLQ3ODVWLF4XDG)ODW1R/HDG3DFNDJH0- [PP%RG\>94)1@ 3XQFK6LQJXODWHG:LWK[([SRVHG3DG 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ & ; (9 * 9 & < (9 * < ; 6,/.6&5((1 ( 5(&200(1'('/$1'3$77(51 8QLWV 'LPHQVLRQ/LPLWV ( &RQWDFW3LWFK 2SWLRQDO&HQWHU3DG:LGWK ; 2SWLRQDO&HQWHU3DG/HQJWK < &RQWDFW3DG6SDFLQJ & &RQWDFW3DG6SDFLQJ & &RQWDFW3DG:LGWK; ; &RQWDFW3DG/HQJWK; < &RQWDFW3DGWR&HQWHU3DG; * &RQWDFW3DGWR&RQWDFW3DG; * 7KHUPDO9LD'LDPHWHU 9 7KHUPDO9LD3LWFK (9 0,1 0,//,0(7(56 120 %6& 0$; 1RWHV 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0 %6&%DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV )RUEHVWVROGHULQJUHVXOWVWKHUPDOYLDVLIXVHGVKRXOGEHILOOHGRUWHQWHGWRDYRLGVROGHUORVVGXULQJ UHIORZSURFHVV 0LFURFKLS7HFKQRORJ\'UDZLQJ&$ 2009-2018 Microchip Technology Inc. DS00002646A-page 87 USB334x APPENDIX A: DATA SHEET REVISION HISTORY Revision Level & Date DS00002646A (02-09-18) Section/Figure/Entry Correction Document is converted to Microchip template; REV A replaces previous SMSC version Rev. 1.2 (02-08-13). Added Section 3.3, "Package Thermal Specifications" Rev. 1.2 (02-08-13) Document co-branded: Microchip logo added; document disclaimer modified. Added to ordering information: "Please contact your SMSC sales representative for additional documentation related to this product such as application notes, anomaly sheets, and design guidelines." Rev. 1.2 (08-15-11) Product Features - cover The following text removed from package information bullet: "USB3341, USB3343, USB3346 and USB3347." Rev 1.2 (08-10-11) Page 2 Added USB3347 product. Table 3-1, Table 3-2 Removed requirement that VDD18 be active while VDDIO is active. Table 4-1, Table 4-2 Updated power specifications Table 2-2 Modified VDDIO Description Section 7.1.3.1 Removed "and LPM" from section title. Throughout Document Updated support for Battery Charging v1.2. Throughout Document Various editorial improvements. Section 1.0, "General Description" Paragraph 6 Add Rapid Charge and BC 1.1 descriptions Figure 1.1 Block Diagram Added BC 1.1 Block Section 5.5.2, "REFCLK Amplitude" Correct REFCLK voltage reference Section 5.9, "USB Charger Detection Support" Added BC 1.1 Details Package Outline Changed format and figure titles Rev. 1.0 (08-25-10) Product Features Added SMSC RapidCharge Anywhere feature Rev. 0.9 (11-16-09) Initial data sheet release Rev 1.1 (01-20-11) DS00002646A-page 88 2009-2018 Microchip Technology Inc. USB334x THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under "Support", click on "Customer Change Notification" and follow the registration instructions. CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://microchip.com/support 2009-2018 Microchip Technology Inc. DS00002646A-page 89 USB334x PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device [X] Temperature Range - XXX Package [X](3) - Examples: a) Tape and Reel Option b) Device: USB3341, USB3343, USB3346, USB3347 Temperature Range: Blank Package: CP = 24-pin punched QFN for USB3343, USB3346 and USB3347 CP = 24-pin sawn QFN for USB3341 Tape and Reel Option: Blank TR = -40C to +85C c) d) e) = Standard packaging (tray) = Tape and Reel(2) f) g) h) USB3341-CP 24-pin, QFN RoHS Compliant (tray), sawn USB3341-CP-TR 24-pin, QFN RoHS Compliant (tape and reel), sawn USB3343-CP 24-pin, QFN RoHS Compliant (tray), punched USB3343-CP-TR 24-pin, QFN RoHS Compliant (tape and reel), punched USB3346-CP 24-pin, QFN RoHS Compliant (tray), punched USB3346-CP-TR 24-pin, QFN RoHS Compliant (tape and reel), punched USB3347-CP 24-pin, QFN RoHS Compliant (tray), punched USB3347-CP-TR 24-pin, QFN RoHS Compliant (tape and reel), punched Note 1: 2: 3: DS00002646A-page 90 Package Package Package Package Package Package Package Package All versions support ULPI Clock In Mode (60 MHz input at REFCLK) This product meets the halogen maximum concentration values per IEC61249-2-21 Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. 2009-2018 Microchip Technology Inc. USB334x Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, CryptoAuthentication, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. (c) 2009-2018, Microchip Technology Incorporated, All Rights Reserved. ISBN: 9781522426578 QUALITYMANAGEMENTSYSTEM CERTIFIEDBYDNV == ISO/TS16949== 2009-2018 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 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