TC74LCX16373AFT TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74LCX16373AFT Low-Voltage 16-Bit D-Type Latch with 5-V Tolerant Inputs and Outputs The TC74LCX16373AFT is a high-performance CMOS 16-bit D-type latch. Designed for use in 3.3-V systems, it achieves high-speed operation while maintaining the CMOS low power dissipation. The device is designed for low-voltage (3.3 V) VCC applications, but it could be used to interface to 5-V supply environment for both inputs and outputs. This 16-bit D-type latch is controlled by a latch enable input (LE) and an output enable input ( OE ) which are common to each byte. It can be used as two 8-bit latches or one 16-bit latch. When the OE input is high, the outputs are in a high-impedance state. All inputs are equipped with protection circuits against static discharge. Weight: 0.25 g (typ.) Features * Low-voltage operation: VCC = 2.0 to 3.6 V * High-speed operation: tpd = 7.0 ns (max) (VCC = 3.0 to 3.6 V) * Ouput current: |IOH|/IOL = 24 mA (min) (VCC = 3.0 V) * Latch-up performance: -500 mA * Package: TSSOP * Power-down protection provided on all inputs and outputs 1 2007-10-19 TC74LCX16373AFT Pin Assignment (top view) IEC Logic Symbol 1OE 1 48 1LE 1Q1 2 47 1D1 1Q2 3 46 1D2 GND 4 45 GND 1Q3 5 44 1D3 1Q4 6 43 1D4 VCC 7 42 VCC 1Q5 8 41 1D5 1Q6 9 40 1D6 GND 10 39 GND 1Q7 11 38 1D7 1Q8 12 37 1D8 2Q1 13 36 2D1 2Q2 14 35 2D2 GND 15 34 GND 2Q3 16 33 2D3 2Q4 17 32 2D4 VCC 18 31 VCC 2Q5 19 30 2D5 2Q6 20 29 2D6 GND 21 28 GND 2Q7 22 27 2D7 2Q8 23 26 2D8 24 25 2LE 2OE 1OE 1LE 2OE 2LE 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 2 1 48 24 25 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 1EN C3 2EN C4 3D 1 4D 2 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2007-10-19 TC74LCX16373AFT Truth Table Inputs Outputs 1OE 1LE 1D1-1D8 1Q1-1Q8 H X X Z L L X Qn L H L L L H H H Inputs Outputs 2OE 2LE 2D1-2D8 2Q1-2Q8 H X X Z L L X Qn L H L L L H H H X: Don't care Z: High impedance Qn: Q outputs are latched at the time when the LE input is taken to a low logic level System Diagram 1D2 46 1D1 47 1LE 1OE 48 2OE 1D4 43 1D5 41 1D6 40 1D7 38 1D8 37 D D D D D D D D LE Q LE Q LE Q LE Q LE Q LE Q LE Q LE Q 2 3 5 6 8 9 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 2D2 35 2D3 33 2D4 32 2D5 30 2D6 29 2D7 27 2D8 26 1 2D1 36 2LE 1D3 44 25 11 12 1Q8 D D D D D D D D LE Q LE Q LE Q LE Q LE Q LE Q LE Q LE Q 24 13 2Q1 14 2Q2 16 17 2Q3 2Q4 3 19 2Q5 20 2Q6 22 2Q7 23 2Q8 2007-10-19 TC74LCX16373AFT Absolute Maximum Ratings (Note 1) Characteristics Symbol Rating Unit Power supply voltage VCC -0.5 to 7.0 V Input voltage VIN -0.5 to 7.0 V -0.5 to 7.0 (Note 2) Output voltage VOUT -0.5 to VCC + 0.5 V (Note 3) Input diode current IIK -50 Output diode current IOK 50 DC output current IOUT 50 mA Power dissipation DC VCC/ground current per supply pin mA (Note 4) mA PD 400 mW ICC/IGND 100 mA Tstg -65 to 150 C Storage temperature Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook ("Handling Precautions"/"Derating Concept and Methods") and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Note 2: Output in OFF state Note 3: High or low state. IOUT absolute maximum rating must be observed. Note 4: VOUT < GND, VOUT > VCC Operating Ranges (Note 1) Characteristics Symbol Power supply voltage VCC Input voltage VIN Output voltage VOUT Output current IOH/IOL Rating Unit 2.0 to 3.6 1.5 to 3.6 (Note 2) 0 to 5.5 V 0 to 5.5 (Note 3) 0 to VCC (Note 4) 24 (Note 5) 12 (Note 6) Operating temperature Topr -40 to 85 Input rise and fall time dt/dv 0 to 10 V V mA C (Note 7) ns/V Note 1: The operating ranges must be maintained to ensure the normal operation of the device. Unused inputs must be tied to either VCC or GND. Note 2: Data retention only Note 3: Output in OFF state Note 4: High or low state Note 5: VCC = 3.0 to 3.6 V Note 6: VCC = 2.7 to 3.0 V Note 7: VIN = 0.8 to 2.0 V, VCC = 3.0 V 4 2007-10-19 TC74LCX16373AFT Electrical Characteristics DC Characteristics (Ta = -40 to 85C) Characteristics Input voltage Symbol Test Condition H-level VIH L-level VIL H-level VOH VIN = VIH or VIL Output voltage VOL VIN = VIH or VIL Input leakage current IIN VIN = 0 to 5.5 V 3-state output OFF state current IOZ Power-off leakage current IOFF Quiescent supply current ICC Increase in Icc per input ICC L-level Min Max 2.7 to 3.6 2.0 2.7 to 3.6 0.8 IOH = -100 A 2.7 to 3.6 VCC - 0.2 IOH = -12 mA 2.7 2.2 IOH = -18 mA 3.0 2.4 IOH = -24 mA 3.0 2.2 IOL = 100 A 2.7 to 3.6 0.2 IOL = 12 mA 2.7 0.4 IOL = 16 mA 3.0 0.4 IOL = 24 mA VCC (V) Unit V V 3.0 0.55 2.7 to 3.6 5.0 A 2.7 to 3.6 5.0 A VIN/VOUT = 5.5 V 0 10.0 A VIN = VCC or GND 2.7 to 3.6 20.0 VIN/VOUT = 3.6 to 5.5 V 2.7 to 3.6 20.0 VIH = VCC - 0.6 V 2.7 to 3.6 500 VIN = VIH or VIL VOUT = 0 to 5.5 V 5 A 2007-10-19 TC74LCX16373AFT AC Characteristics (Ta = -40 to 85C) Characteristics Propagation delay time (D-Q) Symbol tpLH tpHL Propagation delay time tpLH (LE-Q) tpHL 3-state output enable time 3-state output disable time Minimum pulse width tpZL tpZH tpLZ tpHZ Test Condition Figure 1, Figure 2 Figure 1, Figure 2 Figure 1, Figure 3 Figure 1, Figure 3 tw (H) Figure 1, Figure 2 Minimum setup time ts Figure 1, Figure 2 Minimum hold time th Figure 1, Figure 2 (LE) Output to output skew Note: tosLH (Note) tosHL Min Max 2.7 8.0 3.3 0.3 1.5 7.0 VCC (V) 2.7 8.0 3.3 0.3 1.5 7.0 2.7 8.2 3.3 0.3 1.5 7.2 2.7 8.2 3.3 0.3 1.5 7.2 2.7 4.0 3.3 0.3 3.0 2.7 2.5 3.3 0.3 2.5 2.7 1.5 3.3 0.3 1.5 2.7 3.3 0.3 1.0 Unit ns ns ns ns ns ns ns ns Parameter guaranteed by design. (tosLH = |tpLHm - tpLHn|, tosHL = |tpHLm - tpHLn|) Dynamic Switching Characteristics (Ta = 25C, input: tr = tf = 2.5 ns, CL = 50 pF, RL = 500 ) Characteristics Symbol Test Condition VCC (V) Typ. Unit Quiet output maximum dynamic VOL VOLP VIH = 3.3 V, VIL = 0 V 3.3 0.8 V Quiet output minimum dynamic VOL |VOLV| VIH = 3.3 V, VIL = 0 V 3.3 0.8 V Typ. Unit Capacitive Characteristics (Ta = 25C) Characteristics Input capacitance Output capacitance Power dissipation capacitance Note: Symbol Test Condition CIN 3.3 7 pF COUT 3.3 8 pF 3.3 25 pF CPD fIN = 10 MHz VCC (V) (Note) CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr) = CPDVCCfIN + ICC/16 (per bit) 6 2007-10-19 TC74LCX16373AFT AC Test Circuit Open 6.0 V GND RL Switch RL Measure CL Output CL = 50 pF RL = 500 Parameter Switch tpLH, tpHL Open tpLZ, tpZL 6.0 V tpHZ, tpZH GND tw, ts, th, Open Figure 1 AC Waveform tf 2.5 ns 1.5 V 10% tf 2.5 ns tr 2.5 ns GND tw (H) 2.7 V 90% 1.5 V 1.5 V th (H) ts (L) 10% GND ts (H) Output (Q) 2.7 V 90% 1.5 V Input (LE) Input (D) tr 2.5 ns th (L) VOH 1.5 V 1.5 V tpLH tpHL tpHL tpLH VOL Figure 2 tpLH, tpHL, tw, ts, th tr 2.5 ns tf 2.5 ns 2.7 V 90% 1.5 V Output Enable ( OE ) 10% tpLZ GND tpZL 3.0 V Output (Q) Low to Off to Low 1.5 V tpHZ VOL + 0.3 V VOH - 0.3 V Output (Q) High to Off to High VOL tpZH VOH 1.5 V GND Outputs enabled Outputs disabled Outputs enabled Figure 3 tpLZ, tpHZ, tpZL, tpZH 7 2007-10-19 TC74LCX16373AFT Package Dimensions Weight: 0.25 g (typ.) 8 2007-10-19 TC74LCX16373AFT RESTRICTIONS ON PRODUCT USE * Toshiba Corporation, and its subsidiaries and affiliates (collectively "TOSHIBA"), reserve the right to make changes to the information in this document, and related hardware, software and systems (collectively "Product") without notice. * This document and any information herein may not be reproduced without prior written permission from TOSHIBA. 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