Dual 256-Position I2C Digital Potentiometer AD5243/AD5248 Preliminary Technical Data FEATURES applications. 2-Channel, 256-position End-to-end resistance 2.5 k, 10 k, 50 k, 100 k Compact MSOP-10 (3 mm x 4.9 mm) Package Full read/write of wiper register Power-on preset to midscale Extra package address decode pins AD0 and AD1(AD5248) Single supply +2.7 V to +5.5 V Low temperature coefficient 35 ppm/C Low power, IDD = 5 A Wide operating temperature -40C to +125C Evaluation board available All parts are guaranteed to operate over the extended automotive temperature range of -40C to +125C. FUNCTIONAL BLOCK DIAGRAMS VDD SCL SDA A1 I2C INTERFACE W1 B1 WIPER REGISTER 1 APPLICATIONS A2 WIPER REGISTER 2 Mechanical potentiometer replacement in new designs Transducer adjustment of pressure, temperature, position, chemical, and optical sensors RF amplifier biasing Automotive electronics adjustment Gain control and offset adjustment W2 B2 GND Figure 1. AD5243 W1 B1 W2 B2 GENERAL OVERVIEW The AD5243 & AD5248 provide a compact 3x4.9mm packaged solution for dual 256 position adjustment applications. These devices perform the same electronic adjustment function as a 3terminal mechanical potentiometer (AD5243) or a 2-terminal variable resistor (AD5248). Available in four different end-toend resistance values (2.5k, 10k, 50k, 100k ) these low temperature coefficient devices are ideal for high accuracy and stability variable resistance adjustments. The wiper settings are controllable through the I2C compatible digital interface. The AD5248 has extra package address decode pins AD0 & AD1 allowing multiple parts to share the same I2C 2-wire bus on a PCB. The resistance between the wiper and either end point of the fixed resistor varies linearly with respect to the digital code transferred into the RDAC latch1. VDD GND AD0 AD1 SDA SCL RDAC 2REGISTER 2 RDAC REGISTER 1 ADDRESS DECODE 8 SERIAL INPUT REGISTER Figure 2. AD5248 Note: The terms digital potentiometer, VR, and RDAC are used interchangeably. Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. Operating from a 2.7 to 5.5 volt power supply and consuming less than 5A allows for usage in portable battery operated Rev. PrE5/12/03 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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Preliminary Technical Data AD5243/AD5248 TABLE OF CONTENTS Electrical Characteristics--2.5 k Version ................................... 3 Level Shifting for Bidirectional Interface ................................ 12 Electrical Characteristics--10 k, 50 k, 100 k Versions ....... 4 ESD Protection ........................................................................... 12 Timing Characteristics--2.5 k, 10 k, 50 k, 100 k Versions ............................................................................................................. 5 Terminal Voltage Operating Range.......................................... 12 Absolute Maximum Ratings1 .......................................................... 5 Typical Performance Characteristics ............................................. 6 Test Circuits....................................................................................... 7 I2C Interface....................................................................................... 8 Operation......................................................................................... 10 Programming the Variable Resistor ......................................... 10 Programming the Potentiometer Divider ............................... 11 Power-Up Sequence ................................................................... 13 Layout and Power Supply Bypassing ....................................... 13 Pin Configuration and Function Descriptions........................... 14 Pin Configuration ...................................................................... 14 Pin Function Descriptions ........................................................ 14 Outline Dimensions ....................................................................... 15 Ordering Guide .......................................................................... 15 ESD Caution................................................................................ 15 I2C Compatible 2-Wire Serial Bus............................................ 11 REVISION HISTORY Revision 0: Initial Version Rev. PrE 5/12/03 | Page 2 of 16 Preliminary Technical Data AD5243/AD5248 ELECTRICAL CHARACTERISTICS--2.5 k VERSION (VDD = 5 V 10%, or 3 V 10%; VA = +VDD; VB = 0 V; -40C < TA < +125C; unless otherwise noted.) Table 1. Parameter Symbol Conditions DC CHARACTERISTICS--RHEOSTAT MODE Resistor Differential Nonlinearity2 R-DNL RWB, VA = no connect Resistor Integral Nonlinearity2 R-INL RWB, VA = no connect Nominal Resistor Tolerance3 RAB TA = 25C Resistance Temperature Coefficient RAB/T VAB = VDD, Wiper = no connect Wiper Resistance RW DC CHARACTERISTICS--POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs) Resolution N Differential Nonlinearity4 DNL Integral Nonlinearity4 INL Voltage Divider Temperature Coefficient VW/T Code = 0x80 Full-Scale Error VWFSE Code = 0xFF Zero-Scale Error VWZSE Code = 0x00 RESISTOR TERMINALS Voltage Range5 VA,B,W Capacitance6 A, B CA,B f = 1 MHz, measured to GND, Code = 0x80 Capacitance6 W CW f = 1 MHz, measured to GND, Code = 0x80 Shutdown Supply Current7 IDD_SD VDD = 5.5 V Common-Mode Leakage ICM VA = VB = VDD/2 DIGITAL INPUTS AND OUTPUTS Input Logic High VIH Input Logic Low VIL Input Logic High VIH VDD = 3 V Input Logic Low VIL VDD = 3 V Input Current IIL VIN = 0 V or 5 V 6 Input Capacitance CIL POWER SUPPLIES Power Supply Range VDD RANGE Supply Current IDD VIH = 5 V or VIL = 0 V Power Dissipation8 PDISS VIH = 5 V or VIL = 0 V, VDD = 5 V Power Supply Sensitivity PSS VDD = +5 V 10%, Code = Midscale DYNAMIC CHARACTERISTICS6, 9 Bandwidth -3dB BW_5K RAB = 2.5 k, Code = 0x80 Total Harmonic Distortion THDW VA = 1 V rms, VB = 0 V, f = 1 kHz VW Settling Time tS VA= 5 V, VB = 0 V, 1 LSB error band Resistor Noise Voltage Density eN_WB RWB = 2.5 k, RS = 0 Rev. PrE 5/12/03 | Page 3 of 16 Min Typ1 Max Unit -1.8 -5 -30 0.2 0.75 +1.8 +5 +30 LSB LSB % ppm/C 35 50 -1.5 -1.5 -6 0 0.1 0.6 15 -2.5 +2 GND 120 8 +1.5 +1.5 0 +6 VDD Bits LSB LSB ppm/C LSB LSB 45 V pF 60 pF 0.01 1 1 2.4 0.8 2.1 0.6 1 5 2.7 3 0.02 5.5 5 0.2 0.05 A nA V V V V A pF V A mW %/% 2.4 0.05 1 MHz % s 4.5 nV/Hz Preliminary Technical Data AD5243/AD5248 ELECTRICAL CHARACTERISTICS--10 k, 50 k, 100 k VERSIONS (VDD = 5 V 10%, or 3 V 10%; VA = VDD; VB = 0 V; -40C < TA < +125C; unless otherwise noted.) Table 2. Parameter DC CHARACTERISTICS--RHEOSTAT MODE Resistor Differential Nonlinearity2 Resistor Integral Nonlinearity2 Nominal Resistor Tolerance3 Resistance Temperature Coefficient Symbol Conditions RWB, VA = no connect RWB, VA = no connect TA = 25C VAB = VDD, Wiper = no connect Wiper Resistance RW VDD = 5 V DC CHARACTERISTICS--POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs) Resolution N Differential Nonlinearity4 DNL Integral Nonlinearity4 INL Voltage Divider Temperature Coefficient VW/T Code = 0x80 Full-Scale Error VWFSE Code = 0xFF Zero-Scale Error VWZSE Code = 0x00 RESISTOR TERMINALS Voltage Range5 VA,B,W Capacitance6 A, B CA,B f = 1 MHz, measured to GND, Code = 0x80 Capacitance6 W CW f = 1 MHz, measured to GND, Code = 0x80 Shutdown Supply Current7 IDD_SD VDD = 5.5 V Common-Mode Leakage ICM VA = VB = VDD/2 DIGITAL INPUTS AND OUTPUTS Input Logic High VIH Input Logic Low VIL Input Logic High VIH VDD = 3 V Input Logic Low VIL VDD = 3 V Input Current IIL VIN = 0 V or 5 V Input Capacitance6 CIL POWER SUPPLIES Power Supply Range VDD RANGE Supply Current IDD VIH = 5 V or VIL = 0 V Power Dissipation8 PDISS VIH = 5 V or VIL = 0 V, VDD = 5 V Power Supply Sensitivity PSS VDD = +5 V 10%, Code = Midscale DYNAMIC CHARACTERISTICS6, 9 Bandwidth -3dB BW RAB = 10 k/50 k/100 k, Code = 0x80 Total Harmonic Distortion THDW VA =1 V rms, VB = 0 V, f = 1 kHz, RAB = 10 k VW Settling Time (10 k/50 k/100 k) tS VA = 5 V, VB = 0 V, 1 LSB error band Resistor Noise Voltage Density eN_WB RWB = 5 k, RS = 0 R-DNL R-INL RAB RAB/T Rev. PrE 5/12/03 | Page 4 of 16 Min Typ1 Max Unit -1 -2 -30 0.1 0.25 +1 +2 +30 LSB LSB % ppm/C 120 8 +1 +1 Bits LSB LSB ppm/C LSB LSB 35 50 -1 -1 -3 0 0.1 0.3 15 -1 1 GND 0 3 45 VDD V pF 60 pF 0.01 1 1 2.4 0.8 2.1 0.6 1 5 2.7 A nA V V V V A pF 3 5.5 5 0.2 V A mW 0.02 0.05 %/% 600/100/40 kHz 0.05 % 2 s 9 nV/Hz Preliminary Technical Data AD5243/AD5248 TIMING CHARACTERISTICS--2.5 k, 10 k, 50 k, 100 k VERSIONS (VDD = +5V 10%, or +3V 10%; VA = VDD; VB = 0 V; -40C < TA < +125C; unless otherwise noted.) Table 3. Parameter Symbol Conditions I2C INTERFACE TIMING CHARACTERISTICS6, 10 (Specifications Apply to All Parts) SCL Clock Frequency fSCL tBUF Bus Free Time between STOP and START t1 tHD;STA Hold Time (Repeated START) t2 After this period, the first clock pulse is generated. tLOW Low Period of SCL Clock t3 tHIGH High Period of SCL Clock t4 tSU;STA Setup Time for Repeated START Condition t5 tHD;DAT Data Hold Time t6 tSU;DAT Data Setup Time t7 tF Fall Time of Both SDA and SCL Signals t8 tR Rise Time of Both SDA and SCL Signals t9 tSU;STO Setup Time for STOP Condition t10 Min Typ1 Max Unit 400 kHz s s 1.3 0.6 1.3 0.6 0.6 50 0.9 100 300 300 0.6 s s s s ns ns ns s NOTES 1 Typical specifications represent average readings at +25C and VDD = 5 V. 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. 3 VAB = VDD, Wiper (VW) = no connect. 4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor terminals A, B, W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. 7 Measured at the A terminal. The A terminal is open circuited in shutdown mode. 8 PDISS is calculated from (IDD x VDD). CMOS logic level inputs result in minimum power dissipation. 9 All dynamic characteristics use VDD = 5 V. 10 See timing diagrams for locations of measured values. ABSOLUTE MAXIMUM RATINGS1 (TA = +25C, unless otherwise noted.) Table 4. Parameter VDD to GND VA, VB, VW to GND IMAX1 Digital Inputs and Output Voltage to GND Operating Temperature Range Maximum Junction Temperature (TJMAX) Storage Temperature Lead Temperature (Soldering, 10 sec) Thermal Resistance2 JA: MSOP-10 Value -0.3 V to +7 V VDD 20 mA 0 V to +7 V -40C to +125C 150C -65C to +150C 300C 230C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. NOTES 1 Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 2 Package power dissipation = (TJMAX - TA)/JA. Rev. PrE 5/12/03 | Page 5 of 16 Preliminary Technical Data AD5243/AD5248 TYPICAL PERFORMANCE CHARACTERISTICS Rev. PrE 5/12/03 | Page 6 of 16 Preliminary Technical Data AD5243/AD5248 TEST CIRCUITS Figure 3 to Figure 11 illustrate the test circuits that define the test conditions used in the product specification tables. OP279 V+ = VDD 1LSB = V+/2N DUT A 5V VIN W W V+ B OFFSET GND VMS VOUT A DUT B OFFSET BIAS Figure 3. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL) Figure 8. Test Circuit for Noninverting Gain NO CONNECT A DUT A IW W VMS -15V RSW = DUT W I W = VDD /R NOMINAL VW 0.1V ISW CODE = 0x00 W B 0.1V ISW B VMS1 VOUT Figure 9. Test Circuit for Gain vs. Frequency DUT VMS2 AD8610 B 2.5V Figure 4. Test Circuit for Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL) A DUT OFFSET GND B +15V W VIN RW = [VMS1 - VMS2]/I W VSS TO VDD Figure 5. Test Circuit for Wiper Resistance Figure 10. Test Circuit for Incremental ON Resistance VA V+ = VDD 10% VDD PSRR (dB) = 20 LOG A V+ W PSS (%/%) = B V MS% NC V (V MS ) DD V DD% VMS VDD DUT A VSS GND B NC Figure 6. Test Circuit for Power Supply Sensitivity (PSS, PSSR) A DUT B 5V VIN OFFSET GND W OP279 VOUT OFFSET BIAS Figure 7. Test Circuit for Inverting Gain Rev. PrE 5/12/03 | Page 7 of 16 W ICM VCM NC = NO CONNECT Figure 11. Test Circuit for Common-Mode Leakage current Preliminary Technical Data AD5243/AD5248 I2C INTERFACE Table 5. Write Mode AD5243 S 0 1 0 1 1 1 1 A W A0 SD Slave Address Byte X X X X X X A D7 D6 D5 D4 D3 D2 D1 D0 Instruction Byte A P A P Data Byte AD5248 S 0 1 0 1 1 AD1 AD0 W A A0 SD Slave Address Byte X X X X X X A D7 D6 D5 D4 D3 D2 D1 D0 Instruction Byte Data Byte Table 6. Read Mode AD5243 S 0 1 0 1 1 1 Slave Address Byte 1 1 0 1 1 AD1 AD0 Slave Address Byte R A D7 D6 D5 D4 D3 Data Byte D2 D1 D0 A P R A D7 D6 D5 D4 D3 Data Byte D2 D1 D0 A P AD5248 S 0 S = Start Condition A0 = RDAC sub address select bit P = Stop Condition A = Acknowledge SD = Shutdown connects wiper to B terminal and open circuits A terminal. It does not change contents of wiper register. X = Don't Care D7, D6, D5, D4, D3, D2, D1, D0 = Data Bits W = Write R = Read Rev. PrE 5/12/03 | Page 8 of 16 Preliminary Technical Data AD5243/AD5248 t8 t2 t9 SCL t6 t2 t3 t7 t4 t5 t10 t9 t8 SDA t1 P S S P Figure 12. I2C Interface Detailed Timing Diagram 1 1 9 9 9 1 SCL SDA 0 1 0 1 1 1 1 R/W FRAME 1 SLAVE ADDRESS BYTE START BY MASTER A0 SD ACK BY AD5243 X X X X X X D7 D6 D5 ACK BY AD5243 FRAME 2 INSTRUCTION BYTE D4 D3 D2 D1 D0 ACK BY AD5243 STOP BY MASTER FRAME 3 DATA BYTE Figure 13. Writing to the RDAC Register - AD5243 1 1 9 9 9 1 SCL SDA START BY MASTER 0 1 0 1 1 AD1 AD0 R/W A0 SD ACK BY AD5248 FRAME 1 SLAVE ADDRESS BYTE X X X X X X D7 D6 D5 ACK BY AD5248 FRAME 2 INSTRUCTION BYTE D4 D3 D2 FRAME 3 DATA BYTE Figure 14. Writing to the RDAC Register - AD5248 1 9 1 9 SCL SDA 0 1 0 1 1 1 1 R/W FRAME 1 SLAVE ADDRESS BYTE START BY MASTER D7 D6 ACK BY AD5243 D5 D4 D3 D2 D1 D0 NO ACK BY MASTER STOP BY MASTER FRAME 2 RDAC REGISTER Figure 15. Reading Data from a Previously Selected RDAC Register in Write Mode - AD5243 1 9 1 9 SCL SDA START BY MASTER 0 1 0 1 1 AD1 AD0 FRAME 1 SLAVE ADDRESS BYTE R/W D7 D6 ACK BY AD5248 D5 D4 D3 D2 FRAME 2 RDAC REGISTER D1 D0 NO ACK BY MASTER STOP BY MASTER Figure 16 Reading Data from a Previously Selected RDAC Register in Write Mode - AD5248 Rev. PrE 5/12/03 | Page 9 of 16 D1 D0 ACK BY AD5248 STOP BY MASTER Preliminary Technical Data AD5243/AD5248 OPERATION The AD5243/48 is a 256-position digitally controlled variable resistor (VR) device. An internal power-on preset places the wiper at midscale during power-on, which simplifies the fault condition recovery at power-up. PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation The nominal resistance of the RDAC between terminals A and B is available in 5 k, 10 k, 50 k, and 100 k. The final two or three digits of the part number determine the nominal resistance value, e.g., 10 k = 10; 50 k = 50. The nominal resistance (RAB) of the VR has 256 contact points accessed by the wiper terminal, plus the B terminal contact. The 8-bit data in the RDAC latch is decoded to select one of the 256 possible settings. Assume a 10 k part is used, the wiper's first connection starts at the B terminal for data 0x00. Since there is a 60 wiper contact resistance, such connection yields a minimum of 60 resistance between terminals W and B. The second connection is the first tap point, which corresponds to 99 (RWB = RAB/256 + RW = 39 + 60 ) for data 0x01. The third connection is the next tap point, representing 138 (2 x 39 + 60 ) for data 0x02, and so on. Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at 9961 (RAB - 1 LSB + RW). Figure 17 shows a simplified diagram of the equivalent RDAC circuit where the last resistor string will not be accessed; therefore, there is 1 LSB less of the nominal resistance at full scale in addition to the wiper resistance. RWB (D ) = In summary, if RAB = 10 k and the A terminal is open circuited, the following output resistance RWB will be set for the indicated RDAC latch codes. Table 7. Codes and Corresponding RWB Resistance D (Dec.) 255 128 1 0 RWB () 9,961 5,060 99 60 D7 D6 D5 D4 D3 D2 D1 D0 Output State Full Scale (RAB - 1 LSB + RW) Midscale 1 LSB Zero Scale (Wiper Contact Resistance) Note that in the zero-scale condition a finite wiper resistance of 60 is present. Care should be taken to limit the current flow between W and B in this state to a maximum pulse current of no more than 20 mA. Otherwise, degradation or possible destruction of the internal switch contact can occur. Similar to the mechanical potentiometer, the resistance of the RDAC between the wiper W and terminal A also produces a digitally controlled complementary resistance RWA. When these terminals are used, the B terminal can be opened. Setting the resistance value for RWA starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value. The general equation for this operation is RWA (D ) = RS (1) where D is the decimal equivalent of the binary code loaded in the 8-bit RDAC register, RAB is the end-to-end resistance, and RW is the wiper resistance contributed by the on resistance of the internal switch. A SD BIT D x R AB + R W 256 256 - D x R AB + RW 256 (2) For RAB = 10 k and the B terminal open circuited, the following output resistance RWA will be set for the indicated RDAC latch codes. RS RS W Table 8. Codes and Corresponding RWA Resistance RDAC LATCH RS AND DECODER D (Dec.) 255 128 1 0 B Figure 17. AD5243/48 Equivalent RDAC Circuit The general equation determining the digitally programmed output resistance between W and B is RWA () 99 5,060 9,961 10,060 Output State Full Scale Midscale 1 LSB Zero Scale Typical device to device matching is process lot dependent and may vary by up to 30%. Since the resistance element is processed in thin film technology, the change in RAB with temperature has a very low 45 ppm/C temperature coefficient. Rev. PrE 5/12/03 | Page 10 of 16 Preliminary Technical Data AD5243/AD5248 PROGRAMMING THE POTENTIOMETER DIVIDER 2. Voltage Output Operation The digital potentiometer easily generates a voltage divider at wiper-to-B and wiper-to-A proportional to the input voltage at A-to-B. Unlike the polarity of VDD to GND, which must be positive, voltage across A-B, W-A, and W-B can be at either polarity. The second MSB, SD, is a shutdown bit. A logic high causes an open circuit at terminal A while shorting the wiper to terminal B. This operation yields almost 0 in rheostat mode or 0 V in potentiometer mode. It is important to note that the shutdown operation does not disturb the contents of the register. When brought out of shutdown, the previous setting will be applied to the RDAC. Also, during shutdown, new settings can be programmed. When the part is returned from shutdown, the corresponding VR setting will be applied to the RDAC. If ignoring the effect of the wiper resistance for approximation, connecting the A terminal to 5 V and the B terminal to ground produces an output voltage at the wiper-to-B starting at 0 V up to 1 LSB less than 5 V. Each LSB of voltage is equal to the voltage applied across terminal AB divided by the 256 positions of the potentiometer divider. The general equation defining the output voltage at VW with respect to ground for any valid input voltage applied to terminals A and B is VW (D ) = D 256 - D VA + VB 256 256 The remainder of the bits in the instruction byte are don't cares(see Table 5). (3) After acknowledging the instruction byte, the last byte in write mode is the data byte. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Table 5). For a more accurate calculation, which includes the effect of wiper resistance, VW, can be found as VW ( D) = R ( D) RWB ( D) VB V A + WA R AB R AB (4) 3. Operation of the digital potentiometer in the divider mode results in a more accurate operation over temperature. Unlike the rheostat mode, the output voltage is dependent mainly on the ratio of the internal resistors RWA and RWB and not the absolute values. Therefore, the temperature drift reduces to 15 ppm/C. I2C COMPATIBLE 2-WIRE SERIAL BUS 2 The 2-wire I C serial bus protocol operates as follows: 1. In the write mode, the second byte is the instruction byte. The first bit (MSB) of the instruction byte is the RDAC sub address select bit. A logic low will select channel-1 and a logic high will select channel-2. The master initiates data transfer by establishing a START condition, which is when a high-to-low transition on the SDA line occurs while SCL is high (see Figure 13). The following byte is the slave address byte, which consists of the slave address followed by an R/W bit (this bit determines whether data will be read from or written to the slave device). The AD5243 has a fixed slave address byte whereas the AD5248 has two configurable address bits AD0 and AD1 (see Table 5). In the read mode, the data byte follows immediately after the acknowledgment of the slave address byte. Data is transmitted over the serial bus in sequences of nine clock pulses(a slight difference with the write mode, where there are eight data bits followed by an acknowledge bit). Similarly, the transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Figure 15 and Figure 16). Note that the channel of interest is the one that is previously selected in the Write Mode. In the case where users need to read the RDAC values of both channels, they need to program the first channel in the Write Mode and then change to the Read Mode to read the first channel value. After that, they need to change back to the Write Mode with the second channel selected and read the second channel value in the Read Mode again. It is not necessary for users to issue the Frame 3 data byte in the write mode for subsequent readback operation. Users should refer to Figure 15 for the programming format. The slave whose address corresponds to the transmitted address responds by pulling the SDA line low during the ninth clock pulse (this is termed the acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. If the R/W bit is high, the master will read from the slave device. On the other hand, if the R/W bit is low, the master will write to the slave device. Rev. PrE 5/12/03 | Page 11 of 16 Preliminary Technical Data AD5243/AD5248 4. FETs such as the FDV301N. After all data bits have been read or written, a STOP condition is established by the master. A STOP condition is defined as a low-to-high transition on the SDA line while SCL is high. In write mode, the master will pull the SDA line high during the tenth clock pulse to establish a STOP condition (see Figure 13) In read mode, the master will issue a No Acknowledge for the ninth clock pulse (i.e., the SDA line remains high). The master will then bring the SDA line low before the tenth clock pulse which goes high to establish a STOP condition (see Figure 15 and Figure 16). VDD1 = 3.3V VDD2 = 5V RP RP RP RP G S SDA1 D M1 SCL1 SDA2 G S D M2 3.3V 5V AD5243 E2PROM A repeated write function gives the user flexibility to update the RDAC output a number of times after addressing and instructing the part only once. For example, after the RDAC has acknowledged its slave address and instruction bytes in the write mode, the RDAC output will update on each successive byte. If different instructions are needed, the write/read mode has to start again with a new slave address, instruction, and data byte. Similarly, a repeated read function of the RDAC is also allowed. SCL2 Figure 19. Level Shifting for Operation at Different Potentials ESD PROTECTION All digital inputs are protected with a series input resistor and parallel Zener ESD structures shown in Figure 20 and Figure 21. This applies to the digital input pins SDA, SCL, and AD0. 340 LOGIC Multiple Devices on One Bus(applies only to AD5248) VSS Figure 18 shows four AD5248 devices on the same serial bus. Each has a different slave address since the states of their AD0 and AD1 pins are different. This allows each device on the bus to be written to or read from independently. The master device output bus line drivers are open-drain pull-downs in a fully I2C compatible interface. Figure 20. ESD Protection of Digital Pins A,B,W VSS +5V Figure 21. ESD Protection of Resistor Terminals Rp Rp SDA TERMINAL VOLTAGE OPERATING RANGE SCL The AD5243/48 VDD and GND power supply defines the boundary conditions for proper 3-terminal digital potentiometer operation. Supply signals present on terminals A, B, and W that exceed VDD or GND will be clamped by the internal forward biased diodes (see Figure 22). MAST ER +5V +5V +5 V D SD A S CL AD 1 SD A S CL AD1 SDA SC L AD 1 S DA SCL AD1 AD 0 AD0 AD 0 AD0 AD 52 48 AD 5 248 A D 524 8 AD5 24 8 VDD Figure 18. Multiple AD5248 Devices on One I2C Bus LEVEL SHIFTING FOR BIDIRECTIONAL INTERFACE While most legacy systems may be operated at one voltage, a new component may be optimized at another. When two systems operate the same signal at two different voltages, proper level shifting is needed. For instance, one can use a 3.3 V E2PROM to interface with a 5 V digital potentiometer. A level shifting scheme is needed to enable a bidirectional communication so that the setting of the digital potentiometer can be stored to and retrieved from the E2PROM. Figure 19 shows one of the implementations. M1 and M2 can be any N-channel signal FETs, or if VDD falls below 2.5 V, low threshold Rev. PrE 5/12/03 | Page 12 of 16 A W B VSS Figure 22. Maximum Terminal Voltages Set by VDD and VSS Preliminary Technical Data AD5243/AD5248 POWER-UP SEQUENCE Since the ESD protection diodes limit the voltage compliance at terminals A, B, and W (see Figure 22), it is important to power VDD/GND before applying any voltage to terminals A, B, and W; otherwise, the diode will be forward biased such that VDD will be powered unintentionally and may affect the rest of the user's circuit. The ideal power-up sequence is in the following order: GND, VDD, digital inputs, and then VA/B/W. The relative order of powering VA, VB, VW, and the digital inputs is not important as long as they are powered after VDD/GND. device should be bypassed with disc or chip ceramic capacitors of 0.01 F to 0.1 F. Low ESR 1 F to 10 F tantalum or electrolytic capacitors should also be applied at the supplies to minimize any transient disturbance and low frequency ripple (see Figure 23). Note that the digital ground should also be joined remotely to the analog ground at one point to minimize the ground bounce. LAYOUT AND POWER SUPPLY BYPASSING VDD V DD C3 + C1 10F 0.1 F AD5243 GND It is a good practice to employ compact, minimum lead length layout design. The leads to the inputs should be as direct as possible with a minimum conductor length. Ground paths should have low resistance and low inductance. Similarly, it is also a good practice to bypass the power supplies with quality capacitors for optimum stability. Supply leads to the Rev. PrE 5/12/03 | Page 13 of 16 Figure 23. Power Supply Bypassing Preliminary Technical Data AD5243/AD5248 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS Table 9. 1 B1 W1 10 2 A1 B2 9 3 W2 A2 8 4 GND SDA 7 5 VDD SCL 6 Figure 24.- AD5243 Pin Configuration 1 B1 2 AD0 3 4 5 W1 10 B2 9 W2 AD1 8 GND SDA 7 VDD SCL 6 Figure 25. - AD5243 Pin Configuration Pin 1 2 3 4 5 6 7 8 9 10 Name B1 A1 W2 GND VDD SCL SDA A2 B2 W2 Description B1 Terminal. A1 Terminal. W2 Terminal. Digital Ground. Positive Power Supply. Serial Clock Input. Positive edge triggered. Serial Data Input/Output. A2 Terminal. B2 Terminal. W2 Terminal. Table 10. Pin 1 2 Name B1 AD0 3 4 5 6 7 8 W2 GND VDD SCL SDA AD1 9 10 B2 W1 Rev. PrE 5/12/03 | Page 14 of 16 Description B1 Terminal. Programmable address bit 0 for multiple package decoding. W2 Terminal Digital Ground. Positive Power Supply.. Serial Clock Input. Positive edge triggered. Serial Data Input/Output. Programmable address bit 1 for multiple package decoding. B2 Terminal. W1 Terminal. Preliminary Technical Data AD5243/AD5248 OUTLINE DIMENSIONS 3.00 BSC 10 6 4.90 BSC 3.00 BSC 1 5 PIN 1 0.50 BSC 0.95 0.85 0.75 1.10 MAX 0.15 0.00 0.27 0.17 SEATING PLANE 0.23 0.20 0.17 8 0 0.80 0.40 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187BA Figure 26. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters ORDERING GUIDE Model AD5243BRM2.5-R2 AD5243BRM2.5-RL7 AD5243BRM10-R2 AD5243BRM10-RL7 AD5243BRM50-R2 AD5243BRM50-RL7 AD5243BRM100-R2 AD5243BRM100-RL7 AD5243EVAL RAB () 2.5k 2.5k 10k 10k 50k 50k 100k 100k See Note 1 Temperature -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C Package Description MSOP-10 MSOP-10 MSOP-10 MSOP-10 MSOP-10 MSOP-10 MSOP-10 MSOP-10 Evaluation Board Package Option RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 Branding D0L D0L D0M D0M D0N D0N D0P D0P Model AD5248BRM2.5-R2 AD5248BRM2.5-RL7 AD5248BRM10-R2 AD5248BRM10-RL7 AD5248BRM50-R2 AD5248BRM50-RL7 AD5248BRM100-R2 AD5248BRM100-RL7 AD5248EVAL RAB () 2.5k 2.5k 10k 10k 50k 50k 100k 100k See Note 1 Temperature -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C Package Description MSOP-10 MSOP-10 MSOP-10 MSOP-10 MSOP-10 MSOP-10 MSOP-10 MSOP-10 Evaluation Board Package Option RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 Branding D1F D1F D1G D1G D1H D1H D1J D1J 1 The evaluation board is shipped with the 10 k RAB resistor option; however, the board is compatible with all available resistor value options. The AD5243/48 contains 2532 transistors. Die size: 30.7 mil x 76.8 mil = 2,358 sq. mil. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. PrE 5/12/03 | Page 15 of 16 Preliminary Technical Data AD5243/AD5248 NOTES Rev. PrE 5/12/03 | Page 16 of 16