Preliminary Technical Data
AD5243/AD5248
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A proportional to the input voltage at
A-to-B. Unlike the polarity of VDD to GND, which must be
positive, voltage across A-B, W-A, and W-B can be at either
polarity.
If ignoring the effect of the wiper resistance for approximation,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at the wiper-to-B starting at 0 V up
to 1 LSB less than 5 V. Each LSB of voltage is equal to the
voltage applied across terminal AB divided by the 256 positions
of the potentiometer divider. The general equation defining the
output voltage at VW with respect to ground for any valid input
voltage applied to terminals A and B is
B
A
WV
D
V
D
DV
256
256
256
)( −
+= (3)
For a more accurate calculation, which includes the effect of
wiper resistance, VW, can be found as
B
AB
WA
A
AB
WB
WV
R
DR
V
R
DR
DV )()(
)( += (4)
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors RWA and RWB and not the
absolute values. Therefore, the temperature drift reduces to
15 ppm/°C.
I2C COMPATIBLE 2-WIRE SERIAL BUS
The 2-wire I2C serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a START
condition, which is when a high-to-low transition on the
SDA line occurs while SCL is high (see Figure 13). The
following byte is the slave address byte, which consists of
the slave address followed by an R/W bit (this bit
determines whether data will be read from or written to
the slave device). The AD5243 has a fixed slave address
byte whereas the AD5248 has two configurable address bits
AD0 and AD1 (see Table 5).
The slave whose address corresponds to the transmitted
address responds by pulling the SDA line low during the
ninth clock pulse (this is termed the acknowledge bit). At
this stage, all other devices on the bus remain idle while the
selected device waits for data to be written to or read from
its serial register. If the R/W bit is high, the master will read
from the slave device. On the other hand, if the R/W bit is
low, the master will write to the slave device.
2. In the write mode, the second byte is the instruction byte.
The first bit (MSB) of the instruction byte is the RDAC sub
address select bit. A logic low will select channel-1 and a
logic high will select channel-2.
The second MSB, SD, is a shutdown bit. A logic high
causes an open circuit at terminal A while shorting the
wiper to terminal B. This operation yields almost 0 Ω in
rheostat mode or 0 V in potentiometer mode. It is
important to note that the shutdown operation does not
disturb the contents of the register. When brought out of
shutdown, the previous setting will be applied to the
RDAC. Also, during shutdown, new settings can be
programmed. When the part is returned from shutdown,
the corresponding VR setting will be applied to the RDAC.
The remainder of the bits in the instruction byte are don’t
cares(see Table 5).
After acknowledging the instruction byte, the last byte in
write mode is the data byte. Data is transmitted over the
serial bus in sequences of nine clock pulses (eight data bits
followed by an acknowledge bit). The transitions on the
SDA line must occur during the low period of SCL and
remain stable during the high period of SCL (see Table 5).
3. In the read mode, the data byte follows immediately after
the acknowledgment of the slave address byte. Data is
transmitted over the serial bus in sequences of nine clock
pulses(a slight difference with the write mode, where there
are eight data bits followed by an acknowledge bit).
Similarly, the transitions on the SDA line must occur
during the low period of SCL and remain stable during the
high period of SCL (see Figure 15 and Figure 16).
Note that the channel of interest is the one that is
previously selected in the Write Mode. In the case where
users need to read the RDAC values of both channels, they
need to program the first channel in the Write Mode and
then change to the Read Mode to read the first channel
value. After that, they need to change back to the Write
Mode with the second channel selected and read the
second channel value in the Read Mode again. It is not
necessary for users to issue the Frame 3 data byte in the
write mode for subsequent readback operation. Users
should refer to Figure 15 for the programming format.
Rev. PrE 5/12/03 | Page 11 of 16