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GENERAL DESCRIPTION
The DS1100L is a 3. 3V version of the DS1100. I t
is c haract er ized fo r o per at io n over t he rang e 3. 0V
to 3.6V. The DS1100L series delay lines have
five equally spaced taps providing delays from
4ns to 500ns. These devices are offered in
surface-mount packages to save PCB area. Low
cost and superior reliability over hybrid
technology is achieved by the combination of a
100% silicon delay line and industry-standard
µMAX and SO packaging. The DS1100L 5-tap
silicon d ela y line reproduces the input-logic state
at the output after a fixed delay as specified by
the extension of the part number after the dash.
The DS1100L is designed to reproduce both
leading and trailing edges with equal precision.
Each tap is capable of driving up to 10 74LS
loads.
Maxim can customize st andar d products to meet
special needs.
FEATURES
All-S ilicon Timing Cir c uit
Five Taps E qu ally Spaced
De lays are S table and Prec ise
Bot h Leading- a nd Trailin g-E dg e Accur acy
3.3V Version of the DS1100
Low-Power C MOS
TTL-/CMOS-Compatible
Vapor-Phase and IR Soldera b le
Custom Delays Available
Fast-Tur n Prototypes
Delays Specified Over Both Commercial and
Indust rial Temperature Ranges
PIN ASSIGNM ENT
PIN DESCRIPTION
TAP 1 to TAP 5 - T AP Output Number
VCC - +3.3V
GND - Ground
IN - Input
DS1100L
3.3V 5-Tap Economy Timing
Element (Delay Line)
1
2
3
4
8
7
6
5
VCC
TAP 1
TAP 3
TAP 5
IN
TAP 2
TAP 4
GND
DS1100LZ SO (150 mils)
DS1100LU µMAX®
19-5736; Rev 10/11
µ
MAX is a registered trademark of Maxim Integrated Produc t s, Inc.
DS1100L
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ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pi n Rela tive t o Grou nd ...................................... -0.5V to + 6.0V
Short-Circuit Output Current ................................................................ 50mA fo r 1s
Continuous Power Dissipation (TA = +7 0 °C)
SO (derate 5.9mW/°C above +70°C) .................................................. 470.6mW
µMAX (d erate 4.5mW/ °C above +70°C ............................................. 362mW
Operating Temperature Range .............................................................. -40°C to +85°C
Storage Temperature Range .................................................................. -55°C to +125°C
Lead T emper ature (soldering, 10s) ........................................................ +300°C
Soldering Temperature (reflow)
Lead(Pb)-free .................................................................................... +260°C
Contai ning lead(Pb) ........................................................................... +240°C
This is a stress rating only and functional operation of the d evice at these or any other conditions above those ind icated in the operation sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = 3. 0V to 3.6V; TA = -40°C to +85°C, unl ess oth er w i se noted.)
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
VCC
3.0
3.3
3.6
V
5
VIH 2.0
V
CC
+
0.3
V 5
VIL -0.3 0.8 V 5
II 0.0V ≤ VI ≤ VCC -1.0 +1.0 μA
ICC
VCC = Max; Freq. = 1MHz
10
mA
6, 8
IOH VCC = Min. VOH = 2.3 -1 mA
IOL VCC = Min. VOL = 0.5 8 mA
AC ELECTRICAL CHARACTERISTICS
(VCC = 3.0V to 3.6V; TA = -40°C to +85°C, unl ess oth er w i se noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
Input
Pulse Width tWI
20% of
Tap 5
tPLH
ns 9
Input-to-Tap
Delay Tolerance
(Delays ≤ 40ns)
tPLH,
tPHL
+25°C 3.3V -2 Table 1 +2 ns
1, 3, 4,
7, 10
0°C to +70°C -3 Table 1 +3 ns
1, 2, 3,
4, 7, 10
-40°C to +85°C -4 Table 1 +4 ns
1, 2, 3,
4, 7, 10
Input-to-Tap
Delay Tolerance
(Delays > 40ns)
tPLH,
tPHL
+25°C 3.3V
-5
Table 1
+5
%
1, 3, 4, 7
0°C to +70°C -8 Table 1 +8 %
1, 2, 3,
4, 7
-40°C to +85°C -13 Table 1 +13 %
1, 2, 3,
4, 7
Output Rise or Fall
Time
tOF, tOR 2.0 2.5 ns
Power-Up Time
tPU
200
μs
In p ut Pe r iod
Period
2(tWI)
ns
9
DS1100L
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CAPACITANCE
(TA = +25°C, unless ot her w is e no t e d.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
Input Capacitance
CIN
5
10
pF
NOTES:
1) Initial tolerances are ± with respect to the nominal value at +25°C and VCC = 3.3V for both leading and
tra iling edge.
2) Temperature and voltage tolerance is with respect to the nominal delay value over the stated temperature
range, and a supply-voltage range of 3.0V to 3.6V.
3) All tap delays tend to vary unidirectionally with temperature or voltage changes. For example, if TAP 1
slows down, all other taps also slow down; TAP 3 can never be faster than TAP 2.
4) Intermediate delay values are available on a custom basis. For further information, contact the factory at
custom.oscillators@maxim-ic.com.
5) All voltages are referenced to ground.
6) Measured with outputs open.
7) See Test Conditions section at the end of this data sheet.
8) Frequencies higher than 1MHz result in higher ICC values.
9) At or near maximum frequency the delay accuracy can vary and will be application sensitive (i.e.,
decoupling, layou t).
10) The “-75” version is specified and tested with an additional 2ns of tolerance on the specified minimum
input-to-tap delay tolerance parameter for TAP 1. Delay values for TAP 2 to TAP 5 meet data sheet
specifications.
Figure 1. LOGIC DIAGRAM
Figure 2. TIMING DIAGRAM: SILICON DELAY LINE
DS1100L
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TERMINOLOGY
Period: The time elapsed between the leading edge of the first pulse and the leading edge of the
following pulse .
tWI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the
1.5V point on the trailing edge or the 1.5V point on the trailing edge and the 1.5V po int on the leading
edge.
tRISE (Input Rise Time): T he elapsed time between t he 20% and the 80% po int on t he leading edge of the
input pulse.
tFALL (Input Fall Time): The elapsed time between t he 80% and the 20% po int on t he tr ailing edge of the
input pulse.
tPLH (Time Delay, Rising): The elapsed time between the 1.5V point on the leading edge of the input
pulse and the 1.5V point on t he leading edge of any tap output pulse.
tPHL (Time Delay, Falling): The elapsed time between the 1.5V point on the trailing edge of the input
pulse and the 1.5V point on t he trailing edge of a ny tap o utput pulse.
TEST SETUP DESC RIPTI ON
Figure 3 illustrates the hardware configuration used for measuring the timing parameters on the
DS1100L. The input waveform is produced by a precisio n pulse generator under software control. Time
delays are measured by a time interval counter (20ps resolution) connected between the input and each
tap. Each tap is selected and connected to the counter by a VHF switch control unit. All measurements
are fully automated, with each instrument contro lled by a centra l computer over an IEE E 488 bus.
TEST CONDITIONS INPUT:
Ambient Temper atu r e: 25°C ±3°C
Supp ly Voltage (VCC): 3.3V ±0.1V
Input Pulse: Hig h = 3.0V ±0.1V
Low = 0.0V ±0.1V
Source Impedance: 50Ω max
Rise and Fall Time : 3.0ns max (measured between 10% and 90%)
Pu lse Width: 500ns (1μs for -5 00 ve rs ion)
Period: 1μs (2μs for -500 versio n)
OUTPUT:
Each out put is lo aded w ith the equ ivalent of one 74F04 input gate. Delay is measured at the 1.5V le vel o n
t he ris ing a nd falling edge.
Note: Above conditions are for test only and do not restrict the operation of the device under other
data sheet conditions.
DS1100L
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Figure 3. TEST CIRCUIT
Table 1. DS1100L PART NUMBER DELAY
PART
DS1100L-xxx
NOM INAL DELAYS (ns)
TAP 1
TAP 2
TAP 3
TAP 4
TAP 5
-20
4
8
12
16
20
-25
5
10
15
20
25
-30
6
12
18
24
30
-35
7
14
21
28
35
-40
8
16
24
32
40
-45
9
18
27
36
45
-50
10
20
30
40
50
-60
12
24
36
48
60
-75
15
30
45
60
75
-100
20
40
60
80
100
-125
25
50
75
100
125
-150
30
60
90
120
150
-175
35
70
105
140
175
-200
40
80
120
160
200
-250
50
100
150
200
250
-300
60
120
180
240
300
-500
100
200
300
400
500
DS1100L
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ORDERING INFORMATION
PART
TEM P RAN GE
PIN-PACKAGE
DS1100LZ-xxx
-40°C to +85°C
8 SO
DS1100LZ-xxx/T&R
-40°C to +85°C
8 SO
DS1100LZ-xxx+
-40°C to +85°C
8 SO
DS1100LZ-xxx+T
-40°C to +85°C
8 SO
DS1100LU-xxx
-40°C to +85°C
8 µMAX
DS1100LU-xxx/T&R
-40°C to +85°C
8 µMAX
DS1100LU-xxx+
-40°C to +85°C
8 µMAX
DS1100LU-xxx+T
-40°C to +85°C
8 µMAX
xxx D eno tes to tal time d elay (ns) (see Table 1).
+Denotes a lead( Pb)-free/RoHS-compliant package.
T&R and T = Tape and reel.
PACKAGE INFORMATION
For th e latest package outline in formation and land patterns (footprints), go to www.maxim-ic.com/packages. Not e that a “+” ,
“#” , or “-” in the package cod e in dicates RoHS status on ly. Package drawin gs may show a different suffix character, but th e
drawing pertains to the package regardless of R o HS st a tus.
PACKAGE TYPE PACK AG E CODE OU TLINE NO . LAND PATTERN NO.
8 SO (150 mils) S8+4 21-0041 90-0096
8 µMAX U8+1 21-0036 90-0092
DS1100L
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Maxim cannot as sume responsibility for us e of any circuitry other than circuitr y entir ely embodied in a M ax im product . No cir cuit
patent licenses are imp lied. Maxim reserves the right to change the circuitry and specifications without notice at any t ime.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
201 1 M axim Integrat ed Pr od uc ts Maxim is a regi s t ered t r adem ar k of Ma xi m Integrat ed Produc t s .
REVISION HISTORY
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
3/11
Changed µSOP package ty pe to µMAX; updated the Absolute
Maximum Ratings sect io n; added the customer suppo rt email address to
t he electr ical characteristics No te 4; added the Ordering Inf ormation
and Package Inf ormation tables
1−6
10/11
Added co ntinuo us power dis s ipatio n numbers to the Absolute
Maximum Ratings sect io n; added Note 10 to the Input -to-Tap Delay
Tolerance (De lays ≤ 40ns) par ameter in the AC Electrical
Characteristics table
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