AME, Inc.
6
AME8510 / 8520 / 8530 Micropower µµ
µµ
µP W atch Dog T imer
nn
nn
n Detailed Description
The AME8510/8520/8530 are designed to interface with
the reset input of a microprocessor and to prevent CPU
execution errors due to power up, power down, and other
power supply errors. The AME8510/8520 also monitor
the CPU health by checking for signal transitions from
the CPU at the WDI input.
Reset Output
Each output pin in the family can be configured to be
either push/pull or open drain. In addition each output
may be either active high or active low with the condi-
tion that parts with two outputs must have opposite po-
larities. Active high reset outputs are denoted as RE-
SET. Active low reset outputs are denoted as RESETB.
The selection guide on page 2 of this data sheet shows
all possible combinations of output driver configuration.
A reset will be asserted if any of three things happen:
1) VDD drops below the threshold (VTH)
2) The MRB pin is pulled low .
3) The WDI pin does not detect a transition within
the watch dog interval (TWD).
The reset will remain asserted for the prescribed reset
interval after:
1) VDD rises above the threshold (VTH)
2) MRB goes high
3) The watch dog timer has timed out causing the
reset to assert.
Reset Timing Diagram
Manual Reset Input
The AME8510 and AME8530 feature a manual reset fea-
ture (MRB). A logic low on the MRB pin asserts a reset.
The reset remains asserted as long as the MRB pin re-
mains low . After the MRB pin transitions to a high state
the reset remains asserted for the prescribed reset inter-
val (TD2). The MRB pin is internally pulled up to VDD by
a 100kΩ resistor. It is internally debounced to reject
switching transients.
The MRB pin is ESD protected by diodes connected to
VDD and GND. So the MRB pin should never be driven
higher than VDD or lower than GND.
Watchdog Input
The AME8510 and AME8520 are equipped with a watch-
dog input (WDI). If the microprocessor does not produce
a valid logic edge at the the watchdog input (WDI) within
the prescribed watchdog interval (TWD) then a reset as-
serts. The reset remains asserted for the required reset
interval (TD2) At the end of the reset interval the reset is
deasserted and the watchdog interval timer starts again
from zero.
If the watchdog input is left unconnected or is connected
to a tri-stated buffer the watchdog function is disabled.
As soon as the WDI input is driven either low or high the
watchdog function resumes with the watchdog timer set
to zero.
Watchdog Timing Diagram
WDI
RESETB
VDD
T
WD
T
D2
T
D2
V
TH
V
DD
T
D2
V
Release
RESETB
V
TH
T
D1
T
D2
T
D1
RESET
50%
50%
50%
50%