APW7070/A 3A, 18V, 380kHz, Synchronous Step-Down Converter General Description Features * * * * * * * * * * * * Wide Input Voltage from 4.75V to 18V The APW7070/A is a 3A, synchronous, step-down converter Output Current up to 3A with integrated 80m MOSFETs. The device, with current-mode control scheme, can convert 4.75~18V input Adjustable Output Voltage from 0.8V to 90%VIN - 0.8V Reference Voltage - 2.5% System Accuracy voltage to the output voltage adjustable from 0.8 to 90% VIN to provide excellent output voltage regulation. 80m Integrated MOSFETs The APW7070A regulates the output voltage in an auto- High Efficiency up to 93% matic PSM/PWM mode operation, depending on the output current, for high efficiency operation over light to full Current-Mode Operation - Stable with Ceramic Output Capacitors load current. The APW7070 always works in a ForcedPWM mode with constant frequency over full output cur- - Fast Transient Response rent range for low-noise requirements.The APW7070/A is also equipped with power-on-reset, soft-start and whole Power-On-Reset Monitoring protections (including overvoltage, undervoltage, over temperature and current-limit) in a single package. In shut- Fixed 380kHz Switching Frequency in PWM Mode Automatic Pulse-Skipping Mode (PSM)/PWM Mode Operation (APW7070A) down mode, the supply current drops below 5A. This device, available in an 8-pin SOP-8P package, provides a very compact system solution with minimal Forced-PWM Operation (APW7070) Built-in Digital Soft-Start external components and good thermal conductance. Output Current-Limit Protection with Frequency Foldback Typical Efficiency 70% Undervoltage Protection Over-Temperature Protection 100 118% Overvoltage Protection 90 <5A Quiescent Current during Shutdown Pb-Free Available as an Option Lead Free and Green Devices Available (RoHS Compliant) Applications * * * * * * * VOUT V =5V 80 Thermal-Enhanced SOP-8P Package Efficiency (%) * * * * * * * VOUT= 3.3V 70 60 50 40 30 LCD Monitor / TV 20 SetTop Box 10 APW7070A Portable DVD 0.001 0.01 0.1 1 10 Output Current, IOUT (A) Wireless LAN ADSL, Switch HUB Notebook Computer Step-Down Converters Requiring High Efficiency and 3A Output Current ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 1 www.anpec.com.tw APW7070/A Ordering and Marking Information Package Code KA : SOP-8P Operating Ambient Temperature Range I : -40 to 85 C Handling Code TR : Tape & Reel Assembly Material L : Lead Free Device G : Halogen and Lead Free Device APW7070 APW7070A Assembly Material Handling Code Temperature Range Package Code APW7070 KA : APW7070 XXXXX XXXXX - Date Code APW7070A KA : APW7070A XXXXX XXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for MSL classification at lead-free peak reflow temperature. ANPEC defines "Green" to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Simplified Application Circuit Pin Configuration C1 10F VIN EN UGND VCC 8 1 2 3 9 LX 4 7 6 5 GND FB COMP LX C2 VIN L1 3A VCC UGND C3 LX U1 APW7070/A SOP-8P Top View R1 1% EN VIN COMP R4 The Pin 5 must be connected to the Exposed Pad VIN +12 C6 GND FB R2 1% C4 22F VOUT +3.3V C7 (Optional) C5 Absolute Maximum Ratings (Note 1) Symbol Parameter VIN VIN Supply Voltage (VIN to GND) VLX LX to GND Voltage VCC VCC Supply Voltage (VCC to GND) VUGND_GND VVIN_UGND Rating Unit -0.3 ~ 20 V > 100ns -1 ~ VIN +0.3 < 100ns -5 ~ VIN +6 VIN > 6.2V -0.3 ~ 6.5 VIN 6.2V VIN+0.3 V V UGND to GND Voltage -0.3 ~ VIN+0.3 VIN to UGND Voltage -0.3 ~ 6.5V V 20 V EN to GND Voltage FB, COMP to GND Voltage Maximum Junction Temperature TSTG Storage Temperature TSDR Maximum Lead Soldering Temperature, 10 Seconds V -0.3 ~ VCC +0.3 V 150 C -65 ~ 150 C 260 C Note 1: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 2 www.anpec.com.tw APW7070/A Thermal Characteristics Symbol Parameter Typical Value Junction-to-Ambient Resistance in Free Air JA SOP-8P Junction-to-Case Resistance in Free Air (Note 3) JC Unit (Note 2) SOP-8P 50 o 10 o C/W C/W Note 2: JA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad of SOP-8P is soldered directly on the PCB. Note 3: The case temperature is measured at the center of the exposed pad on the underside of the SOP-8P package. Recommended Operating Conditions (Note 4) Symbol VIN Parameter Range Unit 4.75 ~ 18 V 4.0 ~ 5.5 V 0.8 ~ 90% VIN V VIN Supply Voltage VCC Supply Voltage VOUT Converter Output Voltage IOUT Converter Output Current TA TJ 0~3 A VCC Input Capacitor 0.22 ~ 2.2 F VIN-to-UGND Input Capacitor 0.22 ~ 2.2 F -40 ~ 85 o -40 ~ 125 o Ambient Temperature Junction Temperature C C Note 4: Refer to the typical application circuits Electrical Characteristics Refer to the typical application circuits. These specifications apply over VIN=12V, VOUT=3.3V and TA= -40 ~ 85oC, unless otherwise specified. VCC is regulated by an internal regulator. Typical values are at TA=25oC. Symbol Parameter Test Conditions APW7070/A Min Typ Max Unit SUPPLY CURRENT IVIN IVIN_SD IVCC IVCC_SD VIN Supply Current VFB = 0.85V, VEN=3V, LX=Open - 1.0 2.0 mA VIN Shutdown Supply Current VEN = 0V, VIN=18V - - 5 A VCC Supply Current VEN = 3V, VCC = 5.0V - 0.7 - mA VCC Shutdown Supply Current VEN = 0V, VCC = 5.0V - - 1 A VCC 4.2V LINEAR REGULATOR Output Voltage VIN = 5.2 ~ 18V, IO = 0 ~ 8mA 4.0 4.2 4.5 V Load Regulation IO = 0 ~ 8mA -60 -40 0 mV Current-Limit VCC > POR Threshold 8 - 30 mA VIN-to-UGND 5.5V LINEAR REGULATOR Output Voltage (VVIN-UGND) VIN = 6.2 ~ 18V, IO = 0 ~ 10mA 5.3 5.5 5.7 V Load Regulation IO = 0 ~ 10mA -80 -60 0 mV Current-Limit VIN = 6.2 ~ 18V 10 - 30 mA Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 3 www.anpec.com.tw APW7070/A Electrical Characteristics (Cont.) Refer to the typical application circuits. These specifications apply over VIN=12V, VOUT=3.3V and TA= -40 ~ 85oC, unless otherwise specified. VCC is regulated by an internal regulator. Typical values are at TA=25oC. Symbol Parameter Test Conditions APW7070/A Min. Unit Typ. Max. 3.7 3.9 4.1 V - 0.15 - V 2.4 2.5 2.6 V - 0.2 - V - 3.5 - V - 0.2 - V V POWER-ON-RESET (POR) AND LOCKOUT VOLTAGE THRESHOLDS VCC POR Voltage Threshold VCC rising VCC POR Hysteresis EN Lockout Voltage Threshold VEN rising EN Lockout Hysteresis VIN-to-UGND Lockout Voltage Threshold VVIN-UGND rising VIN-to-UGND Lockout Hysteresis REFERENCE VOLTAGE VREF Reference Voltage - 0.8 - TJ = 25oC, IOUT=0A, VIN=12V -0.4 - +1.6 Output Voltage Accuracy TJ = -40 ~ 125oC, IOUT = 0 ~ 3A, VIN = 4.75 ~ 18V -2.5 - +2.5 Line Regulation VIN = 4.75V to 18V, IOUT = 0A - 0.1 - IOUT < 1A - -0.3 - IOUT = 1 ~ 3A - -0.53 - 340 380 420 kHz - 80 - kHz - 93 - % - 200 - ns Load Regulation % % %/A OSCILLATOR AND DUTY FOSC Oscillator Running Frequency VIN = 4.75 ~ 18V Foldback Frequency VFB = 0V Maximum Converter's Duty Cycle Minimum Pulse Width of LX VIN = 4.75 ~ 18V CURRENT-MODE PWM CONVERTER Gm Error Amplifier Transconductance Error Amplifier DC Gain COMP = Open - 400 - A/V 60 80 - dB - 0.12 - High-side Switch Resistance Between VIN and Exposed Pad, TJ=25oC - 80 100 m Low-side Switch Resistance Between GND and Exposed Pad, TJ=25oC - 80 100 m Current-Sense Resistance PROTECTIONS ILIM P-channel Power MOSFET Current-Limit Peak Current 4.0 5.5 7.0 A VUV FB Under-Voltage Threshold VFB falling 66 70 74 % FB Under-Voltage Hysteresis - 40 - mV FB Under-Voltage Debounce - 2 - s VOV TOTP TD 114 118 122 % FB Over-Voltage Hysteresis FB Over-Voltage Threshold - 40 - mV Over-Temperature Trip Point - 150 - o Over-Temperature Hysteresis - 50 - o - 30 - ns Dead-Time Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 VFB Rising VLX= -0.7V, VIN= 4.75 ~ 18V 4 C C www.anpec.com.tw APW7070/A Electrical Characteristics (Cont.) Refer to the typical application circuits. These specifications apply over VIN=12V, VOUT=3.3V and TA= -40 ~ 85oC, unless otherwise specified. VCC is regulated by an internal regulator. Typical values are at TA=25oC. Symbol Parameter Test Conditions APW7070/A Unit Min. Typ. Max. 9 10.8 12 ms SOFT-START, ENABLE, AND INPUT CURRENTS tSS Soft-Start Interval Preceding Delay before Soft-Start EN Shutdown Voltage Threshold VEN falling, VIN = 4 ~ 18V EN Enable Voltage Threshold VEN rising, VIN = 4 ~ 18V EN Pin Clamped Voltage IEN=10mA P-Channel Power MOSFET Leakage VEN = 0V, VLX= 0V, VIN= 18V Current 9 10.8 12 ms 0.5 - - V - - 2.1 V 12 - 17 V - - 4 A IFB FB Pin Input Current VFB =0.8V -100 - +100 A IEN EN Pin Input Current VEN < 3V -500 - +500 A Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 5 www.anpec.com.tw APW7070/A Typical Operating Characteristics Oscillator Frequency vs. Junction Temperature 0.816 420 0.812 410 Oscillator Frequency, FOSC (kHz) Reference Voltage, VREF (V) Reference Voltage vs. Junction Temperature 0.808 0.804 0.800 0.796 0.792 0.788 0.784 -50 -25 0 25 50 75 100 125 400 390 380 370 360 350 340 -50 150 -25 3.35 3.35 3.34 3.34 IOUT=0.2A 3.32 3.31 IOUT=1A 3.30 3.29 IOUT=2A 3.28 3.27 IOUT=3A 3.26 3.25 50 75 100 125 150 3.33 3.32 VIN=5V 3.31 3.30 3.29 VIN=12V 3.28 3.27 3.26 3.25 3.24 4 6 8 10 12 14 16 18 20 3.24 0.0 22 0.5 1.0 1.5 2.0 2.5 3.0 Supply Voltage, VIN (V) Output Current, IOUT (A) VIN Input Current vs. Supply Voltage Current-Limit Level (Peak Current) vs. Junction Temperature 1.6 7.0 VFB=0.85V Current-Limit Level, ILIM (A) 1.4 VIN Input Current, IVIN (mA) 25 Output Voltage vs. Output Current 3.36 Output Voltage, VOUT (V) Output Voltage, VOUT (V) Output Voltage vs. Supply Voltage 3.36 3.33 0 Junction Temperature, TJ (oC) Junction Temperature, TJ (oC) 1.2 1.0 0.8 0.6 0.4 0.2 6.5 6.0 5.5 5.0 4.5 4.0 0.0 0 2 4 6 8 -50 10 12 14 16 18 20 22 Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 -25 0 25 50 75 100 125 150 Junction Temperature, TJ (oC) VIN Supply Voltage, VIN (V) 6 www.anpec.com.tw APW7070/A Typical Operating Characteristics (Cont.) Efficiency vs. Output Current EN Clamp Voltage vs. EN Input Current 18 100% APW7070A 80% VOUT =5V 70% Efficiency EN Clamp Voltage, VEN (V) 90% VOUT=3.3V 60% 50% 40% 30% VIN=12V, L10=H(DCR=50m) C1=10F, C4=22F 20% 16 14 12 TJ=-30 C 10 8 TJ=25 C 6 TJ=100 C 4 2 0 10% 0.001 0.01 0.1 1 10 1 10 Output Current, IOUT (A) 100 1000 10000 EN Input Current, IEN (A) Operating Waveforms (Refer to the application circuit 1 in the section "Typical Application Circuits", VIN=12V, VOUT=3.3V, L1=10H ) Load Transient Response IOUT = 50mA -> 3A -> 50mA IOUT rise/fall time=10s Load Transient Response IOUT = 0.5A -> 3A -> 0.5A IOUT rise/fall time=10s APW7070A VOUT 1 VOUT 1 3A 3A IL1 2 0A IL1 0.5A 2 Ch1 : VOUT, 200mV/Div, DC, Voltage Offset = 3.3V Ch2 : IL1, 1A/Div, DC Time : 50s/Div Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 IL1 Ch1 : VOUT, 100mV/Div, DC, Voltage Offset = 3.3V Ch2 : IL1,1A/Div, DC Time : 50s/Div 7 www.anpec.com.tw APW7070/A Operating Waveforms (Cont.) (Refer to the application circuit 1 in the section "Typical Application Circuits", VIN=12V, VOUT=3.3V, L1=10H ) Power On Power Off IOUT = 3A IOUT = 3A VIN 1 VIN 1 VOUT 2 3 VOUT 2 IL1 IL1 3 Ch1 : VIN, 5V/Div, DC Ch2 : VOUT, 2V/Div, DC Ch3 : IL1, 2A/Div, DC Time : 5ms/Div Ch1 : VIN, 5V/Div, DC Ch2 : VOUT, 2V/Div, DC Ch3 : IL1, 2A/Div, DC Time : 5ms/Div Enable Through EN Pin Shutdown Through EN Pin IOUT = 3A 1 VEN VEN IOUT = 3A 1 VOUT 2 VOUT 2 IL1 3 IL1 3 Ch1 : VEN, 5V/Div, DC Ch2 : VOUT, 2V/Div, DC Ch3 : IL1, 2A/Div, DC Time : 5ms/Div Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 Ch1 : VEN, 5V/Div, DC Ch2 : VOUT, 2V/Div, DC Ch3 : IL1, 2A/Div, DC Time : 5ms/Div 8 www.anpec.com.tw APW7070/A Operating Waveforms (Cont.) (Refer to the application circuit 1 in the section "Typical Application Circuits", VIN=12V, VOUT=3.3V, L1=10H ) Over Current Short Circuit V OUT is shorted to ground by a short wire IOUT = 0.5A->6.4A VOUT 1 VOUT 1 IL1 2 2 Ch1 : VOUT, 1V/Div, DC Ch2 : IL1, 2A/Div, DC Time : 50s/Div IL1 Ch1 : VOUT, 1V/Div, DC Ch2 : IL1, 2A/Div, DC Time : 50ms/Div Switching Waveform Switching Waveform IOUT = 0.2A IOUT = 3A VLX 1 1 VLX IL1 2 IL1 2 Ch1 : VLX, 5V/Div, DC Ch2 : IL1, 0.5A/Div, DC Time : 1.25s/Div Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 Ch1 : VLX, 5V/Div, DC Ch2 : IL1, 2A/Div, DC Time : 1.25s/Div 9 www.anpec.com.tw APW7070/A Operating Waveforms (Cont.) (Refer to the application circuit 1 in the section "Typical Application Circuits", VIN=12V, VOUT=3.3V, L1=10H ) Line Transient Response V IN = 12V --> 20V --> 12V V IN rise/fall time=10s VOUT 1 20V VIN 12V 2 Ch1 : VOUT, 50mV/Div, DC, Voltage Offset = 3.3V Ch2 : VIN, 5V/Div, DC, Time : 50s/Div Pin Description PIN NAME FUNCTION 1 VIN Power Input. VIN supplies the power (4.75V to 18V) to the control circuitry, gate driver and step-down converter switch. Connecting a ceramic bypass capacitor and a suitably large capacitor between VIN and GND eliminates switching noise and voltage ripple on the input to the IC. 2 EN Enable Input. EN is a digital input that turns the regulator on or off. Drive EN high to turn on the regulator, drive it low to turn it off. Pull up with 100k resistor for automatic startup. 3 UGND Gate driver power ground of the P-channel Power MOSFET. A linear regulator regulates a 5.5V voltage between VIN and UGND to supply power to P-channel MOSFET gate driver. Connect a ceramic capacitor (1F typ.) between VIN and UGND for noise decoupling and stability of the linear regulator. 4 VCC Bias input and 4.2V linear regulator's output. This pin supplies the bias to some control circuits. The 4.2V linear regulator converts the voltage on VIN to 4.2V to supply the bias when no external 5V power supply is connected with VCC. Connect a ceramic capacitor (1F typ.) between VCC and GND for noise decoupling and stability of the linear regulator. 5 LX 6 COMP Output of error amplifier. Connect a series RC network from COMP to GND to compensate the regulation control loop. In some cases, an additional capacitor from COMP to GND is required for noise decoupling. 7 FB Feedback Input. The IC senses feedback voltage via FB and regulate the voltage at 0.8V. Connecting FB with a resistor-divider from the output set the output voltage in the range from 0.8V to 90% VIN. 8 GND 9 (Exposed Pad) LX Power Switching Output. Connect this pin to the underside Exposed Pad. Power and Signal Ground. Power Switching Output. LX is the Drain of the P-channel MOSFET to supply power to the output. The Exposed Pad provides current with lower impedance than Pin 5. Connect the pad to output LC filter via a top-layer thermal pad on PCBs. The PCB will be a heat sink of the IC. Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 10 www.anpec.com.tw APW7070/A Block Diagram VIN Current Sense Amplifier 4.2V Regulator and Power-On-Reset VCC Current Limit VCC Zero-Crossing Comparator POR UG OVP 118%VREF 70%VREF Soft-Start and Fault Logic UVP Gate Driver Soft-Start FB Inhibit LX Gate Control Gm VREF 0.8V Error Amplifier VCC LG Current Compartor Gate Driver COMP 2.5V Over Temperature Protection Enable 0.8V FB GND VIN Slope Compensation ENOK EN UGND 5.5V Oscillator 380kHz VIN-to-UGND Linear Regulator Typical Application Circuit 1. 4.75~18V Single Power Input Step-down Converter (with Ceramic Input/Output Capacitors) VIN C1 10F 4.75~18V 1 C2 1F VIN 4 VCC UGND C3 1F LX LX R5 100k VIN 3 L1 3A 9 VOUT 5 0.8V~90%VIN C4 /3A U1 APW7070/A 2 6 22F R1 1% EN COMP R4 GND 8 C6 FB 7 R2 1% C7 (Optional) C5 Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 11 www.anpec.com.tw APW7070/A Typical Application Circuit (Cont.) Recommended Feedback Compensation Network Components List: VIN (V) VOUT (V) L1 (H) C4 (F) C4 ESR (m) R1 (k) R2 (k) C7 (pF) R4 (k) C5 (pF) C6 (pF) 12 5 10 22 5 63 12 68 24 820 22 12 5 10 44 3 63 12 68 51 820 22 12 3.3 10 22 5 46.9 15 82 15 1000 22 12 3.3 10 44 3 46.9 15 82 33 1000 22 12 2 4.7 22 5 30 20 56 10 2200 22 12 2 4.7 44 3 30 20 56 20 2200 22 12 1.2 3.3 22 5 7.5 15 150 6.2 3300 22 12 5 1.2 3.3 3.3 3.3 44 22 3 5 7.5 46.9 15 15 150 68 12 15 3300 560 22 22 5 3.3 3.3 44 3 46.9 15 68 33 560 22 5 1.2 2.2 22 5 7.5 15 270 5.6 1500 22 5 1.2 2.2 44 3 7.5 15 270 12 1500 22 5 0.8 2.2 22 5 0 NC NC 2.7 2700 22 5 0.8 2.2 44 3 0 NC NC 6.2 2700 22 2. Dual Power Inputs Step-down Converter (VIN=4.75~18V) VIN +5V C1 10F 1 D1 Schottky Diode 4.75~18V C2 1F VIN 4 VCC UGND C3 1F LX LX R5 100k VIN 3 L1 3A 9 VOUT 5 0.8V~90%VIN C4 /3A U1 APW7070/A 2 6 22F R1 1% EN COMP R4 GND 8 C6 FB 7 R2 1% C7 (Optional) C5 Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 12 www.anpec.com.tw APW7070/A Typical Application Circuit (Cont.) 3. 4.75~5.5V Single Power Input Step-down Converter VIN C1 10F 4.75~5.5V 1 C2 1F VIN 4 VCC UGND C3 1F R5 100k VIN LX LX U1 APW7070/A 2 3 L1 3A 9 VOUT 5 0.8V~90%VIN C4 /3A R1 1% EN 6 FB COMP R4 22F R2 1% GND 8 C6 7 C7 (Optional) C5 4. +12V Single Power Input Step-down Converter (with Electrolytic Input/Output Capacitors) VIN C1 2.2F C8 +12V 470F 1 C2 1F VIN 4 VCC UGND C3 1F LX LX R5 100k VIN 9 VOUT +3.3V/3A R1 46.9k 1% EN COMP R4 56k FB GND 8 C5 4700pF Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 L1 10H 3A 5 U1 APW7070/A 2 6 C6 22pF 3 7 R2 15k 1% 13 C4 470F (ESR=30m) C7 33pF www.anpec.com.tw APW7070/A Typical Application Circuit (Cont.) 5. -8V Inverting Converter with 4.75~5.5V Single Power Input VIN 4.75~5.5V C1 10F 1 R5 100K VIN 2 UGND EN LX LX 4 C3 1F C6 22pF 3 C2 1F 9 L1 6.8H 3A 5 VCC U1 APW7070/A 6 COMP FB 7 R4 39k R2 10k GND AGND C7 27pF 8 C5 560pF PGND R1 90k C4 22F VOUT -8V Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 14 www.anpec.com.tw APW7070/A Function Description Main Control Loop good noise decoupling, please place the capacitor physically close to the IC. The linear regulator is not intended The APW7070/A is a constant frequency current mode switching regulator. During normal operation, the inter- for powering up any external loads. Do not connect any external loads to VCC. The linear regulator is also nal P-channel power MOSFET is turned on each cycle when the oscillator sets an internal RS latch and would equipped with current-limit protection to protect itself during over-load or short-circuit conditions on VCC pin. be turned off when an internal current comparator (ICMP) resets the latch. The peak inductor current at which ICMP VIN-to-UGND 5.5V Linear Regulator resets the RS latch is controlled by the voltage on the COMP pin, which is the output of the error amplifier The built-in 5.5V linear regulator regulates a 5.5V voltage between VIN and UGND pins to supply bias and gate charge for the P-channel Power MOSFET gate driver. The (EAMP). An external resistive divider connected between VOUT and ground allows the EAMP to receive an output linear regulator is designed to be stable with a low-ESR ceramic output capacitor of at least 0.22F. It is also feedback voltage VFB at FB pin. When the load current increases, it causes a slight decrease in VFB relative to equipped with current-limit function to protect itself during over-load or short-circuit conditions between VIN and the 0.8V reference, which in turn causes the COMP voltage to increase until the average inductor current matches the new load current. UGND. The APW7070/A shuts off the output of the converters VCC Power-On-Reset (POR) and EN Undervoltage when the output voltage of the linear regulator is below 3.5V (typical). The IC resumes working by initiating a new Lockout The APW7070/A keeps monitoring the voltage on VCC soft-start process when the linear regulator's output voltage is above the undervoltage lockout voltage pin to prevent wrong logic operations which may occur when VCC voltage is not high enough for the internal threshold. Digital Soft-Start control circuitry to operate. The VCC POR has a rising threshold of 3.9V (typical) with 0.15V of hysteresis. The APW7070/A has a built-in digital soft-start to control the output voltage rise and limit the input current surge An external undervoltage lockout (UVLO) is sensed and programmed at the EN pin. The EN UVLO has a rising during start-up. During soft-start, an internal ramp, connected to the one of the positive inputs of the error threshold of 2.5V with 0.2V of hysteresis. The EN UVLO should be programmed by connecting a resistive divider amplifier, rises up from 0V to 1V to replace the reference voltage (0.8V) until the ramp voltage reaches the refer- from VIN to EN to GND. After the VCC, EN, and VIN-to-UGND voltages exceed their ence voltage. The device is designed with a preceding delay about respective voltage thresholds, the IC starts a start-up process and then ramps up the output voltage to the setting 10.8ms (typical) before soft-start process. of output voltage. Connecting a RC network from EN to GND is for setting a turn-on delay that can be used to Enable/Shutdown sequence the output voltages of multiple devices. Driving EN to ground places the APW7070/A in shutdown. VCC 4.2V Linear Regulator When in shutdown, the internal power MOSFET turns off, all internal circuitry shuts down and the quiescent supply VCC is the output terminal of the internal 4.2V linear regu- current of VIN reduces to <1A (typical). lator which is powered from VIN and provides power to the APW7070/A. The linear regulator designed to be stable Output Undervoltage Protection In the process of operation, if a short-circuit occurs, the with a low-ESR ceramic output capacitor powers the internal control circuitry, then bypasses VCC to GND with a output voltage will drop quickly. Before the current-limit circuit responds, the output voltage will fall out of the re- ceramic capacitor of at least 0.22F. In order to provide Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 15 www.anpec.com.tw APW7070/A Function Description (Cont.) Output Undervoltage Protection (Cont.) Frequency Foldback quired regulation range. The undervoltage continually monitors the FB voltage after soft-start is completed. If a When the output is shorted to ground, the frequency of the oscillator will be reduced to about 80kHz. This lower load step is strong enough to pull the output voltage lower than the undervoltage threshold, the IC shuts down frequency allows the inductor current to safely discharge, thereby preventing current runaway. The oscillator's fre- converter's output. The undervoltage threshold is 70% of the nominal output voltage. The undervoltage compara- quency will gradually increase to its designed rate when the feedback voltage on FB again approaches 0.8V. tor has a built-in 2s noise filter to prevent the chips from wrong UVP shutdown caused by noise. The undervoltage protection works in a hiccup mode without latched shutdown. The IC will initiate a new soft-start process at the end of the proceeding delay. Over-Temperature Protection (OTP) The over-temperature circuit limits the junction temperature of the APW7070/A. When the junction temperature exceeds TJ = +150C, a thermal sensor turns off the power MOSFET, allowing the devices to cool. The thermal sensor allows the converter to start a start-up process and regulate the output voltage again after the junction temperature cools by 50C. The OTP is designed with a 50C hysteresis to lower the average TJ during continuous thermal overload conditions, increasing lifetime of the IC. Overvoltage Protection The overvoltage function monitors the output voltage by FB pin. The FB voltage should increase over 118% of the reference voltage due to the high-side MOSFET failure, or for other reasons, the overvoltage protection comparator, will force the low-side MOSFET gate driver high. As soon as the output voltage is within regulation, the OVP comparator is disengaged. The chips will restore its normal operation. This OVP scheme only clamps the voltage overshoot, and does not invert the output voltage when otherwise activated with a continuously high output from low-side MOSFET driver - a common problem for OVP schemes with a latch. Current-Limit Protection The APW7070/A monitors the output current, flowing through the P-channel power MOSFET, and limits the current peak at current-limit level to prevent loads and the IC from damages during overload or short-circuit conditions. Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 16 www.anpec.com.tw APW7070/A Application Information Power Sequencing VIN VIN IQ1 The APW7070/A can operate with single or dual power input(s). In dual-power applications, the voltage (VCC) ap- CIN Q1 plied at VCC pin must be lower than the voltage (VIN) on VIN pin. The reason is the internal parasitic diode from IL LX VCC to VIN will conduct due to the forward-voltage between VCC and VIN. Therefore, VIN must be provided VOUT L ICOUT Q2 IOUT ESR COUT before VCC. Setting Output Voltage T=1/FOSC The regulated output voltage is determined by: VOUT = 0.8 (1 + R1 ) R2 VLX (V) Suggested R2 is in the range from 1k to 20k. For portable applications, a 10k resistor is suggested for DT I IOUT IL R2. To prevent stray pickup, please locate resistors R1 and R2 close to APW7070/A. IOUT IQ1 Input Capacitor Selection I ICOUT Use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the surge current VOUT needed each time the P-channel power MOSFET (Q1) turns on. Place the small ceramic capacitors physically close to the VIN and between the VIN and GND. VOUT Figure 1 Converter Waveforms The important parameters for the bulk input capacitor are the voltage rating and the RMS current rating. For reliable Output Capacitor Selection operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and An output capacitor is required to filter the output and supply the load transient current. The filtering requirements are a function of the switching frequency and the ripple largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than current (I). The output ripple is the sum of the voltages, having phase shift, across the ESR and the ideal output the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. The RMS current (IRMS) capacitor. The peak-to-peak voltage of the ESR is calculated as the following equations: of the bulk input capacitor is calculated as the following equation: IRMS = IOUT D (1- D) (A) where D is the duty cycle of the power MOSFET. For a through hole design, several electrolytic capacitors VOUT VIN ........... (1) I = VOUT *(1 - D) FOSC *L ........... (2) VESR = I. ESR may be needed. For surface mount designs, solid tantalum capacitors can be used, but caution must be ........... (3) The peak-to-peak voltage of the ideal output capacitor is exercised with regard to the capacitor surge current rating. Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 D= calculated as the following equations: 17 www.anpec.com.tw APW7070/A Application Information (Cont.) Output Capacitor Selection (Cont.) VCOUT = I (V) 8 FOSC COUT has a direct effect on ripple current. Accepting larger values of ripple current allows the use of low inductances, but results in higher output voltage ripple ........... (4) and greater core losses. A reasonable starting point for setting ripple current is I 0.4 IOUT(MAX) . Remember, the For the applications using bulk capacitors, the V COUT is much smaller than the V ESR and can be ignored. maximum ripple current occurs at the maximum input voltage. The minimum inductance of the inductor is Therefore, the AC peak-to-peak output voltage (VOUT ) is shown below: VOUT = I ESR (V) calculated by using the following equation: ........... (5) VOUT *(VIN - VOUT) 1.2 380000 *L *VIN For the applications using ceramic capacitors, the VESR is much smaller than the V COUT and can be ignored. Therefore, the AC peak-to-peak output voltage (VOUT ) is L VOUT *(VIN - VOUT ) 456000 *VIN ........... (6) (H) where VIN = VIN(MAX) close to VCOUT . The load transient requirement is a function of the slew rate (di/dt) and the magnitude of the transient load current. Layout Consideration In high power switching regulator, a correct layout is These requirements are generally met with a mix of capacitors and careful layout. High frequency capacitors important to ensure proper operation of the regulator. In general, interconnecting impedance should be minimized initially supply the transient and slow the current load rate seen by the bulk capacitors. The bulk filter capacitor by using short, wide printed circuit traces. Signal and power grounds are to be kept separate and finally values are generally determined by the ESR (Effective Series Resistance) and voltage rating requirements rather combined using ground plane construction or single point grounding. Figure 2 illustrates the layout, with bold than actual capacitance requirements. lines indicating high current paths. Components along the bold lines should be placed close together. Below is High frequency decoupling capacitors should be placed as close to the power pins of the load as physically a checklist for your layout: possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these 1. Firstly, to initial the layout by placing the power components. Orient the power circuitry to achieve a low inductance components. An aluminum electrolytic capacitor's ESR value is related to the case size with lower clean power flow path. If possible, make all the connections on one side of the PCB with wide, copper ESR available in larger case sizes. However, the Equivalent Series Inductance (ESL) of these capacitors filled areas. increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. 1 + VIN - C2 3 Inductor Value Calculation 4 C3 The operating frequency and inductor selection are interrelated in that higher operating frequencies permit 2 6 VIN LX 5 9 LX efficiency due to an increase in MOSFET gate charge losses. The equation (2) shows that the inductance value + U1 APW7070/A EN COMP R4 GND C5 Compensation Network L1 C4 8 C6 C8 VCC FB the use of a smaller inductor for the same amount of inductor ripple current. However, this is at the expense of C1 UGND Load VOUT 7 R1 R2 C7 (Optional) Feedback Divider Figure 2 Current Path Diagram Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 18 www.anpec.com.tw APW7070/A Application Information (Cont.) Layout Consideration (Cont.) 2. In Figure 2, the loops with same color bold lines top VLX plane. The copper of the VLX plane on the Top layer conducts heat into the PCB and air. Please enlarge the conduct high slew rate current. These interconnecting impedances should be minimized by using wide, short area of VLX plan to reduces the case-to-ambient resistance (CA). printed circuit traces. 102 mil 3. Keep the sensitive small signal nodes (FB, COMP) away from switching nodes (LX or others) on the PCB. Therefore place the feedback divider and the feedback compensation network close to the IC to avoid 118 mil 1 8 2 7 3 SOP-8P switching noise. Connect the ground of feedback divider directly to the GND pin of the IC using a dedicated ground trace. Die 4. The VCC decoupling capacitor should be right next to the VCC and GND pins. Capacitor C2 should be connected as close to the VIN and UGND pins as 6 5 4 Exposed Pad Top VLX plane Ambient Air PCB possible. 5. Place the decoupling ceramic capacitor C1 near the Figure 4 VIN as close as possible. The bulk capacitors C8 are also placed near VIN. Use a wide power ground plane to connect the C1, C8, and C4 to provide a low impedance path between the components for large 5 SOP-8P L1 4 3 2 1 C1 VIN VLX VOUT C4 6 8 7 and high slew rate current. Load GND GND Figure 3 Recommended Layout Diagram Thermal Consideration In Figure 4, the SOP-8P is a cost-effective package featuring a small size, like a standard SOP-8, and a bottom exposed pad to minimize the thermal resistance of the package, being applicable to high current applications. The exposed pad must be soldered to the Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 19 www.anpec.com.tw APW7070/A Package Information SOP-8P D SEE VIEW A E E1 THERMAL PAD E2 D1 h X 45 c A 0.25 b L 0 GAUGE PLANE SEATING PLANE A1 A2 e VIEW A S Y M B O L SOP-8P MILLIMETERS MIN. MAX. A A1 INCHES MAX. MIN. 0.063 1.60 0.006 0.000 0.15 0.00 0.049 A2 1.25 b 0.31 0.51 0.012 0.020 c 0.17 0.25 0.007 0.010 D 4.80 5.00 0.189 0.197 D1 2.25 3.50 0.098 0.138 0.244 E 5.80 6.20 0.228 E1 3.80 4.00 0.150 0.157 E2 2.00 3.00 0.079 0.118 e 1.27 BSC 0.050 BSC h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 0 0o 8o 0o 8o Note : 1. Follow JEDEC MS-012 BA. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side . 3. Dimension "E" does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 20 www.anpec.com.tw APW7070/A Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application A H 330.0 2.00 50 MIN. SOP- 8P T1 C d D W E1 12.4+2.00 13.0+0.50 -0.00 -0.20 1.5 MIN. 20.2 MIN. 12.00.30 1.750.10 P0 P1 P2 4.00.10 8.0 0.10 2.0 0.05 D0 1.5+0.10 -0.00 D1 1.5 MIN. F 5.5 0.05 T A0 B0 K0 0.6+0.00 6.400.20 5.20 0.20 2.10 0.20 -0.40 (mm) Devices Per Unit Package Type Unit Quantity SOP- 8P Type & Reel 2500 Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 21 www.anpec.com.tw APW7070/A Taping Direction Information SOP-8P USER DIRECTION OF FEED Reflow Condition (IR/Convection or VPR Reflow) tp TP Critical Zone TL to TP Temperature Ramp-up TL tL Tsmax Tsmin Rampdown ts Preheat 25 t 25C to Peak Time Reliability Test Program Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B, A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 22 Description 245C, 5 sec 1000 Hrs Bias @125C 168 Hrs, 100%RH, 121C -65C~150C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms, 1 tr > 100mA www.anpec.com.tw APW7070/A Classification Reflow Profiles Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (TL) - Time (tL) Peak/Classification Temperature (Tp) Time within 5C of actual Peak Temperature (tp) Ramp-down Rate Sn-Pb Eutectic Assembly Pb-Free Assembly 3C/second max. 3C/second max. 100C 150C 60-120 seconds 150C 200C 60-180 seconds 183C 60-150 seconds 217C 60-150 seconds See table 1 See table 2 10-30 seconds 20-40 seconds 6C/second max. 6C/second max. 6 minutes max. 8 minutes max. Time 25C to Peak Temperature Notes: All temperatures refer to topside of the package. Measured on the body surface. Table 1. SnPb Eutectic Process - Package Peak Reflow Temperatures 3 Package Thickness 3 Volume mm <350 240 +0/-5C 225 +0/-5C <2.5 mm 2.5 mm Volume mm 350 225 +0/-5C 225 +0/-5C Table 2. Pb-free Process - Package Classification Reflow Temperatures Package Thickness 3 3 3 Volume mm Volume mm Volume mm <350 350-2000 >2000 <1.6 mm 260 +0C* 260 +0C* 260 +0C* 1.6 mm - 2.5 mm 260 +0C* 250 +0C* 245 +0C* 2.5 mm 250 +0C* 245 +0C* 245 +0C* *Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0C. For example 260C+0C) at the rated MSL level. Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 23 www.anpec.com.tw