High Voltage
Charge Pump, PLL Synthesizer
Data Sheet
ADF4113HV
Rev. B Document Feedback
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FEATURES
High voltage charge pump (15 V)
2.7 V to 5.5 V power supply
200 MHz to 4.0 GHz frequency range
Pin compatible with ADF4110, ADF4111, ADF4112, ADF4113
ADF4106, and ADF4002 synthesizers
Two selectable charge pump currents
Digital lock detect
Power-down mode
Loop filter design possible with ADIsimPLL™
APPLICATIONS
Applications using high voltage VCOs
IF/RF local oscillator (LO) generation in base stations
Point-to-point radio LO generation
Clock for analog-to-digital and digital-to-analog converters
Wireless LANs, PMR
Communications test equipment
GENERAL DESCRIPTION
The ADF4113HV is an integer-N frequency synthesizer with a
high voltage charge pump (15 V). The synthesizer is designed
for use with voltage controlled oscillators (VCOs) that have
high tuning voltages (up to 15 V). Active loop filters are often
used to achieve high tuning voltages, but the ADF4113HV
charge pump can drive a high voltage VCO directly with a
passive-loop filter. The ADF4113HV can be used to implement
local oscillators in the upconversion and downconversion
sections of wireless receivers and transmitters. It consists of a
low noise digital phase frequency detector (PFD), a precision
high voltage charge pump, a programmable reference divider,
programmable A and B counters, and a dual-modulus prescaler
(P/P + 1).
A simple 3-wire interface controls all of the on-chip registers.
The devices operate with a power supply ranging from 2.7 V to
5.5 V and can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
CLK
DATA
LE
MUXOUT
ADF4113HV
CP
CE AGND DGND
CPGND
22
14
REFERENCE
M3 M2 M1
6
HIGH Z
N = BP + A
CHARGE
PUMP
CURRENT
SETTING
MUX
R
SET
V
P
PHASE
FREQUENCY
DETECTOR
LOCK
DETECT
AV
DD
SD
OUT
24-BIT
INPUT REGISTER
DV
DD
AV
DD
19
13
SD
OUT
REF
IN
14-BIT
R COUNTER
RF
IN
A
RF
IN
B
R COUNTER
LATCH
FUNCTION
LATCH
A, B COUNTER
LATCH
FROM
FUNCTION
LATCH
13-BIT
BCOUNTER
6-BIT
A COUNTER
PRESCALER
P/P + 1
06223-001
LOAD
LOAD
Figure 1.
ADF4113HV Data Sheet
Rev. B | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Characteristics ................................................................ 4
Absolute Maximum Ratings ............................................................ 5
Transistor Count ........................................................................... 5
Thermal Resistance ...................................................................... 5
ESD Caution .................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 7
Circuit Description ........................................................................... 9
Reference Input Section ............................................................... 9
RF Input Stage ............................................................................... 9
Prescaler (P/P + 1) ........................................................................9
A and B Counters ..........................................................................9
R Counter .......................................................................................9
Phase Frequency Detector (PFD) and Charge Pump ............ 10
Muxout and Lock Detect ........................................................... 10
Input Shift Register .................................................................... 10
Function Latch ............................................................................ 13
Applications ..................................................................................... 15
Using a Digitial-to-Analog Converter to Drive
the RSET Pin .................................................................................. 15
Interfacing ................................................................................... 15
PCB Design Guidelines for Chip Scale Package .................... 16
Outline Dimensions ....................................................................... 17
Ordering Guide .......................................................................... 17
REVISION HISTORY
10/12—Rev. A to Rev. B
Changed CP-20-1 Package to CP-20-6 Package ............. Universal
Changes to Table 3 and Table 4 ....................................................... 5
Added EPAD Notation..................................................................... 6
Updated Outline Dimensions ....................................................... 17
Changes to Ordering Guide .......................................................... 17
9/08—Rev. 0 to Rev. A
Changes to Figure 22 ...................................................................... 13
1/07—Revision 0: Initial Version
Data Sheet ADF4113HV
Rev. B | Page 3 of 20
SPECIFICATIONS
AVDD = DVDD = 3 V ± 10%, 5 V ± 10%; 13.5 V < VP ≤ 16.5 V; AGND = DGND = CPGND = 0 V; RSET = 4.7 kΩ; dBm referred to 50 Ω;
TA = TMIN to TMAX, unless otherwise noted. Operating temperature range for B version: −40°C to +85°C.
Table 1.
Parameter
B Version
B Chips1
Unit
Test Conditions/Comments
RF CHARACTERISTICS (3 V)
RF Input Sensitivity −15/0 −15/0 dBm min/max
RF Input Frequency
0.2/3.7
0.2/3.7
GHz min/max
For lower frequencies, ensure SR > 130 V/μs
Prescaler Output Frequency2
165
165
MHz max
RF CHARACTERISTICS (5 V)
RF Input Sensitivity
−10/0
−10/0
dBm min/max
RF Input Frequency 0.2/3.7 0.2/3.7 GHz min/max For lower frequencies, ensure SR > 130 V/µs
0.2/4.0 0.2/4.0 GHz min/max Input level = −5 dBm
Prescaler Output Frequency 200 200 MHz max
REF
IN
CHARACTERISTICS
REF
IN
Input Frequency 5/150 5/150 MHz min/max For f < 5 MHz, ensure SR > 100 V/µs
Reference Input Sensitivity
0.4/AVDD
0.4/AVDD
V p-p min/max
AVDD = 3.3 V, biased at AVDD/23
1.0/AVDD
1.0/AVDD
V p-p min/max
For f ≥ 10 MHz, AVDD = 5 V, biased at AVDD/23, 4
REF
IN
Input Capacitance 10 10 pF max
REF
IN
Input Current ±100 ±100 µA max
PHASE DETECTOR FREQUENCY 5 5 MHz max
CHARGE PUMP
I
CP
Sink/Source R
SET
= 4.7 kΩ
High Value 640 640 μA typ
Low Value 80 80 µA typ
Absolute Accuracy
2.5
2.5
% typ
RSET Range
3.9/10
3.9/10
kΩ typ
I
CP
Three-State Leakage Current 5 5 nA max
Sink and Source Current Matching 3 3 % typ 1 V ≤ V
CP
≤ V
P
– 1 V
I
CP
vs. V
CP
1.5 1.5 % typ 1 V ≤ V
CP
≤ V
P
– 1 V
ICP vs. Temperature
2
2
% typ
VCP = VP/2
LOGIC INPUTS
VINH, Input High Voltage
0.8 × DVDD
0.8 × DVDD
V min
VINL, Input Low Voltage
0.2 × DVDD
0.2 × DVDD
V max
I
INH
/I
INL
, Input Current ±1 ±1 µA max
C
IN
, Input Capacitance 10 10 pF max
LOGIC OUTPUTS
V
OH
, Output High Voltage DV
DD
− 0.4 DV
DD
− 0.4 V min I
OH
= 500 µA
V
OL
, Output Low Voltage 0.4 0.4 V max I
OL
= 500 µA
POWER SUPPLIES
AV
DD
2.7/5.5 2.7/5.5 V min/V max
DVDD
AVDD
AVDD
VP
13.5/16.5
13.5/16.5
V min/V max
I
DD
5 (AI
DD
+ DI
DD
) 16 11 mA max 11 mA typical
I
P
0.25 0.25 mA max T
A
= 25°C
Low Power Sleep Mode 1 1 µA typ
NOISE CHARACTERISTICS
Normalized Phase Noise Floor
6
−212 −212 dBc/Hz typ
1 The B chip specifications are given as typical values.
2 This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that
is less than this value.
3 AC coupling ensures AVDD/2 bias.
4 Guaranteed by characterization.
5 TA = 25oC; AVDD = DVDD = 5.5 V; P = 16; RFIN = 900 MHz.
6 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO, PNTOT, and subtracting 20logN (where N is the N divider
value) and 10logfPFD: PNSYNTH = PNTOT − 10logfPFD − 20logN.
ADF4113HV Data Sheet
Rev. B | Page 4 of 20
TIMING CHARACTERISTICS
Guaranteed by design but not production tested. AVDD = DVDD = 3 V ± 10%, 5 V ± 10%; 13.5 V ≤ VP ≤ 16.5 V;
AGND = DGND = CPGND = 0 V; RSET = 4.7 kΩ; TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter Limit at TMIN to TMAX (B Version) Unit Test Conditions/Comments
t1 20 ns min LE setup time
t2 10 ns min DATA to CLK setup time
t3 10 ns min DATA to CLK hold time
t4 25 ns min CLK high duration
t5 25 ns min CLK low duration
t6 10 ns min CLK to LE setup time
t7 20 ns min LE pulse width
Timing Diagram
CLK
DATA
LE
LE
DB23 (MSB) DB22 DB2 DB1
(CONTROL BIT C2) DB0 (LSB)
(CONTROL BIT C1)
t
1
t
2
t
3
t
7
t
6
t
4
t
5
06223-002
Figure 2. Timing Diagram
Data Sheet ADF4113HV
Rev. B | Page 5 of 20
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter Rating
AV
DD
to GND1 −0.3 V to +7 V
AV
DD
to DV
DD
−0.3 V to +0.3 V
V
P
to GND −0.3 V to +18 V
Digital I/O Voltage to GND −0.3 V to V
DD
+ 0.3 V
Analog I/O Voltage to GND −0.3 V to V
P
+ 0.3 V
REF
IN
, RF
IN
A, RF
IN
B to GND −0.3 V to V
DD
+ 0.3 V
RFINA to RFINB
±320 mV
Operating Temperature Range
Industrial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature 150°C
Reflow, Soldering
Peak Temperature 260°C
Time at Peak Temperature 40 sec
1 GND = AGND = DGND = 0 V.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
This device is a high performance RF integrated circuit with an
ESD rating of <1 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.
TRANSISTOR COUNT
The transistor count is 12,150 (CMOS) and 348 (bipolar).
THERMAL RESISTANCE
Table 4. Thermal Resistance
Package Type θ
JA
Unit
TSSOP 150.4 °C/W
LFCSP (Paddle Soldered)
1
62.82 °C/W
1 Two signal planes (that is, on top and bottom surfaces), two buried planes,
and four thermal vias.
ESD CAUTION
ADF4113HV Data Sheet
Rev. B | Page 6 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
CP
C
PGND
AGND
AV
DD
R
FIN
A
R
FIN
B
R
SET
REF
IN
16
15
14
13
12
11
10
9
DV
DD
MUXOUT
LE
CE
DGND
CLK
DATA
V
P
ADF4113HV
TOP VIEW
(Not to Scale)
0
6223-003
Figure 3. TSSOP Pin Configuration
06223-004
AGND
AGND
RFINB
RFINA
DATA
LE
MUXOUT
CLK
CE
AV
DD
AV
DD
REF
IN
DGND
DGND V
P
R
SET
CP
DV
DD
DV
DD
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO AGND.
14
13
12
1
3
4
15
11
CPGND 2
5
7
6
8
9
10
19
20
18
17
16
ADF4113HV
TOP VIEW
(Not to Scale)
Figure 4. LFCSP Pin Configuration
Table 5. Pin Function Descriptions
TSSOP
Pin No.
LFCSP
Pin No. Mnemonic Description
1 19 RSET Connecting a resistor between this pin and CPGND sets the maximum charge pump output current.
The nominal voltage potential at the RSET pin is 0.56 V for the ADF4113HV. The relationship between
ICP and RSET is ICPmax = 3/RSET. Therefore, with RSET = 4.7 kΩ, ICPmax = 640 A.
2 20 CP Charge Pump Output. When enabled, this pin provides ±ICP to the external loop filter; in turn, this
drives the external VCO.
3 1 CPGND Charge Pump Ground. CPGND is the ground return path for the charge pump.
4 2, 3 AGND Analog Ground. This is the ground return path of the prescaler.
5 4 RFINB Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with
a small bypass capacitor, typically 100 pF.
6 5 RFINA Input to the RF Prescaler. This small-signal input is ac-coupled from the VCO.
7 6, 7 AVDD Analog Power Supply. The power supply can range from 2.7 V to 5.5 V. Decoupling capacitors to the
analog ground plane should be placed as close as possible to this pin. AVDD must be the same value
as DVDD.
8 8 REFIN Reference Input. This pin is a CMOS input with a nominal threshold of VDD/2, and an equivalent
input resistance of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or can be
ac-coupled.
9 9, 10 DGND Digital Ground.
10 11 CE Chip Enable. A Logic low on this pin powers down the device and puts the charge pump output
into three-state mode. Taking the pin high powers up the device depending on the status of the
Power-Down Bit PD1.
11 12 CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is
latched into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS
input.
12 13 DATA Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This
input is a high impedance CMOS input.
13 14 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into
one of the four latches; the latch is selected using the control bits.
14 15 MUXOUT Multiplexer Output. This multiplexer output allows either the lock detect, the scaled RF, or the
scaled reference frequency to be externally accessed.
15 16, 17 DVDD Digital Power Supply. This can range from 2.7 V to 5.5 V. Decoupling capacitors to the digital ground
plane (1µF, 1nF) should be placed as close as possible to this pin. For best performance, the 1 µF
capacitor should be placed within 2 mm of the pin. The placing of the 1nF capacitor is less critical
but should still be within 5 mm of the pin. DVDD must have the same value as AVDD.
16 18 VP Charge Pump Power Supply. VP can range from 13.5 V to 16.5 V and should be decoupled
appropriately.
N/A 21 EPAD Exposed Pad. The exposed pad must be connected to AGND.
Data Sheet ADF4113HV
Rev. B | Page 7 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
Loop bandwidth = 25 kHz, reference = 10 MHz reference from Agilent E4440A PSA, VCO = Sirenza VCO190-1500T(Y), evaluation
board = EV-ADF4113HVSDZ1.
FREQ
–UNIT PARAM
–TYPE DATA
–FORMAT KEYWORD IMPEDANCE
–OHMS
GHz S MA R 50
FREQ MAGS11 ANGS11
1.05 0.9512–40.134
1.10 0.93458–43.747
1.15 0.94782–44.393
1.20 0.96875–46.937
1.25 0.92216–49.6
1.30 0.93755–51.884
1.35 0.96178–51.21
1.40 0.94354–53.55
1.45 0.95189–56.786
1.50 0.97647–58.781
1.55 0.98619–60.545
1.60 0.95459–61.43
1.65 0.97945–61.241
1.70 0.98864–64.051
1.75 0.97399–66.19
1.80 0.97216–63.775
FREQ MAGS11 ANGS11
0.05 0.89207–2.0571
0.10 0.8886–4.4427
0.15 0.89022–6.3212
0.20 0.96323–2.1393
0.25 0.90566–12.13
0.30 0.90307–13.52
0.35 0.89318–15.746
0.40 0.89806–18.056
0.45 0.89565–19.693
0.50 0.88538–22.246
0.55 0.89699–24.336
0.60 0.89927–25.948
0.65 0.87797–28.457
0.70 0.90765–29.735
0.75 0.88526–31.879
0.80 0.81267–32.681
0.85 0.90357–31.522
0.90 0.92954–34.222
0.95 0.92087–36.961
1.00 0.93788–39.343
06223-005
Figure 5. S-Parameter Data for the ADF4113HV RF Input (Up to 1.8 GHz)
0
–450 6k
06223-027
RF INPUT FREQU
ENCY (MHz)
RF INPUT P OW E R ( dBm)
–5
–10
–15
–20
–25
–30
–35
–40
1k 2k 3k 4k 5k
+25°C
+85°C
–40°C
Figure 6. Input Sensitivity
100 1M
06223-042
FREQUENCY OFFSET (Hz)
1k 10k 100k
1kHz
–91.08dBc/Hz
–80
–90
–70
–100
–110
–120
–130
–140
–150
–160
–170
PHASE NOISE (d Bc/Hz)
CARRIE R P OWE R: –5.09d Bm
Figure 7. Integrated Phase Noise
(RF = 1000 MHz, PFD = 1 MHz, VTUNE = 1.8 V, RMS Noise = 0.93°)
5
–95
–1.25M
–1.00M
–0.75M
–0.50M
–0.25M
1.00G
0.25M
0.50M
0.75M
1.00M
1.25M
06223-043
FRE QUENCY ( Hz )
POWER (dB)
–5
–15
–25
–35
–45
–55
–65
–75
–85
1MHz
–92.428dBc
Figure 8. Reference Spurs (RF = 1000 MHz, PFD = 1 MHz)
100 1M
06223-040
FREQUENCY OFFSET (Hz)
1k 10k 100k
1kHz
–86.33dBc/Hz
–80
–90
–70
–100
–110
–120
–130
–140
–150
–160
–170
PHASE NOISE (d Bc/Hz)
CARRIE R P OWE R: –0.88d Bm
Figure 9. Integrated Phase Noise
(RF = 1800 MHz, PFD= 1 MHz, VTUNE = 13.1 V, RMS Noise = 1.16°)
0
–100
–1.25M
–1.00M
–0.75M
–0.50M
–0.25M
1.00G
0.25M
0.50M
0.75M
1.00M
1.25M
06223-041
FRE QUENCY ( Hz )
POWER (dB)
–10
–20
–30
–40
–50
–60
–70
–80
–90
1MHz
–87.264dBc
Figure 10. Reference Spurs (RF = 1800 MHz, PFD = 1 MHz)
ADF4113HV Data Sheet
Rev. B | Page 8 of 20
0
–120 016
06223-044
TUNING VOLTAGE (V)
FIRST REFERENCE SPUR LEVEL (d Bc)
–20
–40
–60
–80
–100
246810 12 14
V
DD
= 3V
V
P
= 15V
Figure 11. PFD Spurs (1 MHz) vs. VTUNE
–50
–90
–40 100
06223-045
TEMPERATURE (°C)
PHASE NOISE (d Bc/Hz)
–60
–70
–80
–20 020 40 60 80
V
DD
= 3V
V
P
= 15V
Figure 12. Phase Noise vs. Temperature
(RF = 1500 MHz, PFD = 1 MHz)
800
–8000 15
06223-026
VCP (V)
CHARGE P UM P CURRE NT (µ A)
600
400
200
0
–200
–400
–600
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Figure 13. Charge Pump Output Characteristics
Data Sheet ADF4113HV
Rev. B | Page 9 of 20
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 14. SW1 and SW2
are normally closed switches (NC in Figure 14). SW3 is normally
open (NO in Figure 14). When power-down is initiated, SW3 is
closed and SW1 and SW2 are opened. This ensures that there is
no loading of the REFIN pin on power-down.
BUFFER
TO R COUNTER
REF
IN
100kΩ
NC
SW2
SW3
NO
NC
SW1
POWER-DOWN
CONTROL
06223-014
Figure 14. Reference Input Stage
RF INPUT STAGE
The RF input stage is shown in Figure 15. It is followed by a
two-stage limiting amplifier to generate the current-mode logic
(CML) clock levels needed for the prescaler.
AV
DD
AGND
500Ω
500Ω
1.6V
BIAS
GENERATOR
RF
IN
A
RF
IN
B
06223-015
Figure 15. RF Input Stage
PRESCALER (P/P + 1)
Together with the A and B counters, the dual-modulus prescaler
(P/P + 1) enables the large division ratio, N, to be realized by
N = BP + A
The dual-modulus prescaler, operating at CML levels, takes the
clock from the RF input stage and divides it down to a manageable
frequency for the CMOS A and CMOS B counters. The pre-
scaler is programmable; it can be set in software to 8/9, 16/17,
32/33, or 64/65. It is based on a synchronous 4/5 core.
A AND B COUNTERS
The A and B CMOS counters combine with the dual-modulus
prescaler to allow a wide ranging division ratio in the PLL
feedback counter. The counters are specified to work when the
prescaler output is 200 MHz or less (for AVDD = 5 V). Thus,
with an RF input frequency of 2.5 GHz, a prescaler value of
16/17 is valid but a value of 8/9 is not.
Pulse Swallow Function
The A and B counters, in conjunction with the dual-modulus
prescaler, make it possible to generate output frequencies that
are spaced only by the reference frequency divided by R. The
equation for the VCO frequency is
fVCO = [(P × B) + A]fREFIN/R
where:
fVCO = output frequency of external voltage controlled
oscillator (VCO).
P = preset modulus of dual-modulus prescaler.
B = preset divide ratio of binary 13-bit counter (3 to 8191).
A = preset divide ratio of binary 6-bit swallow counter (0 to 63).
fREFIN = output frequency of the external reference frequency
oscillator.
R = preset divide ratio of binary 14-bit programmable reference
counter (1 to 16,383).
13-BIT B
COUNTER
6-BIT A
COUNTER
PRESCALER
P/P + 1
FROM RF
INPUT STAGE
MODULUS
CONTROL
N=BP+A
LOAD
LOAD
TO PFD
0
6223-016
Figure 16. A and B Counters
R COUNTER
The 14-bit R counter allows the input reference frequency to be
divided down to produce the reference clock to the phase fre-
quency detector (PFD). Division ratios from 1 to 16,383 are
allowed.
ADF4113HV Data Sheet
Rev. B | Page 10 of 20
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 17 is a simplified schematic.
The PFD includes a programmable delay element that controls
the width of the antibacklash pulse. This pulse ensures that
there is no dead zone in the PFD transfer function and mini-
mizes phase noise and reference spurs. Two bits in the reference
counter latch, ABP2 and ABP1, control the width of the pulse.
See Figure 20. The only recommended setting for the antiback-
lash pulse width is 7.2 ns.
PROGRAMMABLE
DELAY U3
CLR2Q2
D2
U2
CLR1
Q1
D1
CHARGE
PUMP
DOWN
UP
HIGH
HIGH
U1
ABP1 ABP2
R DIVIDER
N DIVIDER
CP OUTPUT
R DIVIDER
N DIVIDER
CP
CPGND
V
P
06223-017
Figure 17. PFD Simplified Schematic and Timing (in Lock)
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4113HV allows the user to
access various internal points on the chip. The state of MUXOUT
is controlled by M3, M2, and M1 in the function latch. Figure 22
shows the full truth table (function latch map). Figure 18 shows
the MUXOUT section in block diagram form.
CONTROL
MUX
DV
DD
MUXOUT
DGND
ANALOG LOCK DETECT
DIGITALLOCK DETECT
RCOUNTER OUTPUT
NCOUNTER OUTPUT
SDOUT
06223-018
Figure 18. MUXOUT Circuit
Lock Detect
MUXOUT can be programmed for two types of lock detect:
digital lock detect and analog lock detect.
Digital lock detect is active high. When LDP in the AB counter
latch is set to 0, digital lock detect is set high when the phase
error on five consecutive phase detector (PD) cycles is less than
10 ns. With LDP set to 1, five consecutive cycles of less than
3 ns are required to set the lock detect. It stays high until a phase
error greater than 25 ns is detected on any subsequent PD cycle.
Operate the N-channel, open-drain, analog lock detect with a
10 kΩ nominal external pull-up resistor. When lock has been
detected, this output is high with narrow low-going pulses.
INPUT SHIFT REGISTER
The ADF4113HV digital section includes a 24-bit input shift
register, a 14-bit R counter, and a 19-bit N counter comprising
a 6-bit A counter and a 13-bit B counter. Data is clocked into
the 24-bit shift register on each rising edge of CLK, MSB first.
Data is transferred from the shift register to one of three latches
on the rising edge of LE. The destination latch is determined by
the state of the two control bits (C2, C1) in the shift register.
These are the two LSBs, DB1 and DB0, as shown in Figure 2.
The truth table for these bits is shown in Table 6. Figure 19
shows a summary of how the latches are programmed.
Table 6. C2, C1 Truth Table
Control Bits
C2 C1 Data Latch
0 0 R counter
0 1 N counter (A and B)
1 0 Function latch (including prescaler)
Data Sheet ADF4113HV
Rev. B | Page 11 of 20
Latch Summary
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
000 0 0 0 ABP2 ABP1 R14 R13 R12
R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 C2(0) C1(0)
RESERVED 14-BIT RE FERENCE COUNT E R CONTROL
BITS
REFE RENCE COUNTER LAT CH
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0L1 0B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 A6 A5 A4 A3 A2 A1 C2(0) C1(1)
CONTROL
BITS
RE-
SERVED
LD
PREC
RE-
SERVED
13-BI T B COUNTER 6-BI T A COUNTER
N COUNTE R LAT CH
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
P2 P1 00 0 0CP3 CP2 CP1 0000 0 0F4 F3 M3 M2 M1 F2 F1 C2(1) C1(0)
CONTROL
BITS
CP T HRE E -
STATE
PD
POLARITY
PRE-
SCALER
VALUE RESERVED CURRENT
SETTING RESERVED MUXOUT
CONTROL
POWER
DOWN
COUNTER
RESET
FUNCTIO N L ATCH
06223-019
ANTI-
BACKLASH
PULSE
WIDTH
Figure 19. Latch Summary Tables
Reference Counter Latch Map
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
00 0 0 0 0ABP2 ABP1 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 C2(0) C1(0)
RESERVED
ANTI-
BACKLASH
PULSE
WIDTH 14-BIT RE FERENCE COUNT E R CONTROL
BITS
THESE BITS MUST BE SET AS
INDICATE D FO R NORMAL OPE RATION
R14 R13 R12 .......... R3 R2 R1 DIV IDE RAT IO
0 0 0 .......... 0011
0 0 0 .......... 0 1 0 2
0 0 0 .......... 0113
0 0 0.......... 1 0 0 4
. . . .......... . . . .
. . . .......... . . . .
.. . .......... . . . .
1 1 1 .......... 10016380
1 1 1 .......... 10116381
1 1 1 .......... 11 0 16382
1 1 1 .......... 11 1 16383
06223-020
ABP2 ABP1 ANTI-BACKLASH
PULSE WIDTH
1 0 7.2ns (ONLY ALLOWED
SETTING)
Figure 20. Reference Counter Latch Bit Map
ADF4113HV Data Sheet
Rev. B | Page 12 of 20
AB Counter Latch Map
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
010B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 A6 A5 A4 A3 A2 A1 C2(0) C1(1)
CONTROL
BITS
RE-
SERVED
LD
PREC
RE-
SERVED
13-BI T B COUNTER 6-BI T A COUNTER
L2 LOCK DETECT PRECISION
010ns
13ns
B13 B12 B11 B3 B2 B1 B CO UNTER DI V IDE RATIO
000.......... 000NOT ALLOWED
000.......... 001NOT ALLOWED
000.......... 010NOT ALLOWED
000.......... 1 1 1 3
............. . . . .
............. . . . .
............. . . . .
111.......... 1008188
111.......... 1018189
111.......... 1108190
111.......... 1118191
A6 A5 A2 A1 A COUNTER DIVI DE RATI O
0 0 .......... 0 0 0
0 0 .......... 0 1 1
0 0 .......... 0 0 2
0 0 .......... 1 1 3
. . .......... . . .
. . .......... . . .
. . .......... . . .
1 1 .......... 0 1 61
1 1 .......... 1 0 62
1 1 .......... 1 1 63
06223-021
Figure 21. B Counter Latch Map
Data Sheet ADF4113HV
Rev. B | Page 13 of 20
Function Latch Map
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
P2 P1 0 0 0 0 CP3 CP2 CP1 000000F4 F3 M3 M2 M1 F2 F1 C2(1) C1(0)
CONTROL
BITS
CP THREE-
STATE
PD
POLARITY
PRE-
SCALER
VALUE RESERVED CURRENT
SETTING RESERVED MUXOUT
CONTROL
POWER
DOWN
COUNTER
RESET
P2 P1 PRES CALER V ALUE
0 0 8/9
0 1 16/17
1 0 32/33
1 1 64/65
ICP ( µA)
CPI3 CPI2 CPI1 4.7kΩ
00080
111640
F4 CHARGE P UM P
OUTPUT
0NORMAL
1 THREE-STATE
F3 PHASE DETECTOR
POLARITY
1POSITIVE
0NEGATIVE
M3 M2 M1 OUTPUT
000THREE-STATE OUTPUT
001DIGITAL LOCK DETECT
(ACT IVE HIG H)
010N DIV IDER OUTP UT
011DVDD
100R DIV IDER OUTP UT
101ANALOG LOCK DE TECT
110SERIAL DATA OUTPUT
111DGND
PD1 OPERATION
0NORMAL
1PO WER DO WN
F1 COUNTER
OPERATION
0NORMAL
1R, A, B COUNTERS
HEL D IN RESE T
06223-022
Figure 22. Function Latch Map
FUNCTION LATCH
The on-chip function latch is programmed with C2 and C1 set
to 1,0, respectively. Figure 22 shows the input data format for
programming the function latch.
Counter Reset
DB2 (F1) is the counter reset bit. When DB2 is 1, the R counter
and the AB counters are reset. For normal operation, this bit
should be 0. Upon powering up, the F1 bit must be disabled,
and the N counter resumes counting in close alignment with
the R counter. (The maximum error is one prescaler cycle.)
Power-Down
DB3 (F2) in the function latch provides a software power-down
for the ADF4113HV. The device powers down immediately
after latching a 1 into Bit F2.
When the CE pin is low, the device immediately powers down
regardless of the state of the power-down bit (F2).
When a power-down is activated (either through software or
a CE pin activated power-down), the following events occur:
• All active dc current paths are removed.
• The R, N, and timeout counters are forced to their load
state conditions.
• The charge pump is forced into three-state mode.
• The digital clock detect circuitry is reset.
• The RFINA and RFINB inputs are debiased.
• The reference input buffer circuitry is disabled.
• The input register remains active and capable of loading
and latching data.
MUXOUT Control
The on-chip multiplexer is controlled by M3, M2, and M1 on
the ADF4113HV. Figure 22 shows the truth table.
Charge Pump Currents
CPI3, CPI2, and CPI1 program the current setting for the
charge pump. The truth table is given in Figure 22.
Prescaler Value
P2 and P1 in the function latch set the prescaler values. The
prescaler value should be chosen so that the prescaler output
frequency is always less than or equal to 200 MHz. Thus, with
an RF frequency of 2 GHz, a prescaler value of 16/17 is valid,
but a value of 8/9 is not.
PD Polarity
This bit sets the phase detector polarity bit. See Figure 22.
CP Three-State
This bit controls the CP output pin. With the bit set high, the
CP output is put into three-state. With the bit set low, the CP
output is enabled.
ADF4113HV Data Sheet
Rev. B | Page 14 of 20
DEVICE PROGRAMMING AFTER INITIAL
POWER-UP
After initial power-up of the device, there are two ways to
program the device.
CE Pin Method
1. Apply VDD.
2. Bring CE low to put the device into power-down. This is an
asynchronous power-down in that it happens immediately.
3. Program the function latch (10). Program the R counter
latch (00). Program the AB counter latch (01).
4. Bring CE high to take the device out of power-down. The R
and AB counters resume counting in close alignment.
After CE goes high, a duration of 1 µs is sometimes required for
the prescaler band gap voltage and oscillator input buffer bias to
reach steady state.
CE can be used to power the device up and down to check for
channel activity. The input register does not need to be repro-
grammed each time the device is disabled and enabled as long
as it has been programmed at least once after VDD was initially
applied.
Counter Reset Method
1. Apply VDD.
2. Conduct a function latch load (10 in 2 LSBs). As part of
this, load 1 to the F1 bit. This enables the counter reset.
3. Conduct an R counter load (00 in 2 LSBs).
4. Conduct an AB counter load (01 in 2 LSBs).
5. Conduct a function latch load (10 in 2 LSBs). As part of
this, load 0 to the F1 bit. This disables the counter reset.
This sequence provides the same close alignment as the initiali-
zation method. It offers direct control over the internal reset.
Note that counter reset holds the counters at load point and
three-states the charge pump, but does not trigger synchronous
power-down.
Data Sheet ADF4113HV
Rev. B | Page 15 of 20
APPLICATIONS
ADF4113HV
2.7kΩ
VCO
GND
18Ω
100pF
100pF
18Ω
18Ω
RFOUT
FREFIN
51Ω
100pF
100pF
RFINA
RFINB
RSET
REFIN CP
CE
CLK
DATA
LE
SPI-COMPATIBLE SERIAL BUS
MUXOUT LOCK
DETECT
INPUT OUTPUT
2
14
6
5
1
8
LOOP
FILTER
NOTES
1. POWER SUPPLY CONNECTIONS AND DECOUPLING
CAPACITORS ARE OMITTED FOR CLARITY.
AD5320
12-BIT
V-OUT DAC
06223-023
Figure 23. Driving the RSET Pin with a Digital-to-Analog Converter
USING A DIGITIAL-TO-ANALOG CONVERTER TO
DRIVE THE RSET PIN
A digital-to-analog converter (DAC) can be used to drive the
RSET pin of the ADF4113HV, thus increasing the level of control
over the charge pump current (ICP). This can be advantageous in
wideband applications where the sensitivity of the VCO varies
over the tuning range. To compensate for this, ICP can be varied
to maintain good phase margin and ensure loop stability. See
Figure 23 for this configuration.
INTERFACING
The ADF4113HV has a simple SPI®-compatible serial interface
for writing to the device. CLK, DATA, and LE control the data
transfer. When latch enable (LE) goes high, the 24 bits that have
been clocked into the input register on each rising edge of CLK
are transferred to the appropriate latch. See Figure 2 for the
timing diagram and Table 6 for the latch truth table.
The maximum allowable serial clock rate is 20 MHz. This
means that the maximum update rate possible for the device
is 833 kHz, or one update every 1.2 µs. This rate is more than
adequate for systems that have typical lock times in the
hundreds of microseconds.
ADuC812 Interface
Figure 24 shows the interface between the ADF4113HV and the
ADuC812 MicroConverter®. Because the ADuC812 is based on
an 8051 core, this interface can be used with any 8051-based
microcontroller. The MicroConverter is set up for SPI master
mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF4113HV needs
a 24-bit word. This is accomplished by writing three 8-bit bytes
from the MicroConverter to the device. When the third byte
has been written, the LE input should be brought high to
complete the transfer.
I/O port lines on the ADuC812 are also used to control power-
down (CE input), and to detect lock (MUXOUT configured as
lock detect and polled by the port input).
When the ADuC812 is operating in the SPI master mode, the
maximum SCLOCK rate of the ADuC812 is 4 MHz. This
means that the maximum rate at which the output frequency
can be changed is 166 kHz.
SCLOCK
MOSI
I/O PORTS
ADuC812
CLK
DATA
LE
CE
MUXOUT
(LOCK DETECT)
ADF4113HV
06223-024
Figure 24. ADuC812 to ADF4113HV Interface
ADF4113HV Data Sheet
Rev. B | Page 16 of 20
ADSP-21xx Interface
Figure 25 shows the interface between the ADF4113HV and the
ADSP-21xx digital signal processor. The ADF4113HV needs a
24-bit serial word for each latch write. The easiest way to
accomplish this using the ADSP-21xx family is to use the auto
buffered transmit mode of operation with alternate framing.
This provides a means for transmitting an entire block of serial
data before an interrupt is generated.
SCLK
DT
I/O FLAGS
ADSP-21xx
CLK
DATA
LE
CE
MUXOUT
(LOCK DETECT)
ADF4113HV
TFS
06223-025
Figure 25. ADSP-21xx to ADF4113HV Interface
Set up the word length for eight bits and use three memory
locations for each 24-bit word. To program each 24-bit latch,
store the three 8-bit bytes, enable the auto buffered mode, and
then write to the transmit register of the DSP. This last opera-
tion initiates the autobuffer transfer.
PCB DESIGN GUIDELINES FOR CHIP SCALE
PACKAGE
The lands on the chip scale package (CP-20-6) are rectangular.
The printed circuit board pad for these should be 0.1 mm
longer than the package land length, and 0.05 mm wider than
the package land width. The land should be centered on the pad
to ensure that the solder joint size is maximized.
The bottom of the chip scale package has a central thermal pad.
The thermal pad on the printed circuit board should be at least
as large as this exposed pad. On the printed circuit board, provide
a clearance of at least 0.25 mm between the thermal pad and the
inner edges of the pad pattern. This ensures that shorting is
avoided.
Thermal vias can be used on the printed circuit board thermal
pad to improve thermal performance of the package. If vias are
used, they should be incorporated in the thermal pad at a 1.2 mm
pitch grid. The via diameter should be between 0.3 mm and
0.33 mm, and the via barrel should be plated with 1 oz. copper
to plug the via.
The user should connect the printed circuit board thermal pad
to AGND.
Data Sheet ADF4113HV
Rev. B | Page 17 of 20
OUTLINE DIMENSIONS
0.50
BSC
0.65
0.60
0.55
0.30
0.25
0.18
COMPLIANT
TO
JEDEC STANDARDS MO-220-WGGD-1.
BOTTOM VIEWTOP VIEW
EXPOSED
PAD
PIN1
INDICATOR
4.10
4.00 SQ
3.90
SEATING
PLANE
0.80
0.75
0.70 0.05 MAX
0.02 NOM
0.20 REF
0.20 MIN
COPLANARITY
0.08
PIN 1
INDICATOR
2.30
2.10 SQ
2.00
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
1
20
6
10
11
1516
5
08-16-2010-B
Figure 26. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm x 4 mm Body, Very Very Thin Quad
(CP-20-6)
Dimensions shown in millimeters
16 9
81
PIN 1
SEATING
PLANE
8°
0°
4.50
4.40
4.30
6.40
BSC
5.10
5.00
4.90
0.65
BSC
0.15
0.05
1.20
MAX 0.20
0.09 0.75
0.60
0.45
0.30
0.19
COPLANARITY
0.10
COMPLIA NT TO JEDEC S TANDAR DS MO - 1 53 - A B
Figure 27. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option2
ADF4113HVBRUZ −40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADF4113HVBRUZ-RL −40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADF4113HVBRUZ-RL7 −40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADF4113HVBCPZ −40°C to +85°C 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-6
ADF4113HVBCPZ-RL −40°C to +85°C 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-6
ADF4113HVBCPZ-RL7 −40°C to +85°C 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-6
EV-ADF4113HVSD1Z Evaluation Board
1 Z = RoHS Compliant Part.
2 The CP-20-6 package was formerly the CP-20-1 package.
ADF4113HV Data Sheet
Rev. B | Page 18 of 20
NOTES
Data Sheet ADF4113HV
Rev. B | Page 19 of 20
NOTES
ADF4113HV Data Sheet
Rev. B | Page 20 of 20
NOTES
©2007–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06223-0-10/12(B)
