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MOS INTEGRATED CIRCUIT
μ
PD444008L
4M-BIT CMOS FAST SRAM
512K-WORD BY 8-BIT
DATA SHEET
Document No. M14429EJ6V0DS00 (6th edition)
Date Published September 2006 NS CP(K)
Printed in Japan The mark <R> shows major revised points.
The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field.
1999
Description
The
μ
PD444008L is a high speed, low power, 4,194,304 bits (524,288 words by 8 bits) CMOS static RAM.
Operating supply voltage is 3.3 V ± 0.3 V.
The
μ
PD444008L is packaged in 36-pin PLASTIC SOJ.
Features
• 524,288 words by 8 bits organization
• Fast access time : 8, 10, 12, ns (MAX.)
• Output Enable input for easy application
• Single +3.3 V power supply
Ordering Information
Part number Package Access time Supply current mA (MAX.)
ns (MAX.) At operating At standby
μ
PD444008LLE-A8 36-pin PLASTIC SOJ 8 185 5
μ
PD444008LLE-A10 (10.16 mm (400)) 10 165
μ
PD44008LLE-A12 12 155
μ
PD444008LLE-A8-A 8 185
μ
PD444008LLE-A10-A 10 165
μ
PD444008LLE-A12-A 12 155
Remark Products with -A at the end of the part number are lead-free products.
2
μ
PD444008L
Data Sheet M14429EJ6V0DS
Pin Configuration (Marking Side)
/××× indicates active low signal.
36-pin PLASTIC SOJ (10.16 mm (400))
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
A0
A1
A2
A3
A4
/CS
I/O1
I/O2
V
CC
GND
I/O3
I/O4
/WE
A5
A6
A7
A8
A9
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
A18
A17
A16
A15
/OE
I/O8
I/O7
GND
V
CC
I/O6
I/O5
A14
A13
A12
A11
A10
NC
A0 - A18 : Address Inputs
I/O1 - I/O8 : Data Inputs / Outputs
/CS : Chip Select
/WE : Write Enable
/OE : Output Enable
V
CC : Power supply
GND : Ground
NC : No connection
Remark Refer to Package Drawing for the 1-pin index mark.
3
μ
PD444008L
Data Sheet M14429EJ6V0DS
Block Diagram
A0
|
A18
Address buffer
Row decoder
Memory cell array
4,194,304 bits
GND
V
CC
/WE
/OE
/CS
Input data
controller
Sense amplifier /
Switching circuit
Column decoder
Address buffer
I/O1
|
I/O8
Output data
controller
Truth Table
/CS /OE /WE Mode I/O Supply current
H × × Not selected High impedance ISB
L L H Read DOUT ICC
L × L Write DIN
L H H Output disable High impedance
Remark × : Don’t care
4
μ
PD444008L
Data Sheet M14429EJ6V0DS
Electrical Specifications
Absolute Maximum Ratings
Parameter Symbol Condition Rating Unit
Supply voltage VCC –0.5 Note to +4.0 V
Input / Output voltage VT –0.5 Note to +4.0 V
Operating ambient temperature TA 0 to 70 °C
Storage temperature Tstg –55 to +125 °C
Note –2.0 V (MIN.) (pulse width : 2 ns)
Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter Symbol Condition MIN. TYP. MAX. Unit
Supply voltage VCC 3.0 3.3 3.6 V
High level input voltage VIH 2.0 VCC+0.3 V
Low level input voltage VIL –0.3
Note +0.8 V
Operating ambient temperature TA 0 70 °C
Note –2.0 V (MIN.) (pulse width : 2 ns)
5
μ
PD444008L
Data Sheet M14429EJ6V0DS
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Parameter Symbol Test condition MIN. TYP. MAX. Unit
Input leakage current ILI VIN = 0 V to VCC –2 +2
μ
A
Output leakage current ILO VI/O = 0 V to VCC, –2 +2
μ
A
/CS = VIH or /OE = VIH or /WE = VIL
Operating supply current ICC /CS = VIL, Cycle time : 8 ns 185 mA
II/O = 0 mA, Cycle time : 10 ns 165
Minimum cycle time Cycle time : 12 ns 155
Standby supply current ISB /CS = VIH, VIN = VIH or VIL 40 mA
ISB1 /CS ≥ VCC – 0.2 V, 5
VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V
High level output voltage VOH IOH = –4.0 mA
2.4 V
Low level output voltage VOL IOL = +8.0 mA 0.4 V
Remark VIN : Input voltage
V
I/O : Input / Output voltage
Capacitance (TA = 25 °C, f = 1 MHz)
Parameter Symbol Test condition MIN. TYP. MAX. Unit
Input capacitance CIN VIN = 0 V 6 pF
Input / Output capacitance CI/O VI/O = 0 V 8 pF
Remarks 1. VIN : Input voltage
V
I/O : Input / Output voltage
2. These parameters are periodically sampled and not 100% tested.
6
μ
PD444008L
Data Sheet M14429EJ6V0DS
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Test Conditions
Input Waveform (Rise and Fall Time ≤ 3 ns)
Test Points
GND
3.0 V
1.5 V 1.5 V
Output Waveform
Test Points1.5 V 1.5 V
Output Load
AC characteristics directed with the note should be measured with the output load shown in Figure 1 or Figure
2.
Figure 1 Figure 2
(tAA, tACS, tOE, tOH) (tCLZ, tOLZ, tCHZ, tOHZ, tWHZ, tOW)
V
TT
= +1.5 V
I/O (Output)
50 Ω
Z
O
= 50 Ω
30 pF
C
L
+3.3 V
I/O (Output)
317 Ω
5 pF
C
L
351 Ω
Remark CL includes capacitances of the probe and jig, and stray capacitances.
7
μ
PD444008L
Data Sheet M14429EJ6V0DS
Read Cycle
Parameter Symbol -A8 -A10 -A12 Unit Notes
MIN. MAX. MIN. MAX. MIN. MAX.
Read cycle time tRC 8 10 12 ns
Address access time tAA 8 10 12 ns 1
/CS access time tACS 8 10 12 ns
/OE access time tOE 4 5 6 ns
Output hold from address change tOH 3 3 3 ns
/CS to output in low impedance tCLZ 3 3 3 ns 2, 3
/OE to output in low impedance tOLZ 0 0 0 ns
/CS to output in high impedance tCHZ 4 5 6 ns
/OE to output hold in high impedance tOHZ 4 5 6 ns
Notes 1. See the output load shown in Figure 1.
2. Transition is measured at ± 200 mV from steady-state voltage with the output load shown in Figure 2.
3. These parameters are periodically sampled and not 100% tested.
Read Cycle Timing Chart 1 (Address Access)
t
OH
t
RC
t
AA
Address (Input)
I/O (Output) Previous data out Data out
Remarks 1. In read cycle, /WE should be fixed to high level.
2. /CS = /OE = VIL
8
μ
PD444008L
Data Sheet M14429EJ6V0DS
Read Cycle Timing Chart 2 (/CS Access)
Address (Input)
tRC
tAA
tOLZ
/CS (Input)
I/O (Output) Data out
tOHZ
High impedance
tACS
/OE (Input)
tOE
tCLZ tCHZ
High impedance
Caution Address valid prior to or coincident with /CS low level input.
Remark In read cycle, /WE should be fixed to high level.
9
μ
PD444008L
Data Sheet M14429EJ6V0DS
Write Cycle
Parameter Symbol -A8 -A10 -A12 Unit Notes
MIN. MAX. MIN. MAX. MIN. MAX.
Write cycle time tWC 8 10 12 ns
/CS to end of write tCW 6 7 8 ns
Address valid to end of write tAW 6 7 8 ns
Write pulse width tWP 6 7 8 ns
Data valid to end of write tDW 4 5 6 ns
Data hold time tDH 0 0 0 ns
Address setup time tAS 0 0 0 ns
Write recovery time tWR 0 0 0 ns
/WE to output in high impedance tWHZ 4 5 6 ns 1, 2
Output active from end of write tOW 3 3 3 ns
Notes 1. Transition is measured at ± 200 mV from steady-state voltage with the output load shown in Figure 2.
2. These parameters are periodically sampled and not 100% tested.
Write Cycle Timing Chart 1 (/WE Controlled)
t
WC
t
CW
t
WP
t
AS
t
WR
Address (Input)
/CS (Input)
/WE (Input)
I/O (Input / Output)
t
DH
t
WHZ
t
AW
High
impe-
dance
High
impe-
dance
t
OW
Indefinite data out Data in Indefinite data out
t
DW
Cautions 1. /CS or /WE should be fixed to high level during address transition.
2. Do not input data to the I/O pins while they are in the output state.
Remarks 1. Write operation is done during the overlap time of a low level /CS and a low level /WE.
2. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level, read
operation is executed. Therefore /OE should be at high level to make the I/O pins high impedance.
10
μ
PD444008L
Data Sheet M14429EJ6V0DS
Write Cycle Timing Chart 2 (/CS Controlled)
t
WC
t
AS
t
CW
t
AW
t
WP
t
WR
t
DW
t
DH
Address (Input)
/CS (Input)
/WE (Input)
I/O (Input) High impedance Data in High impedance
Cautions 1. /CS or /WE should be fixed to high level during address transition.
2. Do not input data to the I/O pins while they are in the output state.
Remark Write operation is done during the overlap time of a low level /CS and a low level /WE.
11
μ
PD444008L
Data Sheet M14429EJ6V0DS
Package Drawing
M
N
K
M
Q
G
H
JE
T
U
B
C
D
E
F
G
H
I
J
K
23.6±0.20
11.18±0.2
1.005±0.1
0.74
3.5±0.2
2.545±0.2
0.8 MIN.
10.16±0.1
NOTE
P
Q 0.1
9.4±0.20
0.12
0.42
1.27 (T.P.)
2.6
Each lead centerline is located within 0.12 mm
of its true position (T.P.) at maximum material
condition.
M
N
T
U 0.22
R 0.85
+0.08
−0.07
36-PIN PLASTIC SOJ (10.16 mm (400))
P36LE-400A-2
ITEM MILLIMETERS
+0.08
−0.07
19
18
36
1
SS
I
F
P
C D
B
12
μ
PD444008L
Data Sheet M14429EJ6V0DS
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the
μ
PD444008L.
Type of Surface Mount Device
μ
PD444008LLE : 36-pin PLASTIC SOJ (10.16 mm (400))
μ
PD444008LLE-A : 36-pin PLASTIC SOJ (10.16 mm (400))
Quality Grade
• A quality grade of the products is “Standard”.
• Anti-radioactive design is not implemented in the products.
• Semiconductor devices have the possibility of unexpected defects by affection of cosmic ray that reach to the
ground and so forth.
<R>
13
μ
PD444008L
Data Sheet M14429EJ6V0DS
Revision History
Edition/ Page Type of Location Description
Date This Previous revision (Previous edition → This edition)
edition edition
6th edition/ p.12 p.12 Addition Quality Grade Section of Quality Grade has been added.
Sep. 2006
14
μ
PD444008L
Data Sheet M14429EJ6V0DS
[ MEMO ]
15
μ
PD444008L
Data Sheet M14429EJ6V0DS
1
2
3
4
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between VIL (MAX) and
VIH (MIN).
HANDLING OF UNUSED INPUT PINS
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
NOTES FOR CMOS DEVICES
5
6
μ
PD444008L
The information in this document is current as of September, 2006. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
designated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
(1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
•
•
•
•
•
•
M8E 02. 11-1
