BSC037N08NS5 MOSFET OptiMOSTM5Power-Transistor,80V SuperSO8 8 Features *OptimizedforhighperformanceSMPS,e.g.sync.rec. *100%avalanchetested *Superiorthermalresistance *N-channel *Pb-freeleadplating;RoHScompliant *Halogen-freeaccordingtoIEC61249-2-21 7 5 6 4 1 2 3 6 5 3 2 4 7 8 1 Productvalidation FullyqualifiedaccordingtoJEDECforIndustrialApplications Table1KeyPerformanceParameters Parameter Value Unit VDS 80 V RDS(on),max 3.7 m ID 131 A Qoss 56 nC QG(0V..10V) 46 nC Type/OrderingCode Package BSC037N08NS5 PG-TDSON-8 Final Data Sheet Marking 037N08NS 1 S1 8D S2 7D S3 6D G4 5D RelatedLinks - Rev.2.3,2020-07-27 OptiMOSTM5Power-Transistor,80V BSC037N08NS5 TableofContents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Electrical characteristics diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Final Data Sheet 2 Rev.2.3,2020-07-27 OptiMOSTM5Power-Transistor,80V BSC037N08NS5 1Maximumratings atTA=25C,unlessotherwisespecified Table2Maximumratings Parameter Symbol Continuous drain current1) Values Unit Note/TestCondition 131 83 22 A VGS=10V,TC=25C VGS=10V,TC=100C VGS=10V,TA=25C,RthJA=50K/W2) - 524 A TC=25C - - 140 mJ ID=50A,RGS=25 VGS -20 - 20 V - Power dissipation Ptot - - 114 2.5 W TC=25C TA=25C,RthJA=50K/W2) Operating and storage temperature Tj,Tstg -55 - 150 C IEC climatic category; DIN IEC 68-1: 55/150/56 Unit Note/TestCondition Min. Typ. Max. ID - - Pulsed drain current3) ID,pulse - Avalanche energy, single pulse4) EAS Gate source voltage 2Thermalcharacteristics Table3Thermalcharacteristics Parameter Symbol Thermal resistance, junction - case, bottom Values Min. Typ. Max. RthJC - 0.7 1.1 K/W - Thermal resistance, junction - case, top RthJC - - 20 K/W - Device on PCB, 6 cm2 cooling area2) RthJA - - 50 K/W - 1) Rating refers to the product only with datasheet specified absolute maximum values, maintaining case temperature at 25C. For higher case temperature please refer to Diagram 2. De-rating will be required based on the actual environmental conditions. 2) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 m thick) copper area for drain connection. PCB is vertical in still air. 3) See Diagram 3 for more detailed information 4) See Diagram 13 for more detailed information Final Data Sheet 3 Rev.2.3,2020-07-27 OptiMOSTM5Power-Transistor,80V BSC037N08NS5 3Electricalcharacteristics atTj=25C,unlessotherwisespecified Table4Staticcharacteristics Parameter Symbol Drain-source breakdown voltage Values Unit Note/TestCondition - V VGS=0V,ID=1mA 3 3.8 V VDS=VGS,ID=72A - 0.1 10 1 100 A VDS=80V,VGS=0V,Tj=25C VDS=80V,VGS=0V,Tj=125C IGSS - 10 100 nA VGS=20V,VDS=0V Drain-source on-state resistance RDS(on) - 3.2 4.4 3.7 5.3 m VGS=10V,ID=50A VGS=6V,ID=25A Gate resistance1) RG - 1.3 2.0 - Transconductance gfs 47 94 - S |VDS|>2|ID|RDS(on)max,ID=50A Unit Note/TestCondition Min. Typ. Max. V(BR)DSS 80 - Gate threshold voltage VGS(th) 2.2 Zero gate voltage drain current IDSS Gate-source leakage current Table5Dynamiccharacteristics Parameter Symbol Input capacitance1) Values Min. Typ. Max. Ciss - 3200 4200 pF VGS=0V,VDS=40V,f=1MHz Coss - 530 690 pF VGS=0V,VDS=40V,f=1MHz Reverse transfer capacitance Crss - 25 44 pF VGS=0V,VDS=40V,f=1MHz Turn-on delay time td(on) - 14 - ns VDD=40V,VGS=10V,ID=50A, RG,ext=3 Rise time tr - 10 - ns VDD=40V,VGS=10V,ID=50A, RG,ext=3 Turn-off delay time td(off) - 26 - ns VDD=40V,VGS=10V,ID=50A, RG,ext=3 Fall time tf - 7 - ns VDD=40V,VGS=10V,ID=50A, RG,ext=3 Unit Note/TestCondition Output capacitance1) 1) Table6Gatechargecharacteristics2) Parameter Symbol Gate to source charge Gate charge at threshold Values Min. Typ. Max. Qgs - 15 - nC VDD=40V,ID=50A,VGS=0to10V Qg(th) - 9.0 - nC VDD=40V,ID=50A,VGS=0to10V Gate to drain charge Qgd - 10 15 nC VDD=40V,ID=50A,VGS=0to10V Switching charge Qsw - 16 - nC VDD=40V,ID=50A,VGS=0to10V Gate charge total Qg - 46 58 nC VDD=40V,ID=50A,VGS=0to10V Gate plateau voltage Vplateau - 4.8 - V VDD=40V,ID=50A,VGS=0to10V Gate charge total, sync. FET Qg(sync) - 40 - nC VDS=0.1V,VGS=0to10V Qoss - 56 74 nC VDD=40V,VGS=0V 1) 1) 1) Output charge 1) 2) Defined by design. Not subject to production test See Gate charge waveforms for parameter definition Final Data Sheet 4 Rev.2.3,2020-07-27 OptiMOSTM5Power-Transistor,80V BSC037N08NS5 Table7Reversediode Parameter Symbol Diode continuous forward current Diode pulse current Diode forward voltage 1) Reverse recovery time 1) Reverse recovery charge 1) Values Unit Note/TestCondition 103 A TC=25C - 524 A TC=25C - 0.9 1.1 V VGS=0V,IF=50A,Tj=25C trr - 41 83 ns VR=40V,IF=50A,diF/dt=100A/s Qrr - 36 72 nC VR=40V,IF=50A,diF/dt=100A/s Min. Typ. Max. IS - - IS,pulse - VSD Defined by design. Not subject to production test Final Data Sheet 5 Rev.2.3,2020-07-27 OptiMOSTM5Power-Transistor,80V BSC037N08NS5 4Electricalcharacteristicsdiagrams Diagram1:Powerdissipation Diagram2:Draincurrent 120 140 120 100 100 80 ID[A] Ptot[W] 80 60 60 40 40 20 0 20 0 25 50 75 100 125 150 0 175 0 20 40 60 TC[C] 80 100 120 140 160 TC[C] Ptot=f(TC) ID=f(TC);VGS10V Diagram3:Safeoperatingarea Diagram4:Max.transientthermalimpedance 3 101 10 1 s 10 s 102 100 0.5 ZthJC[K/W] ID[A] 100 s 1 ms 101 10 ms DC 0.2 0.1 10-1 0.05 0.02 0.01 0 10 10-1 10-1 10 100 101 102 -2 10-3 single pulse 10-6 10-5 VDS[V] 10-3 10-2 10-1 tp[s] ID=f(VDS);TC=25C;D=0;parameter:tp Final Data Sheet 10-4 ZthJC=f(tp);parameter:D=tp/T 6 Rev.2.3,2020-07-27 OptiMOSTM5Power-Transistor,80V BSC037N08NS5 Diagram5:Typ.outputcharacteristics Diagram6:Typ.drain-sourceonresistance 400 8 360 6V 7V 10 V 320 5.5 V 5V 7 6 280 5 RDS(on)[m] ID[A] 240 6V 200 160 120 7V 4 10 V 3 5.5 V 2 80 5V 1 40 0 0.0 0.5 1.0 1.5 2.0 2.5 0 3.0 0 50 100 150 VDS[V] 200 250 300 350 400 ID[A] ID=f(VDS);Tj=25C;parameter:VGS RDS(on)=f(ID);Tj=25C;parameter:VGS Diagram7:Typ.transfercharacteristics Diagram8:Typ.forwardtransconductance 400 200 360 175 320 150 280 125 gfs[S] ID[A] 240 200 160 100 75 120 50 80 25 40 150 C 0 0 2 25 C 4 6 8 0 0 40 80 VGS[V] ID=f(VGS);|VDS|>2|ID|RDS(on)max;parameter:Tj Final Data Sheet 120 160 200 240 ID[A] gfs=f(ID),VDS=3V,Tj=25C 7 Rev.2.3,2020-07-27 OptiMOSTM5Power-Transistor,80V BSC037N08NS5 Diagram9:Drain-sourceon-stateresistance Diagram10:Typ.gatethresholdvoltage 7 5 6 4 5 max VGS(th)[V] RDS(on)[m] 720 A 3 4 typ 3 72 A 2 2 1 1 0 -60 -20 20 60 100 140 0 -60 180 -20 20 Tj[C] 60 100 140 180 Tj[C] RDS(on)=f(Tj);ID=50A;VGS=10V VGS(th)=f(Tj);VGS=VDS Diagram11:Typ.capacitances Diagram12:Forwardcharacteristicsofreversediode 4 103 10 25 C 25 C, max 150 C 150 C, max Ciss 103 102 IF[A] C[pF] Coss 102 101 Crss 101 0 20 40 60 80 100 0.0 0.5 VDS[V] C=f(VDS);VGS=0V;f=1MHz Final Data Sheet 1.0 1.5 2.0 VSD[V] IF=f(VSD);parameter:Tj 8 Rev.2.3,2020-07-27 OptiMOSTM5Power-Transistor,80V BSC037N08NS5 Diagram13:Avalanchecharacteristics Diagram14:Typ.gatecharge 2 10 10 9 40 V 8 25 C 7 16 V 64 V 100 C VGS[V] IAV[A] 6 101 5 4 125 C 3 2 1 100 100 101 102 103 tAV[s] 0 0 10 20 30 40 50 Qgate[nC] IAS=f(tAV);RGS=25;parameter:Tj(start) VGS=f(Qgate);ID=50Apulsed;parameter:VDD Diagram15:Drain-sourcebreakdownvoltage Diagram Gate charge waveforms 86 84 VBR(DSS)[V] 82 80 78 76 -60 -20 20 60 100 140 180 Tj[C] VBR(DSS)=f(Tj);ID=1mA Final Data Sheet 9 Rev.2.3,2020-07-27 OptiMOSTM5Power-Transistor,80V BSC037N08NS5 5PackageOutlines DOCUMENT NO. Z8B00003332 REVISION 07 DIMENSION A A1 b D D1 D2 E E1 E2 e L M MILLIMETERS MIN. MAX. 0.90 1.20 0.15 0.35 0.34 0.54 4.80 5.35 3.90 4.40 0.03 0.23 5.70 6.10 5.90 6.42 3.88 4.31 1.27 0.45 0.71 0.45 0.69 SCALE 10:1 0 1 2 3mm EUROPEAN PROJECTION ISSUE DATE 06.06.2019 Figure1OutlinePG-TDSON-8,dimensionsinmm Final Data Sheet 10 Rev.2.3,2020-07-27 OptiMOSTM5Power-Transistor,80V BSC037N08NS5 PG-TDSON-8: RecommenGHd BoDrdpads & Apertures 1.905 1.905 1.27 3x 0.6 1.27 3x copper Figure 2 Final Data Sheet 1.6 0.2 1.27 3x 0.825 2.863 0.5 0.925 2.863 1.27 3x 1.905 0.875 1.5 0.75 0.2 2.9 4.455 3.325 0.8 0.5 1.5 0.4 1.905 stencil apertures solder mask all dimensions in mm Outline Boardpads (TDSON-8), dimensions in mm 11 Rev.2.3,2020-07-27 OptiMOS TM 5 Power-Transistor , 80 V BSC037N08NS5 Dimension in mm Figure 3 Final Data Sheet Outline Tape (TDSON-8) 12 Rev. 2.3, 2020-07-27 OptiMOS TM 5 Power-Transistor , 80 V BSC037N08NS5 Revision History BSC037N08NS5 Revision: 2020-07-27, Rev. 2.3 Previous Revision Revision Date Subjects (major changes since last revision) 2.0 2014-12-17 Release of final version 2.1 2019-03-05 Update Rds(on) typ at Vgs=10V 2.2 2020-02-07 Update package drawings 2.3 2020-07-27 Update current rating Trademarks All referenced product or service names and trademarks are the property of their respective owners. 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The Infineon Technologies component described in this Data Sheet may be used in life-support devices or systems and/or automotive, aviation and aerospace applications or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support, automotive, aviation and aerospace device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Final Data Sheet 13 Rev. 2.3, 2020-07-27