DS1243Y
64K NV SRAM with Phantom Clock
DS1243Y
022798 1/12
FEATURES
•Real time clock keeps track of hundredths of seconds,
seconds, minutes, hours, days, date of the month,
months, and years
•8K x 8 NV SRAM directly replaces volatile static RAM
or EEPROM
•Embedded lithium energy cell maintains calendar op-
eration and retains RAM data
•W atch function is transparent to RAM operation
•Month and year determine the number of days in each
month; valid up to 2100
•Lithium energy source is electrically disconnected to
retain freshness until power is applied for the first time
•Standard 28–pin JEDEC pinout
•Full ±10% operating range
•Operating temperature range 0°C to 70°C
•Accuracy is better than ±1 minute/month @ 25°C
•Over 10 years of data retention in the absence of
power
•Available in 120, 150 and 200 ns access time
ORDERING INFORMATION
DS1243Y–XXX
DS1243Y
–120 120 ns access
–150 150 ns access
200 ns access
PIN ASSIGNMENT
28–PIN ENCAPSULATED PACKAGE
720 MIL EXTENDED
VCC
WE
NC
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
RST
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PIN DESCRIPTION
Ao–A12 – Address Inputs
CE – Chip Enable
GND – Ground
DQ0–DQ7– Data In/Data Out
VCC – Power (+5V)
WE – Write Enable
OE – Output Enable
NC – No Connect
RST – Reset
DESCRIPTION
The DS1243Y 64K NV SRAM with Phantom Clock is a
fully static nonvolatile RAM (organized as 8192 words
by 8 bits) with a built–in real time clock. The DS1243Y
has a self–contained lithium energy source and control
circuitry which constantly monitors VCC for an out–of–
tolerance condition. When such a condition occurs, the
lithium energy source is automatically switched on and
write protection is unconditionally enabled to prevent
corrupted data in both the memory and real time clock.
The Phantom Clock provides timekeeping information
including hundredths of seconds, seconds, minutes,
hours, day, date, month, and year information. The date
at the end of the month is automatically adjusted for
months with less than 31 days, including correction for
leap years. The Phantom Clock operates in either
24–hour or 12–hour format with an AM/PM indicator.
DS1243Y
022798 2/12
RAM READ MODE
The DS1243Y executes a read cycle whenever WE
(Write Enable) is inactive (high) and CE (Chip Enable) is
active (low). The unique address specified by the 13 ad-
dress inputs (A0–A12) defines which of the 8192 bytes
of data is to be accessed. V alid data will be available to
the eight data output drivers within tACC (Access T ime)
after the last address input signal is stable, providing
that CE and OE (Output Enable) access times and
states are also satisfied. If OE and CE access times are
not satisfied, then data access must be measured from
the later occurring signal (CE or OE) and the limiting pa-
rameter is either tCO for CE or tOE for OE rather than ad-
dress access.
RAM WRITE MODE
The DS1243Y is in the write mode whenever the WE
and CE signals are in the active (low) state after address
inputs are stable. The latter occurring falling edge of CE
or WE will determine the start of the write cycle. The
write cycle is terminated by the earlier rising edge of CE
or WE. All address inputs must be kept valid throughout
the write cycle. WE must return to the high state for a
minimum recovery time (tWR) before another cycle can
be initiated. The OE control signal should be kept inac-
tive (high) during write cycles to avoid bus contention.
However, if the output bus has been enabled (CE and
OE active) then WE will disable the outputs in tODW from
its falling edge.
DATA RETENTION MODE
The DS1243Y provides full functional capability for VCC
greater than VTP and write protects by 4.25 volts. Data
is maintained in the absence of VCC without any addi-
tional support circuitry . The nonvolatile static RAM con-
stantly monitors VCC. Should the supply voltage decay ,
the RAM automatically write protects itself. All inputs to
the RAM become “don’t care” and all outputs are high
impedance. As VCC falls below approximately 3.0 volts,
the power switching circuit connects the lithium energy
source to RAM to retain data. During power–up, when
VCC rises above approximately 3.0 volts, the power
switching circuit connects external VCC to the RAM and
disconnects the lithium energy source. Normal RAM
operation can resume after VCC exceeds 4.5 volts.
FRESHNESS SEAL
Each DS1243Y is shipped from Dallas Semiconductor
with its lithium energy source disconnected, insuring full
energy capacity. When VCC is first applied at a level
greater than VTP, the lithium energy source is enabled
for battery backup operation.
PHANTOM CLOCK OPERATION
Communication with the Phantom Clock is established
by pattern recognition on a serial bit stream of 64 bits
which must be matched by executing 64 consecutive
write cycles containing the proper data on DQ0. All ac-
cesses which occur prior to recognition of the 64–bit pat-
tern are directed to memory.
After recognition is established, the next 64 read or write
cycles either extract or update data in the Phantom
Clock, and memory access is inhibited.
Data transfer to and from the timekeeping function is ac-
complished with a serial bit stream under control of Chip
Enable (CE), Output Enable (OE), and Write Enable
(WE). Initially , a read cycle to any memory location us-
ing the CE and OE control of the Phantom Clock starts
the pattern recognition sequence by moving a pointer to
the first bit of the 64–bit comparison register. Next, 64
consecutive write cycles are executed using the CE and
WE control of the SmartWatch. These 64 write cycles
are used only to gain access to the Phantom Clock.
Therefore, any address to the memory in the socket is
acceptable. However, the write cycles generated to
gain access to the Phantom Clock are also writing data
to a location in the mated RAM. The preferred way to
manage this requirement is to set aside just one ad-
dress location in RAM as a Phantom Clock scratch pad.
When the first write cycle is executed, it is compared to
bit 0 of the 64–bit comparison register. If a match is
found, the pointer increments to the next location of the
comparison register and awaits the next write cycle. If a
match is not found, the pointer does not advance and all
subsequent write cycles are ignored. If a read cycle oc-
curs at any time during pattern recognition, the present
sequence is aborted and the comparison register point-
er is reset. Pattern recognition continues for a total of 64
write cycles as described above until all the bits in the
comparison register have been matched (this bit pattern
is shown in Figure 1). With a correct match for 64 bits,
the Phantom Clock is enabled and data transfer to or
from the timekeeping registers can proceed. The next
64 cycles will cause the Phantom Clock to either receive
or transmit data on DQ0, depending on the level of the
OE pin or the WE pin. Cycles to other locations outside
the memory block can be interleaved with CE cycles
without interrupting the pattern recognition sequence or
data transfer sequence to the Phantom Clock.
DS1243Y
022798 3/12
PHANTOM CLOCK
REGISTER INFORMATION
The Phantom Clock information is contained in 8 regis-
ters of 8 bits, each of which is sequentially accessed one
bit at a time after the 64–bit pattern recognition se-
quence has been completed. When updating the Phan-
tom Clock registers, each register must be handled in
groups of 8 bits. Writing and reading individual bits with-
in a register could produce erroneous results. These
read/write registers are defined in Figure 2.
Data contained in the Phantom Clock register is in
binary coded decimal format (BCD). Reading and writ-
ing the registers is always accomplished by stepping
through all 8 registers, starting with bit 0 of register 0 and
ending with bit 7 of register 7.
PHANTOM CLOCK REGISTER DEFINITION Figure 1
76543210
11000101
00111010
10100011
01011100
11000101
00111010
10100011
01011100
C5
3A
A3
5C
C5
3A
A3
5C
BYTE 0
BYTE 1
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE 6
BYTE 7
HEX
VALUE
NOTE:
The pattern recognition in Hex is C5, 3A, A3, 5C, C5, 3A, A3, 5C. The odds of this pattern being accidentally dupli-
cated and causing inadvertent entry to the Phantom Clock is less than 1 in 1019. This pattern is sent to the Phantom
Clock LSB to MSB.
DS1243Y
022798 4/12
PHANTOM CLOCK REGISTER DEFINITION Figure 2
76543210
0.1 SEC 00–99
00–59
00–59
01–12
01–07
01–31
01–12
00–99
0
1
2
3
4
5
6
7
RANGE
(BCD)
REGISTER
0
0
12/24 0 10 HR
00 0
00
0 0 0 10 MONTH
10 YEAR YEAR
0.01 SEC
00–23
10 SEC SECONDS
10 MIN MINUTES
A/P HOUR
OSC RST DAY
10 DATE DATE
MONTH
AM–PM/12/24 MODE
Bit 7 of the hours register is defined as the 12– or
24–hour mode select bit. When high, the 12–hour mode
is selected. In the 12–hour mode, bit 5 is the AM/PM bit
with logic high being PM. In the 24–hour mode, bit 5 is
the second 10–hour bit (20–23 hours).
OSCILLATOR AND RESET BITS
Bits 4 and 5 of the day register are used to control the
RESET and oscillator functions. Bit 4 controls the
RESET (pin 1). When the RESET bit is set to logic 1, the
RESET input pin is ignored. When the RESET bit is set
to logic 0, a low input on the RESET pin will cause the
Phantom Clock to abort data transfer without changing
data in the watch registers. Bit 5 controls the oscillator .
When set to logic 1, the oscillator is off. When set to log-
ic 0, the oscillator turns on and the watch becomes op-
erational. These bits are shipped from the factory set to
a logic 1.
ZERO BITS
Registers 1, 2, 3, 4, 5, and 6 contain one or more bits
which will always read logic 0. When writing these loca-
tions, either a logic 1 or 0 is acceptable.
DS1243Y
022798 5/12
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground –0.3V to +7.0V
Operating Temperature 0°C to 70°C
Storage Temperature –40°C to +70°C
Soldering Temperature 260°C for 10 seconds (See Note 13)
* This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (0°C to 70°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Power Supply Voltage VCC 4.5 5.0 5.5 V
Input Logic 1 VIH 2.2 VCC+0.3 V
Input Logic 0 VIL –0.3 0.8 V
DC ELECTRICAL CHARACTERISTICS (0°C to 70°C; VCC = 5V ± 10%)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Leakage Current IIL –1.0 +1.0 µA 12
I/O Leakage Current
CE VIH VCC IIO –1.0 +1.0 µA
Output Current @ 2.4V IOH –1.0 mA
Output Current @ 0.4V IOL 2.0 mA
Standby Current CE = 2.2V ICCS1 5.0 10 mA
Standby Current CE = VCC – 0.5V ICCS2 3.0 5.0 mA
Operating Current tCYC = 200 ns ICC01 85 mA
Write Protection Voltage VTP 4.25 4.5 V
DC TEST CONDITIONS
Outputs are open; all voltages are referenced to ground.
CAPACITANCE (tA = 25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Capacitance CIN 510 pF
Input/Output Capacitance CI/O 510 pF
DS1243Y
022798 6/12
MEMORY AC ELECTRICAL CHARACTERISTICS (0°C to 70°C; VCC = 5.0V ± 10%)
PARAMETER
SYMBOL
DS1243Y–120 DS1243Y–150 DS1243Y
UNITS
NOTES
PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX UNITS NOTES
Read Cycle Time tRC 120 150 200 ns
Access Time tACC 120 150 200 ns
OE to Output Valid tOE 60 70 100 ns
CE to Output Valid tCO 120 150 200 ns
OE or CE to Output Active tCOE 5 5 5 ns 5
Output High Z from Deselection tOD 40 70 100 ns 5
Output Hold from Address
Change toH 5 5 5 ns
Write Cycle Time tWC 120 150 200 ns
Write Pulse Width tWP 90 100 150 ns 3
Address Setup T ime tAW 0 0 0 ns
Write Recovery Time tWR 20 20 20 ns
Output High Z from WE tODW 40 70 80 ns 5
Output Active from WE tOEW 5 5 5 ns 5
Data Setup T ime tDS 50 60 80 ns 4
Data Hold T ime from WE tDH 20 20 20 ns 4
AC TEST CONDITIONS
Output Load: 50 pF + 1TTL Gate
Input Pulse Levels: 0–3V
T iming Measurement Reference Levels
Input: 1.5V
Output: 1.5V
Input Pulse Rise and Fall T imes: 5 ns
DS1243Y
022798 7/12
PHANTOM CLOCK AC ELECTRICAL CHARACTERISTICS (0°C to 70°C; VCC = 4.5 to 5.5V)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Read Cycle Time tRC 120 ns
CE Access Time tCO 100 ns
OE Access Time tOE 100 ns
CE to Output Low Z tCOE 10 ns
OE to Output Low Z tOEE 10 ns
CE to Output High Z tOD 40 ns 5
OE to Output High Z tODO 40 ns 5
Read Recovery tRR 20 ns
Write Cycle Time tWC 120 ns
Write Pulse Width tWP 100 ns
Write Recovery tWR 20 ns 10
Data Setup T ime tDS 40 ns 11
Data Hold T ime tDH 10 ns 11
CE Pulse Width tCW 100 ns
RESET Pulse Width tRST 200 ns
CE High to Power–Fail tPF 0ns
POWER-DOWN/POWER-UP TIMING
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
CE at VIH before Power–Down tPD 0µs
VCC Slew from 4.5V to 0V
(CE at VIH)tF300 µs
VCC Slew from 0V to 4.5V
(CE at VIH)tR0µs
CE at VIH after Power–Up tREC 2ms
(tA = 25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Expected Data Retention Time tDR 10 years 9
WARNING:
Under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery backup mode.
DS1243Y
022798 8/12
MEMORY READ CYCLE (NOTE 1)
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
ÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌ
ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
tRC
tACC
tCO
tOE
tCOE
tCOE
tOH
tOD
tOD
OUTPUT
DATA VALID
VIL
VIH VIL
VIH VIL
VIH
VIH
VIL
VIH
VIH
VIH
VIL
VOL
VOH VOL
VOH
ADDRESSES
CE
OE
DOUT
MEMORY WRITE CYCLE 1 (NOTES 2, 6, AND 7)
ÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏ
ÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌ
tWC
tWR
VIL
VIH VIL
VIH VIL
VIH
VIL
CE
ÏÏÏÏ
ÏÏÏÏ
VIL
VIL
VIH VIL
VIH
DATA IN
STABLE
tWP
tODW tOEW
tDH
tDS
WE
ADDRESS
DQ0–DQ7
tAW
VIH VIH
HIGH IMPEDANCE
DS1243Y
022798 9/12
MEMORY WRITE CYCLE 2 (NOTES 2 AND 8)
ÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏ
ÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌ
tWC
VIL
VIH VIL
VIH VIL
VIH
VIL
CE
ÏÏÏÏ
ÏÏÏÏ
VIL
VIL
VIH VIL
VIH
DATA IN
STABLE
tWP
tCOE
tOEW
tDH
tDS
WE
ADDRESSES
DQ0–DQ7
tAW
VIH VIH
tWR
VIL VIL
tODW
WE = VIH
RESET FOR PHANTOM CLOCK
RST tRST
READ CYCLE TO PHANTOM CLOCK
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
OUTPUT DATA VALID
tRC
tCO tRR
tOD
tOE
tODO
tCOE
tOEE
CE
OE
Q
DS1243Y
022798 10/12
WRITE CYCLE TO PHANTOM CLOCK
ÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌ
ÌÌÌÌÌÌ
ÌÌÌÌÌÌ
DATA IN STABLE
tWC
tWP
tWR
tCW
tWR
tDS tDH
tDH
WE
CE
D
OE = VIH
POWER-DOWN/POWER-UP CONDITION
DATA RETENTION TIME
tDR
LEAKAGE CURRENT IL
SUPPLIED FROM LITHIUM
CELL
tREC
tPD
VCC
4.50V
3.2V
CE
4.25V
tFtR
VIH VIH VIH VIH
DS1243Y
022798 11/12
NOTES:
1. WE is high for a read cycle.
2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high impedance state.
3. tWP is specified as the logical AND of CE and WE. tWP is measured from the latter of CE or WE going low to the
earlier of CE or WE going high.
4. tDH, tDS are measured from the earlier of CE or WE going high.
5. These parameters are sampled with a 50 pF load and are not 100% tested.
6. If the CE low transition occurs simultaneously with or later than the WE low transition in Write Cycle 1, the output
buffers remain in a high impedance state during this period.
7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain
in a high impedance state during this period.
8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers
remain in a high impedance state during this period.
9. The expected tDR is defined as cumulative time in the absence of VCC with the clock oscillator running.
10.tWR is a function of the latter occurring edge of WE or CE.
11. tDH and tDS are a function of the first occurring edge of WE or CE.
12.RST (Pin1) has an internal pull–up resistor.
13.Real–Time Clock Modules can be successfully processed through conventional wave–soldering techniques as
long as temperature exposure to the lithium energy source contained within does not exceed +85°C. Post solder
cleaning with water washing techniques is acceptable, provided that ultrasonic vibration is not used.
DS1243Y
022798 12/12
DS1243Y 28–PIN EXTENDED BOTTOM 720 MIL BODY WIDTH (DIMENSION B)
A
1
DIM MIN MAX
A IN.
MM
B IN.
MM
C IN.
MM
D IN.
MM
E IN.
MM
F IN.
MM
G IN.
MM
H IN.
MM
J IN.
MM
K IN.
MM
1.520
38.61 1.540
39.12
0.695
17.65 0.720
18.29
0.395
10.03 0.415
10.54
0.100
2.54 0.130
3.30
0.017
0.43 0.030
0.76
0.120
3.05 0.160
4.06
0.090
2.29 0.110
2.79
0.590
14.99 0.630
16.00
0.008
0.20 0.012
0.30
0.015
0.38 0.021
0.53
C
F
GKD
H
B
E
J
28–PINPKG