TECHNICAL DATA IW4027B Dual JK Flip-Flop High-Voltage Silicon-Gate CMOS The IW4027B is a Dual JK Flip-Flop which is edge-triggered and features independent Set, Reset, and Clock inputs. Data is accepted when the Clock is LOW and transferred to the output on the positivegoing edge of the Clock. The active HIGH asynchronous Reset and Set are independent and override the J, K, or Clock inputs. The outputs are buffered for best system performance. * Operating Voltage Range: 3.0 to 18 V * Maximum input current of 1 A at 18 V over full packagetemperature range; 100 nA at 18 V and 25C * Noise margin (over full package temperature range): 1.0 V min @ 5.0 V supply 2.0 V min @ 10.0 V supply 2.5 V min @ 15.0 V supply ORDERING INFORMATION IW4027BN Plastic IW4027BD SOIC TA = -55 to 125 C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs Set Reset Clock PIN 16 =VCC PIN 8 = GND Outputs J K Qn+1 Qn+1 L H X X X L H H L X X X H L H H X X X H H L L L L L L H L H L L L L H L H L L H H Qn Qn No change X = don't care Qn+1 = State After Clock Positive Transition 19 IW4027B MAXIMUM RATINGS* Symbol Parameter Value Unit -0.5 to +20 V VCC DC Supply Voltage (Referenced to GND) VIN DC Input Voltage (Referenced to GND) -0.5 to VCC +0.5 V DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V VOUT IIN DC Input Current, per Pin 10 mA PD Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ 750 500 mW PD Power Dissipation per Output Transistor 100 mW -65 to +150 C 260 C Tstg TL Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Min Max Unit 3.0 18 V 0 VCC V -55 +125 C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 20 IW4027B DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) VCC Guaranteed Limit V -55C 25C 125 C Unit VOUT=0.5 V or VCC - 0.5 V VOUT=1.0 V or VCC - 1.0 V VOUT=1.5 V or VCC - 1.5 V 5.0 10 15 3.5 7 11 3.5 7 11 3.5 7 11 V VIL Maximum Low -Level VOUT=0.5 V or VCC - 0.5 V Input Voltage VOUT=1.0 V or VCC - 1.0 V VOUT=1.5 V or VCC - 1.5 V 5.0 10 15 1.5 3 4 1.5 3 4 1.5 3 4 V VOH Minimum High-Level Output Voltage VIN=GND or VCC 5.0 10 15 4.95 9.95 14.95 4.95 9.95 14.95 4.95 9.95 14.95 V VOL Maximum Low-Level Output Voltage VIN=GND or VCC 5.0 10 15 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 V IIN Maximum Input Leakage Current VIN= GND or VCC 18 0.1 0.1 1.0 A ICC Maximum Quiescent Supply Current (per Package) VIN= GND or VCC 5.0 10 15 20 1.0 2.0 4.0 20 1.0 2.0 4.0 20 30 60 120 600 A IOL Minimum Output Low VIN= GND or VCC (Sink) Current VOL=0.4 V VOL=0.5 V VOL=1.5 V 5.0 10 15 0.64 1.6 4.2 0.51 1.3 3.4 0.36 0.9 2.4 Minimum Output VIN= GND or VCC High (Source) Current VOH=4.6 V VOH=2.5 V VOH=9.5 V VOH=13.5 V 5.0 5.0 10 15 -0.64 -2.0 -1.8 -4.2 -0.51 -1.6 -1.3 -3.4 -0.36 -1.15 -0.9 -2.4 Symbol Parameter VIH Minimum High-Level Input Voltage IOH Test Conditions mA mA 21 IW4027B AC ELECTRICAL CHARACTERISTICS(CL=50pF, RL=200 k, Input tr=tf=20 ns) Guaranteed Limit VCC V -55C 25C 125C Unit Maximum Clock Frequency 5.0 10 15 3.5 8 12 3.5 8 12 1.75 4 6 MHz tPLH, tPHL Maximum Propagation Delay, Clock to Q or Q 5.0 10 15 300 130 90 300 130 90 600 260 180 ns tPLH Maximum Propagation Delay, Set to Q or Reset to Q 5.0 10 15 300 130 90 300 130 90 600 260 180 ns tPHL Maximum Propagation Delay, Set to Q or Reset to Q 5.0 10 15 400 170 120 400 170 120 800 340 240 ns tTLH, tTHL Maximum Output Transition Time, Any Output 5.0 10 15 200 100 80 200 100 80 400 200 160 ns Symbol fmax CIN Parameter Maximum Input Capacitance - 7.5 pF TIMING REQUIREMENTS(CL=50pF, RL=200 k, Input tr=tf=20 ns) Guaranteed Limit VCC Parameter V -55C 25C 125C Unit tw Minimum Pulse Width, Clock 5.0 10 15 140 60 40 140 60 40 280 120 80 ns tw Minimum Pulse Width, Set or Reset 5.0 10 15 180 80 50 180 80 50 360 160 100 ns tsu Minimum Setup Time 5.0 10 15 200 75 50 200 75 50 400 150 100 ns Maximum Input Rise or Fall Time, Clock 5.0 10 15 45 5 2 45 5 2 90 10 4 s Symbol tr, tf 22