TECHNICAL DATA
19
Dual JK Flip-Flop
High-Voltage Silicon-Gate CMOS
The IW4027B is a Dual JK Flip-Flop which is edge-triggered and
features independent Set, Reset, and Clock inputs. Data is accepted
when the Clock is LOW and transferred to the output on the positive-
going edge of the Clock. The active HIGH asynchronous Reset and Set
are independent and override the J, K, or Clock inputs. The outputs are
buffered for best system performance.
• Operating Voltage Range: 3.0 to 18 V
• Maximum input current of 1 µA at 18 V over full package-
temperature range; 100 nA at 18 V and 25°C
• Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
IW4027B
ORDERING INFORMATION
IW4027BN Plastic
IW4027BD SOIC
TA = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN 16 =VCC
PIN 8 = GND
PIN ASSIGNMENT
FUNCTION TABLE
Inputs Outputs
Set Reset Clock J K Qn+1 Qn+1
LHXXXLH
HLXXXHL
HHXXXHH
L L L L No change
LL HLHL
LL LHLH
L L H H Qn Qn
X = don’t care
Qn+1 = State After Clock Positive Transition
IW4027B
20
MAXIMUM RATINGS*
Symbol Parameter Value Unit
VCC DC Supply Voltage (Referenced to GND) -0.5 to +20 V
VIN DC Input Voltage (Referenced to GND) -0.5 to VCC +0.5 V
VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
IIN DC Input Current, per Pin ±10 mA
PDPower Dissipation in Still Air, Plastic DIP+
SOIC Package+ 750
500 mW
PDPower Dissipation per Output Transistor 100 mW
Tstg Storage Temperature -65 to +150 °C
TLLead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package) 260 °C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 3.0 18 V
VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
TAOperating Temperature, All Package Types -55 +125 °C
Thi s device contains p rote ction c ircuitr y to guard a gainst damage due to hi gh static voltage s or electr ic
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range
GND≤(VIN or VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.
IW4027B
21
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
VCC Guaranteed Limit
Symbol Parameter Test Conditions V ≥-55°C25
°C≤125
°CUnit
VIH Minimum High-Level
Input Voltage VOUT=0.5 V or VCC - 0.5 V
VOUT=1.0 V or VCC - 1.0 V
VOUT=1.5 V or VCC - 1.5 V
5.0
10
15
3.5
7
11
3.5
7
11
3.5
7
11
V
VIL Maximum Low -Level
Input Voltage VOUT=0.5 V or VCC - 0.5 V
VOUT=1.0 V or VCC - 1.0 V
VOUT=1.5 V or VCC - 1.5 V
5.0
10
15
1.5
3
4
1.5
3
4
1.5
3
4
V
VOH Minimum High-Level
Output Voltage VIN=GND or VCC 5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
4.95
9.95
14.95
V
VOL Maximum Low-Level
Output Voltage VIN=GND or VCC 5.0
10
15
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
V
IIN Max imum Inp ut
Leakage Current VIN= GND or VCC 18 ±0.1 ±0.1 ±1.0 µA
ICC Max imum Quiescent
Supply Current
(per Package)
VIN= GND or VCC 5.0
10
15
20
1.0
2.0
4.0
20
1.0
2.0
4.0
20
30
60
120
600
µA
IOL Minimu m Ou tput Low
(Sink) Current VIN= GND or VCC
VOL=0.4 V
VOL=0.5 V
VOL=1.5 V
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.36
0.9
2.4
mA
IOH Minimu m Ou tput
High (Source) Current VIN= GND or VCC
VOH=4.6 V
VOH=2.5 V
VOH=9.5 V
VOH=13.5 V
5.0
5.0
10
15
-0.64
–2.0
–1.8
–4.2
-0.51
–1.6
–1.3
–3.4
-0.36
–1.15
–0.9
–2.4
mA
IW4027B
22
AC ELECTRICAL CHARACTERISTICS(CL=50pF, RL=200 kΩ, Input tr=tf=20 ns)
VCC Guaranteed Limit
Symbol Parameter V ≥-55°C25
°C≤125°CUnit
fmax Maximum Clock Fr equenc y 5.0
10
15
3.5
8
12
3.5
8
12
1.75
4
6
MHz
tPLH, tPHL Maximum Prop agation Delay, Clock t o Q or Q 5.0
10
15
300
130
90
300
130
90
600
260
180
ns
tPLH Maximum Propagation Delay, Set to Q or Reset
to Q 5.0
10
15
300
130
90
300
130
90
600
260
180
ns
tPHL Maximum Propagation Delay, Set to Q or Reset
to Q 5.0
10
15
400
170
120
400
170
120
800
340
240
ns
tTLH, tTHL Maximum Output Transition Time, Any Output 5.0
10
15
200
100
80
200
100
80
400
200
160
ns
CIN Maximum Input Capacitance - 7.5 pF
TIMING REQUIREMENTS(CL=50pF, RL=200 kΩ, Input tr=tf=20 ns)
VCC Guaranteed Limit
Symbol Parameter V ≥-55°C25
°C≤125°CUnit
twMinimum Pul se Width, Clock 5.0
10
15
140
60
40
140
60
40
280
120
80
ns
twMinimum Pul se Width, S et o r Re set 5.0
10
15
180
80
50
180
80
50
360
160
100
ns
tsu Minimum Setup Ti me 5.0
10
15
200
75
50
200
75
50
400
150
100
ns
tr, tfMaximum Inp ut Rise or Fall Time , Clock 5.0
10
15
45
5
2
45
5
2
90
10
4
µs
