Rev. 1.0 July 2014 www.aosmd.com Page 1 of 13
AOZ1363DI
16V High Current Load Switch with Rapid Turn-Off
and Current Monitoring Protection
General Description
The AOZ1363DI is a high-side load switch intended for
applications that require circuit protection. The device
operates from voltages between 5V and 16V, and
capable of supplying 6A of continuous current. The
internal current limiting circuit protects the input supply
voltage from large load current. The AOZ1363DI
provides thermal protection function that limits excessive
power dissipation. The device employs an externally
programmable soft-start circuitry to control inrush current
due to highly capacitive loads associated with hot-plug
events. It features low quiescent current of 400µA and
the supply current reduces to less than 10µA in
shutdown.
The device can output current monitoring information
with an accuracy of 10% at a specified load current of 3A.
The device can detect the over-current fault condition
and execute the switch power down within a maximum
delay time of 100ns. It features an input overvoltage
protection where the device powers down when the
power input voltage exceeds 19V.
The AOZ1363DI is available in a 3mm x 3mm DFN-12L
package and can operate over -40 C to +85 C
temperature range.
Features
5V to 16V operating input voltage
40m maximum on resistance
Fast 100ns switch turn off time during OCP
Current monitoring with 10% accuracy (3A)
Externally programmable soft-start
Low quiescent current
Under-voltage lockout
Thermal shutdown protection
Input over-voltage protection
2.0kV ESD rating
Small 3mm x 3mm DFN-12L package
Applications
Notebook PCs
Hot swap supplies
Micro-servers
Typical Application
AOZ1363DI
EN
VCC
GND
FLT_B
IN
NC
OUT
OUT
OUT
NC
ISEN
SS
1
2
3
4
5
6
12
11
10
9
8
7
C3
0.47nF
C4
0.3nF
ONOFF 12V Output
VIN
C2
4.7μF
Rsen
R2
100k
5V
12V Input
C1
100μF
Figure 1. Typial Application Circuit (with Current Monitoring)
AOZ1363DI
Rev. 1.0 July 2014 www.aosmd.com Page 2 of 13
Ordering Information
AOS Green Products use reduced levels of Halogens, and are also RoHS compliant.
Please visit www.aosmd.com/media/AOSGreenPolicy.pdf for additional information.
Pin Configuration
Pin Description
Part Number Ambient Temperature Range Package Environmental
AOZ1363DI -40°C to +85°C 3mm x 3mm DFN-12L RoHS Compliant
Pin Number Pin Name Pin Function
1 EN Enable Input. Active high. For automatic enabling, this pin is highly recommended to
connect to VCC.
2 VCC VCC is a bypass pin. Connect a 0.47nF capacitor from VCC to GND.
3 GND Ground.
4 FLT_B Fault Output pin. This is an open drain output that is externally pulled high with a
pull-up resistor. Drain is internally pulled down to GND to indicate a fault condition.
Connect to 5V, 3.3V, or VCC through a 100k pull-up resistor.
5, EPAD IN N-channel MOSFET Drain. Connect a 100µF capacitor from IN to GND
6, 9 NC No Connection.
7 SS Externally Programmable Soft-Start pin.
8 ISEN Current Sense Information Output. See Figure 3 for Rsen value.
10, 11, 12 OUT N-channel MOSFET Source. Connect a 4.7µF capacitor from OUT to GND.
3mm x 3mm DFN-12L
(Top View)
EN
VCC
NC SS
OUT
1
2
4
7
11
FLT_B
3
OUT
10
NC
9
6
IN ISEN
85
12
GND OUT
IN
AOZ1363DI
Rev. 1.0 July 2014 www.aosmd.com Page 3 of 13
Absolute Maximum Ratings
Exceeding the Absolute Maximum ratings may damage th e
device.
Maximum Operating Ratings
The device is not guaranteed to operate beyond the Maximum
Operating Ratings.
Parameter Rating
IN, OUT, ISEN to GND -0.3V to +24V
VCC, EN, SS, FLAG -0.3V to 6V
Maximum Continuous Current 6A (25°C)
Maximum Junction Temperature (TJ) +150°C
ESD Rating (HBM) 2.0kV
Parameter Rating
Thermal Resistance (DFN 3x3) 40°C/W
Electrical Characteristics
VIN = 12V, TA = 25°C unless otherwise stated.
Note: 1. Guaranteed by design.
Symbol Parameter Conditions Min. Typ. Max Units
VIN Input Supply Voltage 5 16 V
VUVLO Undervoltage Lockout Threshold IN rising 4.1 4.4 V
VUVHYS Undervoltage Lockout Hysteresis 400 mV
VUVP Input Overvoltage Protection IN rising 19 V
VUVHYS Input Overvoltage Protection Hysteresis 1.5 V
IIN_ON Input Quiescent Current EN = 4V, no load 400 600 µA
IIN_OFF Input Shutdown Current EN = GND, no load 10 µA
ILEAK Output Leakage Current EN = GND, no load 10 µA
RDS(ON) Switch On Resistance VIN= 12V 23 40 mΩ
ILIM Current Limit -25% 11 +25% A
IOFF Offset Current in ISEN IIN = 0A 2 µA
AIF Current Monitor Gain IIN = 1A~6A 5 µA/A
IMON Current Monitor Accuracy IIN = 3A 10 %
VLOW Fault Low Voltage IFLT = 1mA 0.5 V
ILK_FLT Fault Leakage Current 1µA
tFLT Fault Flag Delay Time 100 ns
tSS Soft-Start Time CSS = 300pF 100 µs
VEN_L Enable Input Low Voltage 0.8 V
VEN_H Enable Input High Voltage 2 V
VEN_HYS Enable Input Hysteresis 100 mV
IEN_BIAS Enable Input Bias Current 1µA
Td_on Turn-On Delay Time
EN_50% to OUT_10%
RL = 120Ω, CL = 1µF 220 µs
tON Turn-On Rise Time
OUT_10% to 90%
RL=120Ω, CL = 1µF 160 µs
TSD Thermal Shutdown Threshold 130 °C
TSD_HYS Thermal Shutdown Hysteresis 30 °C
TCL Current Limit Detection Delay 50(1) ns
TFDP N-Channel Turn Off Delay 50(1) ns
AOZ1363DI
Rev. 1.0 July 2014 www.aosmd.com Page 4 of 13
Figure 2. Over Current Limit Timing Diagram
Figure 3. Current Monitoring and Reverse Current
CURRENT LIMIT SET
DIFFERENTIAL SENSED
VOLTAGE
FAULT DETECTION (OCP)
INTERNALLY PULLED-DOWN
ON STATE OFF STATE
FLT_B
MAIN SWITCH GATE
(NOT PIN OUT)
MAIN SWITCH
(NOT PIN OUT)
OUT
tD(ON) tr
10%
90% 90%
10%
100ns
(85°C)
tCL tFPD
50ns
10ns
40ns
V(ISEN)
VOFF(=0.2V)
I(OCP)
= 9A
VOCP(~4.7V)
IIN
0
OCP
6A
3.2V
FLAG
V(ISEN) = (AIF * IDC + IOFF) * RSEN
V(ISEN) = (5µA/A * 6A + 2µA) * 100kΩ = 3.2V
RSEN = 100kΩ
Rev. 1.0 July 2014 www.aosmd.com Page 5 of 13
AOZ1363DI
Protection Table
Protection Diagram
Functional Block Diagram
Fault Condition LSW Position Fault Flag System State Comparator Add-on
UVLO (falling) Open Low Stand-by Hysteresis + Deglitch
OCP Open Low Latch-off Deglitch
OTP Open Low Stand-by Hysteresis
EN (low) Open H-Z Shutdown Deglitch
IN
19V
EN
UVLO
VCC
4V
IIN
FLT_B
3.5V
11A
3.9V
Latch-off
OVP OCP UVLO Shutdown
OUT
4.5V
Charge
Pump
Fault Detect
& Latch
OTP
(Temp>130
o
C)
Soft
Start
CSA
UVLO
VCL
Internal
Regulator
C4
0.3nF
IN OUT
ISEN
FLT_B
EN
SS
GND
12V Input
C1
100µF
C2
4.7µF
R2
100k
Rsen
Output
Current
Information
5V
Fault Flag
(Active Low)
Enable
M1
M2
3.9V
OCP
(I
IN
>11A)
VCC(4V)
OSC
Ioff
Vbias
Fast
Turn-off
VCC
C3
0.47nF
IN
OVP
(V
IN
>19V)
UVLO
(V
IN
<3.5V)
Fault Detect
& Recover
Slow
Turn-off
Rev. 1.0 July 2014 www.aosmd.com Page 6 of 13
AOZ1363DI
Functional Characteristics
Fast Output Shutdown During
Current Limit Response
(V
IN
=12V, R
L
=2Ω, C1=100µF, C2=4.7µF)
VIN/VOUT
2V/div
IOUT
2A/div
IOUT
2A/div
FLT_B
1V/div
Current Limit Response: Latch OFF
(V
IN
=12V, R
L
=2Ω, C1=100µF, C2=4.7µF)
VIN/VOUT
2V/div
VIN
VOUT Falling
IOUT Limit Trip Point: 10.5A
50ns
IOUT Limit: 10.5A
FLT_B
1V/div
100ns/div 500µs/div
Turn ON Sequence
(V
IN
=12V, R
L
=2Ω, C1=100µF, C2=4.7µF)
Turn OFF Sequence
(V
IN
=12V, R
L
=2Ω, C1=100µF, C2=4.7µF)
VIN
2V/div
VOUT
2V/div
EN
1V/div
IOUT
1A/div
50µs/div
VIN
2V/div
VOUT
2V/div
EN
1V/div
IOUT
1A/div
5µs/div
Rev. 1.0 July 2014 www.aosmd.com Page 7 of 13
AOZ1363DI
Typical Characteristics
9585
RDSON vs. Temperature
35
34
33
32
31
30
29
28
27
26
25
24 55 65 7545
Ambient Temperature (°C)
N-Channel RDSON A(mΩ)
12525 35 115105
6.5
Ambient Temperature vs. Current
120
110
100
90
80
70
60
50
40 5.5 6.05.0
DC Current (A)
Temperature (°C)
8.04.0 4.5 7.57.09585
Current Limit vs. Temperature
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0 55 65 7545
Temperature (°C)
Current Limit Level (A)
12525 35 115105
Input Shutdown Current vs. Input Voltage
4.8
4.4
4.0
3.6
3.2
2.8
2.4
2.0
Shutdown Current (μA)
9
Input Quiescent Current vs. Input Voltage
620
580
540
500
460
420
380
340
300 87
Input Voltage (V)
Supply Current (μA)
1256 1110
Input Voltage (V)
9871256 1110
AOZ1363DI
Rev. 1.0 July 2014 www.aosmd.com Page 8 of 13
Application Information
Parallel Load Switch Configuration
Figure 4. Parallel Configuration Application Schematic
The AOZ1363DI fast load switch can also be parallel
configured in applications that require efficiency
optimization. Overall conduction losses during the ON
cycle can be reduced in half by mounting two load
switches, as shown above. The EN pins can be tied
together and a common rising edge signal enables both
devices simultaneously. Each load switch device must
have a 470pF surface mounted ceramic capacitor across
VCC and GND (pin 2 and pin 3) – see PCB floor plan in
the Layout Guidelines. The VCC pin then connected
together onto a common 5V VCC rail. A 100k resistor
tied between each of the devices’ VCC pin and FLT_B
pin for user flag function. Both FLT_B pins will be tied
together to a single trace for easy user access. Each
device will employ its own pair of 47µF capacitor next to
the IN (pin 5 and EP) and PGND. Both VIN pins will be
tied together through a wide track, connecting to the 12V
supply rail.
The SS cap of 330pF will be mounted next to each
device’s SS pin and each respective GND. Both SS pins
will be tied to a common trace on the PCB. The ISEN
resistor should be configured such that the typical value
ISEN resistor, Rsen = 100k will be divided by the same
amount of AOZ1363DI devices used.
A 4.7µF capacitor will be mounted between the Output
(pins 10,11 and 12) and EP of each AOZ1363DI load
switch. All output pins of load switch devices will be tied
together through a wide track on the top layer for
optimize cooling. This common Output track will lead to
the Load downstream.
The same techniques and methodology previously
explained should be applied to any Multi-Load Switch
parallel configuration. Layout techniques for multi-load
switch topology should be referenced to the
Recommended Layout Guidelines section.
Short Protection
AOZ1363 has the protection function against the
destructive output short current thanks to the ultra fast
turn-off feature as long as the short phenomenon takes
place in the upper switch of the totem pole. In Figure 5A,
when the short phenomenon happens in the upper
MOSFET(M2) of the totem pole type load the excessive
short current starts ramping up speedily but since
AOZ1363 can detect it, turn off MOSFET quickly within
100ns and flag the fault signal to main controller the
whole system can is protected safely.
However, in case the output is short to the GND like
Figure 5B, AOZ1363 needs a diode(D1) between OUT
and GND to clamp the excessive negative voltage in the
output due to parasitic inductance.
The C1 and C2 capacitor should be located in nearest
point to IN and OUT each other and the C2 should be
lower than 4.7µF for the fast short detection.
Figure 5A. Application Against Totem Pole Load Short
Figure 5B. Application Against Load Rail Short to Ground
AOZ1363DI
M1
C1 C2
OUT
IN
GND
OFF
Load
Short
D1
U1 AOZ1363DI
EN
VCC
GND
FLT_B
IN
NC
OUT
OUT
OUT
NC
ISEN
SS
1
2
3
4
5
6
12
11
10
9
8
7
C3
470pF
C4
330pF
12V Output
ISEN
C2
4.7μF
Rsen/2
ONOFF
R2
100k
5V Input
12V Input
C1
47μF
EP
R3 1M
C5
47μF R4
0Ω
D1
DPAK
EN
VCC
VIN
U2 AOZ1363DI
EN
VCC
GND
FLT_B
IN
NC
OUT
OUT
OUT
NC
ISEN
SS
1
2
3
4
5
6
12
11
10
9
8
7
C3
470pF
C4
330pF
C2
4.7μF
R2
100k
C1
47μF
EP
C5
47μF R4
0Ω
FLT_B
D2
DPAK
AOZ1363DI
M1
M2
M3
C1 C2
OUT
IN
GND
L1
C3
Totem pole
type load
M2 Short
OFF
PWM
Rev. 1.0 July 2014 www.aosmd.com Page 9 of 13
AOZ1363DI
Recommended Bill of Materials
Component Value Description / Rating Vendor Part #
U1 -- -- Alpha Omega AOZ1363DI
C1, C5 4.7µF CAP CER 47UF 16V 20% X5R 1210 Taiyo Yuden EMK325BJ476MM-T
C2 4.7µF CAP CER 4.7UF 50V 10% X5R 1206 Taiyo Yuden UMK316BJ475KL-T
C3 470pF CAP CER 470PF 50V 10% X7R 0603 Murata Elec. GRM188R71H471KA01J
C4 330pF CAP CER 330PF 50V 10% X7R 0603 Murata Elec. GRM188R71H331KA0ID
RSEN 100k1/10W 1% JUMP 0603 SMD Panasonic (ECG) ERJ-3GEYJ104V
R2 100k1/10W 1% JUMP 0603 SMD Panasonic (ECG) ERJ-3GEYJ104V
R3 1M1/10W 1% JUMP 0603 SMD Yaged RC0603FR-071ML
R4 01/10W 1% JUMP 0603 SMD Yaged RC0603JR-070RL
D1 CQ714 CQ 5D CQ714 B2535G AKA CQ714B2535G
U1 AOZ1363DI
EN
VCC
GND
FLT_B
IN
NC
OUT
OUT
OUT
NC
ISEN
SS
1
2
3
4
5
6
12
11
10
9
8
7
C3
470pF
C4
330pF
12V Output
VIN
C2
4.7μF
Rsen
ONOFF
R2
100k
5V
12V Input
C1
47μF
EP
R3 1M
C5
47μF R4
0Ω
D1
DPAK
AOZ1363DI
Rev. 1.0 July 2014 www.aosmd.com Page 10 of 13
Recommended Layout Guidelines
The AOZ1363DI load switch is a device that is capable of
delivering a steady flow of DC current. It provides up to
6A of continuous current into two DrMos modules for
step-down conversion in continuous conduction mode.
The floor plan in Figure 6 is focused on providing the IN
(pin 5 and exposed pad) and the OUT (pins 10,11 and
12) with plenty of top layer exposed copper for thermal
relief, thus, transferring most of the power dissipated as
heat down to the PCB. The top layer layout diagram in
Figure 6 shows an optimal method for cooling.
Furthermore, the input bypass capacitors CIN1 and CIN2
are surface mounted ceramic capacitors mounted
directly to the exposed VIN paddle. The 4.7µF MLCC
should be located as close as physically possible to the
output pins 10-12 with return path star power grounded
with the input capacitors. The AOZ1363DI employs an
extremely fast 100ns turn off mechanism during an over-
current event. When the DC current through the large
internal NMOS switch exceeds its maximum threshold of
11.2A at 25°C, a fast gate discharging circuit is deployed
causing the output to decay to zero. The layout
configuration of Figure 6 enables the fast discharging of
the 4.7µF output capacitor very effectively through the
load downstream.
Please note the GND (upside down triangle) and PGND
(earth ground) symbols in Figure 7. The PGND symbols
should only be connected to the Input and Output
capacitors and nowhere else. All GND symbols should
be used for the rest of the external components including
the IC’s pin 3. All GND connections should be star
grounded together separate from the PGND connections.
Bottom layer has been allocated for PGND use only so
the Input and the Output capacitors are directly tied to the
bottom layer through via connectors. Only a single point
will be used to connect both AGND and PGND for
optimal noise isolation. Please refer to Figure 6 for R4
valued at 0.
All Input (pin 5 and Exposed Pad) and Output (pins 10,
11 and 12) traces should be at top layer for optimal trace
resistances. Current going through vias is not
acceptable. Traces on top layer may be duplicated to the
second layer (bottom layer) and via connecting both the
top and bottom traces as near as possible to the IC
region is advisable to provide thermal relief.
All of the above details must be applied when considering
to implement a multi–device parallel configuration (2 or 3
devices).
Figure 7. Top Layer Floor Plan
Figure 8. Bottom Layer Floor Plan
R4 (0Ω) is the only point to
connect AGND and PGND together
Allcocated area for
Current Sense Information
Allcocated area for
thermal sensing point
Wide VIN track for
thermal sensing location
AOZ1363DI
Rev. 1.0 July 2014 www.aosmd.com Page 11 of 13
Package Dimensions, DFN 3x3, 12L
AOZ1363DI
Rev. 1.0 July 2014 www.aosmd.com Page 12 of 13
Tape and Reel Dimensions, DFN 3x3, 12L
Carrier Tape
Reel
Leader / Trailer & Orientation
Tape Size
12mm
Reel Size
ø330
M
ø330.00
±0.50
Package
DFN 3x3_EP
A0
3.40
±0.10
B0
3.35
±0.10
K0
1.10
±0.10
D1
1.50
+0.10/-0.0
D0
1.50
+0.10/-0.0
E
12.00
E1
1.75
±0.10
±0.30
E2
5.50
±0.05
P0
8.00
±0.10
P1
4.00
±0.10
P2
2.00
±0.05
T
0.30
±0.05
N
ø97.00
±0.10
W
13.00
±±0.30
W1
M
S
K
H
N
Trailer Tape
300mm Min.
Components Tape
Orientation in Pocket
Leader Tape
500mm Min.
UNIT: mm
UNIT: mm
K0
P1
P0 A0
A
B0
P2
E
E2
E1
D0 D1
Feeding Direction
W1
17.40
1.00
H
ø13.00
+0.5/-0.2
K
10.60
±0.50
S
2.00
GR
N/AN/A
V
N/A
T
W
Unit Per Reel:
5000pcs
A–A
A
R
G
V
AOZ1363DI
Rev. 1.0 July 2014 www.aosmd.com Page 13 of 13
Part Marking
AOZ1363DI
(DFN3x3-12)
Assembly Lot Code
Part Number Code
Industrial Temperature
Range
Year & Week Code
Assembly Location Code
1363
I0AW
LT
NoOption
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of
the user.
2. A critical component in any component of a life
support, device, or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
LEGAL DISCLA IM ER
Alpha and Omega Semiconductor makes no representations or warranties with respect to the accuracy or
completeness of the information provided herein and takes no liabilities for the consequences of use of such
information or any product described herein. Alpha and Omega Semiconductor reserves the right to make changes
to such information at any time without further notice. This document does not constitute the grant of any intellectual
property rights or representation of non-infringement of any third party’s intellectual property rights.
LIFE SUPPORT POLICY
ALPHA AND OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.