LTC3862IFE-1#TRPBF - Linear Technology

LTC3862-1

38621f

TYPICAL APPLICATION

FEATURES

APPLICATIONS

DESCRIPTION

Multi-Phase Current Mode

Step-Up DC/DC Controller

The LTC

3862-1 is a two phase constant frequency, current

mode boost and SEPIC controller that drives N-channel

power MOSFETs. Two phase operation reduces system

ﬁ ltering capacitance and inductance requirements. The 10V

gate drive is optimized for most automotive and industrial

grade power MOSFETs.

Adjustable slope compensation gain allows the user to ﬁ ne-

tune the current loop gain, improving noise immunity.

The operating frequency can be set with an external resistor

over a 75kHz to 500kHz range and can be synchronized

to an external clock using the internal PLL. Multi-phase

operation is possible using the SYNC input, the CLKOUT

output and the PHASEMODE control pin allowing 2-, 3-,

4-, 6- or 12-phase operation.

Other features include an internal 10V LDO with

undervoltage lockout protection for the gate drivers, a

precision RUN pin threshold with programmable hyster-

esis, soft-start and programmable leading edge blanking

and maximum duty cycle. The LTC3862 is a 5V gate drive

version of the LTC3862-1.

n Wide VIN Range: 8.5V to 36V Operation

n 2-Phase Operation Reduces Input and Output

Capacitance

n Fixed Frequency, Peak Current Mode Control

n 10V Gate Drive for High Voltage MOSFETs

n Adjustable Slope Compensation Gain

n Adjustable Max Duty Cycle (Up to 96%)

n Adjustable Leading Edge Blanking

n ±1% Internal Voltage Reference

n Programmable Operating Frequency with One

External Resistor (75kHz to 500kHz)

n Phase-Lockable Fixed Frequency 50kHz to 650kHz

n SYNC Input and CLKOUT for 2-, 3-, 4-, 6- or

12-Phase Operation (PHASEMODE Programmable)

n Internal 10V LDO Regulator

n 24-Lead Narrow SSOP Package

n 5mm × 5mm QFN Package with 0.65mm Lead Pitch

n 24-Lead Thermally Enhanced TSSOP Package

n Automotive, Telecom and Industrial Power Supplies L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners. Protected by U.S. Patents,

including 6144194, 6498466, 6611131.

Efﬁ ciency vs Output Current

LOAD CURRENT (mA)

EFFICIENCY (%)

38621 TA01b

100

100 1000 10000

VIN = 32V

VOUT = 72V

VIN = 24V

VIN = 9V

VIN

LTC3862-1

SGND

GATE1

SENSE1+

RUN

150k

24.9k

45.3k

324k 5.62k 45.3k 100pF

0.020

56µH 56µH

22µF

50V

110µF

100V

0.1µF

1nF

1.5nF

4.7µF

INTVCC

3V8

ITH

VOUT

72V

2A (MAX)

38621 TA01a

VIN

8.5V TO 36V

BLANK

FREQ

SYNC

PLLFLTR

SENSE1–

GATE2

SENSE2+

SENSE2–

PGND

CLKOUT

SLOPE

DMAX

PHASEMODE

LTC3862-1

38621f

ABSOLUTE MAXIMUM RATINGS

Input Supply Voltage (VIN) ......................... –0.3V to 40V

INTVCC Voltage .......................................... –0.3V to 11V

INTVCC LDO RMS Output Current .........................50mA

RUN Voltage ................................................ –0.3V to 8V

SYNC Voltage ............................................... –0.3V to 6V

SLOPE, PHASEMODE, DMAX,

BLANK Voltage ........................................... –0.3V to 3V8

SENSE1+, SENSE1–, SENSE2+,

SENSE2– Voltage ....................................... –0.3V to 3V8

(Notes 1, 2)

TOP VIEW

FE PACKAGE

24-LEAD PLASTIC TSSOP

DMAX

SLOPE

BLANK

PHASEMODE

FREQ

ITH

SGND

CLKOUT

SYNC

PLLFLTR

3V8

SENSE1+

SENSE1–

RUN

VIN

INTVCC

GATE1

PGND

GATE2

SENSE2–

SENSE2+

TJMAX = 150°C, θJA = 38°C/W

EXPOSED PAD (PIN 25) IS PGND, MUST BE SOLDERED TO PCB

TOP VIEW

GN PACKAGE

24-LEAD NARROW PLASTIC SSOP

DMAX

SLOPE

BLANK

PHASEMODE

FREQ

ITH

SGND

CLKOUT

SYNC

PLLFLTR

3V8

SENSE1+

SENSE1–

RUN

VIN

INTVCC

GATE1

PGND

GATE2

SENSE2–

SENSE2+

TJMAX = 150°C, θJA = 85°C/W

24 23 22 21 20 19

7 8 9

TOP VIEW

UH PACKAGE

24-LEAD (5mm s 5mm) PLASTIC QFN

10 11 12

18BLANK

PHASEMODE

FREQ

ITH

VIN

INTVCC

GATE1

PGND

GATE2

SLOPE

DMAX

3V8

SENSE1+

SENSE1–

RUN

SGND

CLKOUT

SYNC

PLLFLTR

SENSE2+

SENSE2–

TJMAX = 150°C, θJA = 34°C/W

EXPOSED PAD (PIN 25) IS PGND, MUST BE SOLDERED TO PCB

PIN CONFIGURATION

SS, PLLFLTR Voltage ................................. –0.3V to 3V8

ITH Voltage ............................................... –0.3V to 2.7V

FB Voltage .................................................. –0.3V to 3V8

FREQ Voltage ............................................ –0.3V to 1.5V

Operating Junction Temperature Range (Notes 3, 4)

LTC3862-1E ......................................... –40°C to 85°C

LTC3862-1I ........................................ –40°C to 125°C

LTC3862-1H ....................................... –40°C to 150°C

Storage Temperature Range ................... –65°C to 150°C

Reﬂ ow Peak Body Temperature ........................... 260°C

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC3862EFE-1#PBF LTC3862EFE-1#TRPBF LTC3862FE-1 24-Lead Plastic TSSOP –40°C to 85°C

LTC3862IFE-1#PBF LTC3862IFE-1#TRPBF LTC3862FE-1 24-Lead Plastic TSSOP –40°C to 125°C

LTC3862HFE-1#PBF LTC3862HFE-1#TRPBF LTC3862FE-1 24-Lead Plastic TSSOP –40°C to 150°C

LTC3862EGN-1#PBF LTC3862EGN-1#TRPBF LTC3862GN-1 24-Lead Plastic SSOP –40°C to 85°C

LTC3862IGN-1#PBF LTC3862IGN-1#TRPBF LTC3862GN-1 24-Lead Plastic SSOP –40°C to 125°C

LTC3862HGN-1#PBF LTC3862HGN-1#TRPBF LTC3862GN-1 24-Lead Plastic SSOP –40°C to 150°C

ORDER INFORMATION

LTC3862-1

38621f

ORDER INFORMATION

(Notes 2, 3) The l denotes the speciﬁ cations which apply over the full

operating temperature range, otherwise speciﬁ cations are at TA = 25°C. VIN = 12V, RUN = 2V and SS = open, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Supply Input and INTVCC Linear Regulator

VIN VIN Supply Voltage Range l8.5 36 V

IVIN VIN Supply Current

Normal Mode, No Switching

Shutdown

(Note 5)

VRUN = 0V

1.8

3.0

µA

INTVCC LDO Regulator Output Voltage 9.5 10.0 10.5 V

dVINTVCC(LINE) Line Regulation 12V < VIN < 36V 0.002 0.02 %/V

dVINTVCC(LOAD) Load Regulation Load = 0mA to 20mA –2 %

VUVLO INTVCC UVLO Voltage Rising INTVCC

Falling INTVCC

7.5

7.0

3V8 LDO Regulator Output Voltage 3.8 V

Switcher Control Loop

VFB Reference Voltage VITH = 0.8V (Note 6) E-Grade (Note 3)

I-Grade and H-Grade (Note 3)

1.210

1.199

1.223

1.235

1.248

dVFB/dVIN Feedback Voltage VIN Line Regulation VIN = 8.5V to 36V (Note 6) ±0.002 0.01 %/V

dVFB/dVITH Feedback Voltage Load Regulation VITH = 0.5V to 1.2V (Note 6) 0.01 0.1 %

gmTransconductance Ampliﬁ er Gain VITH = 0.8V (Note 6), ITH Pin Load = ±5µA 660 µMho

f0dB Error Ampliﬁ er Unity-Gain Crossover

Frequency

(Note 7) 1.8 MHz

VITH Error Ampliﬁ er Maximum Output Voltage

(Internally Clamped)

VFB = 1V, No Load 2.7 V

Error Ampliﬁ er Minimum Output Voltage VFB = 1.5V, No Load 50 mV

IITH Error Ampliﬁ er Output Source Current –30 µA

Error Ampliﬁ er Output Sink Current 30 µA

IFB Error Ampliﬁ er Input Bias Currents (Note 6) –50 –200 nA

VITH(PSKIP) Pulse Skip Mode Operation ITH Pin Voltage Rising ITH Voltage (Note 6)

Hysteresis

0.275

ISENSE(ON) SENSE Pin Current 0.01 2 µA

VSENSE(MAX) Maximum Current Sense Input Threshold VSLOPE = Float, Low Duty Cycle

(Note 3) l

VSENSE(MATCH) CH1 to CH2 Maximum Current Sense

Threshold Matching

VSLOPE = Float, Low Duty Cycle (Note 3)

(VSENSE1 – VSENSE2)

l–10 10 mV

ELECTRICAL CHARACTERISTICS

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC3862EUH-1#PBF LTC3862EUH-1#TRPBF 38621 24-Lead (5mm × 5mm) Plastic QFN –40°C to 85°C

LTC3862IUH-1#PBF LTC3862IUH-1#TRPBF 38621 24-Lead (5mm × 5mm) Plastic QFN –40°C to 125°C

LTC3862HUH-1#PBF LTC3862HUH-1#TRPBF 38621 24-Lead (5mm × 5mm) Plastic QFN –40°C to 150°C

Consult LTC Marketing for parts speciﬁ ed with wider operating temperature ranges. *The temperature grade is identiﬁ ed by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based ﬁ nish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁ cations, go to: http://www.linear.com/tapeandreel/

LTC3862-1

38621f

ELECTRICAL CHARACTERISTICS

(Notes 2, 3) The l denotes the speciﬁ cations which apply over the full

operating temperature range, otherwise speciﬁ cations are at TA = 25°C. VIN = 12V, RUN = 2V and SS = open, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

RUN/Soft-Start

IRUN RUN Source Current VRUN = 0V

VRUN = 1.5V

–0.5

–5

µA

VRUN High Level RUN Channel Enable Threshold 1.22 V

VRUNHYS RUN Threshold Hysteresis 80 mV

ISS SS Pull-Up Current VSS = 0V –5 µA

RSS SS Pull-Down Resistance VRUN = 0V 10 k

Oscillator

fOSC Oscillator Frequency RFREQ = 45.6k

RFREQ = 45.6k l

280

260

300

320

340

kHz

Oscillator Frequency Range l75 500 kHz

VFREQ Nominal FREQ Pin Voltage RFREQ = 45.6k 1.223 V

fSYNC SYNC Minimum Input Frequency VSYNC = External Clock l50 kHz

SYNC Maximum Input Frequency VSYNC = External Clock l650 kHz

VSYNC SYNC Input Threshold Rising Threshold 1.5 V

IPLLFLTR Phase Detector Sourcing Output Current fSYNC > fOSC –15 µA

Phase Detector Sinking Output Current fSYNC < fOSC 15 µA

CH1-CH2 Channel 1 to Channel 2 Phase Relationship VPHASEMODE = 0V

VPHASEMODE = Float

VPHASEMODE = 3V8

180

120

Deg

CH1-CLKOUT Channel 1 to CLKOUT Phase Relationship VPHASEMODE = 0V

VPHASEMODE = Float

VPHASEMODE = 3V8

240

Deg

DMAX Maximum Duty Cycle VDMAX = 0V

VDMAX = Float

VDMAX = 3V8

tON(MIN)1 Minimum On-Time VBLANK = 0V (Note 8) 210 ns

tON(MIN)2 Minimum On-Time VBLANK = Float (Note 8) 290 ns

tON(MIN)3 Minimum On-Time VBLANK = 3V8 (Note 8) 375 ns

Gate Driver

RDS(ON) Driver Pull-Up RDS(ON) 3

Driver Pull-Down RDS(ON) 0.9 

Overvoltage

VFB(OV) VFB, Overvoltage Lockout Threshold VFB(OV) – VFB(NOM) in Percent 8 10 12 %

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All currents into device pins are positive; all currents out of device

pins are negative. All voltages are referenced to ground unless otherwise

speciﬁ ed.

Note 3: The LTC3862E-1 is guaranted to meet performance speciﬁ cations

from 0°C to 85°C. Speciﬁ cations over the –40°C to 85°C operating

temperature range are assured by design, characterization and correlation

with statistical process controls. The LTC3862I-1 is guaranteed over the

full –40°C to 125°C operating temperature range and the LTC3862H-1 is

guaranteed over the full –40°C to 150°C operating temperature range.

High junction temperatures degrade operating lifetimes. Operating lifetime

is derated at junction temperatures greater than 125°C.

Note 4: This IC includes overtemperature protection that is intended to

protect the device during momentary overload conditions. Continuous

operation above the speciﬁ ed maximum operating junction temperature

may impair device reliability.

Note 5: Supply current in normal operation is dominated by the current

needed to charge the external MOSFET gates. This current will vary with

supply voltage and the external MOSFETs used.

Note 6: The IC is tested in a feedback loop that adjusts VFB to achieve a

speciﬁ ed error ampliﬁ er output voltage.

Note 7: Guaranteed by design, not subject to test.

Note 8: The minimum on-time condition is speciﬁ ed for an inductor peak-

to-peak ripple current = 30% (see Minimum On-Time Considerations in the

Applications Information section).

LTC3862-1

38621f

TYPICAL PERFORMANCE CHARACTERISTICS

Efﬁ ciency vs Output Current

Efﬁ ciency and Power Loss

vs Input Voltage

Load Step Inductor Current at Light Load

Quiescent Current

vs Input Voltage

Quiescent Current vs Temperature

Shutdown Quiescent Current

vs Input Voltage

Shutdown Quiescent Current

vs Temperature

TEMPERATURE (°C)

–50

SHUTDOWN CURRENT (µA)

25 75 150

38621 G08

–25 0 50 100 125

VIN = 12V

LOAD CURRENT (mA)

EFFICIENCY (%)

38621 G01

100

10 1000 1000100

VOUT = 72V

VIN = 32V

VIN = 24V

VIN = 9V

INPUT VOLTAGE (V)

EFFICIENCY (%)

POWER LOSS (mW)

100

38621 G02

5000

4500

4000

3500

3000

2500

2000

1500

10 20 30

VON = 72V

IOUT = 0.5A

EFFICIENCY

POWER LOSS

38621 G03

ILOAD

1A/DIV

500mA

TO 1A

ILOAD1

2A/DIV

ILOAD2

2A/DIV

VOUT

1V/DIV

VIN = 24V

VOUT = 72V

400µs/DIV 38621 G04

SW1

50V/DIV

SW2

50V/DIV

ILOAD1

1A/DIV

ILOAD2

1A/DIV

VIN = 24V

VOUT = 72V

ILOAD = 100mA

1µs/DIV

INPUT VOLTAGE (V)

QUIESCENT CURRENT (mA)

2.8

3.2

3.6

4.0

4.4

4.8

5.2

5.6

38621 G05

2.4

2.0

1.6

1.2

0.8

0.4

12 16 20 24 3228

TEMPERATURE (°C)

–50

QUIESCENT CURRENT (mA)

1.85

1.90

150

38621 G06

1.80

1.75

1.70

1.65

1.60

1.55

1.50

–25 0 25 50 100 12575

INPUT VOLTAGE (V)

SHUTDOWN CURRENT (µA)

38621 G07

12 16 20 24 3228

LTC3862-1

38621f

TYPICAL PERFORMANCE CHARACTERISTICS

INTVCC Line Regulation INTVCC Load Regulation INTVCC vs Temperature

INTVCC LDO Dropout

vs Load Current, Temperature

INTVCC UVLO Threshold

vs Temperature Feedback Voltage vs Temperature

Feedback Voltage Line

Regulation

Current Sense Threshold

vs ITH Voltage

Current Sense Threshold

vs Temperature

TEMPERATURE (°C)

–50

1.211

FB VOLTAGE (V)

1.215

1.219

1.223

1.227

1.235

–25 02550

38621 G14

75 100 125 150

1.231

1.213

1.217

1.221

1.225

1.233

1.229

INPUT VOLTAGE (V)

1.220

FB VOLTAGE (V)

1.221

1.222

1.223

1.224

12 20 28 36

38621 G15

1.225

1.226

816

24 32

ITH VOLTAGE (V)

CURRENT SENSE THRESHOLD (mV)

38621 G16

00 0.4 0.8 1.2 1.6 2.0 2.4

TEMPERATURE (°C)

–50

CURRENT SENSE THRESHOLD (mV)

050 75

38621 G17

–25 25 100 125 150

INPUT VOLTAGE (V)

INTVCC VOLTAGE (V)

10.0

10.1

10.2

38621 G09

9.9

9.8

12 16 20 24 3228

INTVCC LOAD CURRENT (mA)

INTVCC VOLTAGE (V)

10.00

10.05

10.10

38621 G10

9.95

9.90

10 20 4030

TEMPERATURE (°C)

–50

INTVCC VOLTAGE (V)

10.03

10.04

10.05

25 75 150

38621 G11

10.02

10.01

10.00

9.95

9.96

9.97

9.98

9.99

–25 0 50 100 125

INTVCC LOAD (mA)

DROPOUT VOLTAGE (mV)

800

1000

1200

20 50

38621 G12

600

400

200

010 30 40

150°C

125°C

85°C

25°C

–40°C

TEMPERATURE (°C)

–50

INTVCC VOLTAGE (V)

7.8

7.9

8.0

25 75 150

38621 G13

7.7

7.6

7.5

6.6

6.7

6.8

6.9

7.4

7.3

7.2

7.1

7.0

–25 0 50 100 125

LTC3862-1

38621f

TYPICAL PERFORMANCE CHARACTERISTICS

Maximum Current Sense

Threshold vs Duty Cycle RUN Threshold vs Temperature RUN Threshold vs Input Voltage

RUN (Off) Source Current

vs Temperature

RUN Source Current

vs Input Voltage

RUN (On) Source Current

vs Temperature

Soft-Start Current

vs Soft-Start Voltage

Oscillator Frequency

vs Temperature

Soft-Start Current vs Temperature

TEMPERATURE (°C)

–50

1.10

RUN PIN VOLTAGE (V)

1.15

1.20

1.25

1.30

–25 0 25 50

38612 G19

OFF

100 125 150

INPUT VOLTAGE (V)

RUN PIN VOLTAGE (V)

1.3

1.4

1.5

15 25 40

38621 G20

1.2

1.1

1.0

510 20

OFF

30 35

TEMPERATURE (°C)

–50

–1.0

RUN PIN CURRENT (µA)

–0.9

–0.7

–0.6

–0.5

–0.3

050 75

38621 G21

–0.8

–0.2

–0.1

–0.4

–25 25 100 125 150

TEMPERATURE (°C)

–50

RUN PIN CURRENT (µA)

–4

–2

150

38621 G22

–6

–8 050 100

–25 25 75 125

–5

–3

–7

–1

INPUT VOLTAGE (V)

RUN PIN CURRENT (µA)

–3

–2

–1

38621 G23

–4

–5

12 16 20 32

24 36

–6

–7

TEMPERATURE (°C)

–50

–5.6

SOFT-START CURRENT (µA)

–5.5

–5.4

–5.3

–5.2

050

100 150

38621 G24

–5.1

–5.0

–25 25 75 125

SOFT-START VOLTAGE (V)

–6

SOFT-START CURRENT (µA)

–5

–4

–3

–2

12 34

38621 G25

–1

0.5 1.5 2.5 3.5

TEMPERATURE (°C)

–50

FREQUENCY (kHz)

302

303

304

305

150

38621 G26

301

300

298 050 100

–25 25 75 125

299

307

306

DUTY CYCLE (%)

MAXIMUM CURRENT SENSE THRESHOLD (mV)

20 5040 7060

38621 G18

10 30 80 90 100

SLOPE = 0.625

SLOPE = 1

SLOPE = 1.66

LTC3862-1

38621f

TYPICAL PERFORMANCE CHARACTERISTICS

Oscillator Frequency

vs Input Voltage RFREQ vs Frequency Frequency vs PLLFLTR Voltage

Frequency Pin Voltage

vs Temperature

Minimum On-Time

vs Input Voltage

Minimum On-Time

vs Temperature

Gate Turn-On Waveform Driving

Renesas HAT2267H

Gate Turn-Off Waveform Driving

Renesas HAT2267H

FREQUENCY (kHz)

100

RFREQ (k)

300

1000

38621 G28

100

200 1000

900

800700600

500

400

PLLFLTR VOLTAGE (V)

1000

1200

1400

38621 G29

800

600

0.5 1 1.5 2.5

400

200

FREQUENCY (kHz)

TEMPERATURE (°C)

–50

FREQ VOLTAGE (V)

1.223

1.229

1.231

150

38621 G30

1.221

1.219

1.211 050 100

–25 25 75 125

1.215

1.235

1.233

1.227

1.225

1.217

1.213

TEMPERATURE (°C)

–50

130

MINIMUM ON-TIME (ns)

180

230

280

330

050

100 150

38621 G31

380

430

–25 25 75 125

BLANK = 3V8

BLANK = FLOAT

BLANK = SGND

INPUT VOLTAGE (V)

130

MINIMUM ON-TIME (ns)

180

230

280

330

12 20 28 36

38621 G32

380

430

16 24 32

BLANK = 3V8

BLANK = FLOAT

BLANK = SGND

38621 G33

20ns/DIV

VGATE

2V/DIV

VIN = 24V

VOUT = 72V

ILOAD = 0.25A

38621 G34

20ns/DIV

VGATE

2V/DIV

VIN = 24V

VOUT = 72V

ILOAD = 0.25A

INPUT VOLTAGE (V)

FREQUENCY (kHz)

300

305

310

315

38621 G27

295

290

280 12 20 2816 24 32

285

320

LTC3862-1

38621f

PIN FUNCTIONS

3V8: Output of the Internal 3.8V LDO from INTVCC. Supply

pin for the low voltage analog and digital circuits. A low

ESR 1nF ceramic bypass capacitor should be connected

between 3V8 and SGND, as close as possible to the IC.

BLANK: Blanking Time. Floating this pin provides a nominal

minimum on-time of 290ns. Connecting this pin to 3V8

provides a minimum on-time of 375ns, while connecting

it to SGND provides a minimum on-time of 210ns.

CLKOUT: Digital Output Used for Daisy-Chaining Multiple

LTC3862-1 ICs in Multi-Phase Systems. The PHASEMODE

pin voltage controls the relationship between CH1 and CH2

as well as between CH1 and CLKOUT.

DMAX: Maximum Duty Cycle.This pin programs the maxi-

mum duty cycle. Floating this pin provides 84% duty cycle.

Connecting this pin to 3V8 provides 75% duty cycle, while

connecting it to SGND provides 96% duty cycle.

FB: Error Ampliﬁ er Input. The FB pin should be connected

through a resistive divider network to VOUT to set the

output voltage.

FREQ: A resistor from FREQ to SGND sets the operating

frequency.

GATE1, GATE2: Gate Drive Output. The LTC3862-1 pro-

vides a 10V gate drive referenced to PGND to drive a high

voltage MOSFET.

INTVCC: Output of the Internal 10V Low Dropout Regulator

(LDO). A low ESR 4.7µF (X5R or better) ceramic bypass

capacitor should be connected between INTVCC and PGND,

as close as possible to the IC.

ITH: Error Ampliﬁ er Output. The current comparator trip

threshold increases with the ITH control voltage. The ITH

pin is also used for compensating the control loop of the

converter.

PGND: Power Ground. Connect this pin close to the

sources of the power MOSFETs. PGND should also be

connected to the negative terminals of VIN and INTVCC

bypass capacitors. PGND is electrically isolated from the

SGND pin. The Exposed Pad of the QFN and FE packages

is connected to PGND.

PHASEMODE: The PHASEMODE pin voltage programs

the phase relationship between CH1 and CH2 rising gate

signals, as well as the phase relationship between CH1

gate signal and CLKOUT. Floating this pin or connecting

it to either 3V8, or SGND changes the phase relationship

between CH1, CH2 and CLKOUT.

PLLFLTR: PLL Lowpass Filter Input. When synchroniz-

ing to an external clock, this pin serves as the lowpass

ﬁ lter input for the PLL. A series resistor and capacitor

connected from PLLFLTR to SGND compensate the PLL

feedback loop.

RUN: Run Control Input. A voltage above 1.22V on the pin

turns on the IC. Forcing the pin below 1.22V causes the

IC to shut down. There is a 0.5µA pull-up current for this

pin. Once the RUN pin raises above 1.22V, an additional

4.5µA pull-up current is added to the pin for program-

mable hysteresis.

LTC3862-1

38621f

PIN FUNCTIONS

SENSE1+, SENSE2+: Positive Inputs to the Current

Comparators. The ITH pin voltage programs the current

comparator offset in order to set the peak current trip

threshold. This pin is normally connected to a sense

resistor in the source of the power MOSFET.

SENSE1–, SENSE2–: Negative Inputs to the Current Com-

parators. This pin is normally connected to the bottom of

the sense resistor.

SGND: Signal Ground. All feedback and soft-start con-

nections should return to SGND. For optimum load

regulation, the SGND pin should be kelvin connected to

the PCB location between the negative terminals of the

output capacitors.

SLOPE: This pin programs the gain of the internal slope

compensation. Floating this pin provides a normalized

slope compensation gain of 1.00. Connecting this pin

to 3V8 increases the normalized slope compensation by

66%, and connecting it to SGND decreases the normalized

slope compensation by 37.5%. See Applications Informa-

tion for more details.

SS: Soft-Start Input. For soft-start operation, connecting

a capacitor from this pin to SGND will clamp the output of

the error amp. An internal 5µA current source will charge

the capacitor and set the rate of increase of the peak switch

current of the converter.

SYNC: PLL Synchronization Input. Applying an external

clock between 50kHz and 650kHz will cause the operating

frequency to synchronize to the clock. SYNC is pulled down

by a 50k internal resistor. The rising edge of the SYNC

input waveform will align with the rising edge of GATE1

in closed-loop operation.

VIN: Main Supply Input. A low ESR ceramic capacitor

should be connected between this pin and SGND.

LTC3862-1

38621f

FUNCTIONAL DIAGRAM

DMAX

PHASEMODE

FREQ

SLOPE

RFREQ

PLLFLTR

SYNC

CLKOUT

SLOPE

COMPENSATION

SYNC

DETECT

BLANK

3V8

5µA

BLOGIC

BLANK

LOGIC LOGIC

OVER

TEMP BIAS

CSS

CLK1

CLK2

DMAX

1.223V

PSKIP

0.275V

PSKIP

ITRIP

VCO

PWM LATCH

R1 Q

UVLO 3.8V

LDO

10V

LDO

BLOGIC

–

+–

ICMP RLOOP

V TO I

ITH

RUN

–

1.345V

–

RUN 4.5µA

1.22V

–

EA 0.5µA

SGND

VFB

38621 FD

GATE

3V8

INTVCC

VIN

PGND

SENSE+

SENSE–

DUPLICATE FOR

SECOND CHANNEL

CVCC

CIN

COUT

VOUT

C3V8

LTC3862-1

38621f

OPERATION

The Control Loop

The LTC3862-1 uses a constant frequency, peak current

mode step-up architecture with its two channels operat-

ing 180 degrees out of phase. During normal operation,

each external MOSFET is turned on when the clock for

that channel sets the PWM latch, and is turned off when

the main current comparator, ICMP, resets the latch. The

peak inductor current at which ICMP trips and resets the

latch is controlled by the voltage on the ITH pin, which is

the output of the error ampliﬁ er, EA. The error ampliﬁ er

compares the output feedback signal at the VFB pin to the

internal 1.223V reference and generates an error signal

at the ITH pin. When the load current increases it causes

a slight decrease in VFB relative to the reference voltage,

which causes the EA to increase the ITH voltage until the

average inductor current matches the new load current.

After the MOSFET is turned off, the inductor current ﬂ ows

through the boost diode into the output capacitor and load,

until the beginning of the next clock cycle.

Cascaded LDOs Supply Power to the Gate Driver and

Control Circuitry

The LTC3862-1 contains two cascaded PMOS output stage

low dropout voltage regulators (LDOs), one for the gate

drive supply (INTVCC) and one for the low voltage analog

and digital control circuitry (3V8). A block diagram of this

power supply arrangement is shown in Figure 1.

The Gate Driver Supply LDO (INTVCC)

The 10V output (INTVCC) of the ﬁ rst LDO is powered from

VIN and supplies power to the power MOSFET gate driv-

ers. The INTVCC pin should be bypassed to PGND with a

minimum of 4.7F of ceramic capacitance (X5R or better),

placed as close as possible to the IC pins. If two power

MOSFETs are connected in parallel for each channel in

order to increase the output power level, or if a single

MOSFET with a QG greater than 50nC is used, then it is

recommended that the bypass capacitance be increased

to a minimum of 10F.

An undervoltage lockout (UVLO) circuit senses the INTVCC

regulator output in order to protect the power MOSFETs from

operating with inadequate gate drive. For the LTC3862-1

the rising UVLO threshold is typically 7.5V and the hys-

teresis is typically 500mV. The LTC3862-1 was optimized

for high voltage power MOSFETs and applications. For

applications requiring logic-level power MOSFETs, please

refer to the LTC3862 data sheet.

Figure 1. Cascaded LDOs Provide Gate Drive and Control Circuitry Power

–

SGND

R2 R1

1.223V

LTC3862-1

INTVCC

3V8

GATE

–

SGND

R4 R3

1.223V

P-CH

ANALOG

CIRCUITS LOGIC

INTVCC

VIN

CIN

CVCC

C3V8

38621 F01

PGND

3V8

SGND

NOTE: PLACE CVCC AND C3V8 CAPACITORS AS CLOSE AS POSSIBLE TO DEVICE PINS

LTC3862-1

38621f

OPERATION

In multi-phase applications, all of the FB pins are connected

together and all of the error ampliﬁ er output pins (ITH) are

connected together. The INTVCC pins, however, should not

be connected together. The INTVCC regulator is capable of

sourcing current but is not capable of sinking current. As

a result, when two or more INTVCC regulator outputs are

connected together, the highest voltage regulator supplies

all of the gate drive and control circuit current, and the

other regulators are off. This would place a thermal burden

on the highest output voltage LDO and could cause the

maximum die temperature to be exceeded. In multi-phase

LTC3862-1 applications, each INTVCC regulator output

should be independently bypassed to its respective PGND

pin as close as possible to each IC.

The Low Voltage Analog and Digital Supply LDO (3V8)

The second LDO within the LTC3862-1 is powered off

of INTVCC and serves as the supply to the low voltage

analog and digital control circuitry, as shown in Figure 1.

The output voltage of this LDO (which also has a PMOS

output device) is 3.8V. Most of the analog and digital con-

trol circuitry is powered from the internal 3V8 LDO. The

3V8 pin should be bypassed to SGND with a 1nF ceramic

capacitor (X5R or better), placed as close as possible

to the IC pins. This LDO is not intended to be used as a

supply for external circuitry.

Thermal Considerations and Package Options

The LTC3862-1 is offered in three package options. The

5mm × 5mm QFN package (UH24) has a thermal resistance

RTH(JA) of 34°C/W, the 24-pin TSSOP (FE24) package has a

thermal resistance of 38°C/W, and the 24-pin SSOP (GN24)

package has a thermal resistance of 85°C/W. The QFN and

TSSOP package options have a lead pitch of 0.65mm, and

the GN24 option has a lead pitch of 0.025in.

The INTVCC regulator can supply up to 50mA of total

current. As a result, care must be taken to ensure that

the maximum junction temperature of the IC is never

exceeded. The junction temperature can be estimated

using the following equations:

Q(TOT) = IQ + QG(TOT) • f

DISS = VIN • (IQ + QG(TOT) • f)

J = TA + PDISS • RTH(JA)

The total quiescent current (IQ(TOT)) consists of the static

supply current (IQ) and the current required to charge

the gate capacitance of the power MOSFETs. The value

of QG(TOT) should come from the plot of VGS vs QG in the

Typical Performance Characteristics section of the MOSFET

data sheet. The value listed in the electrical speciﬁ cations

may be measured at a higher VGS, such as 15V, whereas the

value of interest is at the 10V INTVCC gate drive voltage.

As an example of the required thermal analysis, consider a

2-phase boost converter with a 8.5V to 24V input voltage

range and an output voltage of 72V at 1.5A. The switching

frequency is 150kHz and the maximum ambient tempera-

ture is 70°C. The power MOSFET used for this application

is the Renesas HAT2267H, which has a typical RDS(ON) of

13m at VGS = 10V. From the plot of VGS vs QG, the total

gate charge at VGS = 10V is 30nC (the temperature coef-

ﬁ cient of the gate charge is low). One power MOSFET is

used for each phase. For the QFN package option:

Q(TOT) = 3mA + 2 • 30nC • 150kHz = 12mA

DISS = 24V • 12mA = 288mW

J = 70°C + 288mW • 34°C/W = 79.8°C

In this example, the junction temperature rise is only 9.8°C.

These equations demonstrate how the gate charge current

typically dominates the quiescent current of the IC, and

how the choice of package option and board heat sinking

can have a signiﬁ cant effect on the thermal performance

of the solution.

LTC3862-1

38621f

OPERATION

To prevent the maximum junction temperature from be-

ing exceeded, the input supply current to the IC should

be checked when operating in continuous mode (heavy

load) at maximum VIN. A tradeoff between the operating

frequency and the size of the power MOSFETs may need

to be made in order to maintain a reliable junction tem-

perature. Finally, it is important to verify the calculations

by performing a thermal analysis of the ﬁ nal PCB using

an infrared camera or thermal probe. As an option, an

exernal regulator shown in Figure 3 can be used to reduce

the total power dissipation on the IC.

Thermal Shutdown Protection

In the event of an overtemperature condition (external

or internal), an internal thermal monitor will shut down

the gate drivers and reset the soft-start capacitor if the

die temperature exceeds 170°C. This thermal sensor has

a hysteresis of 10°C to prevent erratic behavior at hot

temperatures. The LTC3862-1’s internal thermal sen-

sor is intended to protect the device during momentary

overtemperature conditions. Continuous operation above

the speciﬁ ed maximum operating junction temperature,

however, may result in device degradation.

Operation at Low Supply Voltage

The LTC3862-1 has a minimum input voltage of 8.5V, making

it a good choice for applications that require high voltage

power MOSFETs. The gate driver for the LTC3862-1 consists

of PMOS pull-up and NMOS pull-down devices, allowing

the full INTVCC voltage to be applied to the gates during

power MOSFET switching. Nonetheless, care should be

taken to determine the minimum gate drive supply voltage

(INTVCC) in order to choose the optimum power MOSFETs.

Important parameters that can affect the minimum gate

drive voltage are the minimum input voltage (VIN(MIN)),

the LDO dropout voltage, the QG of the power MOSFETs,

and the operating frequency.

If the input voltage VIN is low enough for the INTVCC LDO

to be in dropout, then the minimum gate drive supply

voltage is:

INTVCC = VIN(MIN) – VDROPOUT

The LDO dropout voltage is a function of the total gate

drive current and the quiescent current of the IC (typically

3mA). A curve of dropout voltage vs output current for the

LDO is shown in Figure 2. The temperature coefﬁ cient of

the LDO dropout voltage is approximately 6000ppm/°C.

The total Q-current (IQ(TOT)) ﬂ owing in the LDO is the sum

of the controller quiescent current (3mA) and the total gate

charge drive current.

Q(TOT) = IQ + QG(TOT) • f

After the calculations have been completed, it is impor-

tant to measure the gate drive waveforms and the gate

driver supply voltage (INTVCC to PGND) over all operating

conditions (low VIN, nominal VIN and high VIN, as well

as from light load to full load) to ensure adequate power

MOSFET enhancement. Consult the power MOSFET data

sheet to determine the actual RDS(ON) for the measured

VGS, and verify your thermal calculations by measuring

the component temperatures using an infrared camera

or thermal probe.

Figure 2. INTVCC LDO Dropout Voltage vs Current

INTVCC LOAD (mA)

DROPOUT VOLTAGE (mV)

800

1000

1200

20 50

38621 F02

600

400

200

010 30 40

150°C

125°C

85°C

25°C

–40°C

LTC3862-1

38621f

OPERATION

Operation at High Supply Voltage

At high input voltages, the LTC3862-1’s internal LDO

can dissipate a signiﬁ cant amount of power, which could

cause the maximum junction temperature to be exceeded.

Conditions such as a high operating frequency, or the use

of more than one power MOSFET per channel, could push

the junction temperature rise to high levels. If the thermal

equations above indicate too high a rise in the junction

temperature, an external bias supply can always be used

to reduce the power dissipation on the IC, as shown in

Figure 3.

For example, a 12V system rail that is available would be

more suitable than the 24V main input power rail to power

the LTC3862-1. Also, the bias power can be generated with

a separate switching or LDO regulator. An example of an

LDO regulator is shown in Figure 3. The output voltage

of the LDO regulator can be set by selecting an appropri-

ate zener diode to be higher than 10V but low enough to

divide the power dissipation between LTC3862-1 and Q1

in Figure 3. The absolute maximum voltage rating of the

INTVCC pin is 11V.

supplies. Independently biasing the INTVCC pin from a

separate power supply can cause one of two possible

failure modes during supply sequencing. If the INTVCC

supply comes up before the VIN supply, high current will

ﬂ ow from the external INTVCC supply, through the body

diode of the LDO PMOS device, to the input capacitor

and VIN pin. This high current ﬂ ow could trigger a latchup

condition and cause catastrophic failure of the IC.

If, however, the VIN supply to the IC comes up before the

INTVCC supply, the external INTVCC supply will act as a

load to the internal LDO in the LTC3862-1, and the LDO will

attempt to charge the INTVCC output with its short-circuit

current. This will result in excessive power dissipation and

possible thermal overload of the LTC3862-1.

Programming the Output Voltage

The output voltage is set by a resistor divider according

to the following formula:

VOUT =1.223V 1+R2











The external resistor divider is connected to the output

as shown in Figure 4. Resistor R1 is normally chosen so

that the output voltage error caused by the current ﬂ owing

out of the VFB pin during normal operation is negligible

compared to the current in the divider. For an output volt-

age error due to the error amp input bias current of less

than 0.5%, this translates to a maximum value of R1 of

about 30k.

Figure 3. Using the LTC3862-1 with an External Bias Supply

Figure 4. Programming the Output Voltage

with a Resistor Divider

Power Supply Sequencing

As shown in Figure 1, there are body diodes in parallel with

the PMOS output transistors in the two LDO regulators

in the LTC3862-1. As a result, it is not possible to bias

the INTVCC and VIN pins of the chip from separate power

VIN

CVCC

38621 F03

LTC3862-1

VIN

INTVCC

LTC3862-1

SGND

38621 F04

VOUT

LTC3862-1

38621f

OPERATION

Operation of the RUN Pin

The control circuitry in the LTC3862-1 is turned on and

off using the RUN pin. Pulling the RUN pin below 1.22V

forces shutdown mode and releasing it allows a 0.5A

current source to pull this pin up, allowing a “normally

on” converter to be designed. Alternatively, the RUN pin

can be externally pulled up or driven directly by logic.

Care must be taken not to exceed the absolute maximum

rating of 8V for this pin.

The comparator on the RUN pin can also be used to sense

the input voltage, allowing an undervoltage detection

circuit to be designed. This is helpful in boost converter

applications where the input current can reach very high

levels at low input voltage:

IIN =IOUT •V

OUT

VIN

The 1.22V input threshold of the RUN comparator is derived

from a precise bandgap reference, in order to maximize

the accuracy of the undervoltage-sensing function. The

RUN comparator has 80mV built-in hysteresis. When

the voltage on the RUN pin exceeds 1.22V, the current

sourced into the RUN pin is switched from 0.5A to 5A

PTAT current. The user can therefore program both the

rising threshold and the amount of hysteresis using the

values of the resistors in the external divider, as shown in

the following equations:

VIN(ON) =1.22V 1+RA









– 0.5µ • RA

VIN(OFF) =1.22V 1+RA









–5µ•RA

Several of the possible RUN pin control techniques are

illustrated in Figure 5.

Frequency Selection and the Phase Lock Loop

The selection of the switching frequency is a tradeoff

between efﬁ ciency and component size. Low frequency

operation increases efﬁ ciency by reducing MOSFET

switching losses, but requires a larger inductor and output

capacitor to maintain low output ripple.

Figure 5a. Using the RUN Pin for a “Normally On” Converter

Figure 5b. On/Off Control Using External Logic

Figure 5c. Programming the Input Voltage Turn-On and Turn-Off

Thresholds Using the RUN Pin

–

RUN

COMPARATOR

1.22V

38621 F05a

VIN LTC3862-1

RUN

10V

INTERNAL 5V

0.5µA 4.5µA

SGND

BIAS AND

START-UP

CONTROL

–

RUN

COMPARATOR

1.22V

38621 F05b

VIN LTC3862-1

RUN

10V

INTERNAL 5V

EXTERNAL

LOGIC

CONTROL 0.5µA 4.5µA

SGND

BIAS AND

START-UP

CONTROL

–

RUN

COMPARATOR

1.22V

38621 F05c

VIN LTC3862-1

RUN

10V

INTERNAL 5V

0.5µA

4.5µA

SGND

BIAS AND

START-UP

CONTROL

LTC3862-1

38621f

OPERATION

The LTC3862-1 uses a constant frequency architecture that

can be programmed over a 75kHz to 500kHz range using

a single resistor from the FREQ pin to ground. Figure 6

illustrates the relationship between the FREQ pin resistance

and the operating frequency.

The operating frequency of the LTC3862-1 can be ap-

proximated using the following formula:

FREQ = 5.5096E9(fOSC)–0.9255

A phase-lock loop is available on the LTC3862-1 to syn-

chronize the internal oscillator to an external clock source

connected to the SYNC pin. Connect a series RC network

from the PLLFLTR pin to SGND to compensate PLL’s

feedback loop. Typical compensation components are a

0.01F capacitor in series with a 10k resistor. The PLLFLTR

pin is both the output of the phase detector and the input

to the voltage controlled oscillator (VCO). The LTC3862-1

phase detector adjusts the voltage on the PLLFLTR pin

to align the rising edge of GATE1 to the leading edge of

the external clock signal, as shown in Figure 7. The ris-

ing edge of GATE2 will depend upon the voltage on the

PHASEMODE pin. The capture range of the LTC3862-1’s

PLL is 50kHz to 650kHz.

Because the operating frequency of the LTC3862-1 can be

programmed using an external resistor, in synchronized

applications, it is recommended that the free-running fre-

quency (as deﬁ ned by the external resistor) be set to the

same value as the synchronized frequency. This results in

a start-up of the IC at approximately the same frequency

as the external clock, so that when the sync signal comes

alive, no discontinuity at the output will be observed. It also

ensures that the operating frequency remains essentially

constant in the event the sync signal is lost. The SYNC

pin has an internal 50k resistor to ground.

Using the CLKOUT and PHASEMODE Pins

in Multi-Phase Applications

The LTC3862-1 features two pins (CLKOUT and PHASE-

MODE) that allow multiple ICs to be daisy-chained together

for higher current multi-phase applications. For a 3- or

4-phase design, the CLKOUT signal of the master controller

Figure 6. FREQ Pin Resistor Value vs Frequency

Figure 7: Synchronization of the LTC3862-1

to an External Clock Using the PLL

is connected to the SYNC input of the slave controller in

order to synchronize additional power stages for a single

high current output. The PHASEMODE pin is used to adjust

the phase relationship between channel 1 and channel

2, as well as the phase relationship between channel 1

and CLKOUT, as summarized in Table 1. The phases are

calculated relative to the zero degrees, deﬁ ned as the ris-

ing edge of the GATE1 output. In a 6-phase application

the CLKOUT pin of the master controller connects to the

SYNC input of the 2nd controller and the CLKOUT pin of

the 2nd controller connects to the SYNC pin of the 3rd

controller.

FREQUENCY (kHz)

100

RFREQ (k)

300

1000

38621 F06

100

200 1000

900

800700600

500

400

SYNC

10V/DIV

GATE1

20V/DIV

GATE2

20V/DIV

CLKOUT

10V/DIV

2µs/DIVVIN = 24V

VOUT = 72V

IOUT = 0.5A

PHASEMODE = SGND

38621 F07

LTC3862-1

38621f

OPERATION

Table 1

PHASEMODE

CH-1 to CH-2

PHASE

CH-1 to CLKOUT

PHASE APPLICATION

SGND 180° 90° 2-Phase, 4-Phase

Float 180° 60° 6-Phase

3V8 120° 240° 3-Phase

Using the LTC3862-1 Transconductance (gm) Error

Ampliﬁ er in Multi-Phase Applications

The LTC3862-1 error ampliﬁ er is a transconductance, or gm

ampliﬁ er, meaning that it has high DC gain but high output

impedance (the output of the error ampliﬁ er is a current

proportional to the differential input voltage). This style

of error ampliﬁ er greatly eases the task of implementing

a multi-phase solution, because the ampliﬁ ers from two

or more chips can be connected in parallel. In this case

the FB pins of multiple LTC3862-1s can be connected to-

gether, as well as the ITH pins, as shown in Figure 8. The

gm of the composite error ampliﬁ er is simply n times the

transconductance of one ampliﬁ er, or gm(TOT) = n • 660S,

where n is the number of ampliﬁ ers connected in paral-

lel. The transfer function from the ITH pin to the current

comparator inputs was carefully designed to be accurate,

both from channel-to-channel and chip-to-chip. This way

the peak inductor current matching is kept accurate.

A buffered version of the output of the error ampliﬁ er deter-

mines the threshold at the input of the current comparator.

The ITH voltage that represents zero peak current is 0.4V

and the voltage that represents current limit is 1.2V (at

low duty cycle). During an overload condition, the output

of the error ampliﬁ er is clamped to 2.6V at low duty cycle,

in order to reduce the latency when the overload condition

terminates. A patented circuit in the LTC3862-1 is used

to recover the slope compensation signal, so that the

maximum peak inductor current is not a strong function

of the duty cycle.

Soft-Start

The start-up of the LTC3862-1 is controlled by the volt-

age on the SS pin. An internal PNP transistor clamps the

current comparator sense threshold during soft-start,

thereby limiting the peak switch current. The base of the

PNP is connected to the SS pin and the emitter to an

Figure 8. LTC3862-1 Error Ampliﬁ er Conﬁ guration

for Multi-Phase Operation

internal, buffered ITH node (please note that the ITH pin

voltage may not track the soft-start voltage during this time

period). An internal 5A current source charges the SS

capacitor, and clamps the peak sense threshold until the

voltage on the soft-start capacitor reaches approximately

0.6V. The required amount of soft-start capacitance can

be estimated using the following equation:

CSS =5µA tSS

0.6V











The SS pin has an internal open-drain NMOS pull-down

transistor that turns on when the RUN pin is pulled low,

when the voltage on the INTVCC pin is below its undervoltage

lockout threshold, or during an overtemperature condi-

tion. In multi-phase applications that use more than one

FREQ

CLKOUT

SYNC

PLLFLTR

LTC3862-1

MASTER

SGND

ITH

VOUT

INTVCC

RUN ON/OFF

CONTROL

ALL RUN PINS

CONNNECTED

TOGETHER

INDIVIDUAL

INTVCC PINS

LOCALLY

DECOUPLED

FREQ

CLKOUT

SYNC

PLLFLTR

LTC3862-1

SLAVE

SGND

ITH

INTVCC

RUN

SLAVE

38621 F08

ALL SS PINS

CONNNECTED

TOGETHER

FREQ

ALL FB PINS

CONNECTED

TOGETHER

ALL ITH PINS

CONNECTED

TOGETHER

CLKOUT

SYNC

PLLFLTR

LTC3862-1

SGND

ITH

INTVCC

RUN

LTC3862-1

38621f

OPERATION

LTC3862-1 chip, connect all of the SS pins together and

use one external capacitor to program the soft-start time.

In this case, the current into the soft-start capacitor will be

ISS = n • 5A, where n is the number of SS pins connected

together. Figure 9 illustrates the start-up waveforms for a

2-phase LTC3862-1 application.

an excessively large inductor would result in too much

effective slope compensation, and the converter could

become unstable. Likewise, if too small an inductor were

used, the internal ramp compensation could be inadequate

to prevent sub-harmonic oscillation.

The LTC3862-1 contains a pin that allows the user to

program the slope compensation gain in order to opti-

mize performance for a wider range of inductance. With

the SLOPE pin left ﬂ oating, the normalized slope gain is

1.00. Connecting the SLOPE pin to ground reduces the

normalized gain to 0.625 and connecting this pin to the

3V8 supply increases the normalized slope gain to 1.66.

With the normalized slope compensation gain set to 1.00,

the design equations assume an inductor ripple current of

20% to 40%, as with previous designs. Depending upon

the application circuit, however, a normalized gain of 1.00

may not be optimum for the inductor chosen. If the ripple

current in the inductor is greater than 40%, the normalized

slope gain can be increased to 1.66 (an increase of 66%)

by connecting the SLOPE pin to the 3V8 supply. If the

inductor ripple current is less than 20%, the normalized

slope gain can be reduced to 0.625 (a decrease of 37.5%)

by connecting the SLOPE pin to SGND.

To check the effectiveness of the slope compensation, apply

a load step to the output and monitor the cycle-by-cycle

behavior of the inductor current during the leading and

trailing edges of the load current. Vary the input voltage

over its full range and check for signs of cycle-by-cycle

SW node instability or sub-harmonic oscillation. When

Figure 9. Typical Start-Up Waveforms for a

Boost Converter Using the LTC3862-1

Figure 10. Light Load Switching Waveforms for

the LTC3862-1 at the Onset of Pulse Skipping

Pulse Skip Operation at Light Load

As the load current is decreased, the controller enters

discontinuous mode (DCM). The peak inductor current can

be reduced until the minimum on-time of the controller

is reached. Any further decrease in the load current will

cause pulse skipping to occur, in order to maintain output

regulation, which is normal. The minimum on-time of the

controller in this mode is approximately 210ns (with the

blanking time set to its minimum value), the majority of

which is leading edge blanking. Figure 10 illustrates the

LTC3862-1 switching waveforms at the onset of pulse

skipping.

Programmable Slope Compensation

For a current mode boost regulator operating in CCM,

slope compensation must be added for duty cycles above

50%, in order to avoid sub-harmonic oscillation. For the

LTC3862-1, this ramp compensation is internal and user

adjustable. Having an internally ﬁ xed ramp compensation

waveform normally places some constraints on the value

of the inductor and the operating frequency. For example,

with a ﬁ xed amount of internal slope compensation, using

RUN

5V/DIV

VOUT

100V/DIV

IL1

2A/DIV

IL2

2A/DIV

1ms/DIVVIN = 24V

VOUT = 72V

RL = 100Ω

38621 F09

SW1

50V/DIV

SW2

50V/DIV

IL1

500mA/DIV

IL2

500mA/DIV

2µs/DIV 3862 F10

VIN = 51V

VOUT = 72V

LIGHT LOAD (10mA)

LTC3862-1

38621f

OPERATION

Figure 12. Effect of Slope Gain on the Peak SENSE Threshold

the slope compensation is too low the converter can

suffer from excessive jitter or, worst case, sub-harmonic

oscillation. When excess slope compensation is applied to

the internal current sense signal, the phase margin of the

control loop suffers. Figure 11 illustrates inductor current

waveforms for a properly compensated loop.

The LTC3862-1 contains a patented circuit whereby most

of the applied slope compensation is recovered, in order

to provide a SENSE+ to SENSE– threshold which is not

a strong function of the duty cycle. This sense threshold

is, however, a function of the programmed slope gain, as

shown in Figure 12. The data sheet typical speciﬁ cation of

75mV for SENSE+ minus SENSE– is measured at a normal-

ized slope gain of 1.00 at low duty cycle. For applications

where the normalized slope gain is not 1.00, use Figure 12

to determine the correct value of the sense resistor.

Programmable Blanking and the Minimum On-Time

The BLANK pin on the LTC3862-1 allows the user to pro-

gram the amount of leading edge blanking at the SENSE

pins. Connecting the BLANK pin to SGND results in a

minimum on-time of 210ns, ﬂ oating the pin increases

this time to 290ns, and connecting the BLANK pin to the

3V8 supply results in a minimum on-time of 375ns. The

majority of the minimum on-time consists of this leading

edge blanking, due to the inherently low propagation delay

of the current comparator (25ns typ) and logic circuitry

(10ns to 15ns).

The purpose of leading edge blanking is to ﬁ lter out noise on

the SENSE pins at the leading edge of the power MOSFET

turn-on. During the turn-on of the power MOSFET the gate

drive current, the discharge of any parasitic capacitance

on the SW node, the recovery of the boost diode charge,

and parasitic series inductance in the high di/dt path all

contribute to overshoot and high frequency noise that could

cause false-tripping of the current comparator. Due to the

wide range of applications the LTC3862-1 is well-suited

to, ﬁ xing one value of the internal leading edge blanking

time would have required the longest delay time to have

been used. Providing a means to program the blank time

allows users to optimize the SENSE pin ﬁ ltering for each

application. Figure 13 illustrates the effect of the program-

mable leading edge blank time on the minimum on-time

of a boost converter.

Programmable Maximum Duty Cycle

In order to maintain constant frequency and a low output

ripple voltage, a single-ended boost (or ﬂ yback or SEPIC)

converter is required to turn off the switch every cycle

for some minimum amount of time. This off-time allows

the transfer of energy from the inductor to the output

capacitor and load, and prevents excessive ripple current

and voltage. For inductor-based topologies like boost and

SEPIC converters, having a maximum duty cycle as close

as possible to 100% may be desirable, especially in low

VIN to high VOUT applications. However, for transformer-

based solutions, having a maximum duty cycle near 100%

is undesirable, due to the need for V • sec reset during the

primary switch off-time.

Figure 11. Inductor Current Waveforms for a

Properly Compensated Control Loop

DUTY CYCLE (%)

MAXIMUM CURRENT SENSE THRESHOLD (mV)

20 40 60 80

38621 F12

100100 30507090

SLOPE = 0.625

SLOPE = 1

SLOPE = 1.66

ILOAD

1A/DIV

VOUT

2V/DIV

IL1

1A/DIV

IL2

1A/DIV

20µs/DIV 38621 F11

VIN = 24V

VOUT = 72V

LTC3862-1

38621f

OPERATION

Figure 13. Leading Edge Blanking Effects

on the Minimum On-Time

Figure 14. SW Node Waveforms with Different Duty Cycle Limits

In order to satisfy these different applications require-

ments, the LTC3862-1 has a simple way to program the

maximum duty cycle. Connecting the DMAX pin to SGND

limits the maximum duty cycle to 96%. Floating this pin

limits the duty cycle to 84% and connecting the DMAX pin

to the 3V8 supply limits it to 75%. Figure 14 illustrates

the effect of limiting the maximum duty cycle on the SW

node waveform of a boost converter.

The LTC3862-1 contains an oscillator that runs at a multiple

of the switching frequency, in order to provide for 2-, 3-,

4-, 6- and 12-phase operation. A digital counter is used

to divide down the fundamental oscillator frequency in

order to obtain the operating frequency of the gate drivers.

Since the maximum duty cycle limit is obtained from this

digital counter, the percentage maximum duty cycle does

not vary with process tolerances or temperature.

SW NODE

20V/DIV

GATE

5V/DIV

500ns/DIV

MINIMUM ON-TIME AT LIGHT LOAD WITH BLANK = SGND

VIN = 36V

VOUT = 72V

MEASURED ON-TIME = 210ns

VIN = 36V

VOUT = 72V

MEASURED ON-TIME = 290ns

VIN = 36V

VOUT = 72V

MEASURED ON-TIME = 375ns

INDUCTOR

CURRENT

200mA/DIV

SW NODE

20V/DIV

GATE

5V/DIV

INDUCTOR

CURRENT

200mA/DIV

SW NODE

20V/DIV

GATE

5V/DIV

INDUCTOR

CURRENT

200mA/DIV

500ns/DIV

MINIMUM ON-TIME AT LIGHT LOAD WITH BLANK = FLOAT

500ns/DIV 38621 F13

MINIMUM ON-TIME AT LIGHT LOAD WITH BLANK = 3V8

SW NODE

20V/DIV

SW NODE

20V/DIV

1µs/DIV

96% MAXIMUM DUTY CYCLE WITH DMAX = SGND

INDUCTOR

CURRENT

1A/DIV

1µs/DIV

84% MAXIMUM DUTY CYCLE WITH DMAX = FLOAT

INDUCTOR

CURRENT

1A/DIV

SW NODE

20V/DIV

INDUCTOR

CURRENT

1A/DIV

1µs/DIV 3862 F14

75% MAXIMUM DUTY CYCLE WITH DMAX = 3V8

LTC3862-1

38621f

The SENSE+ and SENSE– Pins

The SENSE+ and SENSE– pins are high impedance inputs

to the CMOS current comparators for each channel.

Nominally, there is no DC current into or out of these

pins. There are ESD protection diodes connected from

these pins to SGND, although even at hot temperature the

leakage current into the SENSE+ and SENSE– pins should

be less than 1A.

Since the LTC3862-1 contains leading edge blanking, an

external RC ﬁ lter is not required for proper operation.

However, if an external ﬁ lter is used, the ﬁ lter components

should be placed close to the SENSE+ and SENSE– pins on

the IC, as shown in Figure 15. The positive and negative

sense node traces should then run parallel to each other

to a Kelvin connection underneath the sense resistor, as

shown in Figure 16. Sensing current elsewhere on the

board can add parasitic inductance and capacitance to

the current sense element, degrading the information

at the sense pins and making the programmed current

limit unpredictable. Avoid the temptation to connect the

SENSE– line to the ground plane using a PCB via; this

could result in unpredictable behavior.

The sense resistor should be connected to the source

of the power MOSFET and the ground node using short,

wide PCB traces, as shown in Figure 16. Ideally, the bot-

tom terminal of the sense resistors will be immediately

Figure 16. Connecting the SENSE+ and SENSE– Traces to the

Sense Resistor Using a Kelvin Connection

adjacent to the negative terminal of the output capacitor,

since this path is a part of the high di/dt loop formed by

the switch, boost diode, output capacitor and sense resis-

tor. Placement of the inductors is less critical, since the

current in the inductors is a triangle waveform.

Checking the Load Transient Response

The regulator loop response can be checked by looking at

the load current transient response. Switching regulators

take several cycles to respond to a step in DC (resistive)

load current. When a load step occurs, VOUT shifts by an

amount equal to ΔILOAD (ESR), where ESR is the effective

series resistance of COUT

. ΔILOAD also begins to charge or

discharge COUT

, generating the feedback error signal that

forces the regulator to adapt to the current change and

return VOUT to its steady-state value. During this recovery

time VOUT can be monitored for excessive overshoot or

ringing, which would indicate a stability problem.

The availability of the ITH pin not only allows optimization

of control loop behavior but also provides a DC-coupled

and AC-ﬁ ltered closed-loop response test point. The DC

step, rise time and settling at this test point truly reﬂ ects the

closed-loop response. Assuming a predominantly second

order system, phase margin and/or damping factor can be

estimated using the percentage of overshoot seen at this

pin. The bandwidth can also be estimated by examining

the rise time at the pin.

OPERATION

Figure 15. Proper Current Sense Filter Component Placement

SENSE–

SENSE+

LTC3862-1

GATE

VOUT

RSENSE

38621 F15

FILTER COMPONENTS

PLACED NEAR

SENSE PINS

VIN

PGND

INTVCC

VIN MOSFET SOURCE

TO SENSE

FILTER NEXT

TO CONTROLLER

RSENSE

GND

38621 F16

LTC3862-1

38621f

OPERATION

Figure 17: Load Step Response of a Properly

Compensated Boost Converter

The ITH series RC • CC ﬁ lter sets the dominant pole-zero

loop compensation. The transfer function for boost and

ﬂ yback converters contains a right half plane zero that

normally requires the loop crossover frequency to be

reduced signiﬁ cantly in order to maintain good phase

margin. The RC • CC ﬁ lter values can typically be modiﬁ ed

slightly (from 0.5 to 2 times their suggested values) to

optimize transient response once the ﬁ nal PC layout is done

and the particular output capacitor type(s) and value(s)

have been determined. The output capacitor conﬁ guration

needs to be selected in advance because the effective ESR

and bulk capacitance have a signiﬁ cant effect on the loop

gain and phase. An output current pulse of 20% to 80%

of full-load current having a rise time of 1s to 10s will

produce output voltage and ITH pin waveforms that will

give a sense of the overall loop stability without breaking

the feedback loop. Placing a power MOSFET and load

resistor directly across the output capacitor and driving

the gate with an appropriate signal generator is a practi-

cal way to produce a fast load step condition. The initial

output voltage step resulting from the step change in the

output current may not be within the bandwidth of the

feedback loop, so this signal cannot be used to determine

phase margin. This is why it is better to look at the ITH

pin signal which is in the feedback loop and is the ﬁ ltered

and compensated control loop response. The gain of the

loop will be increased by increasing RC and the bandwidth

of the loop will be increased by decreasing CC. If RC is

increased by the same factor that CC is decreased, the

zero frequency will be kept the same, thereby keeping the

phase shift the same in the most critical frequency range

of the feedback loop. The output voltage settling behavior

is related to the stability of the closed-loop system and

will demonstrate the actual overall supply performance.

Figure 17 illustrates the load step response of a properly

compensated boost converter.

ILOAD

1A/DIV

500mA TO 1A

VOUT

1V/DIV

IL1

2A/DIV

IL2

2A/DIV

400µs/DIV 38621 F17

VIN = 24V

VOUT = 72V

LTC3862-1

38621f

Figure 18. A Typical 2-Phase, Single Output Boost Converter Application Circuit

Typical Boost Applications Circuit

A basic 2-phase, single output LTC3862-1 application

circuit is shown in Figure 18. External component selec-

tion is driven by the characteristics of the load and the

input supply.

Duty Cycle Considerations

For a boost converter operating in a continuous conduction

mode (CCM), the duty cycle of the main switch is:

D=VO+VF–V

VO+VF









=tON •f

where VF is the forward voltage of the boost diode. The

minimum on-time for a given application operating in

CCM is:

tON(MIN) =1

VO+VF–V

IN(MAX)

VO+VF











For a given input voltage range and output voltage, it is

important to know how close the minimum on-time of the

application comes to the minimum on-time of the control

IC. The LTC3862-1 minimum on-time can be programmed

from 210ns to 375ns using the BLANK pin.

Minimum On-Time Limitations

In a single-ended boost converter, two steady-state condi-

tions can result in operation at the minimum on-time of

the controller. The ﬁ rst condition is when the input voltage

is close to the output voltage. When VIN approaches VOUT

the voltage across the inductor approaches zero during

the switch off-time. Under this operating condition the

converter can become unstable and the output can experi-

ence high ripple voltage oscillation at audible frequencies.

For applications where the input voltage can approach

or exceed the output voltage, consider using a SEPIC or

buck-boost topology instead of a boost converter.

The second condition that can result in operation at the

minimum on-time of the controller is at light load, in deep

discontinuous mode. As the load current is decreased,

the on-time of the switch decreases, until the minimum

on-time limit of the controller is reached. Any further de-

crease in the output current will result in pulse skipping,

a typically benign condition where cycles are skipped in

order to maintain output regulation.

APPLICATIONS INFORMATION

SENSE1+

3V8

SLOPE

BLANK

CLKOUT

SYNC

PLLFLTR

PHASEMODE

DMAX

10nF

SENSE1–

SENSE2–

SENSE2+

RUN

FREQ

VIN

66.5k 24.9k

150k

VIN

8.5V TO 36V D1

PDS760

10

19µH

PA2050-193

ITH

SGND

VOUT

12.4k

39.2k

475k

0.1µF

1µF

1nF

6.8µF 50V

0.005

HAT2279H

0.005

VOUT

48V

3A TO 5A

38621 F18

100µF

63V

100µF

63V

6.8µF 50V

LTC3862-1

10nF

100pF

INTVCC

GATE1

GATE2

PGND

4.7µF

10nF

6.8µF 50V

19µH

PA2050-193

10

LTC3862-1

38621f

APPLICATIONS INFORMATION

Maximum Duty Cycle Limitations

Another operating extreme occurs at high duty cycle,

when the input voltage is low and the output voltage is

high. In this case:

DMAX =VO+VF–V

IN(MIN)

VO+VF











A single-ended boost converter needs a minimum off-time

every cycle in order to allow energy transfer from the input

inductor to the output capacitor. This minimum off-time

translates to a maximum duty cycle for the converter. The

equation above can be rearranged to obtain the maximum

output voltage for a given minimum input or maximum

duty cycle.

VO(MAX ) =VIN

1–DMAX

–V

The equation for DMAX above can be used as an initial

guideline for determining the maximum duty cycle of

the application circuit. However, losses in the inductor,

input and output capacitors, the power MOSFETs, the

sense resistors and the controller (gate drive losses) all

contribute to an increasing of the duty cycle. The effect

of these losses will be to decrease the maximum output

voltage for a given minimum input voltage.

After the initial calculations have been completed for an

application circuit, it is important to build a prototype of

the circuit and measure it over the entire input voltage

range, from light load to full load, and over temperature,

in order to verify proper operation of the circuit.

Peak and Average Input Currents

The control circuit in the LTC3862-1 measures the input

current (by means of resistors in the sources of the power

MOSFETs), so the output current needs to be reﬂ ected back

to the input in order to dimension the power MOSFETs

properly. Based on the fact that, ideally, the output power

is equal to the input power, the maximum average input

current is:

IIN(MAX) =IO(MAX)

1–DMAX

The peak current in each inductor is:

IIN(PK) =1

n•1+









•IO(MAX )

1–DMAX

where n represents the number of phases and χ represents

the percentage peak-to-peak ripple current in the inductor.

For example, if the design goal is to have 30% ripple cur-

rent in the inductor, then χ = 0.30, and the peak current

is 15% greater than the average.

Inductor Selection

Given an input voltage range, operating frequency and

ripple current, the inductor value can be determined using

the following equation:

L=VIN(MIN)

ΔIL•f •D

MAX

where:

ΔIL=χ

n•IO(MAX)

1–DMAX

Choosing a larger value of ΔIL allows the use of a lower

value inductor but results in higher output voltage ripple,

greater core losses, and higher ripple current ratings for

the input and output capacitors. A reasonable starting point

is 30% ripple current in the inductor (χ = 0.3), or:

ΔIL=0.3

n•IO(MAX)

1–DMAX

LTC3862-1

38621f

APPLICATIONS INFORMATION

The inductor saturation current rating needs to be higher

than the worst-case peak inductor current during an

overload condition. If IO(MAX) is the maximum rated load

current, then the maximum current limit value (IO(CL))

would normally be chosen to be some factor (e.g., 30%)

greater than IO(MAX).

O(CL) = 1.3 • IO(MAX)

Reﬂ ecting this back to the input, where the current is being

measured, and accounting for the ripple current, gives a

minimum saturation current rating for the inductor of:

IL(SAT) 1

n•1+









•1.3 •IO(MAX)

1–DMAX

The saturation current rating for the inductor should be

determined at the minimum input voltage (which results

in the highest duty cycle and maximum input current),

maximum output current and the maximum expected core

temperature. The saturation current ratings for most com-

mercially available inductors drop at high temperature. To

verify safe operation, it is a good idea to characterize the

inductor’s core/winding temperature under the following

conditions: 1) worst-case operating conditions, 2) maxi-

mum allowable ambient temperature and 3) with the power

supply mounted in the ﬁ nal enclosure. Thermal character-

ization can be done by placing a thermocouple in intimate

contact with the winding/core structure, or by burying the

thermocouple within the windings themselves.

Remember that a single-ended boost converter is not

short-circuit protected, and that under a shorted output

condition, the output current is limited only by the input

supply capability. For applications requiring a step-up

converter that is short-circuit protected, consider using

a SEPIC or forward converter topology.

Power MOSFET Selection

The peak-to-peak gate drive level is set by the INTVCC

voltage is 10V for the LTC3862-1 under normal operat-

ing conditions. Selection criteria for the power MOSFETs

include the RDS(ON), gate charge QG, drain-to-source break-

down voltage BVDSS, maximum continuous drain current

ID(MAX), and thermal resistances RTH(JA) and RTH(JC)—both

junction-to-ambient and junction-to-case.

The gate driver for the LTC3862-1 consists of PMOS pull-

up and NMOS pull-down devices, allowing the full INTVCC

voltage to be applied to the gates during power MOSFET

switching. Nonetheless, care must be taken to ensure

that the minimum gate drive voltage is still sufﬁ cient to

full enhance the power MOSFET. Check the MOSFET data

sheet carefully to verify that the RDS(ON) of the MOSFET

is speciﬁ ed for a voltage less than or equal to the nomi-

nal INTVCC voltage of 10V. For applications that require a

power MOSFET rated at 5V, please refer to the LTC3862

data sheet.

Also pay close attention to the BVDSS speciﬁ cations for

the MOSFETs relative to the maximum actual switch volt-

age in the application. Check the switching waveforms of

the MOSFET directly on the drain terminal using a single

probe and a high bandwidth oscilloscope. Ensure that the

drain voltage ringing does not approach the BVDSS of the

MOSFET. Excessive ringing at high frequency is normally

an indicator of too much series inductance in the high di/dt

current path that includes the MOSFET, the boost diode,

the output capacitor, the sense resistor and the PCB traces

connecting these components. In some challenging ap-

plications it may be necessary to use a snubber in order

to limit the switch node dV/dt.

Finally, check the MOSFET manufacturer’s data sheet for

an avalanche energy rating (EAS). Some MOSFETs are not

rated for body diode avalanche and will fail catastrophi-

cally if the VDS exceeds the device BVDSS, even if only by

a fraction of a volt. Avalanche-rated MOSFETs are better

able to sustain high frequency drain-to-source ringing near

the device BVDSS during the turn-off transition.

Calculating Power MOSFET Switching and Conduction

Losses and Junction Temperatures

In order to calculate the junction temperature of the power

MOSFET, the power dissipated by the device must be known.

This power dissipation is a function of the duty cycle, the

load current and the junction temperature itself (due to

the positive temperature coefﬁ cient of its RDS(ON)). As a

LTC3862-1

38621f

result, some iterative calculation is normally required to

determine a reasonably accurate value.

The power dissipated by the MOSFET in a multi-phase

boost converter with n phases is:

PFET =IO(MAX)

n• 1–D

MAX

( )











•RDS(ON) •D

MAX •T

+k•V

OUT2•IO(MAX)

n• 1–D

MAX

( )

•C

RSS •f

The ﬁ rst term in the equation above represents the I2R

losses in the device, and the second term, the switching

losses. The constant, k = 1.7, is an empirical factor inversely

related to the gate drive current and has the dimension

of 1/current.

The ρT term accounts for the temperature coefﬁ cient of

the RDS(ON) of the MOSFET, which is typically 0.4%/ºC.

Figure 19 illustrates the variation of normalized RDS(ON)

over temperature for a typical power MOSFET.

From a known power dissipated in the power MOSFET, its

junction temperature can be obtained using the following

formula:

J = TA + PFET • RTH(JA)

The RTH(JA) to be used in this equation normally includes

the RTH(JC) for the device plus the thermal resistance from

the case to the ambient temperature (RTH(CA)). This value

of TJ can then be compared to the original, assumed value

used in the iterative calculation process.

It is tempting to choose a power MOSFET with a very low

RDS(ON) in order to reduce conduction losses. In doing

so, however, the gate charge QG is usually signiﬁ cantly

higher, which increases switching and gate drive losses.

Since the switching losses increase with the square of

the output voltage, applications with a low output voltage

generally have higher MOSFET conduction losses, and

high output voltage applications generally have higher

MOSFET switching losses. At high output voltages, the

highest efﬁ ciency is usually obtained by using a MOSFET

with a higher RDS(ON) and lower QG. The equation above

can easily be split into two components (conduction and

switching) and entered into a spreadsheet, in order to

compare the performance of different MOSFETs.

Programming the Current Limit

The peak sense voltage threshold for the LTC3862-1 is

75mV at low duty cycle and with a normalized slope gain of

1.00, and is measured from SENSE+ to SENSE–. Figure 20

illustrates the change in the sense threshold with varying

duty cycle and slope gain.

APPLICATIONS INFORMATION

Figure 19. Normalized Power MOSFET RDS(ON) vs Temperature

JUNCTION TEMPERATURE (°C)

–50

RT NORMALIZED ON RESISTANCE

1.0

1.5

150

38621 F19

0.5

0050 100

2.0

DUTY CYCLE (%)

MAXIMUM CURRENT SENSE THRESHOLD (mV)

20 40 60 80

38621 F20

10010030507090

SLOPE = 0.625

SLOPE = 1

SLOPE = 1.66

Figure 20. Maximum Sense Voltage Variation

with Duty Cycle and Slope Gain

LTC3862-1

38621f

For a boost converter where the current limit value is

chosen to be 30% higher than the maximum load current,

the peak current in the MOSFET and sense resistor is:

ISW(MAX) =IR(SENSE) =1

n•1+









•1.3 •IO(MAX)

1–DMAX

The sense resistor value is then:

RSENSE =VSENSE(MAX) •n• 1–D

MAX

()

1.3 • 1+









•IO(MAX)

Again, the factor n is the number of phases used, and χ

represents the percentage ripple current in the inductor.

The number 1.3 represents the factor by which the cur-

rent limit exceeds the maximum load current, IO(MAX).

For example, if the current limit needs to exceed the

maximum load current by 50%, then the 1.3 factor should

be replaced with 1.5.

The average power dissipated in the sense resistor can

easily be calculated as:

PR(SENSE) =1.3 •IO(MAX )

n• 1–D

MAX

( )











•RSENSE •D

MAX

This equation assumes no temperature coefﬁ cient for

the sense resistor. If the resistor chosen has a signiﬁ cant

temperature coefﬁ cient, then substitute the worst-case

high resistance value into the equation.

The resistor temperature can be calculated using the

equation:

D = TA + PR(SENSE) • RTH(JA)

Selecting the Output Diodes

To maximize efﬁ ciency, a fast switching diode with low

forward drop and low reverse leakage is required. The

output diode in a boost converter conducts current during

the switch off-time. The peak reverse voltage that the diode

must withstand is equal to the regulator output voltage.

The average forward current in normal operation is equal

to the output current, and the peak current is equal to the

peak inductor current:

ID(PEAK) =1

n•1+









•IO(MAX )

1–DMAX

Although the average diode current is equal to the output

current, in very high duty cycle applications (low VIN to

high VOUT) the peak diode current can be several times

higher than the average, as shown in Figure 21. In this

case check the diode manufacturer’s data sheet to ensure

that its peak current rating exceeds the peak current in

the equation above. In addition, when calculating the

power dissipation in the diode, use the value of the

forward voltage (VF) measured at the peak current, not

the average output current. Excess power will be dissi-

pated in the series resistance of the diode, which would

not be accounted for if the average output current and

forward voltage were used in the equations. Finally, this

APPLICATIONS INFORMATION

Figure 21. Diode Current Waveform for a High Duty Cycle Application

SW NODE

50V/DIV

INDUCTOR

CURRENT

1A/DIV

DIODE

CURRENT

1A/DIV

1µs/DIV 38621 F21

VIN = 12V

VOUT = 72V

LTC3862-1

38621f

additional power dissipation is important when deciding

on a diode current rating, package type, and method of

heat sinking.

To a close approximation, the power dissipated by the

diode is:

D = ID(PEAK) • VF(PEAK) • (1 – DMAX)

The diode junction temperature is:

J = TA + PD • RTH(JA)

The RTH(JA) to be used in this equation normally includes

the RTH(JC) for the device plus the thermal resistance from

the board to the ambient temperature in the enclosure.

Once the proper diode has been selected and the circuit

performance has been veriﬁ ed, measure the temperature

of the power components using a thermal probe or infrared

camera over all operating conditions to ensure a good

thermal design.

Finally, remember to keep the diode lead lengths short

and to observe proper switch-node layout (see Board

Layout Checklist) to avoid excessive ringing and increased

dissipation.

Output Capacitor Selection

Contributions of ESR (equivalent series resistance), ESL

(equivalent series inductance) and the bulk capacitance

must be considered when choosing the correct combination

of output capacitors for a boost converter application. The

effects of these three parameters on the output voltage

ripple waveform are illustrated in Figure 22 for a typical

boost converter.

The choice of component(s) begins with the maximum

acceptable ripple voltage (expressed as a percentage of

the output voltage), and how this ripple should be divided

between the ESR step and the charging/discharging ΔV.

For the purpose of simplicity we will choose 2% for the

maximum output ripple, to be divided equally between the

ESR step and the charging/discharging ΔV. This percentage

ripple will change, depending on the requirements of the

application, and the equations provided below can easily

be modiﬁ ed.

One of the key beneﬁ ts of multi-phase operation is a reduc-

tion in the peak current supplied to the output capacitor

by the boost diodes. As a result, the ESR requirement

of the capacitor is relaxed. For a 1% contribution to the

total ripple voltage, the ESR of the output capacitor can

be determined using the following equation:

ESRCOUT ≤0.01• VOUT

ID(PEAK)

where:

ID(PEAK) =1

n•1+









•IO(MAX)

1–DMAX

The factor n represents the number of phases and the factor

χ represents the percentage inductor ripple current.

APPLICATIONS INFORMATION

Figure 22. Switching Waveforms for a Boost Converter

SW1

100V/DIV

SW2

100V/DIV

VOUT

100mV/DIV

AC COUPLED

IL1

2A/DIV

IL2

2A/DIV

1µs/DIV 38621 F22

VIN = 24V

VOUT = 72V

350mA LOAD

LTC3862-1

38621f

For the bulk capacitance, which we assume contributes

1% to the total output ripple, the minimum required ca-

pacitance is approximately:

COUT ≥IO(MAX)

0.01• n • VOUT •f

For many designs it will be necessary to use one type of

capacitor to obtain the required ESR, and another type

to satisfy the bulk capacitance. For example, using a

low ESR ceramic capacitor can minimize the ESR step,

while an electrolytic capacitor can be used to supply the

required bulk C.

The voltage rating of the output capacitor must be greater

than the maximum output voltage, with sufﬁ cient derating

to account for the maximum capacitor temperature.

Because the ripple current in the output capacitor is a

square wave, the ripple current requirements for this

capacitor depend on the duty cycle, the number of phases

and the maximum output current. Figure 23 illustrates the

normalized output capacitor ripple current as a function of

duty cycle. In order to choose a ripple current rating for

the output capacitor, ﬁ rst establish the duty cycle range,

based on the output voltage and range of input voltage.

Referring to Figure 23, choose the worst-case high nor-

malized ripple current, as a percentage of the maximum

load current.

The output ripple current is divided between the various

capacitors connected in parallel at the output voltage.

Although ceramic capacitors are generally known for low

ESR (especially X5R and X7R), these capacitors suffer

from a relatively high voltage coefﬁ cient. Therefore, it is

not safe to assume that the entire ripple current ﬂ ows in

the ceramic capacitor. Aluminum electrolytic capacitors are

generally chosen because of their high bulk capacitance,

but they have a relatively high ESR. As a result, some

amount of ripple current will ﬂ ow in this capacitor. If the

ripple current ﬂ owing into a capacitor exceeds its RMS

rating, the capacitor will heat up, reducing its effective

capacitance and adversely affecting its reliability. After

the output capacitor conﬁ guration has been determined

using the equations provided, measure the individual

capacitor case temperatures in order to verify good

thermal performance.

Input Capacitor Selection

The input capacitor voltage rating in a boost converter

should comfortably exceed the maximum input voltage.

Although ceramic capacitors can be relatively tolerant of

overvoltage conditions, aluminum electrolytic capacitors

are not. Be sure to characterize the input voltage for any

possible overvoltage transients that could apply excess

stress to the input capacitors.

APPLICATIONS INFORMATION

Figure 23: Normalized Output Capacitor

Ripple Current (RMS) for a Boost Converter

0.1

IORIPPLE/IOUT

0.9

38621 F23

0.3 0.5 0.7 0.8

0.2 0.4 0.6

3.25

3.00

2.75

2.50

2.25

2.00

1.75

1.50

1.25

1.00

0.75

0.50

0.25

DUTY CYCLE OR (1-VIN/VOUT)

1-PHASE

2-PHASE

LTC3862-1

38621f

Figure 24. Normalized Input Peak-to-Peak Ripple Current

The value of the input capacitor is a function of the

source impedance, and in general, the higher the source

impedance, the higher the required input capacitance.

The required amount of input capacitance is also greatly

affected by the duty cycle. High output current applica-

tions that also experience high duty cycles can place great

demands on the input supply, both in terms of DC current

and ripple current.

The input ripple current in a multi-phase boost converter

is relatively low (compared with the output ripple current),

because this current is continuous and is being divided

between two or more inductors. Nonetheless, signiﬁ cant

stress can be placed on the input capacitor, especially

in high duty cycle applications. Figure 24 illustrates the

normalized input ripple current, where:

INORM =VIN

L•f

APPLICATIONS INFORMATION

A Design Example

Consider the LTC3862-1 application circuit is shown in

Figure 25a. The output voltage is 72V and the input voltage

range is 8.5V to 36V. The maximum output current is 1.5A

when the input voltage is 24V and 2A at an input of 32V.

Below 32V, current limit will linearly reduce the maximum

load to 0.5A at 8.5V input voltage (see Figure 25b).

1. The duty cycle range (where 1.5A is available at the

output) is:

DMAX =VO+VF–V

VO+VF











=72V +0.5V – 24V

72V +0.5V









=66.9%

DMIN =72V +0.5V – 36V

72V +0.5V









=50.3%

2. The operating frequency is chosen to be 300kHz so

the period is 3.33s. From Figure 6, the resistor from

the FREQ pin to ground is 45.3k.

3. The minimum on-time for this application operating

in CCM is:

tON(MIN) =1

f•VO+VF–V

IN(MAX)

VO+VF









=1

300kHz•

72V +0.5V – 36V

72V +0.5V









=1.678µs

The maximum DC input current is:

IIN(MAX) =IO(MAX)

1–DMAX

=1.5A

1– 0.669 =4.5A

DUTY CYCLE

$IIN/INORM

1.00

0.90

0.80

0.60

0.70

0.50

0.40

0.30

0.20

0.10

00.8

38621 F24

0.2 0.4 0.6 1.0

1-PHASE

2-PHASE

LTC3862-1

38621f

APPLICATIONS INFORMATION

Figure 25a. A 8.5V to 36V Input, 72V/2A Output 2-Phase Boost Converter Application Circuit

Figure 25b. Output Current vs Input Voltage

INPUT VOLTAGE (V)

0.5

OUTPUT LOAD CURRENT (A)

1.0

1.5

2.0

2.5

10 20 30 40

38621 F25b

4. A ripple current of 40% is chosen so the peak current

in each inductor is:

IIN(PK) =1

n•1–











•IO(MAX )

1–DMAX

2•1+0.4









•1.5A

1– 0.669 =2.7A

5. The inductor ripple current is:

ΔIL=χ

n•IO(MAX)

1–DMAX

=0.4

2•1.5A

1– 0.669 =0.9A

6. The inductor value is therefore:

L=VIN(MIN)

ΔIL•f •D

MAX =24V

0.9A • 300kHz • 0.669

=59.5µH

7. For a current limit value 30% higher than the maximum

load current:

O(CL) = 1.3 • IO(MAX) = 1.3 • 1.5A = 1.95A

The saturation current rating of the inductors must

therefore exceed:

IL(SAT) 1

n•1+









•1.3 •IO(MAX)

1–DMAX

2•1+0.4









•1.3 • 1.5A

1– 0.669 =3.5A

SENSE1+

3V8

SLOPE

BLANK

CLKOUT

SYNC

PLLFLTR

PHASEMODE

DMAX

10nF

SENSE1–

SENSE2–

SENSE2+

RUN

FREQ

VIN

45.3k 24.9k

150k

10

VIN

8.5V TO 36V D1

MURS320T3H

10

58µH

PA2050-583

ITH

SGND

VOUT

5.62k

45.3k

324k

0.1µF

1µF

1nF

6.8µF 50V

0.020

HAT2267H

0.020

VOUT

72V

2A (MAX)

38621 F25a

47µF

100V

47µF

100V

6.8µF 50V

2.2µF

100V

×6

LTC3862-1

1.5nF

100pF

INTVCC

GATE1

GATE2

PGND

4.7µF

10nF

58µH

PA2050-583

LTC3862-1

38621f

The inductor value chosen was 57.8H and the part

number is PA2050-583, manufactured by Pulse Engi-

neering. This inductor has a saturation current rating

of 5A.

8. The power MOSFET chosen for this application is

a Renesas HAT2267H. This MOSFET has a typical

RDS(ON) of 13m at VGS = 10V. The BVDSS is rated

at a minimum of 80V and the maximum continuous

drain current is 25A. The typical gate charge is 30nC

for a VGS = 10V. Last but not least, this MOSFET has

an absolute maximum avalanche energy rating EAS

of 30mJ, indicating that it is capable of avalanche

without catastrophic failure.

9. The total IC quiescent current, IC power dissipation and

maximum junction temperature are approximately:

Q(TOT) = IQ + 2 • QG(TOT) • f

= 3mA + 2 • 30nC • 300kHz = 21mA

DISS = 24V • 21mA = 504mW

J = 70°C + 504mW • 34°C/W = 87.1°C

10. The inductor ripple current was chosen to be 40%

and the maximum load current is 1.5A. For a current

limit set at 30% above the maximum load current, the

maximum switch and sense resistor currents are:

ISW(MAX) =IR(SENSE) =1

n•1+









•1.3 •IO(MAX)

1–DMAX

2•1+0.4









•1.3 • 1.5A

1– 0.669 =3.5A

11. The maximum current sense threshold for the

LTC3862-1 is 75mV at low duty cycle and a normalized

slope gain of 1.0. Using Figure 20, the maximum sense

voltage drops to 68mV at a duty cycle of 70% with a

normalized slope gain of 1, so the sense resistor is

calculated to be:

RSENSE =VSENSE(MAX)

ISW(MAX)

=68mV

3.5A =19.4mΩ

For this application a 20m, 1W surface mount resis-

tor was used for each phase.

12. The power dissipated in the sense resistors in current

limit is:

R(SENSE) =1.3 •IO(MAX)

n• 1–D

MAX

( )











•RSENSE •D

MAX

=1.3 • 1.5

2 • 1– 0.669

( )











• 0.020 • 0.669

=0.12W

13. The average current in the boost diodes is half the

output current (1.5A/2 = 0.75A), but the peak current

in each diode is:

ID(PEAK) =1

n•1+









•IO(MAX )

1–DMAX

2•1+0.4









•1.5A

1– 0.669 =2.7A

The diode chosen for this application is the

MURS320T3H, manufactured by ON Semiconductor.

This surface mount diode has a maximum average

forward current of 3A at 140°C and a maximum reverse

voltage of 200V. The maximum forward voltage drop

at 25°C is 0.875V and is 0.71V at 150°C (the positive

TC of the series resistance is compensated by the

negative TC of the diode forward voltage).

The power dissipated by the diode is approximately:

D = ID(PEAK) • VF(PEAK) • (1 – DMAX)

= 2.7A • 0.71V • (1 – 0.669) = 0.64W

14.

Two types of output capacitors are connected in paral-

lel for this application; a low ESR ceramic capacitor

and an aluminum electrolytic for bulk storage. For

a 1% contribution to the total ripple voltage, the

maximum ESR of the composite output capacitance

is approximately:

ESRCOUT ≤0.01• VOUT

ID(PEAK)

=0.01• 72V

2.7A =0.267Ω

APPLICATIONS INFORMATION

LTC3862-1

38621f

For the bulk capacitance, which we assume contributes

1% to the total output ripple, the minimum required

capacitance is approximately:

COUT ≥IO(MAX)

0.01• n • VOUT •f=1.5A

0.01• 2 • 72V • 300kHz

=3.45µF

For this application, in order to obtain both low ESR

and an adequate ripple current rating (see Figure 23),

two 47F, 100V aluminum electrolytic capacitors were

connected in parallel with six 2.2F, 100V ceramic

capacitors. Figure 26 illustrates the switching wave-

forms for this application circuit.

2. In order to help dissipate the power from the MOSFETs

and diodes, keep the ground plane on the layers closest

to the power components. Use power planes for the

MOSFETs and diodes in order to maximize the heat

spreading from these components into the PCB.

3. Place all power components in a tight area. This will

minimize the size of high current loops. The high di/dt

loops formed by the sense resistor, power MOSFET,

the boost diode and the output capacitor should be

kept as small as possible to avoid EMI.

4. Orient the input and output capacitors and current

sense resistors in a way that minimizes the distance

between the pads connected to the ground plane.

Keep the capacitors for INTVCC, 3V8 and VIN as close

as possible to LTC3862-1.

5. Place the INTVCC decoupling capacitor as close as

possible to the INTVCC and PGND pins, on the same

layer as the IC. A low ESR (X5R or better) 4.7F to

10F ceramic capacitor should be used.

6. Use a local via to ground plane for all pads that

connect to the ground. Use multiple vias for power

components.

7. Place the small-signal components away from high

frequency switching nodes on the board. The pinout

of the LTC3862-1 was carefully designed in order to

make component placement easy. All of the power

components can be placed on one side of the IC, away

from all of the small-signal components.

8. The exposed area on the bottom of the QFN package

is internally connected to PGND; however it should

not be used as the main path for high current ﬂ ow.

9. The MOSFETs should also be placed on the same

layer of the board as the sense resistors. The MOSFET

source should connect to the sense resistor using a

short, wide PCB trace.

APPLICATIONS INFORMATION

Figure 26. LTC3862-1 Switching Waveforms

for 72V Output Boost Converter

PC Board Layout Checklist

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of

the converter:

1. For lower power applications a 2-layer PC board is suf-

ﬁ cient. However, for higher power levels, a multilayer

PC board is recommended. Using a solid ground plane

and proper component placement under the circuit is

the easiest way to ensure that switching noise does

not affect the operation.

SW1

100V/DIV

SW2

100V/DIV

VOUT

200mV/DIV

AC COUPLED

IL1

2A/DIV

IL2

2A/DIV

2µs/DIV 38621 F26

VIN = 24V

VOUT = 72V

IOUT = 0.6A

LTC3862-1

38621f

APPLICATIONS INFORMATION

10. The output resistor divider should be located as

close as possible to the IC, with the bottom resistor

connected between FB and SGND. The PCB trace

connecting the top resistor to the upper terminal of

the output capacitor should avoid any high frequency

switching nodes.

11. Since the inductor acts like a current source in a

peak current mode control topology, its placement

on the board is less critical than the high di/dt com-

ponents.

12. The SENSE+ and SENSE– PCB traces should be routed

parallel to one another with minimum spacing in be-

tween all the way to the sense resistor. These traces

should avoid any high frequency switching nodes in

the layout. These PCB traces should also be Kelvin-

connected to the interior of the sense resistor pads,

in order to avoid sensing errors due to parasitic PCB

resistance IR drops.

13. If an external RC ﬁ lter is used between the sense

resistor and the SENSE+ and SENSE– pins, these ﬁ lter

components should be placed as close as possible to

the SENSE+ and SENSE– pins of the IC. Ensure that

the SENSE– line is connected to the ground only at the

point where the current sense resistor is grounded.

14. Keep the MOSFET drain nodes (SW1, SW2) away

from sensitive small-signal nodes, especially from

the opposite channel’s current-sensing signals. The

SW nodes can have slew rates in excess of 1V/ns

relative to ground and should therefore be kept on

the “output side” of the LTC3862-1.

15. Check the stress on the power MOSFETs by indepen-

dently measuring the drain-to-source voltages directly

across the devices terminals. Beware of inductive

ringing that could exceed the maximum voltage rating

of the MOSFET. If this ringing cannot be avoided and

exceeds the maximum rating of the device, choose

a higher voltage rated MOSFET or consider using a

snubber.

16. When synchronizing the LTC3862-1 to an external

clock, use a low impedance source such as a logic

gate to drive the SYNC pin and keep the lead as short

as possible.

LTC3862-1

38621f

TYPICAL APPLICATION

A 24V Input, 48V/6A Output 2-Phase Boost Converter Application Circuit

Start-Up Load Step

Efﬁ ciency

SENSE1+

3V8

SLOPE

BLANK

CLKOUT

SYNC

PLLFLTR

PHASEMODE

DMAX

10nF

SENSE1–

SENSE2–

SENSE2+

RUN

FREQ

VIN

45.3k 24.9k

150k

10

VIN

8.5V TO 36V D1

30BQ060

10

19µH

PA2050-193

ITH

SGND

VOUT

7.87k

30.1k

301k

0.1µF

1µF

1nF

22µF 25V

0.005

HAT2279H

0.005

VOUT

48V

6A (MAX)

3862 TA02a

100µF

35V

22µF 25V

10µF 50V

LTC3862-1

4.7nF

100pF

INTVCC

GATE1

GATE2

PGND

4.7µF

10nF

19µH

PA2050-193

100µF

35V

10µF 50V

RUN

5V/DIV

VIN = 24V

VOUT = 48V

RL = 100Ω

VOUT

50V/DIV

IL1

5A/DIV

IL2

5A/DIV

1ms/DIV 38621 TA02b

IOUT

5A/DIV

VIN = 24V

VOUT = 48V

ΔIOUT = 1A TO 5A

VOUT

1V/DIV

AC COUPLED

IL1

5A/DIV

IL2

5A/DIV

500µs/DIV 38621 TA02c

LOAD CURRENT (mA)

EFFICIENCY (%)

POWER LOSS (mW)

100

38621 TA02d

10000

1000

10000

100 1000

VIN = 24V

VOUT = 48V

EFFICIENCY

POWER LOSS

LTC3862-1

38621f

TYPICAL APPLICATION

A 24V Input, 107V/1.5A Output 2-Phase Boost Converter Application Circuit

Start-Up Load Step

Efﬁ ciency

SENSE1+

3V8

SLOPE

BLANK

CLKOUT

SYNC

PLLFLTR

PHASEMODE

DMAX

10nF

SENSE1–

SENSE2–

SENSE2+

RUN

FREQ

VIN

68.1k 24.9k

150k

10

VIN

8.5V TO 36V D1

PDS4150

10

58µH

ITH

SGND

VOUT

6.65k

43.5k

576k

0.1µF

1µF

1nF

22µF 25V

0.010

Si7430DP

Si743ODP

0.010

VOUT

107V

1.5A (MAX)

3862 TA03a

100µF

150V

22µF 25V

8× 1µF 250V

LTC3862-1

44pF

2200pF

INTVCC

GATE1

GATE2

PGND

4.7µF

10nF

58µH

L1, L2: CHAMPS TECHNOLOGIES HRPQA2050-57

PULSE ENGINEERING PA2050-583

RUN

5V/DIV

VIN = 24V

VOUT = 107V

ILOAD = 400mA

VOUT

50V/DIV

IL1

2A/DIV

IL2

2A/DIV

2ms/DIV 38621 TA03b

IOUT

2A/DIV

VIN = 24V

VOUT = 107V

ILOAD = 500mA TO 1.5A

VOUT

1V/DIV

AC COUPLED

IL1

2A/DIV

IL2

2A/DIV

500µs/DIV 38621 TA03c

LOAD CURRENT (mA)

EFFICIENCY (%)

POWER LOSS (mW)

100

38621 TA03d

100000

1000

1000088

10000

100 1000

VIN = 24V

VOUT = 107V

EFFICIENCY

POWER LOSS

LTC3862-1

38621f

PACKAGE DESCRIPTION

GN Package

24-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

.337 – .344*

(8.560 – 8.738)

GN24 (SSOP) 0204

345678 9 10 11 12

.229 – .244

(5.817 – 6.198)

.150 – .157**

(3.810 – 3.988)

161718192021222324 15 1413

.016 – .050

(0.406 – 1.270)

.015 p .004

(0.38 p 0.10) s 45o

0o – 8o TYP

.0075 – .0098

(0.19 – 0.25)

.0532 – .0688

(1.35 – 1.75)

.008 – .012

(0.203 – 0.305)

TYP

.004 – .0098

(0.102 – 0.249)

.0250

(0.635)

BSC

.033

(0.838)

REF

.254 MIN

RECOMMENDED SOLDER PAD LAYOUT

.150 – .165

.0250 BSC.0165 p.0015

.045 p.005

* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

INCHES

(MILLIMETERS)

NOTE:

1. CONTROLLING DIMENSION: INCHES

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

FE Package

24-Lead Plastic TSSOP (4.4mm)

(Reference LTC DWG # 05-08-1663)

Exposed Pad Variation AA

FE24 (AA) TSSOP 0208 REV Ø

0.09 – 0.20

(.0035 – .0079)

0o – 8o

0.25

REF

RECOMMENDED SOLDER PAD LAYOUT

0.50 – 0.75

(.020 – .030)

4.30 – 4.50*

(.169 – .177)

134

5678 9 10 11 12

14 13

7.70 – 7.90*

(.303 – .311)

3.25

(.128)

2.74

(.108)

2021222324 19 18 17 16 15

1.20

(.047)

MAX

0.05 – 0.15

(.002 – .006)

0.65

(.0256)

BSC 0.195 – 0.30

(.0077 – .0118)

TYP

2.74

(.108)

0.45 p0.05

0.65 BSC

4.50 p0.10

6.60 p0.10

1.05 p0.10

3.25

(.128)

MILLIMETERS

(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.150mm (.006") PER SIDE

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

SEE NOTE 4

4. RECOMMENDED MINIMUM PCB METAL SIZE

FOR EXPOSED PAD ATTACHMENT

6.40

(.252)

BSC

LTC3862-1

38621f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

PACKAGE DESCRIPTION

UH Package

24-Lead Plastic QFN (5mm × 5mm)

(Reference LTC DWG # 05-08-1747 Rev Ø)

5.00 ± 0.10

NOTE:

1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

PIN 1

TOP MARK

(NOTE 6)

0.55 ± 0.10

BOTTOM VIEW—EXPOSED PAD

3.25 REF

3.20 ± 0.10

0.75 ± 0.05 R = 0.115

TYP

0.30 ± 0.05

(UH24) QFN 1206 REV Ø

0.65 BSC

0.200 REF

0.00 – 0.05

0.75 ±0.05

3.25 REF

3.90 ±0.05

5.40 ±0.05

0.30 ± 0.05

PACKAGE OUTLINE

0.65 BSC

RECOMMENDED SOLDER PAD LAYOUT

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

PIN 1 NOTCH

R = 0.30 TYP

OR 0.35 × 45°

CHAMFER

R = 0.05

TYP

3.20 ± 0.05

LTC3862-1

38621f

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

LT 1008 • PRINTED IN USA

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