TLV5628C, TLV5628I OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS108A - JANUARY 1995 - REVISED NOVEMBER 1995 D D D D D D D D D DW OR N PACKAGE (TOP VIEW) Eight 8-Bit Voltage Output DACs 3-V Single Supply Operation Serial Interface High-Impedance Reference Inputs Programmable for 1 or 2 Times Output Range Simultaneous Update Facility Internal Power-On Reset Low Power Consumption Half-Buffered Output DACB DACA GND DATA CLK VDD DACE DACF 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 DACC DACD REF1 LDAC LOAD REF2 DACH DACG applications D D D D D D Programmable Voltage Sources Digitally Controlled Amplifiers/Attenuators Mobile Communications Automatic Test Equipment Process Monitoring and Control Signal Synthesis description The TLV5628C and TLV5628I are octal 8-bit voltage output digital-to-analog converters (DACs) with buffered reference inputs (high impedance). The DACs produce an output voltage that varies between one or two times the reference voltages and GND, and the DACs are monotonic. The device is simple to use, running from a single supply of 3 to 3.6 V. A power-on reset function is incorporated to ensure repeatable start-up conditions. Digital control of the TLV5628C and TLV5628I is over a simple 3-wire serial bus that is CMOS compatible and easily interfaced to all popular microprocessor and microcontroller devices. The 12-bit command word comprises 8 bits of data, 3 DAC select bits and a range bit, the latter allowing selection between the times 1 or times 2 output range. The DAC registers are double buffered, allowing a complete set of new values to be written to the device, then all DAC outputs are updated simultaneously through control of the LDAC terminal. The digital inputs feature Schmitt triggers for high noise immunity. The 16-terminal small-outline D package allows digital control of analog functions in space-critical applications. The TLV5628C is characterized for operation from 0C to 70C. The TLV5628I is characterized for operation from - 40C to 85C. The TLV5628C and TLV5628I do not require external trimming. AVAILABLE OPTIONS PACKAGE TA SMALL OUTLINE (DW) PLASTIC DIP (N) 0C to 70C TLV5628CDW TLV5628CN - 40C to 85C TLV5628IDW TLV5628IN Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 TLV5628C, TLV5628I OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS108A - JANUARY 1995 - REVISED NOVEMBER 1995 functional block diagram REF1 + - DAC 9 Latch Latch 8 Latch Latch 8 Latch Latch 8 Latch Latch 8 DAC REF2 + - DAC DAC CLK DATA Serial Interface x2 + - DACA x2 + - DACD x2 + - DACE x2 + - DACH Power-On Reset LDAC LOAD Terminal Functions TERMINAL NAME 2 NO. I/O DESCRIPTION CLK 5 I Serial-interface clock, data enters on the negative edge DACA 2 O DACA analog output DACB 1 O DACB analog output DACC 16 O DACC analog output DACD 15 O DACD analog output DACE 7 O DACE analog output DACF 8 O DACF analog output DACG 9 O DACG analog output DACH 10 O DACH analog output DATA 4 I Serial-interface digital data input GND 3 I Ground return and reference terminal LDAC 13 I DAC-update latch control LOAD 12 I Serial-interface load control REF1 14 I Reference voltage input to DACA REF2 11 I Reference voltage input to DACB VDD 6 I Positive supply voltage POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TLV5628C, TLV5628I OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS108A - JANUARY 1995 - REVISED NOVEMBER 1995 detailed description The TLV5628 is implemented using eight resistor-string DACs. The core of each DAC is a single resistor with 256 taps, corresponding to the 256 possible codes listed in Table 1. One end of each resistor string is connected to the GND terminal and the other end is fed from the output of the reference input buffer. Monotonicity is maintained by use of the resistor strings. Linearity depends upon the matching of the resistor elements and upon the performance of the output buffer. Because the inputs are buffered, the DACs always present a high-impedance load to the reference sources. There are two input reference terminals; REF1 is used for DACA through DACD and REF2 is used by DACE through DACH. Each DAC output is buffered by a configurable-gain output amplifier, which can be programmed to times 1 or times 2 gain. On power-up, the DACs are reset to CODE 0. Each output voltage is given by: V (DACA|B|C|D|E|F|G|H) O + REF CODE 256 (1 ) RNG bit value) where CODE is in the range of 0 to 255 and the range (RNG) bit is a 0 or 1 within the serial-control word. data interface With LOAD high, data is clocked into the DATA terminal on each falling edge of CLK. Once all data bits have been clocked in, LOAD is pulsed low to transfer the data from the serial-input register to the selected DAC as shown in Figure 1. When LDAC is low, the selected DAC output voltage is updated and LOAD goes low. When LDAC is high during serial programming, the new value is stored within the device and can be transferred to the DAC output at a later time by pulsing LDAC low as shown in Figure 2. Data is entered MSB first. Data transfers using two 8 clock cycle periods are shown in Figures 3 and 4. CLK tsu(DATA-CLK) tv(DATA-CLK) DATA A2 A1 A0 tsu(LOAD-CLK) RNG D7 D6 D5 D4 D2 D1 D0 tsu(CLK-LOAD) tw(LOAD) LOAD DAC Update Figure 1. LOAD-Controlled Update (LDAC = Low) CLK tsu(DATA-CLK) tv(DATA-CLK) DATA A2 A1 A0 RNG D7 D6 D5 D4 D2 D1 D0 tsu(LOAD - LDAC) LOAD tw(LDAC) LDAC DAC Update Figure 2. LDAC-Controlled Update POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 LOAD IIIIIIIIIII IIIIIIIIIII A1 A0 IIII IIII RNG D7 D6 D5 D4 D3 IIII IIII D2 D1 D0 D2 D1 D0 LDAC Figure 3. Load Controlled Update Using 8-Bit Serial Word (LDAC = Low) CLK Low CLK POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 DATA IIIIIIIIIII IIIIIIIIIII A1 A0 III III RNG D7 D6 D5 D4 LOAD LDAC Figure 4. LDAC Controlled Update Using 8-Bit Serial Word D3 IIIII IIIII Template Release Date: 7-11-94 DATA TLV5628C, TLV5628I OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS CLK SLAS108A - JANUARY 1995 - REVISED NOVEMBER 1995 4 CLK Low TLV5628C, TLV5628I OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS108A - JANUARY 1995 - REVISED NOVEMBER 1995 data interface (continued) Table 2 lists the A2, A1, and A0 bits and the selection of the updated DACs. The RNG bit controls the DAC output range. When RNG = low, the output range is between the applied reference voltage and GND, and when RNG = high, the range is between twice the applied reference voltage and GND. Table 1. Ideal Output Transfer D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 OUTPUT VOLTAGE GND 0 0 0 0 0 0 0 1 (1/256) x REF (1+RNG) * * * * * * * * * * * * * * * * * * 0 1 1 1 1 1 1 1 (127/256) x REF (1+RNG) 1 0 0 0 0 0 0 0 (128/256) x REF (1+RNG) * * * * * * * * * * * * * * * * * * 1 1 1 1 1 1 1 1 (255/256) x REF (1+RNG) Table 2. Serial Input Decode A2 A1 A0 DAC UPDATED 0 0 0 DACA 0 0 1 DACB 0 1 0 DACC 0 1 1 DACD 1 0 0 DACE 1 0 1 DACF 1 1 0 DACG 1 1 1 DACH POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 TLV5628C, TLV5628I OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS108A - JANUARY 1995 - REVISED NOVEMBER 1995 linearity, offset, and gain error When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With a positive offset, the output voltage changes on the first code change. With a negative offset the output voltage may not change with the first code depending on the magnitude of the offset voltage. The output amplifier, with a negative voltage offset, attempts to drive the output to a negative voltage. However, since the most negative supply rail is ground, the output cannot drive to a negative voltage. So when the output offset voltage is negative, the output voltage remains at 0 volts until the input code value produces a sufficient output voltage to overcome the inherent negative offset voltage resulting in the transfer function shown in Figure 5. Output Voltage 0V DAC Code Negative Offset Figure 5. Effect of Negative Offset (Single Supply) The negative offset error produces a breakpoint, not a linearity error. The transfer function would follow the dotted line if the output buffer could drive to a negative voltage. For a DAC, linearity is measured between zero input code (all inputs 0) and full scale code (all inputs 1) after offset and full scale is adjusted out or accounted for in some way. However, single supply operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. The linearity in the unipolar mode is measured between full scale code and the lowest code which produces a positive output voltage. The code is calculated from the maximum specification for the negative offset. equivalent inputs and outputs INPUT CIRCUIT OUTPUT CIRCUIT VDD VDD _ Input from Decoded DAC Register String Vref Input To DAC Resistor String + DAC Voltage Output x1 Output Range x 2 Select 84 k 84 k GND 6 ISINK 60 A Typical GND POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TLV5628C, TLV5628I OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS108A - JANUARY 1995 - REVISED NOVEMBER 1995 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage (VDD - GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Digital input voltage range, VID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3 V to VDD + 0.3 V Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3 V to VDD + 0.3 V Operating free-air temperature range, TA: TLV5628C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C TLV5628I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 85C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 50C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions Supply voltage, VDD High-level digital input voltage, VIH MIN NOM MAX UNIT 2.7 3.3 5.25 V 0.8 VDD Low-level digital input voltage, VIL V 0.8 Reference voltage, Vref [A|B|C|D|E|F|G|H], X1 gain VDD- 1.5 V V Load resistance, RL 10 k Setup time, data input, tsu(DATA-CLK) (see Figures 1 and 2) 50 ns Valid time, data input valid after CLK, tv(DATA-CLK) (see Figures 1 and 2) 50 ns Setup time, CLK eleventh falling edge to LOAD, tsu(CLK-LOAD) (see Figure 1) 50 ns Setup time, LOAD to CLK, tsu(LOAD-CLK) (see Figure 1) 50 ns Pulse duration, LOAD, tw(LOAD) (see Figure 1) 250 ns Pulse duration, LDAC, tw(LDAC) (see Figure 2) 250 ns Setup time, LOAD to LDAC, tsu(LOAD-LDAC) (see Figure 2) 0 CLK frequency Operating free-air free air temperature, temperature TA TLV5628C TLV5628I POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 ns 1 MHz 0 70 C - 40 85 C 7 TLV5628C, TLV5628I OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS108A - JANUARY 1995 - REVISED NOVEMBER 1995 electrical characteristics over recommended operating free-air temperature range, VDD = 3 V to 3.6 V, Vref = 2 V, x 1 gain output range (unless otherwise noted) PARAMETER IIH IIL High-level digital input current IO(sink) IO(source) Output sink current Ci TEST CONDITIONS Low-level digital input current Each DAC output Output source current Linearity error (end point corrected) EZS Zero-scale error Zero-scale error temperature coefficient Full-scale error temperature coefficient Vref = 1.25 V, x 2 gain (see Note 5) Vref = 1.25 V, x 2 gain (see Note 6) Power supply sensitivity See Notes 7 and 8 Full-scale error A pF 4 Vref = 1.5 V Vref = 1.25 V, x 2 gain (see Note 1) Vref = 1.25 V, x 2 gain (see Note 2) Vref = 1.25 V, x 2 gain (see Note 3) Vref = 1.25 V, x 2 gain (see Note 4) 10 A VDD = 3.3 V VDD = 3.3 V, Differential linearity error A mA 15 Reference input current UNIT 10 1 15 EL ED MAX 20 Reference input capacitance Supply current PSRR TYP Input capacitance IDD Iref EFS MIN VI = VDD VI = 0 V 0 mA 10 A 1 LSB 0.9 LSB 30 mV V/C 10 60 mV 25 V/C 0.5 mV/V NOTES: 1. Integral nonlinearity (INL) is the maximum deviation of the output from the line between zero-scale and full scale (excluding the effects of zero code and full-scale errors). 2. Differential nonlinearity (DNL) is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. 3. Zero-scale error is the deviation from zero voltage output when the digital input code is zero. 4. Zero-scale error temperature coefficient is given by: ZSETC = [ZSE(Tmax) - ZSE(Tmin)]/Vref x 106/(Tmax - Tmin). 5. Full-scale error is the deviation from the ideal full-scale output (Vref - 1 LSB) with an output load of 10 k . 6. Full-scale temperature coefficient is given by: FSETC = [FSE(Tmax) - FSE (Tmin)]/Vref x 106/(Tmax - Tmin). 7. Zero-scale error rejection ratio (ZSE-RR) is measured by varying the VDD voltage from 4.5 V to 5.5 V dc and measuring the effect of this signal on the zero-code output voltage. 8. Full-scale error rejection ratio (FSE-RR) is measured by varing the VDD voltage from 3 V to 3.6 V dc and measuring the effect of this signal on the full-scale output voltage. operating characteristics over recommended operating free-air temperature range, VDD = 3 V to 3.6 V, Vref = 2 V, x 1 gain output range (unless otherwise noted) TEST CONDITIONS Output slew rate CL = 100 pF, RL = 10 k Output settling time To 0.5 LSB, CL = 100 pF, Large-signal bandwidth MIN TYP 1 MAX UNIT V/s 10 s Measured at - 3 dB point 100 kHz Digital crosstalk CLK = 1-MHz square wave measured at DACA-DACH - 50 dB Reference feedthrough See Note 10 - 60 dB Channel-to-channel isolation See Note 11 - 60 dB Reference input bandwidth See Note 12 100 kHz RL = 10 k, See Note 9 NOTES: 9. Settling time is the time for the output signal to remain within 0.5 LSB of the final measured value for a digital input code change of 00 hex to FF hex or FF hex to 00 hex. For TLC5628C VDD = 5 V, Vref = 2 V and range = x 2. For TLC5628I VDD = 3 V, Vref = 1.25 V and range x 2. 10. Reference feedthrough is measured at any DAC output with an input code = 00 hex with a Vref input = 1 V dc + 1 VPP at 10 kHz. 11. Channel-to-channel isolation is measured by setting the input code of one DAC to FF hex and the code of all other DACs to 00 hex with Vref input = 1 V dc + 1 VPP at 10 kHz. 12. Reference bandwidth is a -3 dB bandwidth with an input at Vref = 1.25 V dc + 2 VPP and with a full-scale digital input code. 8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TLV5628C, TLV5628I OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS108A - JANUARY 1995 - REVISED NOVEMBER 1995 PARAMETER MEASUREMENT INFORMATION TLV5628 DACA DACB * * * DACH 10 k CL = 100 pF Figure 6. Slewing Settling Time and Linearity Measurements TYPICAL CHARACTERISTICS NEGATIVE FALL TIME AND SETTLING TIME 3 3 2.5 2.5 2 2 VO - Output Voltage - V VO - Output Voltage - V POSITIVE RISE TIME AND SETTLING TIME 1.5 1 VDD = 3 V TA = 25C Code 00 to FF Hex Range = x2 Vref = 1.25 V (see Note A) 0.5 0 - 0.5 VDD = 3 V TA = 25C Code FF to 00 Hex Range = x2 Vref = 1.25 V (see Note B) 1.5 1 0.5 0 - 0.5 -1 -1 0 2 4 6 8 10 12 Time - s 14 16 18 20 NOTE A: Rise time = 2.05 s, positive slew rate = 0.96 V/s, settling time = 4.5 s. 0 2 4 6 8 10 12 14 16 18 20 Time - s NOTE B: Fall time = 4.25 s, negative slew rate = 0.46 V/s, settling time = 8.5 s. Figure 8 Figure 7 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 TLV5628C, TLV5628I OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS108A - JANUARY 1995 - REVISED NOVEMBER 1995 TYPICAL CHARACTERISTICS DAC OUTPUT VOLTAGE vs LOAD DAC OUTPUT VOLTAGE vs LOAD 3 1.6 1.4 VO - DAC Output Voltage - V VO - DAC Output Voltage - V 2.8 2.6 2.4 2.2 2 1.8 1.6 VDD = 3 V, Vref = 1.5 V, Range = 2x 1.4 1.2 1 0.8 0.6 0.4 VDD = 3 V, Vref = 1.5 V, Range = 1x 0.2 1.2 1 0 10 20 30 40 50 60 Load - k 70 80 0 90 100 0 10 20 30 40 Figure 9 Figure 10 SUPPLY CURRENT vs TEMPERATURE 1.2 Range = x 2 Input Code = 255 VDD = 3 V Vref 1.25 V I DD - Supply Current - mA 1.15 1.1 1.05 1 0.95 0.9 0.85 0.8 - 50 0 50 t - Temperature - C Figure 11 10 50 60 Load - k POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 100 70 80 90 100 TLV5628C, TLV5628I OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS108A - JANUARY 1995 - REVISED NOVEMBER 1995 APPLICATION INFORMATION _ TLV5628 DACA DACB * * * DACH R NOTE A: Resistor R w 10 k + VO Figure 12. Output Buffering Scheme POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 11 TLV5628C, TLV5628I OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS108A - JANUARY 1995 - REVISED NOVEMBER 1995 MECHANICAL DATA DW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 16 PIN SHOWN PINS ** 0.050 (1,27) 16 20 24 28 A MAX 0.410 (10,41) 0.510 (12,95) 0.610 (15,49) 0.710 (18,03) A MIN 0.400 (10,16) 0.500 (12,70) 0.600 (15,24) 0.700 (17,78) DIM 0.020 (0,51) 0.014 (0,35) 16 0.010 (0,25) M 9 0.419 (10,65) 0.400 (10,15) 0.299 (7,59) 0.293 (7,45) 0.010 (0,25) NOM Gage Plane 0.010 (0,25) 1 8 0- 8 A 0.050 (1,27) 0.016 (0,40) Seating Plane 0.104 (2,65) MAX 0.012 (0,30) 0.004 (0,10) 0.004 (0,10) 4040000 / B 10/94 NOTES: A. B. C. D. 12 All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MS-013 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TLV5628C, TLV5628I OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS108A - JANUARY 1995 - REVISED NOVEMBER 1995 MECHANICAL DATA N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE 16 PIN SHOWN A 16 PINS ** 9 14 16 18 20 A MAX 0.775 (19,69) 0.775 (19,69) 0.920 (23.37) 0.975 (24,77) A MIN 0.745 (18,92) 0.745 (18,92) 0.850 (21.59) 0.940 (23,88) DIM 0.260 (6,60) 0.240 (6,10) 1 8 0.070 (1,78) MAX 0.035 (0,89) MAX 0.310 (7,87) 0.290 (7,37) 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0- 15 0.010 (0,25) M 0.010 (0,25) NOM 14 Pin Only 4040049 / C 7/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 (20-pin package is shorter than MS-001) POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 13 PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TLV5628CDW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV5628CDWG4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV5628CDWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV5628CDWRG4 ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV5628CN ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPD N / A for Pkg Type TLV5628CNE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPD N / A for Pkg Type TLV5628IDW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV5628IDWG4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV5628IDWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV5628IDWRG4 ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV5628IN ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPD N / A for Pkg Type TLV5628INE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPD N / A for Pkg Type Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2006 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLV5628CDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 TLV5628IDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV5628CDWR SOIC DW 16 2000 346.0 346.0 33.0 TLV5628IDWR SOIC DW 16 2000 346.0 346.0 33.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications. TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Amplifiers Data Converters DSP Clocks and Timers Interface Logic Power Mgmt Microcontrollers RFID RF/IF and ZigBee(R) Solutions amplifier.ti.com dataconverter.ti.com dsp.ti.com www.ti.com/clocks interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com www.ti-rfid.com www.ti.com/lprf Applications Audio Automotive Broadband Digital Control Medical Military Optical Networking Security Telephony Video & Imaging Wireless www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/medical www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright (c) 2008, Texas Instruments Incorporated