TLV5628C, TLV5628I
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS108A – JANUARY 1995 – REVISED NOVEMBER 1995
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Eight 8-Bit Voltage Output DACs
D
3-V Single Supply Operation
D
Serial Interface
D
High-Impedance Reference Inputs
D
Programmable for 1 or 2 Times Output
Range
D
Simultaneous Update Facility
D
Internal Power-On Reset
D
Low Power Consumption
D
Half-Buffered Output
applications
D
Programmable Voltage Sources
D
Digitally Controlled Amplifiers/Attenuators
D
Mobile Communications
D
Automatic Test Equipment
D
Process Monitoring and Control
D
Signal Synthesis
description
The TLV5628C and TLV5628I are octal 8-bit voltage output digital-to-analog converters (DACs) with buffered
reference inputs (high impedance). The DACs produce an output voltage that varies between one or two times
the reference voltages and GND, and the DACs are monotonic. The device is simple to use, running from a
single supply of 3 to 3.6 V. A power-on reset function is incorporated to ensure repeatable start-up conditions.
Digital control of the TLV5628C and TLV5628I is over a simple 3-wire serial bus that is CMOS compatible and
easily interfaced to all popular microprocessor and microcontroller devices. The 12-bit command word
comprises 8 bits of data, 3 DAC select bits and a range bit, the latter allowing selection between the times 1
or times 2 output range. The DAC registers are double buffered, allowing a complete set of new values to be
written to the device, then all DAC outputs are updated simultaneously through control of the LDAC terminal.
The digital inputs feature Schmitt triggers for high noise immunity.
The 16-terminal small-outline D package allows digital control of analog functions in space-critical applications.
The TLV5628C is characterized for operation from 0°C to 70°C. The TLV5628I is characterized for operation
from –40°C to 85°C. The TLV5628C and TLV5628I do not require external trimming.
AVAILABLE OPTIONS
PACKAGE
TASMALL OUTLINE
(DW) PLASTIC DIP
(N)
0°C to 70°C TLV5628CDW TLV5628CN
–40°C to 85°C TLV5628IDW TLV5628IN
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DACB
DACA
GND
DATA
CLK
VDD
DACE
DACF
DACC
DACD
REF1
LDAC
LOAD
REF2
DACH
DACG
DW OR N PACKAGE
(TOP VIEW)
TLV5628C, TLV5628I
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS108A – JANUARY 1995 – REVISED NOVEMBER 1995
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
Power-On
Reset
Serial
Interface
× 2
DAC
LatchLatch
Latch Latch DAC × 2
× 2
DAC
LatchLatch
Latch Latch DAC × 2
LDAC
REF1 +
–
+
–
+
–
+
–
+
–
+
–
REF2
CLK
DATA
LOAD
DACA
DACD
DACE
DACH
9 8
8
8
8
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
CLK 5 I Serial-interface clock, data enters on the negative edge
DACA 2 O DACA analog output
DACB 1 O DACB analog output
DACC 16 O DACC analog output
DACD 15 O DACD analog output
DACE 7 O DACE analog output
DACF 8 O DACF analog output
DACG 9 O DACG analog output
DACH 10 O DACH analog output
DATA 4 I Serial-interface digital data input
GND 3 I Ground return and reference terminal
LDAC 13 I DAC-update latch control
LOAD 12 I Serial-interface load control
REF1 14 I Reference voltage input to DACA
REF2 11 I Reference voltage input to DACB
VDD 6 I Positive supply voltage
TLV5628C, TLV5628I
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS108A – JANUARY 1995 – REVISED NOVEMBER 1995
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
detailed description
The TLV5628 is implemented using eight resistor-string DACs. The core of each DAC is a single resistor with
256 taps, corresponding to the 256 possible codes listed in T able 1. One end of each resistor string is connected
to the GND terminal and the other end is fed from the output of the reference input buffer. Monotonicity is
maintained by use of the resistor strings. Linearity depends upon the matching of the resistor elements and upon
the performance of the output buffer. Because the inputs are buffered, the DACs always present a
high-impedance load to the reference sources. There are two input reference terminals; REF1 is used for DACA
through DACD and REF2 is used by DACE through DACH.
Each DAC output is buffered by a configurable-gain output amplifier, which can be programmed to times 1 or
times 2 gain.
On power-up, the DACs are reset to CODE 0.
Each output voltage is given by:
VO(DACA|B|C|D|E|F|G|H)
+
REF
CODE
256
(1
)
RNG bit value)
where CODE is in the range of 0 to 255 and the range (RNG) bit is a 0 or 1 within the serial-control word.
data interface
With LOAD high, data is clocked into the DATA terminal on each falling edge of CLK. Once all data bits have
been clocked in, LOAD is pulsed low to transfer the data from the serial-input register to the selected DAC as
shown in Figure 1. When LDAC is low , the selected DAC output voltage is updated and LOAD goes low . When
LDAC is high during serial programming, the new value is stored within the device and can be transferred to
the DAC output at a later time by pulsing LDAC low as shown in Figure 2. Data is entered MSB first. Data
transfers using two 8 clock cycle periods are shown in Figures 3 and 4.
A2 A1 A0 RNG D7 D6 D5 D4 D2 D1 D0
DAC Update
CLK
DATA
LOAD
tsu(DATA-CLK)
tv(DATA-CLK)
tsu(CLK-LOAD) tw(LOAD)
tsu(LOAD-CLK)
Figure 1. LOAD-Controlled Update (LDAC = Low)
CLK
DATA
LOAD
LDAC
DAC Update
A2 A1 A0 RNG D7 D6 D5 D4 D2 D1 D0
tsu(DATA-CLK)
tv(DATA-CLK)
tw(LDAC)
tsu(LOAD–LDAC)
Figure 2. LDAC-Controlled Update
TLV5628C, TLV5628I
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS108A – JANUARY 1995 – REVISED NOVEMBER 1995
T
emp
l
ate
R
e
l
ease
D
ate:
7
–
11
–
94
4POST OFFICE BOX 655303 DALLAS, TEXAS 75265
•
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
A1 A0 RNG D7 D6 D5 D4 D3 D2 D1 D0
CLK
DATA
LOAD
LDAC
CLK Low
Figure 3. Load Controlled Update Using 8-Bit Serial Word (LDAC = Low)
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
A1 A0 RNG D7 D6 D5 D4 D3 D2 D1 D0
CLK
DATA
LOAD
LDAC
CLK Low
Figure 4. LDAC Controlled Update Using 8-Bit Serial Word
TLV5628C, TLV5628I
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS108A – JANUARY 1995 – REVISED NOVEMBER 1995
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
data interface (continued)
T able 2 lists the A2, A1, and A0 bits and the selection of the updated DACs. The RNG bit controls the DAC output
range. When RNG = low, the output range is between the applied reference voltage and GND, and when
RNG = high, the range is between twice the applied reference voltage and GND.
Table 1. Ideal Output Transfer
D7 D6 D5 D4 D3 D2 D1 D0 OUTPUT VOLTAGE
0 0 0 0 0 0 0 0 GND
00000001 (1/256) × REF (1+RNG)
•••••••• •
•••••••• •
01111111 (127/256) × REF (1+RNG)
10000000 (128/256) × REF (1+RNG)
•••••••• •
•••••••• •
11111111 (255/256) × REF (1+RNG)
Table 2. Serial Input Decode
A2 A1 A0 DAC UPDATED
0 0 0 DACA
0 0 1 DACB
0 1 0 DACC
0 1 1 DACD
1 0 0 DACE
1 0 1 DACF
1 1 0 DACG
1 1 1 DACH
TLV5628C, TLV5628I
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS108A – JANUARY 1995 – REVISED NOVEMBER 1995
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
linearity, offset, and gain error
When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With
a positive offset, the output voltage changes on the first code change. With a negative of fset the output voltage
may not change with the first code depending on the magnitude of the offset voltage.
The output amplifier , with a negative voltage offset, attempts to drive the output to a negative voltage. However,
since the most negative supply rail is ground, the output cannot drive to a negative voltage.
So when the output offset voltage is negative, the output voltage remains at 0 volts until the input code value
produces a sufficient output voltage to overcome the inherent negative offset voltage resulting in the transfer
function shown in Figure 5.
DAC Code
Output
Voltage
0 V
Negative
Offset
Figure 5. Effect of Negative Offset (Single Supply)
The negative offset error produces a breakpoint, not a linearity error. The transfer function would follow the
dotted line if the output buffer could drive to a negative voltage.
For a DAC, linearity is measured between zero input code (all inputs 0) and full scale code (all inputs 1) after
offset and full scale is adjusted out or accounted for in some way. However, single supply operation does not
allow for adjustment when the offset is negative due to the breakpoint in the transfer function. The linearity in
the unipolar mode is measured between full scale code and the lowest code which produces a positive output
voltage.
The code is calculated from the maximum specification for the negative offset.
equivalent inputs and outputs
GND
Vref
Input
VDD
To DAC
Resistor
String
_
+
VDD
DAC
Voltage Output
ISINK
60 µA
Typical
84 kΩ
84 kΩ
× 1
× 2
Output
Range
Select
Input from
Decoded DAC
Register String
INPUT CIRCUIT OUTPUT CIRCUIT
GND
TLV5628C, TLV5628I
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS108A – JANUARY 1995 – REVISED NOVEMBER 1995
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage (VDD – GND) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital input voltage range, VID GND – 0.3 V to VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference input voltage range GND – 0.3 V to VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: TLV5628C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TLV5628I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –50°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 230°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, VDD 2.7 3.3 5.25 V
High-level digital input voltage, VIH 0.8 VDD V
Low-level digital input voltage, VIL 0.8 V
Reference voltage, V ref [A|B|C|D|E|F|G|H], X1 gain VDD–1.5 V
Load resistance, RL10 kΩ
Setup time, data input, tsu(DATA-CLK) (see Figures 1 and 2) 50 ns
Valid time, data input valid after CLK↓, tv(DATA-CLK) (see Figures 1 and 2) 50 ns
Setup time, CLK eleventh falling edge to LOAD, tsu(CLK-LOAD) (see Figure 1) 50 ns
Setup time, LOAD↑ to CLK↓, tsu(LOAD-CLK) (see Figure 1) 50 ns
Pulse duration, LOAD, tw(LOAD) (see Figure 1) 250 ns
Pulse duration, LDAC, tw(LDAC) (see Figure 2) 250 ns
Setup time, LOAD↑ to LDAC↓, tsu(LOAD-LDAC) (see Figure 2) 0 ns
CLK frequency 1 MHz
O
p
erating free air tem
p
erature TA
TLV5628C 0 70 °C
Operating
free
-
air
temperat
u
re
,
T
ATLV5628I –40 85 °C
TLV5628C, TLV5628I
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS108A – JANUARY 1995 – REVISED NOVEMBER 1995
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range,
VDD = 3 V to 3.6 V, Vref = 2 V, × 1 gain output range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IIH High-level digital input current VI = VDD ±10 µA
IIL Low-level digital input current VI = 0 V ±10 µA
IO(sink) Output sink current
Each DAC out
p
ut
20 µA
IO(source) Output source current
Each
DAC
o
u
tp
u
t
1 mA
Ci
Input capacitance 15 p
F
C
iReference input capacitance 15
pF
IDD Supply current VDD = 3.3 V 4 mA
Iref Reference input current VDD = 3.3 V, V ref = 1.5 V ±10 µA
ELLinearity error (end point corrected) V ref = 1.25 V, ×2 gain (see Note 1) ±1 LSB
EDDifferential linearity error V ref = 1.25 V, ×2 gain (see Note 2) ±0.9 LSB
EZS Zero-scale error V ref = 1.25 V, ×2 gain (see Note 3) 0 30 mV
Zero-scale error temperature coefficient V ref = 1.25 V, ×2 gain (see Note 4) 10 µV/°C
EFS Full-scale error V ref = 1.25 V, ×2 gain (see Note 5) ±60 mV
Full-scale error temperature coefficient Vref = 1.25 V, ×2 gain (see Note 6) ±25 µV/°C
PSRR Power supply sensitivity See Notes 7 and 8 0.5 mV/V
NOTES: 1. Integral nonlinearity (INL) is the maximum deviation of the output from the line between zero-scale and full scale (excluding the
effects of zero code and full-scale errors).
2. Differential nonlinearity (DNL) is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes.
Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code.
3. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
4. Zero-scale error temperature coefficient is given by: ZSETC = [ZSE(Tmax) – ZSE(Tmin)]/Vref × 106/(Tmax – Tmin).
5. Full-scale error is the deviation from the ideal full-scale output (V ref – 1 LSB) with an output load of 10 kΩ.
6. Full-scale temperature coefficient is given by: FSETC = [FSE(Tmax) – FSE (Tmin)]/Vref × 106/(Tmax – Tmin).
7. Zero-scale error rejection ratio (ZSE-RR) is measured by varying the VDD voltage from 4.5 V to 5.5 V dc and measuring the effect
of this signal on the zero-code output voltage.
8. Full-scale error rejection ratio (FSE-RR) is measured by varing the VDD voltage from 3 V to 3.6 V dc and measuring the ef fect of
this signal on the full-scale output voltage.
operating characteristics over recommended operating free-air temperature range,
VDD = 3 V to 3.6 V, Vref = 2 V, × 1 gain output range (unless otherwise noted)
TEST CONDITIONS MIN TYP MAX UNIT
Output slew rate CL = 100 pF, RL = 10 kΩ1V/µs
Output settling time To 0.5 LSB, CL = 100 pF, RL = 10 kΩ, See Note 9 10 µs
Large-signal bandwidth Measured at –3 dB point 100 kHz
Digital crosstalk CLK = 1-MHz square wave measured at DACA-DACH –50 dB
Reference feedthrough See Note 10 –60 dB
Channel-to-channel isolation See Note 11 –60 dB
Reference input bandwidth See Note 12 100 kHz
NOTES: 9. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change
of 00 hex to FF hex or FF hex to 00 hex. For TLC5628C VDD = 5 V, Vref = 2 V and range = ×2. For TLC5628I VDD = 3 V,
Vref = 1.25 V and range ×2.
10. Reference feedthrough is measured at any DAC output with an input code = 00 hex with a Vref input = 1 V dc + 1 VPP at 10 kHz.
1 1. Channel-to-channel isolation is measured by setting the input code of one DAC to FF hex and the code of all other DACs to 00 hex
with Vref input = 1 V dc + 1 VPP at 10 kHz.
12. Reference bandwidth is a –3 dB bandwidth with an input at V ref = 1.25 V dc + 2 VPP and with a full-scale digital input code.
TLV5628C, TLV5628I
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS108A – JANUARY 1995 – REVISED NOVEMBER 1995
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
10 kΩCL = 100 pF
TLV5628
DACA
DACB
•
•
•
DACH
Figure 6. Slewing Settling Time and Linearity Measurements
TYPICAL CHARACTERISTICS
Figure 7
024681012
– Output Voltage – V
POSITIVE RISE TIME AND SETTLING TIME
14 16 18 20
VDD = 3 V
TA = 25°C
Code 00 to
FF Hex
Range = ×2
Vref = 1.25 V
(see Note A)
Time – µs
–1
–0.5
0.5
1
1.5
2
2.5
0
3
VO
NOTE A: Rise time = 2.05 µs, positive slew rate = 0.96 V/µs,
settling time = 4.5 µs. Figure 8
NEGATIVE FALL TIME AND SETTLING TIME
VDD = 3 V
TA = 25°C
Code FF to
00 Hex
Range = ×2
Vref = 1.25 V
(see Note B)
Time – µs
–1
–0.5
0.5
1
1.5
2
2.5
0
3
– Output Voltage – V
VO
0 2 4 6 8 101214161820
NOTE B: Fall time = 4.25 µs, negative slew rate = 0.46
V/
µs,
settling time = 8.5 µs.
TLV5628C, TLV5628I
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS108A – JANUARY 1995 – REVISED NOVEMBER 1995
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
2
1.8
1.4
1.2
1
2.8
1.6
0 102030405060
– DAC Output Voltage – V
2.4
2.2
2.6
DAC OUTPUT VOLTAGE
vs
LOAD
3
70 80 90 100
VO
Load – kΩ
VDD = 3 V,
Vref = 1.5 V,
Range = 2x
Figure 9
0.8
0.6
0.2
00102030405060
1
1.4
1.6
70 80 90 100
0.4
1.2
DAC OUTPUT VOLTAGE
vs
LOAD
VDD = 3 V,
Vref = 1.5 V,
Range = 1x
– DAC Output Voltage – V
VO
Load – kΩ
Figure 10
1
0.9
0.85
0.8
– Supply Current – mA
1.1
1.15
SUPPLY CURRENT
vs
TEMPERATURE
1.2
1.05
0.95
–50 0 50 100
Range = ×2
Input Code = 255
VDD = 3 V
Vref 1.25 V
IDD
t – Temperature – °C
Figure 11
TLV5628C, TLV5628I
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS108A – JANUARY 1995 – REVISED NOVEMBER 1995
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
NOTE A: Resistor R
w
10 kΩ
R
TLV5628
DACA
DACB
•
•
•
DACH
_
+VO
Figure 12. Output Buffering Scheme
TLV5628C, TLV5628I
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS108A – JANUARY 1995 – REVISED NOVEMBER 1995
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
DW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
16 PIN SHOWN
4040000/B 10/94
Seating Plane
0.400 (10,15)
0.419 (10,65)
0.104 (2,65) MAX
1
0.012 (0,30)
0.004 (0,10)
A
8
16
0.020 (0,51)
0.014 (0,35)
0.293 (7,45)
0.299 (7,59)
9
0.010 (0,25)
0.050 (1,27)
0.016 (0,40)
(15,24)
(15,49)
PINS **
0.010 (0,25) NOM
A MAX
DIM
A MIN
Gage Plane
20
0.500
(12,70)
(12,95)
0.510
(10,16)
(10,41)
0.400
0.410
16
0.600
24
0.610
(17,78)
28
0.700
(18,03)
0.710
0.004 (0,10)
M
0.010 (0,25)
0.050 (1,27)
0°–8°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-013
TLV5628C, TLV5628I
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS108A – JANUARY 1995 – REVISED NOVEMBER 1995
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE
4040049/C 7/95
16 PIN SHOWN
0.310 (7,87)
0.290 (7,37)
Seating Plane
0.010 (0,25) NOM
14 Pin Only
9
8
0.070 (1,78) MAX
A
0.035 (0,89) MAX 0.020 (0,51) MIN
16
1
0.015 (0,38)
0.021 (0,53)
0.200 (5,08) MAX
0.125 (3,18) MIN
0.240 (6,10)
0.260 (6,60)
0.100 (2,54)
M
0.010 (0,25)
0°–15°
20
0.975
(24,77)
(23,88)
0.940
18
0.920
0.850
14
0.775
(19,69)
0.745
(18,92)
16
0.775
(19,69)
(18,92)
0.745
PINS **
A MIN
DIM
A MAX (23.37)
(21.59)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001 (20-pin package is shorter than MS-001)
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TLV5628CDW ACTIVE SOIC DW 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5628CDWG4 ACTIVE SOIC DW 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5628CDWR ACTIVE SOIC DW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5628CDWRG4 ACTIVE SOIC DW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5628CN ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPD N / A for Pkg Type
TLV5628CNE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPD N / A for Pkg Type
TLV5628IDW ACTIVE SOIC DW 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5628IDWG4 ACTIVE SOIC DW 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5628IDWR ACTIVE SOIC DW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5628IDWRG4 ACTIVE SOIC DW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5628IN ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPD N / A for Pkg Type
TLV5628INE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPD N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 18-Jul-2006
Addendum-Page 1
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 18-Jul-2006
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
TLV5628CDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
TLV5628IDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV5628CDWR SOIC DW 16 2000 346.0 346.0 33.0
TLV5628IDWR SOIC DW 16 2000 346.0 346.0 33.0
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2008
Pack Materials-Page 2
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