1
®
FN4910.20
ICL3221E, ICL3222E, ICL3223E,
ICL3232E, ICL3241E, ICL3243E
±15kV ESD Protected, +3V to +5.5V,
1Microamp, 250kbps, RS-232
Transmitters/Receivers
The Intersil ICL32xxE devices are 3.0V to 5.5V powered
RS-232 transmitters/receivers which meet ElA/T IA-232 and
V.28/V.24 specifications, even at VCC = 3.0V. Additionally,
they provide ±15kV ESD protection (IEC61000-4-2 Air Gap
and Human Body Model) on transmitter outputs and receiver
inputs (RS-232 pins). Targeted applications are PDAs,
Palmtops, and notebook and laptop computers where the
low operational, and even lower standby, powe r
consumption is critical. Efficient on-chip charge pumps,
coupled with manual and automatic power-down functions
(except for the ICL3232E), reduce the standby supply
current to a 1µA trickle. Small footprint packaging, and the
use of small, low value capacitors ensure board space
savings as well. Data rates greater than 250kbps are
guaranteed at worst case load conditions. This family is fully
compatible with 3.3V-only systems, mixed 3.3V and 5.0V
systems, and 5.0V-only systems.
The ICL324XE are 3-driver, 5-receiver devices that provide a
complete serial port suitable for laptop or notebook
computers. Both devices also include noninverting
always-active receivers for “wake-up” capability.
The ICL3221E, ICL3223E and ICL3243E, feature an
automatic power-down function which powers down the
on-chip power-supply an d dr iver circuits. This occurs when
an attached peripheral device is shut off or the RS-232 cable
is removed, conserving system power automatica lly without
changes to the hardware or operating system. These
devices power up again when a valid RS-232 voltage is
applied to any receiver input.
Table 1 summarizes the features of the devices represented
by this data sheet, while Application Note AN9863
summarizes the features of each device comprising the
ICL32xxE 3V family.
Features
• ESD Protection for RS-232 I/O Pins to ±15kV (IEC6100 0)
• Drop in Replacements for MAX3221E, MAX3222E,
MAX3223E, MAX3232E, MAX3241E, MAX3243 E,
SP3243E
• ICL3221E is a Low Power , Pin Compatible Upgrade for 5V
MAX221E
• ICL3222E is a Low Power , Pin Compatible Upgrade for 5V
MAX242E, and SP312E
• ICL3232E is a Low Power Upgrade for HIN232E, ICL232
and Pin Compatible Competitor Devices
• RS-232 Compatible with VCC = 2.7V
• Meets EIA/TIA-232 and V.28/V.24 Specifications at 3V
• Latch-Up Free
• On-Chip Voltage Converters Require Only Four External
0.1µF Capacitors
• Manual and Automatic Power-down Features
• Guaranteed Mouse Drivea bility (ICL324XE Only)
• Receiver Hysteresis For Improved Noise Immunity
• Guaranteed Minimum Data Rate . . . . . . . . . . . . . 250kbps
• Wide Power Supply Range . . . . . . . Single +3V to +5.5V
• Low Supply Current in Power-down State . . . . . . . . . .1µA
• Pb-Free Available (RoHS Compliant)
Applications
• Any System Requiring RS-232 Communication Ports
- Batte ry Powered, Hand-Held, and Portable Equipment
- Lapto p Computers, Noteboo ks, Palmtops
- Modems, Printers and other Peripherals
- Digital Cameras
- Cellular/Mobile Phones
Related Literature
• Technical Brief TB36 3 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mo unt Devices
(SMDs)”
TABLE 1. SUMMARY OF FEATURES
PART
NUMBER NUMBER
OF Tx NUMBER
OF Rx
NUMBER OF
MONITOR
RECEIVERS
(ROUTB)
DATA
RATE
(kbps)
RECEIVER
ENABLE
FUNCTION? READY
OUTPUT? MANUAL
POWER-DOWN?
AUTOMATIC
POWER-DOWN
FUNCTION?
ICL3221E 1 1 0 250 Yes No Yes Yes
ICL3222E 2 2 0 250 Yes No Yes No
ICL3223E 2 2 0 250 Yes No Yes Yes
ICL3232E 2 2 0 250 No No No No
ICL3241E 3 5 2 250 Yes No Yes No
ICL3243E 3 5 1 250 No No Yes Yes
Data Sheet September 15, 2008
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2000-2005, 2007, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
2FN4910.20
September 15, 2008
Ordering Information
PART
NUMBER PART
MARKING TEMP RANGE
(°C) PACKAGE PKG.
DWG. #
ICL3221ECA* ICL 3221ECA 0 to +70 16 Ld SSOP M16.209
ICL3221ECAZ* (Note) ICL32 21ECAZ 0 to +70 16 Ld SSOP (Pb-free) M16.209
ICL3221ECAZA* (Note) ICL32 21ECAZ 0 to +70 16 Ld SSOP (Pb-free) M16.209
ICL3221ECV* 3221 ECV 0 to +70 16 Ld TSSOP M16.173
ICL3221ECVZ* (Note) 3221 ECVZ 0 to +70 16 Ld TSSOP (Pb-free) M16.173
ICL3221EIA* ICL 3221EIA -40 to +85 16 Ld SSOP M16.209
ICL3221EIAZ* (Note) ICL32 21EIAZ -40 to +85 16 Ld SSOP (Pb-free) M16.209
ICL3221EIV* 3221 EIV -40 to +85 16 Ld TSSOP M16.173
ICL3221EIVZ* (Note) 3221 EIVZ -40 to +85 16 Ld TSSOP (Pb-free) M16.173
ICL3222ECA* ICL 3222ECA 0 to +70 20 Ld SSOP M20.209
ICL3222ECAZ* (Note) ICL32 22ECAZ 0 to +70 20 Ld SSOP (Pb-free) M20.209
ICL3222ECP ICL3222ECP 0 to +70 18 Ld PDIP E18.3
ICL3222ECV* ICL 3222ECV 0 to +70 20 Ld TSSOP M20.173
ICL3222ECVZ* (Note) ICL32 22ECVZ 0 to +70 20 Ld TSSOP (Pb-free) M20.173
ICL3222EIA* ICL 3222EIA -40 to +85 20 Ld SSOP M20.209
ICL3222EIAZ* (Note) ICL32 22EIAZ -40 to +85 20 Ld SSOP (Pb-free) M20.209
ICL3222EIB* ICL3222EIB -40 to +85 18 Ld SOIC M18.3
ICL3222EIBZ* (Note) 3222EIBZ -40 to +85 18 Ld SOIC (Pb-free) M18.3
ICL3222EIV* ICL 3222EIV -40 to +85 20 Ld TSSOP M20.173
ICL3222EIVZ* (Note) ICL32 22EIVZ -40 to +85 20 Ld TSSOP (Pb-free) M20.173
ICL3223ECA* ICL 3223ECA 0 to +70 20 Ld SSOP M20.209
ICL3223ECAZ* (Note) ICL32 23ECAZ 0 to +70 20 Ld SSOP (Pb-free) M20.209
ICL3223ECV* ICL 3223ECV 0 to +70 20 Ld TSSOP M20.173
ICL3223ECVZ* (Note) ICL32 23ECVZ 0 to +70 20 Ld TSSOP (Pb-free) M20.173
ICL3223EIA* ICL 3223EIA -40 to +85 20 Ld SSOP M20.209
ICL3223EIAZ* (Note) ICL32 23EIAZ -40 to +85 20 Ld SSOP (Pb-free) M20.209
ICL3223EIV* ICL 3223EIV -40 to +85 20 Ld TSSOP M20.173
ICL3223EIVZ* (Note) ICL32 23EIVZ -40 to +85 20 Ld TSSOP (Pb-free) M20.173
ICL3232ECA* ICL 3232ECA 0 to +70 16 Ld SSOP M16.209
ICL3232ECAZ* (Note) 3232 ECAZ 0 to +70 16 Ld SSOP (Pb-free) M16.209
ICL3232ECB* ICL3232ECB 0 to +70 16 Ld SOIC M16.3
ICL3232ECBZ* (Note) 3232ECBZ 0 to +70 16 Ld SOIC (Pb-free) M16.3
ICL3232ECBN* 3232ECBN 0 to +70 16 Ld SOIC M16.15
ICL3232ECBNZ* (Note) 3232ECBNZ 0 to +70 16 Ld SOIC (Pb-free) M16.15
ICL3232ECV-16* 3232E CV-16 0 to +70 16 Ld TSSOP M16.173
ICL3232ECV-16Z* (Note) 3232E CV-16Z 0 to +70 16 Ld TSSOP (Pb-free) M16.173
ICL3232ECV-20* ICL3232 ECV-20 0 to +70 20 Ld TSSOP M20.173
ICL3232ECV-20Z *(Note) ICL3232 ECV-20Z 0 to +70 20 Ld TSSOP (Pb-free) M20.173
ICL3232EIA* ICL3232 EIA -40 to +85 16 Ld SSOP M16.209
ICL3232EIAZ* (Note) 3232 EIAZ -40 to +85 16 Ld SSOP (Pb-free) M16.209
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
3FN4910.20
September 15, 2008
ICL3232EIB* ICL3232EIB -40 to +85 16 Ld SOIC M16.3
ICL3232EIBZ* (Note) 3232EIBZ -40 to +85 16 Ld SOIC (Pb-free) M16.3
ICL3232EIBNZ* (Note) 3232EIBNZ -40 to +85 16 Ld SOIC (Pb-free) M16.15
ICL3232EIV-16* 3232E IV-16 -40 to +85 16 Ld TSSOP M16.173
ICL3232EIV-16Z* (Note) 3232E IV-16Z -40 to +85 16 Ld TSSOP (Pb-free) M16.173
ICL3232EIV-20* ICL3232 EIV-20 -40 to +85 20 Ld TSSOP M20.173
ICL3232EIV-20Z* (Note) ICL3232 EIV -20Z -40 to +85 20 Ld TSSOP (Pb-free) M20.173
ICL3241ECA* ICL 3241ECA 0 to +70 28 Ld SSOP M28.209
ICL3241ECAZ* (Note) ICL3241 ECAZ 0 to +70 28 Ld SSOP (Pb-free) M28.209
ICL3241ECB* ICL3241ECB 0 to +70 28 Ld SOIC M28.3
ICL3241ECBZ* (Note) ICL3241ECBZ 0 to +70 28 Ld SOIC (Pb-free) M28.3
ICL3241ECV* ICL3241 ECV 0 to +70 28 Ld TSSOP M28.173
ICL3241ECVZ* (Note) ICL3241 ECVZ 0 to +70 28 Ld TSSOP (Pb-free) M28.173
ICL3241EIA* ICL 3241EIA -40 to +85 28 Ld SSOP M28.209
ICL3241EIAZ* (Note) ICL3241 EIAZ -40 to +85 28 Ld SSOP (Pb-free) M28.209
ICL3241EIB* ICL3241EIB -40 to +85 28 Ld SOIC M28.3
ICL3241EIBZ* (Note) ICL3241EIBZ -40 to +85 28 Ld SOIC (Pb-free) M28.3
ICL3241EIV* ICL3241 EIV -40 to +85 28 Ld TSSOP M28.173
ICL3241EIVZ* (Note) ICL3241 EIVZ -40 to +85 28 Ld TSSOP (Pb-free) M28.173
ICL3243ECA* ICL 3243ECA 0 to +70 28 Ld SSOP M28.209
ICL3243ECAZ* (Note) ICL32 43ECAZ 0 to +70 28 Ld SSOP (Pb-free) M28.209
ICL3243ECB* ICL3243ECB 0 to +70 28 Ld SOIC M28.3
ICL3243ECBZ* (Note) ICL3243ECBZ 0 to +70 28 Ld SOIC (Pb-free) M28.3
ICL3243ECV* ICL3243 ECV 0 to +70 28 Ld TSSOP M28.173
ICL3243ECVZA* (Note) ICL3243 ECVZ 0 to +70 28 Ld TSSOP (Pb-free) M28.173
ICL3243ECVZ* (Note) ICL3243 ECVZ 0 to +70 28 Ld TSSOP (Pb-free) M28.173
ICL3243EIA* ICL 3243EIA -40 to +85 28 Ld SSOP M28.209
ICL3243EIAZ* (Note) ICL32 43EIAZ -40 to +85 28 Ld SSOP (Pb-free) M28.209
ICL3243EIV* ICL3243 EIV -40 to +85 28 Ld TSSOP M28.173
ICL3243EIVZ* (Note) ICL3243 EIVZ -40 to +85 28 Ld TSSOP (Pb-free) M28.173
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die att ach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Ordering Information (Continued)
PART
NUMBER PART
MARKING TEMP RANGE
(°C) PACKAGE PKG.
DWG. #
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
4FN4910.20
September 15, 2008
Pinouts ICL3221E
(16 LD SSOP, TSSOP)
TOP VIEW
ICL3222E
(18 LD PDIP, SOIC)
TOP VIEW
ICL3222E
(20 LD SSOP, TSSOP)
TOP VIEW
ICL3223E
(20 LD SSOP, TSSOP)
TOP VIEW
ICL3232E
(16 LD SOIC, SSOP, TSSOP-16)
TOP VIEW
ICL3232E
(20 LD TSSOP-20)
TOP VIEW
EN
C1+
V+
C1-
C2+
C2-
V-
R1IN
FORCEOFF
GND
T1OUT
FORCEON
T1IN
R1OUT
VCC
INVALID
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
EN
C1+
V+
C1-
C2+
C2-
V-
T2OUT
R2IN
SHDN
GND
T1OUT
R1IN
R1OUT
T2IN
VCC
T1IN
R2OUT
18
17
16
15
14
13
12
11
10
1
2
3
4
5
6
7
8
9
EN
C1+
V+
C1-
C2+
C2-
V-
T2OUT
R2IN
SHDN
GND
T1OUT
R1IN
R1OUT
T1IN
NC
VCC
NC
T2IN
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
R2OUT
EN
C1+
V+
C1-
C2+
C2-
V-
T2OUT
R2IN
FORCEOFF
GND
T1OUT
R1IN
R1OUT
T1IN
INVALID
VCC
FORCEON
T2IN
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
R2OUT
C1+
V+
C1-
C2+
C2-
V-
T2OUT
R2IN
VCC
T1OUT
R1IN
R1OUT
T1IN
R2OUT
GND
T2IN
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
NC
C1+
V+
C1-
C2+
C2-
V-
T2OUT
R2IN
NC
GND
T1OUT
R1IN
R1OUT
T1IN
NC
VCC
T2IN
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
NC
R2OUT
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
5FN4910.20
September 15, 2008
ICL3241E
(28 LD SOIC, SSOP, TSSOP)
TOP VIEW
ICL3243E
(28 LD SOIC, SSOP, TSSOP)
TOP VIEW
Pinouts (Continued)
C2+
C2-
V-
R1IN
R2IN
R3IN
R4IN
R5IN
T1OUT
T3OUT
T3IN
T2IN
T1IN
C1+
VCC
GND
C1-
EN
R1OUTB
R1OUT
R2OUT
R3OUT
R4OUT
R5OUT
V+
SHDN
R2OUTB
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
T2OUT
C2+
C2-
V-
R1IN
R2IN
R3IN
R4IN
R5IN
T1OUT
T3OUT
T3IN
T2IN
T1IN
C1+
VCC
GND
C1-
FORCEON
INVALID
R1OUT
R2OUT
R3OUT
R4OUT
R5OUT
V+
FORCEOFF
R2OUTB
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
T2OUT
Pin Descriptions
PIN FUNCTION
VCC System power supply input (3.0V to 5.5V).
V+ Internally generated positive transmitter supply (+5.5V).
V- Internally generated negative transmitter supply (-5.5V).
GND Ground connection.
C1+ External capacitor (voltage doubler) is connected to this lead.
C1- External capacitor (voltage doubler) is connected to this lead.
C2+ External capacitor (voltage inverter) is connected to this lead.
C2- External capacitor (voltage inverter) is connected to this lead.
TIN TTL/CMOS compatible transmitter Input s.
TOUT ±15kV ESD Protected, RS-232 level (nominally ±5.5V) transmitter outputs.
RIN ±15kV ESD Protected, RS-232 compatible receiver inputs.
ROUT TTL/CMOS level receiver outputs.
ROUTB TTL/CMOS level, noninverting, always enabled receiver outputs.
INVALID Active low output that indicates if no valid RS-232 levels are present on any receiver input.
EN Active low receiver enable control; doesn’t disable ROUTB outputs.
SHDN Active low input to shut down transmitters and on-board power supply, to place device in low power mode.
FORCEOFF Active low to shut down transmitters and on-chip power supply . This overrides any automatic circuitry and FORCEON (see Table 2).
FORCEON Active high input to override automatic power-down circuitry thereby keeping transmitters active (F ORCEOFF must be high).
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
6FN4910.20
September 15, 2008
Typical Operating Circuits ICL3221E
ICL3222E
15
VCC
T1OUT
T1IN
T1
0.1µF
+0.1µF
+
0.1µF
11 13
2
43
7
V+
V-
C1+
C1-
C2+
C2-
+
0.1µF 5
6
R1OUT R1IN
R1
89
5kΩ
C1
C2
+C3
C4
EN
1
GND
+3.3V +0.1µF
14
TTL/CMOS
LOGIC LEVELS RS-232
LEVELS
FORCEON
FORCEOFF
12
16 VCC
10
INVALID TO POWER
CONTROL LOGIC
+
C3 (OPTIONAL CONNECTION, NOTE)
NOTE: The negative terminal of C3 can be connected to either VCC or GND
17
VCC
T1OUT
T2OUT
T1IN
T2IN
T1
T2
0.1µF
+0.1µF
+
0.1µF
12
11
15
8
2
4
3
7
V+
V-
C1+
C1-
C2+
C2-
+
0.1µF
5
6
R1OUT R1IN
14
5kΩ
R2OUT R2IN
9
10
5kΩ
13
C1
C2
+C3
C4
EN
SHDN
1
GND
18
+3.3V +0.1µF
16
VCC
TTL/CMOS
LOGIC LEVELS RS-232
LEVELS
R1
R2
+
C3 (OPTIONAL CONNECTION, NOTE)
NOTE: The negative terminal of C3 can be connected to either VCC or GND
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
7FN4910.20
September 15, 2008
ICL3223E
ICL3232E
Typical Operating Circuits (Continued)
19
VCC
T1OUT
T2OUT
T1IN
T2IN
T1
T2
0.1µF
+0.1µF
+
0.1µF
13
12
17
8
2
43
7
V+
V-
C1+
C1-
C2+
C2-
+
0.1µF
5
6
R1OUT R1IN
16
5kΩ
R2OUT R2IN
910
5kΩ
15
C1
C2
+C3
C4
EN
1
GND
+3.3V +0.1µF
18
TTL/CMOS
LOGIC LEVELS RS-232
LEVELS
R1
R2
FORCEON
FORCEOFF
14
20 VCC
11
INVALID TO P OWER
CONTROL LOGIC
16
VCC
T1OUT
T2OUT
T1IN
T2IN
T1
T2
0.1µF
+0.1µF
+
0.1µF
11
10
14
7
1
32
6
V+
V-
C1+
C1-
C2+
C2-
+
0.1µF
4
5
R1OUT R1IN
13
5kΩ
R2OUT R2IN
8
9
5kΩ
12
C1
C2
+C3
C4
GND
+3.3V +0.1µF
15
TTL/CMOS
LOGIC LEVELS RS-232
LEVELS
R1
R2
+
C3 (OPTIONAL CONNECTION, NOTE)
NOTE: The negative terminal of C3 can be connected to either VCC or GND
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
8FN4910.20
September 15, 2008
ICL3241E ICL3243E
Typical Operating Circuits (Continued)
26
VCC
T1OUT
T2OUT
T3OUT
T1IN
T2IN
T3IN
T1
T2
T3
0.1µF
+0.1µF
+
0.1µF
14
13
9
10
12 11
28
24
27
3
V+
V-
C1+
C1-
C2+
C2-
+
0.1µF 1
2
R1OUT R1IN
4
5kΩ
R2OUT R2IN
518
5kΩ
R3OUT R3IN
617
5kΩ
R4OUT R4IN
716
5kΩ
R5OUT R5IN
R5
815
5kΩ
19
R2OUTB
C1
C2
+C3
C4
EN
SHDN
23
GND
22
+3.3V +0.1µF
20
25
VCC
TTL/CMOS
LOGIC
RS-232
LEVELS
RS-232
LEVELS
R1OUTB 21
R1
R2
R3
R4
LEVELS
26
VCC
T1OUT
T2OUT
T3OUT
T1IN
T2IN
T3IN
T1
T2
T3
0.1µF
+0.1µF
+
0.1µF
14
13
9
10
12 11
28
24
27
3
V+
V-
C1+
C1-
C2+
C2-
+
0.1µF 1
2
R1OUT R1IN
4
5kΩ
R2OUT R2IN
518
5kΩ
R3OUT R3IN
617
5kΩ
R4OUT R4IN
716
5kΩ
R5OUT R5IN
R5
815
5kΩ
19
R2OUTB
C1
C2
+C3
C4
FORCEON
FORCEOFF
23
GND
22
+3.3V +0.1µF
20
25
VCC
TTL/CMOS
LOGIC
RS-232
LEVELS
RS-232
LEVELS
R1
R2
R3
R4
21 INVALID
TO POWER
CONTROL
LEVELS
LOGIC
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
9FN4910.20
September 15, 2008
Absolute Maximum Ratings Thermal Information
VCC to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V
V- to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3V to -7V
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14V
Input Voltages
TIN, FORCEOFF, FORCEON, EN, SHDN . . . . . . . . . -0.3V to 6V
RIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V
Output Voltages
TOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±13.2V
ROUT, INVALID. . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC +0.3V
Short Circuit Duration
TOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . See Specification Table
Operating Conditions
Temperature Range
ICL32xxECX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
ICL32xxEIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Thermal Resistance (Typical, Note 1) θJA (°C/W)
18 Ld PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . 80
16 Ld Wide SOIC Package . . . . . . . . . . . . . . . . . . . 100
16 Ld Narrow SOIC Package. . . . . . . . . . . . . . . . . . 115
18 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . 75
28 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . 75
16 Ld SSOP Package . . . . . . . . . . . . . . . . . . . . . . . 135
20 Ld SSOP Package . . . . . . . . . . . . . . . . . . . . . . . 122
16 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . 145
20 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . 140
28 Ld SSOP and TSSOP Packages . . . . . . . . . . . . 100
Maximum Junction Temperature (Plastic Package) . . . . . . +150°C
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications Te st Conditions: VCC = 3V to 5.5V, C1 - C4 = 0.1µF; Unless Otherwise Specified.
Typicals are at TA = +25°C.
PARAMETER TEST CONDITIONS TEMP
(°C) MIN
(Note 3) TYP MAX
(Note 3) UNITS
DC CHARACTERISTICS
Supply Current, Automatic
Power-down All RIN Open, FORCEON = GND, FORCEOFF = VCC
(ICL3221E, ICL3223E, ICL3243E Only) 25 - 1.0 10 µA
Supply Current, Power-down FORCEOFF = SHDN = GND (Except ICL3232E) 25 - 1.0 10 µA
Supply Current,
Automatic Power-down Disabled All Outputs Unloaded,
FORCEON = FORCEOFF =
SHDN = VCC
VCC = 3.0V, ICL3241,
ICL3243 25 - 0.3 1.0 mA
VCC = 3.0V, ICL3223 25 - 0.7 3.0 mA
VCC = 3.15V, ICL3221,
ICL3222, ICL3223, ICL3232 25 - 0.3 1.0 mA
LOGIC AND TRANSMITTER INPUTS AND RECEIVER OUTPUTS
Input Logic Threshold Low TIN, FORCEON, FORCEOFF, EN, SHDN Full - - 0.8 V
Input Logic Threshold High TIN, FORCEON,
FORCEOFF, EN, SHDN VCC = 3.3V Full 2.0 - - V
VCC = 5.0V Full 2.4 - - V
Input Leakage Current TIN, FORCEON, FORCEOFF, EN, SHDN Full - ±0.01 ±1.0 µA
Output Leakage Current
(Except ICL3232E) FORCEOFF = GND or EN = VCC Full - ±0.05 ±10 µA
Output Voltage Low IOUT = 1.6mA Full - - 0.4 V
Output Voltage High IOUT = -1.0mA Full VCC - 0.6 VCC - 0.1 - V
AUTOMATIC POWER-DOWN (ICL3221E, ICL3223E, ICL3243E Only, FORCEON = GND, FORCEOFF = VCC)
Receiver Input Thresholds to
Enable Transmitters ICL32xxE Powers Up (see Figure 6) Full -2.7 - 2.7 V
Receiver Input Thresholds to
Disable Transmitters ICL32xxE Powers Down (see Figure 6) Full -0.3 - 0.3 V
INVALID Output Voltage Low IOUT = 1.6mA Full - - 0.4 V
INVALID Output Voltage High IOUT = -1.0mA Full VCC - 0.6 - - V
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
10 FN4910.20
September 15, 2008
Receiver Threshold to Transmitters
Enabled Delay (tWU)25 - 100 - µs
Receiver Positive or Negative
Threshold to INVALID High Delay
(tINVH)
25 - 1 - µs
Receiver Positive or Negative
Threshold to INVALID Low Delay
(tINVL)
25 - 30 - µs
RECEIVER INPUTS
Input Voltage Range 25 -25 - 25 V
Input Threshold Low VCC = 3.3V 25 0.6 1.2 - V
VCC = 5.0V 25 0.8 1.5 - V
Input Threshold High VCC = 3.3V 25 - 1.5 2.4 V
VCC = 5.0V 25 - 1.8 2.4 V
Input Hysteresis 25 - 0.5 - V
Input Resistance 25 3 5 7 kΩ
TRANSMITTER OUTPUTS
Output Voltage Swing All Transmitter Outputs Loaded with 3kΩ to Ground Full ±5.0 ±5.4 - V
Output Resistance VCC = V+ = V- = 0V, Transmitter Output = ±2V Full 300 10M - Ω
Output Short-Circuit Current Full - ±35 ±60 mA
Output Leakage Current VOUT = ±12V, VCC = 0V or 3V to 5.5V,
Automatic Power-down or FORCEOFF = SHDN = GND Full - - ±25 µA
MOUSE DRIVEABILITY (ICL324XE Only)
Transmitter Output Voltage
(see Figure 9) T1IN = T2IN = GND, T3IN = VCC, T3OUT Loaded with 3kΩ
to GND, T1OUT and T2OUT Loaded with 2.5mA Each Full ±5--V
TIMING CHARACTERISTICS
Maximum Data Rate RL = 3kΩ, CL = 1000pF, One Transmitter Switching Full 250 500 - kbps
Receiver Propagation Delay Receiver Input to Receiver
Output, CL = 150pF tPHL 25 - 0.15 - µs
tPLH 25 - 0.15 - μs
Receiver Output Enable Time Normal Operation (Except ICL3232E) 25 - 200 - ns
Receiver Output Disable Time Normal Operation (Except ICL3232E) 25 - 200 - ns
Transmitter Skew tPHL to tPLH (Note 2) 25 - 100 - ns
Receiver Skew tPHL to tPLH 25 - 50 - ns
Transition Region Slew Rate VCC = 3.3V,
RL = 3kΩ to 7kΩ,
Measured from 3V to -3V or
-3V to 3V
CL = 150pF to 2500pF 25 4 - 30 V/μs
CL = 150pF to 1000pF 25 6 - 30 V/μs
ESD PERFORMANCE
RS-232 Pins (TOUT, RIN) Human Body Model 25 - ±15 - kV
IEC61000-4-2 Contact Discharge 25 - ±8-kV
IEC61000-4-2 Air Gap Discharge 25 - ±15 - kV
All Other Pins Human Body Model 25 - ±2-kV
NOTES:
2. Transmitter skew is measured at the transmitter zero crossing points.
3. Parts are 100% tested at +25°C. Full temp limits are guaranteed by bench and tester characterization
Electrical Specifications Te st Conditions: VCC = 3V to 5.5V, C1 - C4 = 0.1µF; Unless Otherwise Specified.
Typicals are at TA = +25°C. (Continued)
PARAMETER TEST CONDITIONS TEMP
(°C) MIN
(Note 3) TYP MAX
(Note 3) UNITS
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
11 FN4910.20
September 15, 2008
Detailed Description
ICL32xxE interface ICs operate from a single +3V to +5.5V
supply, guarantee a 250kbps minimum data rate, require
only four small external 0.1µF capacitors, feature low power
consumption, and meet all ElA RS-232C and V.28
specifications. The circuit is divided into three sections:
charge pump, transmitters and receivers.
Charge-Pump
Intersil’s new ICL32xxE family utilizes regulated on-chip dual
charge pumps as volta ge doublers, and voltage inverters to
generate ±5.5V transmitter supplies from a VCC supply as
low as 3.0V. This allows these device s to maint ai n RS-2 32
compliant output levels over the ±10% tolerance range of
3.3V powered systems. The efficient on-chip power supplies
require only four small, external 0.1µF capacitors for the
voltage doubler and inverter functions at VCC = 3.3V. See
“Capacitor Selection” on page 14 and Table 3 on page 14 for
capacitor recommendations for other operating conditions.
The char ge pump s operate discontinuously (i.e., they turn off
as soon as the V+ and V- supplies are pumped up to the
nominal values), resulting in significant power savings.
Transmitters
The transmitters are proprietary, low dropout, inverting
drivers that translate TTL/CMOS inputs to EIA/TIA-232
output levels. Coupled with the on-chip ±5.5V supplies,
these transmitters deliver true RS-232 levels over a wide
range of single supply system voltages.
Except for the ICL3232E, all transmitter outputs disable and
assume a high impedance state when the device enters the
power-down mode (see Table 2). These outputs may be
driven to ±12V when disabled.
All devices guarantee a 250kbps data rate for full load
conditions (3kΩ and 1000pF), VCC ≥ 3.0V, with one
transmitter operating at full speed. Und er more typical
conditions of VCC ≥ 3.3V, RL = 3kΩ, and CL = 250pF, one
transmitter easily operates at 900kbps.
Transmitter inputs float if left unconnected, and may cause
ICC increases. Connect unused inputs to GND for the best
performance.
Receivers
All the ICL32xxE devices co ntai n st anda rd in ve rting receivers
that three-state (except for the ICL3232E) vi a the EN or
FORCEOFF control lines. Additionall y, the two ICL324XE
products in clude noninverting (monitor) receivers (denoted by
the ROUTB label) that are always active, regard less of the
state of any control lines. Al l the recei vers con vert RS-232
signals to CMOS output levels and accept input s up to ±25V
while presenting the required 3kW to 7kW input i mpedance
(see Figure 1) even if the power is off (VCC = 0V). The
receivers’ Schmitt trigger input st age use s hysteresis to
increase noise immunity and decrea se errors due to slow
input signal transitions.
The ICL3221E, ICL3222E, ICL322 3E, ICL3241E inverting
receivers disable only when EN is driven high. ICL3243E
receivers disable during forced (manual) power-down, but
not during automatic power-down (see Table 2).
ICL3241E and ICL3243E monitor receive rs remain acti ve
even during manual power-down an d forced receiver di sable,
making them extremely useful for Ring Indicator monitoring.
S tandard receivers driving powere d down peripherals must be
disabled to prevent current flow through the periph eral’ s
protection diodes (see Figures 2 and 3). Thi s renders th em
useless for wake up fu nctions, b ut the corresp onding monitor
receiver can be dedicated to this task as sh own in Figure 3.
Low Power Operation
These 3V devices require a nomi nal supply current of
0.3mA, even at VCC = 5.5V, during no rmal operation (not in
power-down mode). This is considerably le ss than the 5mA
to 1 1mA current required by comparable 5V RS-232 devices,
allowing users to reduce system power simply by switching
to this new fa mily.
Pin Compatible Replacements for 5V Dev ices
The ICL3221E, ICL3222E, ICL3232E are pin compatible
with existing 5V RS-232 transceivers - See the “Features”
section on page 1 for details.
This pin compatibility co upled with the l ow ICC and wide
operating supply range, make th e ICL32 xxE pote ntial lower
power, higher performance drop-in re placement s for existing
5V applications. As long as the ±5V RS-232 output swings are
acceptable, and transmitter inpu t pull-up resistors aren’t
required, the IICL32xxE should work in most 5V application s.
When replacing a device in an existing 5V appli cation, it is
acceptable to terminate C3 to V CC as shown on the “Typical
Operating Circuit s” on p age 6. Nevertheless, terminate C3 to
GND if possible, as slightly better p erformance re sult s from
this configuration.
Power-down Functionality
(Except ICL3232E)
The already low current requ ire ment drops significantly when
the device enters power-dow n mode. In powe r-down, sup ply
current drop s to 1µA, because the on-chip ch arge pump turns
off (V+ collap ses to VCC, V- collapses to GND), and the
transmitter outputs three-st ate. Inverting receiver outputs may
or may not disable in power-down; refer to Table 2 for details.
This micro-power mode makes these devices ideal for
battery powered and portable applications.
RXOUT
GND ≤ VROUT ≤ VCC
5kΩ
RXIN
-25V ≤ VRIN ≤ +25V
GND
VCC
FIGURE 1. INVERTING RECEIVER CONNECTIONS
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
12 FN4910.20
September 15, 2008
Software Controlled (Manual) Power-down
Most devices in the ICL32xxE family provide pi ns that allow
the user to force the IC into the low power , st andby state.
On the ICL3222E and ICL3241E, the power-down control is
via a simple shutdown (SHDN) pin. Driving this pin high
enables normal operation, while driving it low forces the IC
into its power-down state. Connect SHDN to VCC if the
power-down function isn’t needed. Note that all the receiver
outputs remain enabled during shutdown (see Table 2). For
the lowest power consumption during power-down, the
receivers should also be disabled by driving the EN input
high (see next section, and Figures 2 and 3).
The ICL3221E, ICL3223E, and ICL3243E utili ze a two pin
approach where the FORCEON and FORCEOF F inputs
determine the IC’s mode. For always enabled operati on,
FORCEON and FORCEOFF are both strapped high. To
switch between active and power-down modes, under logic
or software contro l, only the FORCEOFF input need be
driven. The FORCEON state isn’t critical, as FORCEOFF
dominates over FORCEON. Nevertheless, if strictly manual
control over power-down is desired, the user must strap
FORCEON high to disable the automatic power-down
circuitry . ICL3243E inverting (standard) receiver outputs also
disable when the device is in manual power-down, thereby
eliminating the possible current path through a shutdown
periphera l’s input protection diode (see Figures 2 and 3).
TABLE 2. POWER-DOWN AND ENABLE LOGIC TRUTH TABLE
RS-232
SIGNAL
PRESENT
AT
RECEIVER
INPUT?
FORCEOFF
OR SHDN
INPUT FORCEON
INPUT EN
INPUT TRANSMITTER
OUTPUTS RECEIVER
OUTPUTS
ROUTB
OUTPUTS
(NOTE 4) INVALID
OUTPUT MODE OF OPERATION
ICL3222E, ICL3241E
N/A L N/A L High-Z Active Active N/A Manual Power-down
N/A L N/A H High-Z High-Z Active N/A Manual Power-down with Receiver
Disabled
N/A H N/A L Active Active Active N/A Normal Operation
N/A H N/A H Active High-Z Active N/A Normal Operation withReceiver
Disabled
ICL3221E, ICL3223E
No H H L Active Active N/A L Normal Operation
(Auto Power-down Disabled)
No H H H Active High-Z N/A L
Yes H L L Active Active N/A H Normal Operation
(Auto Power-down Enabled)
Yes H L H Active High-Z N/A H
No H L L High-Z Active N/A L Power-down Due to Auto Power-down
Logic
No H L H High-Z High-Z N/A L
Yes L X L High-Z Active N/A H Manual Power-down
Yes L X H High-Z High-Z N/A H Manual Power-down with Receiver
Disabled
No L X L High-Z Active N/A L Manual Power-down
No L X H High-Z High-Z N/A L Manual Power-down with Receiver
Disabled
ICL3243E
No H H N/A Active Active Active L Normal Operation
(Auto Power-down Disabled)
Yes H L N/A Active Active Active H Normal Operation
(Auto Power-down Enabled)
No H L N/A High-Z Active Active L Power-down Due to Auto Power-down
Logic
Yes L X N/A High-Z High-Z Active H Manual Power-down
No L X N/A High-Z High-Z Active L Manual Power-down
NOTE:
4. Applies only to the ICL3241E and ICL3243E.
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
13 FN4910.20
September 15, 2008
The INVALID output always indicates whether or not a valid
RS-232 signal is present at any of the receiver inputs (see
Table 2), giving the user an easy way to determine when the
interface block should power down. In the case of a
disconnected interface cable where all the receiver inputs
are floating (but pulled to GND by the internal receiver pull
down resistors), the INVALID logic detects the invalid levels
and drives the output low. The power management logic
then uses this indicator to power down the interface block.
Reconnecting the cable restores valid levels at the receiver
inputs, INVALID switches high, and the power management
logic wakes up the interface block. INVALID can also be
used to indicate the DTR or RING INDICATOR signal, as
long as the other receiver inputs are floating, or driven to
GND (as in the case of a powered down driver). Connecting
FORCEOFF and FORCEON together disables the
automatic power-down feature, enabling them to function as
a manual SHUTDOWN input (see Figure 4).
With any of the control schemes, the time required to exit
power-down, and resume transmission is only 100µs. A
mouse, or other application, may need more time to wake up
from shutdown. If automatic power-down is being utilized,
the RS-232 device will reenter power-down if valid receiver
levels aren’t reestablished within 30µs of the ICL32xxE
powering up. Figure 5 illustrates a circuit that keeps the
ICL32xxE from initiating automatic power-down for 100ms
after powering up. This gives the slow-to-wake peripheral
circuit time to reestablish valid RS-232 output levels.
Automatic Power-down
(ICL3221E, ICL3223E, ICL3243E Only)
Even greater power savings is available by using the
devices which feature an automatic power-down function.
When no valid RS-232 voltages (see Figure 6) are sensed
on any receiver input for 30µs, the charge pump and
transmitters power-down, thereby reducing supply current to
1µA. Invalid receiver levels occur whenever the driving
peripheral’s outputs are shut off (powered down) or when the
RS-232 interface cable is disconnected. The ICL32xxE
powers back up whenever it detects a valid RS-232 voltage
level on any receiver input. This automatic power-down
feature provides additional system power savings without
changes to the existing operating system.
FIGURE 2. POWER DRAIN THROUGH POWERED DOWN
PERIPHERAL
OLD
VCC
POWERED
GND SHDN = GND
VCC
Rx
Tx
VCC
CURRENT
VOUT = VCC
FLOW
RS-232 CHIP
DOWN
UART
FIGURE 3. DISABLED RECEIVERS PREVENT POWER DRAIN
ICL324XE
TRANSITION
RX
TX
R2OUTB
R2OUT
T1IN
FORCEOFF = GND
VCC
VCC
TO
R2IN
T1OUT
VOUT = HI-Z
POWERED
OR SHDN = GND, EN = VCC
DETECTOR
DOWN
UART
WAKE-UP
LOGIC
FIGURE 4. CONNECTIONS FOR MANUAL POWER-DOWN
WHEN NO VALID RECEIVER SIGNALS ARE
PRESENT
PWR
FORCEOFF
INVALID
CPU
I/O
FORCEON
ICL3221E,
MGT
LOGIC
UART
ICL3243E
ICL3223E,
FIGURE 5. CIRCUIT TO PREVENT AUT O POWER-DOWN
FOR 100ms AFTER FORCED POWERUP
ICL3221E, ICL3223E, ICL3243E
FORCEOFF FORCEON
POWER MASTER POWER-DOWN LINE
1MΩ
0.1µF
MANAGEMENT
UNIT
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
14 FN4910.20
September 15, 2008
Automatic power-down operates when the FORCEON input
is low, and the FORCEOFF input is high. Tying FORCEON
high disables automatic power-down, but manual power-
down is always available via the overriding FORCEOFF
input. Table 2 summarizes the automatic power-down
functionality.
Devices with the automatic po wer-down feature include an
INVALID output signal, which switches low to indicate that
invalid levels have persisted on all of the receiver inputs for
more than 30µs (see Figure 7). INVALID switches high 1µs
after detecting a valid RS-232 level on a receiver input.
INVALID operates in all modes (forced or automatic
power-down, or forced on), so it is also useful for systems
employing manual power-down circuitry. When automatic
power-down is utilized, INVALID = 0 indicates that the
ICL32xxE is in power-down mode.
The time to recover from automatic po wer-down mode is
typically 100µs.
Receiver ENABLE Control
(ICL3221E, ICL3222E, ICL3223E, ICL3241E Only)
Several devices also feature an EN input to control the
receiver outputs. Driving EN high disables all the inverting
(standard) receiver outputs placing them in a high
impedance state. This is useful to eliminate supply current,
due to a receiver output forward biasing the protection diode,
when driving the input of a powered down (VCC = GND)
peripheral (se e Figure 2). The enable input has no effect on
transmitter nor monitor (ROUTB) outputs.
Capacitor Selection
The charge pumps require 0.1µF capacitors for 3.3V
operation. For other supply voltages refer to Table 3 for
capacitor values. Do not use values smaller than those listed
in Table 3. Increasing the capacitor values (by a factor of 2)
reduces ripple on the transmitter outputs and slightly
reduces power consumption. C2, C3, and C4 can be
increased without increasing C1’s value, however, do not
increase C1 without also increasing C2, C3, and C4 to
maintain the proper ratios (C1 to the other capacitors).
When using minimum required capacitor values, make sure
that capacitor values do not degrade excessively with
temperature. If in doubt, use capacitors with a larger nominal
value. The capacitor’s equivalent series resistance (ESR)
usually rises at low temperatures and it influences the
amount of ripple on V+ and V-.
Power Supply Decoupling
In most circumstances a 0.1µF bypass capacitor is
adequate. In application s that are particularly sensitive to
power supply noise, decouple VCC to ground with a
capacitor of the same valu e as the charge-pump cap acitor C1.
Connect the byp ass cap acitor as close as possible to the IC .
Operation Down to 2.7V
ICL32xxE transmitter outputs meet RS-562 levels (±3.7V), at
full data rate, with VCC as low as 2.7V. RS-562 levels
typically ensure interoperability with RS-232 devices.
Transmitter Outputs when Exiting
Power-down
Figure 8 shows the response of two transmitter outputs
when exiting power-down mode. As they activate, the two
transmitter outputs properly go to opposite RS-232 levels,
with no glitching, ringing, nor undesirable tra nsients. Each
transmitter is loaded with 3kΩ in parallel with 2500pF. Note
that the transmitters enable only when the magnitud e of the
supplies exceed appro ximately 3V.
FIGURE 6. DEFINITION OF VALID RS-232 RECEIVER LEVELS
0.3V
-0.3V
-2.7V
2.7V
INVALID LEVEL - POWER-DOWN OCCURS AFTER 30µs
VALID RS-232 LEVEL - ICL32xxE IS ACTIVE
VALID RS-232 LEVEL - ICL32xxE IS ACTIVE
INDETERMINATE - POWER-DOWN MAY OR
INDETERMINAT E - POWER-DOWN MAY OR
MAY NOT OCCUR
MAY NOT OCCUR
RECEIVER
INPUTS
TRANSMITTER
OUTPUTS
INVALID
OUTPUT
V+
VCC
0
V-
VCC
0
tINVL tINVH
INVALID
REGION
}
FIGURE 7. AUTOMA TIC POWER-DOWN AND INVALID
TIMING DIAGRAMS
AUTOPWDN PWR UP
TABLE 3. REQUIRED CAPACITOR VALUES
VCC
(V) C1
(µF) C2, C3, C4
(µF)
3.0 to 3.6 0.1 0.1
4.5 to 5.5 0.047 0.33
3.0 to 5.5 0.1 0.47
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
15 FN4910.20
September 15, 2008
.
Mouse Driveability
The ICL3241E and ICL3243E have been specifically
designed to power a serial mouse while ope rating from low
voltage supplies. Figure 9 shows the transmitter output
voltages under increasing load current. The on-chip
switching regulator ensures the transmitters will supply at
least ±5V during worst case conditions (15mA for paralleled
V+ transmitters, 7.3mA for single V- transmitter). The
Automatic Power-down feature does not work with a mouse,
so FORCEOFF and FORCEON should be connecte d to VCC.
High Data Rates
The ICL32xxE maintain the RS-232 ±5V minimum
transmitter output voltages even at high data rates.
Figure 10 details a transmitter loopback test circuit, and
Figure 11 illustrates the loopback test result at 120kbps. For
this test, all transmitters were simultaneously driving RS-232
loads in parallel with 1000pF, at 120kbps. Figure 12 shows
the loopback results for a single transmitter driving 1000pF
and an RS-232 load at 250kbps. The static transmitters were
also loaded with an RS-232 receiver.
.
TIME (20µs/DIV)
T1
T2
2V/DIV
5V/DIV
VCC = +3.3V
FORCEOFF
FIGURE 8. TRANSMITTER OUTPUTS WHEN EXITING
POWER-DOWN
C1 - C4 = 0.1µF
FIGURE 9. TRANSMITTER OUTPUT VOL T AGE vs LOAD
CURRENT (PER TRANSMITTER, i.e., DOUBLE
CURRENT AXIS FOR TOTAL VOUT+ CURRENT)
TRANSMITTER OUTPUT VOLTAGE (V)
LOAD CURRENT PER TRANSMITTER (mA)
0246810
-6
-4
-2
0
2
4
6
-5
-3
-1
1
3
5
13579
VOUT+
VOUT -
VCC
VOUT+
VOUT -
T1
T2
T3
VCC = 3.0V
ICL3241E, ICL3243E
FIGURE 10. TRANSMITTER LOOPBACK TEST CIRCUIT
FIGURE 11. LOOPBACK TEST AT 120kbps
FIGURE 12. LOOPBACK TEST AT 250kbps
ICL32xxE
VCC FORCEOFF
C1
C2C4
C3
+
+
+
+
1000pF
V+
V-
5K
TIN
ROUT
C1+
C1-
C2+
C2-
RIN
TOUT
+
VCC 0.1µF
VCC
EN
SHDN OR
T1IN
T1OUT
R1OUT
5µs/DIV
VCC = +3.3V
5V/DIV
C1 - C4 = 0.1µF
T1IN
T1OUT
R1OUT
2µs/DIV
5V/DIV
VCC = +3.3V
C1 - C4 = 0.1µF
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
16 FN4910.20
September 15, 2008
Interconnection with 3V and 5V Logic
The ICL32XX directly interface with 5V CMOS and TTL logic
families. Nevertheless, with the ICL32XX at 3.3V, and the logic
supply at 5V, AC, HC, and CD4000 outputs can drive ICL32XX
inputs, but ICL32XX outputs do not reach the minimum VIH for
these logic families. See Table 4 for more information.
±15kV ESD Protection
All pins on ICL32XX devices include ESD protection
structures, but the ICL32xxE family incorporates advanced
structures which allow the RS-232 pins (transmitter outputs
and receiver inputs) to survive ESD events up to ±15kV. The
RS-232 pins are particularly vulnerable to ESD damage
because they typically connect to an exposed port on th e
exterior of the finished product. Simply touching the port
pins, or connecting a cable, can cause an ESD event that
might destroy unprotected ICs. These new ESD structures
protect the de vi ce wh e th er or not it is powered up, protect
without allowing any latch-up mechanism to activate, and
don’t interfere with RS-232 signals as large as ±25V.
Human Body Model (HBM) Testing
As the name implies, this test me thod emulates the ESD
event delivered to an IC during human handling. The tester
delivers the charge through a 1.5kΩ current limiting res istor,
making the test less severe than the IEC61000 test which
utilizes a 330Ω limiting resistor. The HBM method
determines an IC’s ability to withstand the ESD transients
typically present during handling and manufacturing. Due to
the random nature of these events, each pin is tested with
respect to all other pins. The RS-232 pins on “E” family
devices can withstand HBM ESD events to ±15kV.
IEC61000-4-2 Testing
The IEC61000 test method applies to finished equipment,
rather than to an individual IC. Therefore, the pins most likely
to suffer an ESD event are those that are exposed to the
outside world (the RS-232 pins in this case), and the IC is
tested in its typical application configuration (power applied)
rather than testing each pin-to-pin combination. The lower
current limiting resistor coupled with the larger charge
storage capacitor yields a test that is much more severe than
the HBM test. The extra ESD protection built into this
device’s RS-232 pins allows the design of equipment
meeting level 4 criteria without the need for additional board
level protection on the RS-232 port.
AIR-GAP DISCHARGE TEST METHOD
For this test method, a charged probe tip moves toward the
IC pin until the voltage arcs to it. The current waveform
delivered to the IC pin depends on approach speed,
humidity, temperature, etc., so it is difficult to obtain
repeatable results. The “E” device RS-232 pins withstand
±15kV air-gap discharges.
CONTACT DISCH ARGE TEST METHOD
During the contact discharge test, the probe contacts the
tested pin before the probe tip is energized, thereby
eliminating the variables asso ciated with the air-gap
discharge. The result is a more repeatable and predictable
test, but equipment limits prevent testing devices at voltages
higher than ±8kV. All “E” family devices survive ±8kV contact
discharges on the RS-232 pins.
T ABLE 4. LOGIC F AMILY COMP ATIBILITY WITH V ARIOUS
SUPPLY VOLTAGES
SYSTEM
POWER-SUPPLY
VOLTAGE (V) VCC SUPPLY
VO LTAGE ( V ) COMPATIBILITY
3.3 3.3 Compatible with all CMOS
families.
5 5 Compatible with all TTL and
CMOS logic families.
5 3.3 Compatible with ACT and HCT
CMOS, and with TTL. ICL32XX
outputs are inco mp at ible with
AC, HC, and CD4000 CMOS
inputs.
Typical Performance Curves VCC = 3.3V, TA = +25°C.
FIGURE 13. TRANSMITTER OUTPUT VOL T AGE vs LOAD
CAPACITANCE FIGURE 14. SLEW RATE vs LOAD CAPACITANCE
-6
-4
-2
0
2
4
6
1000 2000 3000 4000 50000
LOAD CAPACITANCE (pF)
TRANSMITTER OUTPUT VOLTAGE (V)
1 TRANSMITTER AT 250kbps
VOUT+
VOUT -
1 OR 2 TRANSMITTERS AT 30kbp s
LOAD CAPACITANCE (pF)
SLEW RATE (V/μs)
0 1000 2000 3000 4000 5000
5
10
15
20
25
+SLEW
-SLEW
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
17 FN4910.20
September 15, 2008
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND
TRANSISTOR COUNT:
ICL3221E: 286
ICL3222E: 338
ICL3223E: 357
ICL3232E: 296
ICL324XE: 464
PROCESS:
Si Gate CMOS
FIGURE 15. SUPPL Y CURRENT vs LOAD CAP ACIT ANCE
WHEN TRANSMITTING DATA FIGURE 16. SUPPL Y CURRENT vs LOAD CAP ACITANCE
WHEN TRANSMITTING DATA
FIGURE 17. SUPPL Y CURRENT vs LOAD CAP ACIT ANCE
WHEN TRANSMITTING DATA FIGURE 18. SUPPLY CURRENT vs SUPPLY VOLTAGE
Typical Performance Curves VCC = 3.3V, TA = +25°C. (Continued)
0
5
10
15
20
25
30
45
35
40
0 1000 2000 3000 4000 5000
LOAD CAPACITANCE (pF)
SUPPLY CURRENT (mA)
20kbps
250kbps
120kbps
ICL3221E
0
5
10
15
20
25
30
45
35
40
0 1000 2000 3000 4000 5000
LOAD CAPACITANCE (pF)
SUPPLY CURRENT (mA)
20kbps
250kbps
120kbps
ICL3222E, ICL3223E, ICL3232E
10
15
20
25
30
45
35
40
01000 2000 3000 4000 5000
LOAD CAPACITANCE (pF)
SUPPLY CURRENT (mA)
20kbps
250kbps
120kbps
ICL324XE
SUPPLY CURRENT (mA)
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
0
0.5
1.0
1.5
2.0
SUPPLY VOLTAGE (V)
2.5
3.0
3.5 NO LOAD
ALL OUTPUTS STATIC
ICL3221E, ICL3222E, ICL3223E, ICL3232E
ICL324XE
ICL324XE
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
18 FN4910.20
September 15, 2008
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Dual-In-Line Plastic Packages (PDIP)
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and are measured with the leads constrained to be perpendic-
ular to datum .
7. eB and eC are measured at the lead tips with the leads unconstrained.
eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3
may have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
eA
-C-
C
L
E
eA
C
eB
eC
-B-
E1
INDEX 12 3 N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-C-
D1
B1
B
e
D
D1
A
A2
L
A1
-A-
0.010 (0.25) C AMBS
E18.3 (JEDEC MS-001-BC ISSUE D)
18 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.210 - 5.33 4
A1 0.015 - 0.39 - 4
A2 0.115 0.195 2.93 4.95 -
B 0.014 0.022 0.356 0.558 -
B1 0.045 0.070 1.15 1.77 8, 10
C 0.008 0.014 0.204 0.355 -
D 0.845 0.880 21.47 22.35 5
D1 0.005 - 0.13 - 5
E 0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5
e 0.100 BSC 2.54 BSC -
eA0.300 BSC 7.62 BSC 6
eB- 0.430 - 10.92 7
L 0.115 0.150 2.93 3.81 4
N18 189
Rev. 2 11/03
19 FN4910.20
September 15, 2008
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Small Outline Plastic Packages (SOIC)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
INDEX
AREA E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45°
C
H0.25(0.010) BM M
α
M16.15 (JEDEC MS-012-AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0532 0.0688 1.35 1.75 -
A1 0.0040 0.0098 0.10 0.25 -
B 0.013 0.020 0.33 0.51 9
C 0.0075 0.0098 0.19 0.25 -
D 0.3859 0.3937 9.80 10.00 3
E 0.1497 0.1574 3.80 4.00 4
e 0.050 BSC 1.27 BSC -
H 0.2284 0.2440 5.80 6.20 -
h 0.0099 0.0196 0.25 0.50 5
L 0.016 0.050 0.40 1.27 6
N16 167
α0° 8° 0° 8° -
Rev. 1 6/05
20 FN4910.20
September 15, 2008
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Thin Shrink Small Outline Plastic Packages (TSSOP)
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AB, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.15mm (0.006
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact. (Angles in degrees)
α
INDEX
AREA E1
D
N
123
-B-
0.10(0.004) C AMBS
e
-A-
b
M
-C-
A1
A
SEATING PLAN E
0.10(0.004) c
E0.25(0.010) BM M
L
0.25
0.010
GAUGE
PLANE
A2
0.05(0.002)
M16.173
16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A-0.043 -1.10 -
A1 0.002 0.006 0.05 0.15 -
A2 0.033 0.037 0.85 0.95 -
b0.0075 0.012 0.19 0.30 9
c0.0035 0.008 0.09 0.20 -
D0.193 0.201 4.90 5.10 3
E1 0.169 0.177 4.30 4.50 4
e 0.026 BSC 0.65 BSC -
E0.246 0.256 6.25 6.50 -
L0.020 0.028 0.50 0.70 6
N16 167
α0o8o0o8o-
Rev. 1 2/02
21 FN4910.20
September 15, 2008
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Small Outline Plastic Packages (SSOP)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.20mm (0.0078
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.20mm (0.0078 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.13mm (0.005 inch) total in excess of “B” dimen-
sion at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
INDEX
AREA E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004) C
H0.25(0.010) BM M
α
0.25
0.010
GAUGE
PLANE
A2
M16.209 (JEDEC MO-150-AC ISSUE B)
16 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.078 - 2.00 -
A1 0.002 - 0.05 - -
A2 0.065 0.072 1.65 1.85 -
B 0.009 0.014 0.22 0.38 9
C 0.004 0.009 0.09 0.25 -
D 0.233 0.255 5.90 6.50 3
E 0.197 0.220 5.00 5.60 4
e 0.026 BSC 0.65 BSC -
H 0.292 0.322 7.40 8.20 -
L 0.022 0.037 0.55 0.95 6
N16 167
α0° 8° 0° 8° -
Rev. 3 6/05
22 FN4910.20
September 15, 2008
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Small Outline Plastic Packages (SOIC)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm (0.024
inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
INDEX
AREA E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45°
C
H0.25(0.010) BM M
α
M16.3 (JEDEC MS-013-AA ISSUE C)
16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0926 0.1043 2.35 2.65 -
A1 0.0040 0.0118 0.10 0.30 -
B 0.013 0.0200 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 -
D 0.3977 0.4133 10.10 10.50 3
E 0.2914 0.2992 7.40 7.60 4
e 0.050 BSC 1.27 BSC -
H 0.394 0.419 10.00 10.65 -
h 0.010 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6
N16 167
α0° 8° 0° 8° -
Rev. 1 6/05
23 FN4910.20
September 15, 2008
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Small Outline Plastic Packages (SOIC)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
INDEX
AREA E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45°
C
H0.25(0.010) BM M
α
M18.3 (JEDEC MS-013-AB ISSUE C)
18 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0926 0.1043 2.35 2.65 -
A1 0.0040 0.0118 0.10 0.30 -
B 0.013 0.0200 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 -
D 0.4469 0.4625 11.35 11.75 3
E 0.2914 0.2992 7.40 7.60 4
e 0.050 BSC 1.27 BSC -
H 0.394 0.419 10.00 10.65 -
h 0.010 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6
N18 187
α0° 8° 0° 8° -
Rev. 1 6/05
24 FN4910.20
September 15, 2008
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Thin Shrink Small Outline Plastic Packages (TSSOP)
α
INDEX
AREA E1
D
N
123
-B-
0.10(0.004) C AMBS
e
-A-
b
M
-C-
A1
A
SEATING PLANE
0.10(0.004) c
E0.25(0.010) BM M
L
0.25
0.010
GAUGE
PLANE
A2
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
0.05(0.002)
M20.173
20 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A-0.047 -1.20 -
A1 0.002 0.006 0.05 0.15 -
A2 0.031 0.051 0.80 1.05 -
b0.0075 0.0118 0.19 0.30 9
c0.0035 0.0079 0.09 0.20 -
D0.252 0.260 6.40 6.60 3
E1 0.169 0.177 4.30 4.50 4
e 0.026 BSC 0.65 BSC -
E0.246 0.256 6.25 6.50 -
L0.0177 0.0295 0.45 0.75 6
N20 207
α0o8o0o8o-
Rev. 1 6/98
25 FN4910.20
September 15, 2008
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Shrink Small Outline Plastic Packages (SSOP)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.20mm (0.0078 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall no t exceed 0.20mm (0.0078
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.13mm (0.005 inch) total in excess
of “B” dimension at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
α
INDEX
AREA E
D
N
123
-B-
0.25(0.010) C A
MBS
e
-A-
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004) C
H0.25(0.010) B
MM
L
0.25
0.010
GAUGE
PLANE
A2
M20.209 (JEDEC MO-150-AE ISSUE B)
20 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A0.068 0.078 1.73 1.99
A1 0.002 0.008’ 0.05 0.21
A2 0.066 0.070’ 1.68 1.78
B0.010’ 0.015 0.25 0.38 9
C0.004 0.008 0.09 0.20’
D0.278 0.289 7.07 7.33 3
E0.205 0.212 5.20’ 5.38 4
e 0.026 BSC 0.65 BSC
H0.301 0.311 7.65 7.90’
L0.025 0.037 0.63 0.95 6
N20 207
α0 deg. 8 deg. 0 deg. 8 deg.
Rev. 3 11/02
26 FN4910.20
September 15, 2008
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Thin Shrink Small Outline Plastic Packages (TSSOP)
α
INDEX
AREA E1
D
N
123
-B-
0.10(0.004) C AMBS
e
-A-
b
M
-C-
A1
A
SEATING PLANE
0.10(0.004) c
E0.25(0.010) BM M
L
0.25
0.010
GAUGE
PLANE
A2
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AE, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
0.05(0.002)
M28.173
28 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A-0.047 -1.20 -
A1 0.002 0.006 0.05 0.15 -
A2 0.031 0.051 0.80 1.05 -
b0.0075 0.0118 0.19 0.30 9
c0.0035 0.0079 0.09 0.20 -
D0.378 0.386 9.60 9.80 3
E1 0.169 0.177 4.30 4.50 4
e 0.026 BSC 0.65 BSC -
E0.246 0.256 6.25 6.50 -
L0.0177 0.0295 0.45 0.75 6
N28 287
α0o8o0o8o-
Rev. 0 6/98
27 FN4910.20
September 15, 2008
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Shrink Small Outline Plastic Packages (SSOP)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and ga te burrs shall not exceed
0.20mm (0.0078 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.20mm (0.0078
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.13mm (0.005 inch) total in excess of
“B” dimension at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
INDEX
AREA E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004) C
H0.25(0.010) BM M
α
0.25
0.010
GAUGE
PLANE
A2
M28.209 (JEDEC MO-150-AH ISSUE B)
28 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.078 - 2.00 -
A1 0.002 - 0.05 - -
A2 0.065 0.072 1.65 1.85 -
B 0.009 0.014 0.22 0.38 9
C 0.004 0.009 0.09 0.25 -
D 0.390 0.413 9.90 10.50 3
E 0.197 0.220 5.00 5.60 4
e 0.026 BSC 0.65 BSC -
H 0.292 0.322 7.40 8.20 -
L 0.022 0.037 0.55 0.95 6
N28 287
α0° 8° 0° 8° -
Rev. 2 6/05
28
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent rights of Int ersi l or it s sub sidi ari es.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN4910.20
September 15, 2008
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Small Outline Plastic Packages (SOIC)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
INDEX
AREA E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45o
C
H
µ
0.25(0.010) BM M
α
M28.3 (JEDEC MS-013-AE ISSUE C)
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A0.0926 0.1043 2.35 2.65 -
A1 0.0040 0.0118 0.10 0.30 -
B0.013 0.0200 0.33 0.51 9
C0.0091 0.0125 0.23 0.32 -
D0.6969 0.7125 17.70 18.10 3
E0.2914 0.2992 7.40 7.60 4
e 0.05 BSC 1.27 BSC -
H0.394 0.419 10.00 10.65 -
h0.01 0.029 0.25 0.75 5
L0.016 0.050 0.40 1.27 6
N28 287
α0o8o0o8o-
Rev. 0 12/93
