16-Bit, 1 MSPS, 8-Channel, Data Acquisition System ADAS3022 Data Sheet FEATURES and buffer; and a 16-bit charge redistribution analog-to-digital converter (ADC) with successive approximation register (SAR) architecture. The ADAS3022 can resolve eight single-ended inputs or four fully differential inputs up to 24.576 V when using 15 V supplies. In addition, the device can accept the commonly used bipolar differential, bipolar single-ended, pseudo bipolar, or pseudo unipolar input signals, as shown in Table 1, thus enabling the use of almost any direct sensor interface. Ease of use--16-bit, 1 MSPS complete data acquisition system High impedance, 8-channel input: >500 M Differential input voltage range: 24.576 V maximum High input common-mode rejection: >100 dB User-programmable input ranges Channel sequencer with individual channel gains On-chip 4.096 V reference and buffer Auxiliary input--direct interface to PulSAR ADC inputs No latency or pipeline delay (SAR architecture) Serial 4-wire, 1.8 V to 5 V SPI-/SPORT-compatible interface LFCSP package (6 mm x 6 mm) LQFP package (7 mm x 7 mm) -40C to +85C industrial temperature range The ADAS3022 simplifies design challenges by eliminating signal buffering, level shifting, amplification/attenuation, common-mode rejection, settling time, and any other analog signal conditioning challenge while allowing a smaller form factor, faster time to market, and lower cost. APPLICATIONS Table 1. Typical Input Range Selection Multichannel data acquisition and system monitoring Process control Power line monitoring Automated test equipment Instrumentation Signal Differential 1 V 2.5 V 5 V 10 V Single Ended 1 0 V to 1 V 0 V to 2.5 V 0 V to 5 V 0 V to 10 V GENERAL DESCRIPTION The ADAS3022 is a complete 16-bit, 1 MSPS, successive approximation based analog-to-digital data acquisition system, which is manufactured on Analog Devices, Inc., proprietary iCMOS(R) high voltage industrial process technology. The device integrates an 8-channel, low leakage multiplexer; a high impedance programmable gain instrumentation amplifier (PGIA) stage with high common-mode rejection; a precision, low drift 4.096 V reference 1 Input Range, VIN 1.28 V 2.56 V 5.12 V 10.24 V 1.28 V 2.56 V 5.12 V 10.24 V See Figure 60 and Figure 61 in the Analog Inputs section for more information. FUNCTIONAL BLOCK DIAGRAM VDDH IN0/IN1 DIFF TO COM DVDD VIO RESET ADAS3022 CNV LOGIC/ INTERFACE IN0 IN1 IN2/IN3 IN4/IN5 IN4 IN6/IN7 IN6 PulSAR ADC PGIA MUX IN5 IN7 COM BUSY CS IN2 IN3 PD SCK DIN SDO TEMP SENSOR REFIN BUF AUX+ REF AUX- VSSH AGND DGND REFx 10516-001 DIFF PAIR AVDD Figure 1. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2012-2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADAS3022 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Typical Application Connection Diagram .............................. 26 Applications ....................................................................................... 1 Analog Inputs.............................................................................. 27 General Description ......................................................................... 1 Voltage Reference Output/Input .............................................. 30 Functional Block Diagram .............................................................. 1 Power Supply............................................................................... 31 Revision History ............................................................................... 2 Conversion Modes ..................................................................... 32 Specifications..................................................................................... 3 Digital Interface .............................................................................. 33 Timing Specifications .................................................................. 7 Conversion Control ................................................................... 33 Absolute Maximum Ratings ............................................................ 9 Reset and Power-Down (PD) Inputs ....................................... 33 ESD Caution .................................................................................. 9 Serial Data Interface ................................................................... 34 Pin Configuration and Function Descriptions ........................... 10 General Considerations ............................................................. 35 Typical Performance Characteristics ........................................... 12 General Timing........................................................................... 36 Terminology .................................................................................... 22 Configuration Register .............................................................. 38 Theory of Operation ...................................................................... 24 On Demand Conversion Mode ................................................ 39 Overview...................................................................................... 24 Channel Sequencer Details ....................................................... 39 Operation..................................................................................... 24 Outline Dimensions ....................................................................... 42 Transfer Function ....................................................................... 25 Ordering Guide .......................................................................... 42 REVISION HISTORY 8/2018--Rev. C to Rev. D Added LQFP Package.................................................... Throughout Changes to Table 1 ............................................................................ 5 Changes to Table 3 ............................................................................ 7 Changes to Figure 5, Figure 5 Caption, and Table 5 .................. 11 Added Figure 6; Renumbered Sequentially and Table 6; Renumbered Sequentially.............................................................. 13 Changed ADAS3022 Operation Section to Operation Section ..... 25 Changes to Operation Section ...................................................... 25 Updated Outline Dimensions ....................................................... 43 Changes to Ordering Guide .......................................................... 43 2/2014--Rev. B to Rev. C Change to Figure 49 ....................................................................... 19 Change to Figure 54 ....................................................................... 24 Change to Table 7 ........................................................................... 25 Changes to Power-Down Mode Section ...................................... 30 Added On Demand Conversion Mode Section and Table 12; Renumbered Sequentially.............................................................. 37 Change to Table 13 ......................................................................... 37 Change to JEDEC Note, Figure 75 ............................................... 40 4/2013--Rev. A to Rev. B Changes to Table 1.............................................................................1 Added Input Impedance of 500 M Min, Table 2 ........................3 1/2013--Rev. 0 to Rev. A Removed Endnote 3 and Added TA = 25C to Gain Error Test Conditions/Comments, Table 2.......................................................3 Changes to REF1 and REF2 Description .................................... 11 Added Figure 25 to Figure 28; Renumbered Sequentially ........ 15 Changes to Figure 29...................................................................... 15 Added Figure 30 ............................................................................. 16 Changes to Figure 33, Figure 34, and Figure 35 ......................... 16 Changes to Figure 36 and Figure 37 ............................................ 17 Changes to Figure 50...................................................................... 19 Changes to Figure 54...................................................................... 24 Changes to Figure 56...................................................................... 25 Changes to Figure 57, Figure 58, Figure 59, and Figure 60....... 26 Changes to Voltage Reference Output/Input Section, Figure 62, and Figure 63................................................................................... 28 Changes to Core Supplies Section ................................................ 29 11/2012--Revision 0: Initial Version Rev. D | Page 2 of 42 Data Sheet ADAS3022 SPECIFICATIONS VDDH = 15 V 5%, VSSH = -15 V 5%, AVDD = DVDD = 5 V 5%, VIO = 1.8 V to AVDD, internal reference, VREF = 4.096 V, fS = 1 MSPS. All specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter RESOLUTION ANALOG INPUTS--IN[7:0], COM Operating Input Voltage Range Differential Input Voltage Range, VIN Input Impedance Channel Off Leakage Channel On Leakage Common-Mode Voltage Range 2 ANALOG INPUTS--AUX+, AUX- Differential Input Voltage Range THROUGHPUT Conversion Rate Transient Response DC ACCURACY No Missing Codes Integral Linearity Error Differential Linearity Error Transition Noise Gain Error Gain Error Temperature Drift Offset Error Test Conditions/Comments Min 16 VIN VIN+ - VIN- PGIA gain = 0.16, VIN = 49.15 V p-p PGIA gain = 0.2, VIN = 40.96 V p-p PGIA gain = 0.4, VIN = 20.48 V p-p PGIA gain = 0.8, VIN = 10.24 V p-p PGIA gain = 1.6, VIN = 5.12 V p-p PGIA gain = 3.2, VIN = 2.56 V p-p PGIA gain = 6.4, VIN = 1.28 V p-p ZIN Typ Max Unit 1 Bits -VSSH + 2.5 VDDH - 2.5 V -6 VREF -5 VREF -2.5 VREF -1.25 VREF -0.625 VREF -0.3125 VREF -0.1563 VREF 500 +6 VREF +5 VREF +2.5 VREF +1.25 VREF +0.625 VREF +0.3125 VREF +0.1563 VREF V V V V V V V M nA nA -5.12 -7.68 -8.96 -9.60 -9.92 +5.12 +7.68 +8.96 +9.60 +9.92 V V V V V -VREF +VREF V 0 0 0 0 1000 500 250 125 520 kSPS kSPS kSPS kSPS ns +2 +3 +5 +1.0 +1.25 +1.25 Bits LSB LSB LSB LSB LSB LSB +9 0.1 LSB LSB LSB LSB ppm/C +3.0 +4.0 +7.5 +12.5 LSB LSB LSB LSB 0.6 0.02 VIN+, VIN-; full-scale differential inputs PGIA gain = 0.4 PGIA gain = 0.8 PGIA gain = 1.6 PGIA gain = 3.2 PGIA gain = 6.4 One channel/one pair Two channels/two pairs Four channels/four pairs Eight channels Full-scale step PGIA gain = 0.16, 0.2, 0.4, 0.8, 1.6 PGIA gain = 3.2 PGIA gain = 6.4 PGIA gain = 0.16, 0.2, 0.4, 0.8, 1.6 PGIA gain = 3.2 PGIA gain = 6.4 External reference PGIA gain = 0.16, 0.2, 0.4, 0.8, 1.6 PGIA gain = 3.2 PGIA gain = 6.4 External reference, all PGIA gains, TA = 25C External reference, all PGIA gains External reference, TA = 25C PGIA gain = 0.16, 0.2, 0.4, 0.8 PGIA gain = 1.6 PGIA gain = 3.2 PGIA gain = 6.4 Rev. D | Page 3 of 42 16 -2 -3 -5 -0.9 -0.9 -0.9 0.6 1.0 1.5 0.6 0.75 0.75 5 7 11 -9 -3.0 -4.0 -7.5 -12.5 +0.2 +0.2 +0.2 +0.2 ADAS3022 Parameter Offset Error Temperature Drift Total Unadjusted Error AC ACCURACY 3 Signal-to-Noise Ratio (SNR) Signal-to-Noise-and-Distortion (SINAD) Dynamic Range Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR) Channel-to-Channel Crosstalk Common-Mode Rejection Ratio (CMRR) -3 dB Input Bandwidth AUXILIARY ADC INPUT CHANNEL DC Accuracy Integral Nonlinearity Error Differential Nonlinearity Error Gain Error Offset Error Data Sheet Test Conditions/Comments External reference PGIA gain = 0.16, 0.2, 0.4, 0.8 PGIA gain = 1.6 PGIA gain = 3.2 PGIA gain = 6.4 External reference, TA = 25C PGIA gain = 0.16, 0.2, 0.4, 0.8, 1.6, 3.2 PGIA gain = 6.4 fIN = 10 kHz PGIA gain = 0.16 PGIA gain = 0.2 PGIA gain = 0.4 PGIA gain = 0.8 PGIA gain = 1.6 PGIA gain = 3.2 PGIA gain = 6.4 fIN = 10 kHz PGIA gain = 0.16 PGIA gain = 0.2 PGIA gain = 0.4 PGIA gain = 0.8 PGIA gain = 1.6 PGIA gain = 3.2 PGIA gain = 6.4 fIN = 10 kHz, -60 dB input PGIA gain = 0.16 PGIA gain = 0.2 PGIA gain = 0.4 PGIA gain = 0.8 PGIA gain = 1.6 PGIA gain = 3.2 PGIA gain = 6.4 fIN = 10 kHz, all PGIA gains fIN = 10 kHz, all PGIA gains Min Max Unit 1 0.1 0.2 0.4 0.8 0.5 1.0 2.0 4.0 ppm/C ppm/C ppm/C ppm/C +9 +15 LSB LSB -9 -15 90.0 90.0 89.5 89.0 88.0 86.0 83.0 91.5 91.5 91.5 91.0 89.7 86.8 84.5 dB dB dB dB dB dB dB 88.0 88.0 88.5 88.5 87.5 85.5 82.5 90.0 90.0 91.0 90.5 89.5 86.5 84.0 dB dB dB dB dB dB dB 91.0 91.0 90.5 90.0 89.0 86.0 83.5 92.0 92.0 91.5 91.0 90.0 87.0 85.0 -100 101 dB dB dB dB dB dB dB dB dB -120 dB 90.0 90.0 90.0 90.0 110.0 105.0 98.0 98.0 8 dB dB dB dB MHz -1.5 -0.8 -2.5 -5 0.5 0.6 0.2 0.2 fIN = 10 kHz, all channels inactive fIN = 2 kHz PGIA gain = 0.16, 0.2, 0.4, 0.8 PGIA gain = 1.6 PGIA gain = 3.2 PGIA gain = 6.4 -40 dBFS Typ External reference Rev. D | Page 4 of 42 +1.5 +1.0 +2.5 +5 LSB LSB LSB LSB Data Sheet Parameter AC Performance Signal-to-Noise Ratio LFCSP LQFP Signal-to-Noise-and-Distortion LFCSP LQFP Total Harmonic Distortion Spurious-Free Dynamic Range INTERNAL REFERENCE REFx Output Voltage REFx Output Current REFx Temperature Drift REFx Line Regulation Internal Reference Buffer Only REFIN Output Voltage 4 Turn-On Settling Time EXTERNAL REFERENCE Voltage Range Current Drain TEMPERATURE SENSOR Output Voltage Temperature Sensitivity DIGITAL INPUTS Logic Levels VIL VIH VIL VIH IIL IIH DIGITAL OUTPUTS 5 Data Format VOL VOH POWER SUPPLIES VIO AVDD DVDD VDDH 6 VSSH6 IVDDH ADAS3022 Test Conditions/Comments Internal reference TA = 25C TA = 25C REFEN = 1 REFEN = 0 AVDD = 5 V 5% Min Typ 90.0 93.0 91 dB dB 89.5 92.5 90.5 -105 110 dB dB dB dB 4.088 4.096 250 5 1 TA = 25C CREFIN, CREF1, CREF2 = 10 F and 0.1 F 2.495 REFx input REFIN input (buffered) VREF = 4.096 V 4.000 TA = 25 C 20 4 2.500 100 4.096 2.5 100 Max 4.104 2.505 4.104 2.505 275 800 VIO > 3 V VIO > 3 V VIO 3 V VIO 3 V -0.3 0.7 x VIO -0.3 0.9 x VIO -1 -1 +0.3 x VIO VIO + 0.3 +0.1 x VIO VIO + 0.3 +1 +1 VIO - 0.3 VDDH > input voltage + 2.5 V VSSH < input voltage - 2.5 V PGIA gain = 0.16 PGIA gain = 0.2 PGIA gain = 0.4 PGIA gain = 0.8 PGIA gain = 1.6 PGIA gain = 3.2 PGIA gain = 6.4 All PGIA gains, PD = 1 Rev. D | Page 5 of 42 1.8 4.75 4.75 14.25 -15.75 5 5 15 -15 3.0 3.0 3.5 5.0 8.5 15.5 15.5 100 V A ppm/C ppm/C V/V V/V V ms V V A mV V/C Twos complement 0.4 ISINK = +500 A ISOURCE = -500 A PD = 0 Unit 1 AVDD + 0.3 5.25 5.25 15.75 -14.25 3.5 3.5 4.0 5.5 9.5 17.5 17.5 V V V V A A V V V V V V V mA mA mA mA mA mA mA A ADAS3022 Parameter IVSSH IAVDD IDVDD IVIO Power Supply Sensitivity At TA = 25C TEMPERATURE RANGE Specified Performance Data Sheet Test Conditions/Comments PGIA gain = 0.16 PGIA gain = 0.2 PGIA gain = 0.4 PGIA gain = 0.8 PGIA gain = 1.6 PGIA gain = 3.2 PGIA gain = 6.4 All PGIA gains, PD = 1 PGIA gain = 6.4, reference buffer enabled All other PGIA gains, reference buffer enabled PGIA gain = 6.4, reference buffer disabled All other PGIA gains, reference buffer disabled All PGIA gains, PD = 1 All PGIA gains, PD = 0 All PGIA gains, PD = 1 VIO = 3.3 V, PD = 0 PD = 1 Min -3.0 -3.0 -3.5 -5.5 -9.5 -17.5 -17.5 21.0 19.0 Unit 1 mA mA mA mA mA mA mA A mA mA 14 12 17.5 16.0 mA mA 100 2.5 10 0.30 10 External reference PGIA gain = 0.16, 0.2, 0.4, 0.8; VDDH/VSSH 5% PGIA gain = 3.2, VDDH/VSSH 5% PGIA gain = 6.4, VDDH/VSSH 5% PGIA gain = 0.16, AVDD/DVDD 5% PGIA gain = 0.2, AVDD/DVDD 5% PGIA gain = 0.4, AVDD/DVDD 5% PGIA gain = 0.8, AVDD/DVDD 5% PGIA gain = 1.6, AVDD/DVDD 5% PGIA gain = 3.2, AVDD/DVDD 5% PGIA gain = 6.4, AVDD/DVDD 5% TMIN to TMAX Typ -2.5 -2.5 -3.0 -4.5 -8.0 -15 -15 10 18 16 -40 Max 3.5 1.2 A mA A mA A 0.5 LSB 1.0 2.0 0.6 0.8 1.0 1.5 2.0 3.5 7.0 LSB LSB LSB LSB LSB LSB LSB LSB LSB +85 C LSB means least significant bit and changes depending on the voltage range. See the Programmable Gain section for the LSB size. The common-mode voltage (VCM) range for a PGIA gain of 0.16 or 0.2 is 0 V. All ac accuracy specifications expressed in decibels are referred to a full-scale input FSR and tested with an input signal at 0.5 dB below full scale, unless otherwise specified. 4 This is the output from the internal band gap reference. 5 There is no pipeline delay. Conversion results are available immediately after a conversion is complete. 6 The differential input common-mode voltage (VCM) range changes according to the maximum input range selected and the high voltage power supplies (VDDH and VSSH). Note that the specified operating input voltage of any input pin requires 2.5 V of headroom from the VDDH and VSSH supplies; therefore, (VSSH + 2.5 V) INx/COM (VDDH - 2.5 V). 1 2 3 Rev. D | Page 6 of 42 Data Sheet ADAS3022 TIMING SPECIFICATIONS VDDH = 15 V 5%, VSSH = -15 V 5%, AVDD = DVDD = 5 V 5%, VIO = 1.8 V to AVDD, internal reference, VREF = 4.096 V, fS = 1 MSPS. All specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter TIME BETWEEN CONVERSIONS Warp Mode, 1 CMS = 0 Normal Mode (Default), CMS = 1 CONVERSION TIME: CNV RISING EDGE TO DATA AVAILABLE Warp Mode, CMS = 0 Normal Mode (Default), CMS = 1 AUXILIARY ADC INPUT CHANNEL ACQUISITION TIME CNV Pulse Width High to Hold Time (Aperture Delay) High to Busy Delay SAFE DATA ACCESS TIME DURING CONVERSION QUIET CONVERSION TIME (BUSY HIGH) Warp Mode, CMS = 0 Normal Mode (Default), CMS = 1 DATA ACCESS DURING QUIET CONVERSION TIME Warp Mode, CMS = 0 Normal Mode (Default), CMS = 1 SCK Period Low Time High Time Falling Edge to Data Valid Falling Edge to Data Valid Delay VIO > 4.5 V VIO > 3.0 V VIO > 2.7 V VIO > 2.3 V VIO > 1.8 V CS/RESET/PD Low to SDO VIO > 4.5 V VIO > 3.0 V VIO > 2.7 V VIO > 2.3 V VIO > 1.8 V High to SDO High Impedance DIN VALID TIME FROM SCK RISING EDGE Setup Hold Time CNV Rising to CS RESET/PD High Pulse 1 Symbol tCYC Min Typ 1 1.1 Max Unit 1000 s s tCONV 825 925 tACQ 600 tCH tAD tCBD tDDC tQUIET 10 1000 ns ns ns 520 500 ns ns ns ns 415 500 ns ns 200 300 ns ns 2 tDDCA tSCK tSCKL tSCKH tSDOH tSDOD 15 5 5 4 ns ns ns ns 12 18 24 25 37 ns ns ns ns ns 15 16 18 23 28 25 ns ns ns ns ns ns tEN tDIS tDINS tDINH tCCS tRH 4 4 5 5 Exceeding the maximum time has an effect on the accuracy of the conversion (see the Conversion Modes section). Rev. D | Page 7 of 42 ns ns ns ns ADAS3022 Data Sheet 500A IOL 70% VIO 30% VIO CL 50pF tDELAY tDELAY 1.4V 2V OR VIO - IOH 12V IF VIO > 20.8V IF VIO 2.5V; VIO - 0.5V IF VIO < 2.5V. > 2.5V; 0.5V IF VIO < 2.5V. Figure 3. Voltage Levels for Timing Figure 2. Load Circuit for Digital Interface Timing tACQ SOC tCYC EOC SOC tQUIET tDDC POWER UP tDAC NOTE 1 ACQUISITION (n + 1) UNDEFINED CONVERSION (n) UNDEFINED ACQUISITION (n) UNDEFINED EOC NOTE 2 NOTE 1 CONVERSION (n - 1) UNDEFINED 0.8V OR 0.5V2 10516-003 500A PHASE 2V OR VIO - 0.5V1 0.5V1 0.8V OR 0.5V2 10516-002 TO SDO CONVERSION (n + 1) UNDEFINED CNV BUSY tDDCA NOTE 5 NOTE 2 tAD NOTE 4 CS X SCK 16/32 NOTE 3 1 16 1 DIN CFG INVALID CFG (n + 2) CFG (n + 2) CFG (n + 3) SDO DATA INVALID DATA (n - 1) INVALID DATA (n - 1) INVALID DATA (n) INVALID EOC ACQUISITION (n + 3) CONVERSION (n + 2) DATA (n) INVALID EOC EOC ACQUISITION (n + 2) PHASE CFG (n + 3) ACQUISITION (n + 4) CONVERSION (n + 3) CONVERSION (n + 4) CNV BUSY CS 1 16 1 16 1 DIN CFG (n + 4) CFG (n + 4) CFG (n + 5) CFG (n + 5) CFG (n + 6) CFG (n + 6) SDO DATA (n + 1) INVALID DATA (n + 1) INVALID DATA (n + 2) DATA (n + 2) DATA (n + 3) DATA (n + 3) NOTES 1. DATA ACCESS CAN OCCUR DURING A CONVERSION ( tDDC ), AFTER A CONVERSION (tDAC ), OR BOTH DURING AND AFTER A CONVERSION. THE CONVERSION RESULT AND THE CFG REGISTER ARE UPDATED AT THE END OF A CONVERSION (EOC). 2. DATA ACCESS CAN ALSO OCCUR UP TO tDDCA WHILE BUSY IS ACTIVE (SEE THE DIGITAL INTERFACE SECTION FOR DETAILS). ALL OF THE BUSY TIME CAN BE USED TO ACQUIRE DATA. 3. A TOTAL OF 16 SCK FALLING EDGES IS REQUIRED FOR A CONVERSION RESULT. AN ADDITIONAL 16 EDGES ARE REQUIRED TO READ BACK THE CFG RESULT ASSOCIATED WITH THE CURRENT CONVERSION. 4. CS CAN BE HELD LOW OR CONNECTED TO CNV. CS WITH FULL INDEPENDENT CONTROL IS SHOWN IN THIS FIGURE. 5. FOR OPTIMAL PERFORMANCE, DATA ACCESS SHOULD NOT OCCUR DURING THE SAMPLING EDGE. A MINIMUM TIME OF THE APERTURE DELAY (tAD) SHOULD ELAPSE PRIOR TO DATA ACCESS. Figure 4. General Timing Diagram Rev. D | Page 8 of 42 10516-028 SCK Data Sheet ADAS3022 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Analog Inputs/Outputs INx, COM to AGND AUX+, AUX- to AGND REFx to AGND REFIN to AGND REFN to AGND Ground Voltage Differences AGND, RGND, DGND Supply Voltages VDDH to AGND VSSH to AGND AVDD, DVDD, VIO to AGND ACAP, DCAP, RCAP to GND Digital Inputs/Outputs CNV, DIN, SCK, RESET, PD, CS to DGND SDO, BUSY to DGND Internal Power Dissipation Junction Temperature Storage Temperature Range JA Thermal Impedance JC Thermal Impedance Rating VSSH - 0.3 V to VDDH + 0.3 V -0.3 V to AVDD + 0.3 V AGND - 0.3 V to AVDD + 0.3 V AGND -0.3 V to +2.7 V 0.3 V Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION 0.3 V -0.3 V to +16.5 V +0.3 V to -16.5 V -0.3 V to +7 V -0.3 V to +2.7 V -0.3 V to VIO + 0.3 V -0.3 V to VIO + 0.3 V 2W 125C -65C to +125C 44.1C/W 0.28C/W Rev. D | Page 9 of 42 ADAS3022 Data Sheet 40 39 38 37 36 35 34 33 32 31 AUX- VDDH VSSH REFN REFN RGND REF2 REF1 REFIN RCAP PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADAS3022 TOP VIEW (Not to Scale) 30 29 28 27 26 25 24 23 22 21 NC NC AVDD DVDD ACAP DCAP AGND AGND DGND DGND NOTES 1. NC = NO CONNECT. THIS PIN IS NOT INTERNALLY CONNECTED. 2. EXPOSED PADDLE. THE EXPOSED PADDLE MUST BE CONNECTED TO VSSH. 10516-004 CS DIN RESET NC PD SCK VIO SDO BUSY CNV 11 12 13 14 15 16 17 18 19 20 IN0 1 IN1 2 IN2 3 IN3 4 AUX+ 5 IN4 6 IN5 7 IN6 8 IN7 9 COM 10 Figure 5. LFCSP Pin Configuration Table 5. LFCSP Pin Function Descriptions Pin No. 1 to 4 5 6 to 9 10 Mnemonic IN0 to IN3 AUX+ IN4 to IN7 COM Type 1 AI AI AI AI 11 CS DI 12 DIN DI 13 RESET DI 14, 29, 30 15 NC PD NC DI 16 17 SCK VIO DI P 18 SDO DO 19 BUSY DO 20 21, 22 23, 24 25 CNV DGND AGND DCAP DI P P P 26 ACAP P Description Input Channel 0 to Input Channel 3. Auxiliary Input Channel Positive Input. Input Channel 4 to Input Channel 7. IN[7:0] Common Channel Input. The IN[7:0] input channels can be referenced to a common point. The maximum voltage on this pin is 10.24 V for all PGIA gains except for a PGIA gain of 0.16, in which case the maximum voltage on this pin is 12.228 V. AUX+ and AUX- are not referenced to COM. Chip Select. Active low signal. Enables the digital interface for writing and reading data. Use this pin when sharing the serial bus. For a dedicated ADAS3022 serial interface, CS can be tied to DGND or CNV to simplify the interface. Data Input. Serial data input used for writing the 16-bit configuration word (CFG) that is latched on SCK rising edges. CFG is an internal register that is updated on the rising edge of the end of a conversion, which is the falling edge of BUSY. The configuration register can be written to during and after a conversion. Asynchronous Reset. A low-to-high transition resets the ADAS3022. The current conversion, if active, is aborted and CFG is reset to the default state. No Connect. This pin is not connected internally. Power-Down. A low-to-high transition powers down the ADAS3022, minimizing the bias current. Note that this pin must be held high until the user is ready to power on the device; after powering on the device, the user must wait 100 ms until the reference is enabled and then wait for the completion of two dummy conversions before the device is ready to convert. See the Power-Down Mode section for more information. Serial Clock Input. The DIN and SDO data sent to and from the ADAS3022 are synchronized with SCK. Digital Interface Supply. Nominally, this supply must be at the same voltage as the supply of the host interface: 1.8 V, 2.5 V, 3.3 V, or 5 V. Serial Data Output. The conversion result is output on this pin and is synchronized to SCK falling edges. The conversion result is output in twos complement format. Busy Output. An active high signal on this pin indicates that a conversion is in process. Reading or writing data during the quiet conversion phase (tQUIET) may cause incorrect bit decisions. Convert Input. A conversion is initiated on the rising edge of this pin. Digital Ground. Connect these pins to the system digital ground plane. Analog Ground. Connect these pins to the system analog ground plane. Internal 2.5 V Digital Regulator Output. Decouple this internally regulated output using a 10 F capacitor and a 0.1 F local capacitor. Internal 2.5 V Analog Regulator Output. This regulator supplies power to the internal ADC core and all of the supporting analog circuits with the exception of the internal reference. Decouple this internally regulated output using a 10 F capacitor and a 0.1 F local capacitor. Rev. D | Page 10 of 42 Data Sheet ADAS3022 Pin No. 27 28 31 Mnemonic DVDD AVDD RCAP Type 1 P P P 32 REFIN AI/O 33, 34 REF1, REF2 AI/O 35 36, 37 RGND REFN P P 38 VSSH P 39 VDDH P 40 AUX- EPAD AI Description Digital 5 V Supply. Decouple this supply using a 10 F capacitor and a 0.1 F local capacitor. Analog 5 V Supply. Decouple this supply using a 10 F capacitor and a 0.1 F local capacitor. Internal 2.5 V Analog Regulator Output. This regulator supplies power to the internal reference. Decouple this pin using a 1 F capacitor connected to RCAP and a 0.1 F local capacitor. Internal 2.5 V Band Gap Reference Output, Reference Buffer Input, or Reference Power-Down Input. See the Voltage Reference Input/Output section for more information. Reference Input/Output. Regardless of the reference method, these pins need individual decoupling using external 10 F ceramic capacitors connected as close to REF1, REF2, and REFN as possible. See the Voltage Reference Output/Input section for more information. REF1 and REF2 must be tied together externally. Reference Supply Ground. Connect this pin to the system analog ground plane. Reference Input/Output Ground. Connect the 10 F capacitors on REF1 and REF2 to these pins, and connect these pins to the system analog ground plane. High Voltage Analog Negative Supply. Nominally, the supply of this pin must be -15 V. Decouple this pin using a 10 F capacitor and a 0.1 F local capacitor. High Voltage Analog Positive Supply. Nominally, the supply of this pin must be +15 V. Decouple this pin using a 10 F capacitor and a 0.1 F local capacitor. Auxiliary Input Channel Negative Input. Exposed Paddle. The exposed paddle must be connected to VSSH. AI = analog input, AI/O = analog input/output, DI = digital input, DO = digital output, and P = power. 1 Rev. D | Page 11 of 42 RCAP REFIN REF1 REF2 NIC RGND REFN NIC NIC VSSH VDDH Data Sheet AUX- ADAS3022 48 47 46 45 44 43 42 41 40 39 38 37 IN0 1 36 NIC IN1 2 35 NIC IN2 3 34 NIC IN3 4 33 AVDD ADAS3022 NIC 5 32 NIC TOP VIEW (Not to Scale) AUX+ 6 IN4 7 31 DVDD 30 ACAP IN5 8 29 DCAP IN6 9 28 AGND IN7 10 27 AGND COM 11 26 DGND 25 DGND NIC 12 NIC = NOT INTERNALLY CONNECTED. 10516-306 CNV BUSY/SDO2 NIC SDO VIO SCK NIC PD AGND RESET CS DIN 13 14 15 16 17 18 19 20 21 22 23 24 Figure 6. LQFP Pin Configuration Table 6. 48-Lead LQFP Pin Function Descriptions Pin No. 1 to 4, 7 to 10 5, 12, 18, 22, 32, 34 to 36, 41, 44, 45 6 16, 27, 28 11 Mnemonic IN0 to IN7 Type 1 AI 13 CS 14 DIN DI 15 RESET DI 17 PD DI 19 SCK DI 20 VIO P 21 SDO DO NIC AUX+ AGND COM Description Input Channel 0 to Input Channel 7. Not Internally Connected PI AI Auxiliary Input Channel Positive Input. Analog Ground. Connect AGND to the system analog ground plane. IN0 to IN7 Common Channel Input. Input Channel IN0 to Input Channel IN7 are referenced to a common point. The maximum input voltage on this pin is 10.24 V for all PGIA gains. Chip Select. Active low signal. Enables the digital interface for writing and reading data. Use the CS pin when sharing the serial bus. For a dedicated and simplified ADAS3022 serial interface, tie CS to DGND or CNV. Data Input. DIN is the serial data input for writing the 16-bit configuration (CFG) word that is clocked into the device on the SCK rising edges. CFG is an internal register that is updated on the rising edge of the next end of a conversion pulse, which coincides with the falling edge of BUSY/SDO2. The CFG register is written into the device on the first 16 clocks after conversion. To avoid corrupting a conversion due to digital activity on the serial bus, do not write data during a conversion. Asynchronous Reset. A low to high transition resets the ADAS3022. The current conversion, if active, is aborted and the CFG register is reset to the default state. Power-Down. A low to high transition powers down the ADAS3022, minimizing the device operating current. PD must be held high until the user is ready to power on the device. After powering on the device, the user must wait 100 ms until the reference is enabled and then wait for the completion of one dummy conversion before the device is ready to convert. The RESET pin remains low for 100 ns after the release of PD. See the Power-Down Mode section for more information. Serial Clock Input. The DIN and SDO data sent to and from the ADAS3022 are synchronized with SCK. Digital Interface Supply. Nominally, it is recommended that VIO be at the same voltage as the supply of the host interface: 1.8 V, 2.5 V, 3.3 V, or 5 V. Serial Data Output. The conversion result is output on this pin and synchronized to the SCK falling edges. The conversion results are presented on this pin in twos complement format. Rev. D | Page 12 of 42 Data Sheet ADAS3022 Pin No. 23 Mnemonic BUSY/SDO2 Type 1 DO 24 25, 26 29 CNV DGND DCAP DI P P 30 ACAP P 31 DVDD P 33 AVDD P 37 RCAP P 38 REFIN 39, 40 REF1, REF2 AI/O 42 43 RGND REFN P P 46 VSSH P 47 VDDH P 48 AUX- AI 1 Description Busy/Serial Data Output 2. The converter busy signal is always output on the BUSY/SDO2 pin when CS is logic high. If SDO2 is enabled when CS is brought low after the end of conversion (EOC), the SDO outputs the data. The conversion result is output on this pin and synchronized to the SCK falling edges. The conversion results are presented on this pin in twos complement format. Convert Input. A conversion initiates on the rising edge of the CNV pin. Digital Ground. Connect DGND to the system digital ground plane. Internal 2.5 V Digital Regulator Output. Decouple DCAP, an internally regulated output, using a 10 F and a 0.1 F local capacitor. Internal 2.5 V Analog Regulator Output. This regulator supplies power to the internal ADC core and to all of the supporting analog circuits, except for the internal reference. Decouple this internally regulated output (ACAP) using a 10 F capacitor and a 0.1 F local capacitor. Digital 5 V Supply. Decouple the DVDD supply to DGND using a 10 F capacitor and 0.1 F local capacitor. Analog 5 V Supply. Decouple the AVDD supply to AGND using a 10 F capacitor and 0.1 F local capacitor. Internal 2.5 V Analog Regulator Output. RCAP supplies power to the internal reference. Decouple this internally regulated output (RCAP) using a 10 F capacitor and a 0.1 F local capacitor. Internal 2.5 V Band Gap Reference Output, Reference Buffer Input, or Reference Power-Down Input. REF1 and REF2 must be tied together externally. See the Voltage Reference Output/Input section for more information. Reference Input/Output. Regardless of the reference method, REF1 and REF2 require individual decoupling using external 10 F ceramic capacitors connected as close to REF1, REF2, and REFN as possible. See the Voltage Reference Output/Input section for more information. Reference Supply Ground. Connect RGND to the system analog ground plane. Reference Input/Output Ground. Connect the 10 F capacitors that are on REF1 and REF2 to the REFN pins, then connect the REFN pins to the system analog ground plane. High Voltage Analog Negative Supply. Nominally, the supply of VSSH is -15 V. Decouple VSSH using a 10 F capacitor and a 0.1 F local capacitor. Connect the exposed pad to VSSH. High Voltage Analog Positive Supply. Nominally, the supply of VDDH is 15 V. Decouple VDDH using a 10 F capacitor and a 0.1 F local capacitor. Auxiliary Input Channel Negative Input. AI = analog input, AI/O = analog input/output, DI = digital input, DO = digital output, and P = power. Rev. D | Page 13 of 42 ADAS3022 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS VDDH = 15 V, VSSH = -15 V, AVDD = DVDD = 5 V, VIO = 1.8 V to AVDD, unless otherwise noted. 0.50 0.5 0.25 0 -0.5 -0.25 -1.0 -0.50 -1.5 -0.75 24576 32768 40960 49152 57344 65536 -1.00 GAIN = 0.16, 0.2, 0.4, 0.8, 1.6 250,000 200,000 CODE IN HEX Figure 8. Integral Nonlinearity vs. Code, PGIA Gain = 3.2 400,000 GAIN = 6.4 INL MAX = 0.558 INL MIN = -1.319 GAIN = 3.2 350,000 300,000 0.5 250,000 213,200 200,000 8192 16384 24576 32768 40960 49152 CODE 57344 65536 1,600 CODE IN HEX Figure 9. Integral Nonlinearity vs. Code, PGIA Gain = 6.4 Figure 12. Histogram of a DC Input at Code Center, PGIA Gain = 3.2 Rev. D | Page 14 of 42 10516-119 0 25,500 22,700 1,400 8009 0 8008 -2.0 8007 50,000 129,000 8006 -1.5 118,400 8005 100,000 8004 -1.0 8003 150,000 10516-106 -0.5 8002 0 8001 COUNT 1.0 8000 1.5 INL (LSB) Figure 11. Histogram of a DC Input at Code Center, PGIA Gain = 0.16, 0.2, 0.4, 0.8, and 1.6 7FFF 2.0 6,400 600 8009 CODE 0 10516-117 57344 65536 8008 49152 8007 40960 8006 32768 8005 24576 10516-105 16384 52,300 8004 50,000 8003 -1.5 8002 100,000 8001 -1.0 152,600 8000 150,000 7FFF -0.5 7FFE 0 300,200 7FFD COUNT 0.5 8192 57344 65536 350,000 300,000 0 49152 40960 32768 400,000 1.0 -2.0 24576 16384 Figure 10. Differential Nonlinearity vs. Code for All PGIA Gains GAIN = 3.2 INL MAX = 1.026 INL MIN = -0.948 1.5 8192 CODE Figure 7. Integral Nonlinearity vs. Code, PGIA Gain = 0.16, 0.2, 0.4, 0.8, and 1.6 2.0 0 7FFE 16384 7FFD 8192 10516-101 0 CODE INL (LSB) 0 10516-108 DNL (LSB) 1.0 -2.0 FOR ALL GAINS 0.75 7FFC 1.5 INL (LSB) 1.00 GAIN = 0.16, 0.2, 0.4, 0.8, 1.6 INL MAX = 0.649 INL MIN = -0.592 7FFC 2.0 Data Sheet ADAS3022 400,000 100 GAIN = 6.4 80 300,000 70 COUNT 200,000 157,300 151,900 150,000 60 50 40 30 21,700 20 10 8009 CODE IN HEX 0 10516-120 8008 8007 8006 8004 8003 18,400 2,400 100 8001 7FFF 7FFE 7FFD 7FFC 200 300 8000 50,000 75,100 0 0.4 0.8 80 120 112 2.8 3.2 3.6 4.0 fS = 1000kSPS EXTERNAL 2.5V REFERENCE INTERNAL BUFFER 100 70 80 60 COUNT COUNT 2.4 2.0 Figure 16. Offset Drift, PGIA Gain = 6.4 EXTERNAL REFERENCE GAIN = 0.16, 0.2, 0.4, 0.8, 1.6 fS = 1000kSPS 90 1.6 OFFSET DRIFT (ppm/C) Figure 13. Histogram of a DC Input at Code Center, PGIA Gain = 6.4 100 1.2 10516-157 82,000 8005 100,000 8002 COUNT 250,000 0 EXTERNAL REFERENCE GAIN = 6.4 fS = 1000kSPS 90 350,000 50 72 60 40 40 30 23 20 20 10 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 OFFSET DRIFT (ppm/C) 0 1 2 3 4 5 6 7 8 REFERENCE BUFFER DRIFT (ppm/C) 120 100 EXTERNAL REFERENCE GAIN = 3.2 fS = 1000kSPS 90 80 10 fS = 1000kSPS INTERNAL 2.5V REFERENCE INTERNAL BUFFER 100 70 80 COUNT 60 50 60 46 38 40 30 20 35 30 20 15 10 0.2 0.4 0.6 0.8 1.0 1.2 1.4 OFFSET DRIFT (ppm/C) 1.6 1.8 2.0 10516-156 0 0 0 1 2 3 4 5 15 6 11 10 7 8 6 9 2 1 10 11 12 13 14 15 REFERENCE BUFFER DRIFT (ppm/C) Figure 18. Reference Buffer Drift, Internal Reference Figure 15. Offset Drift, PGIA Gain = 3.2 Rev. D | Page 15 of 42 10516-141 40 0 9 Figure 17. Reference Buffer Drift, External Reference Figure 14. Offset Drift, PGIA Gain = 0.16, 0.2, 0.4, 0.8, and 1.6 COUNT 2 0 10516-140 0 10516-155 0 ADAS3022 Data Sheet 0 0 -60 -40 -80 -100 -120 -60 -80 -100 -120 -140 -140 -160 -160 0 100 200 300 400 500 FREQUENCY (kHz) -180 0 100 Figure 19. 10 kHz FFT, PGIA Gain = 0.16 500 -40 -80 -100 -120 -80 -100 -120 -140 -140 -160 -160 0 100 200 300 400 500 FREQUENCY (kHz) SNR = 89.8dB SINAD = 89.7dB THD = -106dB SFDR = 107dB -60 -180 0 100 200 300 400 500 10516-125 AMPLITUDE (dBFS) -60 GAIN = 1.6 fS = 1000kSPS fIN = 10.1kHz -20 10516-122 AMPLITUDE (dBFS) -40 500 FREQUENCY (kHz) Figure 20. 10 kHz FFT, PGIA Gain = 0.2 Figure 23. 10 kHz FFT, PGIA Gain = 1.6 0 0 GAIN = 0.4 fS = 1000kSPS fIN = 10.1kHz SNR = 91.2dB SINAD = 91.0dB THD = -103dB SFDR = 104dB -40 -60 -40 -80 -100 -120 -80 -100 -120 -160 -160 200 300 FREQUENCY (kHz) 400 500 10516-123 -140 100 Figure 21. 10 kHz FFT, PGIA Gain = 0.4 SNR = 87.6dB SINAD = 87.5dB THD = -105dB SFDR = 106dB -60 -140 0 GAIN = 3.2 fS = 1000kSPS fIN = 10.1kHz -20 AMPLITUDE (dBFS) -20 AMPLITUDE (dBFS) 400 0 GAIN = 0.2 fS = 1000kSPS fIN = 10.1kHz SNR = 91.4dB SINAD = 89.9dB THD = -94.7dB SFDR = 94.8dB -20 -180 300 Figure 22. 10 kHz FFT, PGIA Gain = 0.8 0 -180 200 FREQUENCY (kHz) 10516-126 -180 10516-121 AMPLITUDE (dBFS) -40 GAIN = 0.8 fS = 1000kSPS fIN = 10.1kHz SNR = 90.7dB SINAD = 90.6dB THD = -107dB SFDR = 106dB -20 AMPLITUDE (dBFS) -20 10516-124 GAIN = 0.16 fS = 1000kSPS fIN = 10.1kHz SNR = 91.7dB SINAD = 89.2dB THD = -92.5dB SFDR = 92.5dB -180 0 100 200 300 FREQUENCY (kHz) Figure 24. 10 kHz FFT, PGIA Gain = 3.2 Rev. D | Page 16 of 42 400 Data Sheet ADAS3022 -55 0 GAIN = 6.4 fS = 1000kSPS fIN = 10.1kHz SNR = 85.7dB SINAD = 85.6dB THD = -101dB SFDR = 103dB -20 -60 -65 -70 -75 -80 THD (dB) -80 -100 -90 -95 -100 -120 -105 -140 -110 -115 -160 -120 0 100 200 300 400 500 FREQUENCY (kHz) -125 10516-127 -180 -85 -0.5dBFS -0.5dBFS -0.5dBFS -0.5dBFS -10dBFS -10dBFS -10dBFS -10dBFS 1 10 100 1000 FREQUENCY (kHz) 10516-304 AMPLITUDE (dBFS) -40 GAIN = 0.4, GAIN = 0.8, GAIN = 1.6, GAIN = 3.2, GAIN = 0.4, GAIN = 0.8, GAIN = 1.6, GAIN = 3.2, -60 Figure 28. THD vs. Frequency Figure 25. 10 kHz FFT, PGIA Gain = 6.4 -60 100 INTERNAL REFERENCE CHANNEL 4 TO COM, SEQUENCER DISABLED VIN = -0.5dBFS ON CHANNELS 0 TO 3, 5 TO 7 fS = 1000kSPS -70 95 -80 75 70 1 10 -100 -110 -120 -130 100 1000 FREQUENCY (kHz) -140 40 60 80 100 120 130 95 90 110 85 CMRR (dB) 80 75 GAIN = 0.4, -0.5dBFS GAIN = 0.8, -0.5dBFS GAIN = 1.6, -0.5dBFS GAIN = 3.2, -0.5dBFS GAIN = 0.4, -10dBFS GAIN = 0.8, -10dBFS GAIN = 1.6, -10dBFS GAIN = 3.2, -10dBFS 60 55 1 10 FREQUENCY (kHz) 200 90 COMMON-MODE AMPLITUDE = 20.48V p-p INTERNAL REFERENCE fS = 1000kSPS 70 100 180 100 80 1000 10516-302 65 160 GAIN = 0.16 GAIN = 0.20 GAIN = 0.40 GAIN = 0.80 GAIN = 1.60 GAIN = 3.20 GAIN = 6.40 120 70 140 Figure 29. Crosstalk vs. Frequency 100 SINAD (dB) 20 FREQUENCY (kHz) Figure 26. SNR vs. Frequency 50 0 10516-300 80 -0.5dBFS -0.5dBFS -0.5dBFS -0.5dBFS -10dBFS -10dBFS -10dBFS -10dBFS -90 Figure 27. SINAD vs. Frequency 60 1 10 100 1k FREQUENCY (Hz) Figure 30. CMRR vs. Frequency Rev. D | Page 17 of 42 10k 100k 10516-139 GAIN = 0.4, GAIN = 0.8, GAIN = 1.6, GAIN = 3.2, GAIN = 0.4, GAIN = 0.8, GAIN = 1.6, GAIN = 3.2, CROSSTALK (dB) 85 10516-303 SNR (dB) 90 ADAS3022 -50 PSRR VDDH AVDD, GAIN = 0.2 AVDD, GAIN = 3.2 -55 POWER SUPPLY REJECTION RATIO (dB) Data Sheet 20 PSRR VSSH AVDD, GAIN = 1.6 AVDD, GAIN = 6.4 GAIN = 0.2 GAIN = 1.6 -60 GAIN = 0.8 GAIN = 6.4 18 AVDD CURRENT (mA) -65 -70 -75 -80 -85 -90 16 14 12 1 10 100 FREQUENCY (kHz) 10 10516-301 0.1 GAIN = 0.2 GAIN = 1.6 15 GAIN = 0.2 GAIN = 1.6 GAIN = 0.4 GAIN = 3.2 GAIN = 0.8 GAIN = 6.4 14 AVDD CURRENT (mA) 18 17 16 15 13 12 11 4.8 4.9 5.0 5.1 5.2 AVDD SUPPLY (V) 5.3 9 10516-130 13 4.7 10 100 1000 THROUGHPUT (kSPS) 10516-135 10 14 Figure 35. AVDD Current vs. Throughput, External Reference Figure 32. AVDD Current vs. Supply, Internal Reference 4.5 15 GAIN = 0.2 GAIN = 1.6 4.0 DVDD CURRENT (mA) 14 13 12 GAIN = 0.4 GAIN = 3.2 GAIN = 0.8 GAIN = 6.4 3.5 3.0 2.5 2.0 1.5 11 10 4.7 4.8 GAIN = 0.4 GAIN = 3.2 4.9 1.0 GAIN = 0.8 GAIN = 6.4 5.0 5.1 5.2 AVDD SUPPLY (V) 5.3 10516-131 GAIN = 0.2 GAIN = 1.6 0.5 10 100 THROUGHPUT (kSPS) Figure 36. DVDD Current vs. Throughput Figure 33. AVDD Current vs. Supply, External Reference Rev. D | Page 18 of 42 1000 10516-136 AVDD CURRENT (mA) 1000 Figure 34. AVDD Current vs. Throughput, Internal Reference GAIN = 0.8 GAIN = 6.4 GAIN = 0.4 GAIN = 3.2 100 THROUGHPUT (kSPS) Figure 31. PSRR vs. Frequency 19 10 10516-134 -95 -100 0.01 AVDD CURRENT (mA) GAIN = 0.4 GAIN = 3.2 Data Sheet 18 GAIN = 0.2 GAIN = 1.6 ADAS3022 GAIN = 0.4 GAIN = 3.2 0 GAIN = 0.8 GAIN = 6.4 -2 -4 -6 VSSH CURRENT (mA) 12 9 6 -8 -10 -12 -14 -16 -18 10 100 -20 -50 -40 -30 -20 -10 10516-137 1000 THROUGHPUT (kSPS) 19.5 20 30 40 50 60 70 80 90 fS = 1000kSPS GAIN = 0.2 GAIN = 1.6 GAIN = 0.4 GAIN = 3.2 GAIN = 0.8 GAIN = 6.4 19.0 AVDD CURRENT (mA) -3 -6 -9 -12 -15 GAIN = 0.2 GAIN = 1.6 GAIN = 0.4 GAIN = 3.2 10 18.5 18.0 17.5 17.0 16.5 GAIN = 0.8 GAIN = 6.4 100 1000 THROUGHPUT (kSPS) 16.0 -50 -40 -30 -20 -10 10516-138 VSSH CURRENT (mA) 10 GAIN = 0.8 GAIN = 6.4 Figure 40. VSSH Current vs. Temperature 0 20 18 16 GAIN = 0.2 GAIN = 1.6 GAIN = 0.4 GAIN = 3.2 10 20 30 40 50 60 70 80 90 Figure 41. AVDD Current vs. Temperature 1.0 GAIN = 0.8 GAIN = 6.4 0.9 fS = 1000kSPS VIO = 3.3V fS = 1000kSPS GAIN = 0.2 GAIN = 1.6 GAIN = 0.8 GAIN = 6.4 GAIN = 0.4 GAIN = 3.2 0.8 DVDD CURRENT (mA) 14 12 10 8 6 0.7 0.6 0.5 0.4 0.3 0.2 2 0.1 0 10 20 30 40 50 60 TEMPERATURE (C) 70 80 90 10516-142 4 0 -50 -40 -30 -20 -10 0 TEMPERATURE (C) Figure 38. VSSH Current vs. Throughput VDDH CURRENT (mA) 0 GAIN = 0.4 GAIN = 3.2 TEMPERATURE (C) Figure 37. VDDH Current vs. Throughput -18 GAIN = 0.2 GAIN = 1.6 10516-144 0 10516-143 3 Figure 39. VDDH Current vs. Temperature 0 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 TEMPERATURE (C) Figure 42. DVDD Current vs. Temperature Rev. D | Page 19 of 42 70 80 90 10516-146 VDDH CURRENT (mA) 15 fS = 1000kSPS ADAS3022 3.75 fS = 1000kSPS GAIN = 0.2 GAIN = 1.6 GAIN = 0.4 GAIN = 3.2 5 GAIN = 0.8 GAIN = 6.4 4 3 GAIN ERROR (LSB) VIO CURRENT (mA) 3.50 3.25 3.00 2.75 2.50 2 10 20 30 40 50 60 70 80 90 1 0 -1 -2 -5 -50 -40 -30 -20 -10 10516-145 0 TEMPERATURE (C) fS = 1000kSPS 12 GAIN = 0.16 GAIN = 0.2 GAIN = 0.4 GAIN = 0.8 GAIN = 1.6 GAIN = 3.2 GAIN = 6.4 94 8 OFFSET ERROR (LSB) 96 0 10 20 30 40 TEMPERATURE (C) 50 60 70 80 90 70 80 90 70 80 90 Figure 46. Gain Error vs. Temperature Figure 43. VIO Current vs. Temperature SNR (dB) EXTERNAL REFERENCE -4 2.00 -50 -40 -30 -20 -10 98 fS = 1000kSPS -3 2.25 100 GAIN = 0.16 GAIN = 0.2 GAIN = 0.4 GAIN = 0.8 GAIN = 1.6 GAIN = 3.2 GAIN = 6.4 10516-149 4.00 Data Sheet 92 90 88 86 84 4 GAIN = 0.16 GAIN = 0.2 GAIN = 0.4 GAIN = 0.8 GAIN = 1.6 GAIN = 3.2 GAIN = 6.4 fS = 1000kSPS EXTERNAL REFERENCE 0 -4 -8 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (C) -12 -50 -40 -30 -20 -10 10516-147 80 -50 -40 -30 -20 -10 4 20 30 40 50 60 fS = 1000kSPS EXTERNAL REFERENCE 3 2 -95 -100 -105 1 GAIN ERROR 0 -1 OFFSET ERROR -2 -110 -3 -115 -120 -50 -40 -30 -20 -10 0 10 20 30 40 50 TEMPERATURE (C) Figure 45. THD vs. Temperature 60 70 80 90 -5 -50 -40 -30 -20 -10 0 10 20 30 40 TEMPERATURE (C) 50 60 10516-151 -4 10516-148 THD (dB) -90 5 GAIN = 0.16 GAIN = 0.2 GAIN = 0.4 GAIN = 0.8 GAIN = 1.6 GAIN = 3.2 GAIN = 6.4 ERROR (LSB) -85 10 Figure 47. Offset Error vs. Temperature Figure 44. SNR vs. Temperature -80 0 TEMPERATURE (C) 10516-150 82 Figure 48. Offset and Gain Errors of the AUX ADC Channel Pair vs. Temperature Rev. D | Page 20 of 42 Data Sheet ADAS3022 5200 5000 4800 4600 4400 4200 4000 3800 3400 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (C) 10516-152 3600 Figure 49. Temperature Sensor Output Code vs. Temperature fS = 1000 kSPS 0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -0.5dBFS -3.5 -4.0 -4.5 10k GAIN = 0.2 GAIN = 0.8 GAIN = 3.2 GAIN = 0.4 GAIN = 1.6 GAIN = 6.4 100k 1M FREQUENCY (Hz) 10M 28 20 24 20 15 16 10 12 8 5 4 0 0 100 200 300 400 500 600 700 800 900 0 1000 THROUGHPUT (kSPS) Figure 51. Temperature Sensor Output Error vs. Throughput 10516-153 NORMALIZED CLOSED-LOOP GAIN (dB) 0.5 TA = 25C INTERNAL REFERENCE Figure 50. Large Signal Frequency Response vs. Gain Rev. D | Page 21 of 42 TEMPERATURE SENSOR OUTPUT ERROR (C) TEMP SENSOR OUTPUT CODE (LSB) 5400 32 25 10516-154 TEMPERATURE SENSOR OUTPUT ERROR (mV) 5600 ADAS3022 Data Sheet TERMINOLOGY Operating Input Voltage Range Operating input voltage range is the maximum input voltage range, including the common-mode voltage, allowed on the input channels IN[7:0] and COM. Differential Nonlinearity (DNL) Error In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Differential Input Voltage Range Differential input voltage range is the maximum differential full-scale input range. The value changes according to the programmable gain setting. Offset Error Offset error is the deviation of the actual MSB transition from the ideal MSB transition point. The ideal MSB transition occurs at an input level 1/2 LSB above analog ground. Channel Off Leakage Channel off leakage is the leakage current with the channel off. Gain Error The last transition (from 111 ... 10 to 111 ... 11) for an analog voltage must occur 11/2 LSB below the nominal full scale. The gain error is the deviation expressed in LSB (or as a percentage of the full-scale range) of the actual level of the last transition from the ideal level after the offset error is removed. Closely related to this parameter is the full-scale error (also expressed in LSB or as a percentage of the full-scale range), which includes the effects of the offset error. Channel On Leakage Channel on leakage is the leakage current with the channel on. Charge Injection Charge injection is a measure of the glitch impulse that is transferred through the analog input pin into the source when the sample is taken and/or the multiplexer is switched. Common-Mode Rejection Ratio CMRR is the ratio of the amplitude of a signal referred to input in the converted result to the amplitude of the modulation common to a pair of inputs and is expressed in decibels. CMRR is a measure of the ability of the ADAS3022 to reject signals, such as power line noise, that are common to the inputs. This specification is for a 2 kHz sine wave of 20.48 V p-p applied to both channels of an input pair. Transient Response Transient response is a measure of the time required for the ADAS3022 to properly acquire the input after a full-scale step function is applied to the system. Least Significant Bit LSB is the smallest increment that can be represented by a converter. For a fully differential input ADC with N bits of resolution, the LSB expressed in volts is LSB (V) = 2VREF 2N Integral Nonlinearity Error INL refers to the deviation of each individual code from a line drawn from negative full scale to positive full scale. The point used as negative full scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as a level 11/2 LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (see Figure 54). Total Unadjusted Error (TUE) TUE is the deviation of each code from an ideal transfer function and is a combination of all error contributors, including nonlinearity, offset error, and gain error. TUE for the ADAS3022 is expressed as the maximum deviation in LSB or as a percentage of the full-scale range. Aperture Delay Aperture delay is a measure of the acquisition performance. It is the time between the rising edge of the CNV input and the point at which the input signal is held for a conversion. Dynamic Range Dynamic range is the ratio of the rms value of the full-scale signal to the total rms noise measured with the inputs shorted together. The value for the dynamic range is expressed in decibels. Signal-to-Noise Ratio SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Signal-to-Noise-and-Distortion Ratio SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels. Rev. D | Page 22 of 42 Data Sheet ADAS3022 Total Harmonic Distortion THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. Spurious-Free Dynamic Range SFDR is the difference, expressed in decibels, between the rms amplitude of the input signal and the peak spurious signal. Channel-to-Channel Crosstalk Channel-to-channel crosstalk is a measure of the level of crosstalk between any channel and all other channels. The crosstalk is measured by applying a dc input to the channel under test and applying a full-scale, 10 kHz sine wave signal to all other channels. The crosstalk is the amount of signal that leaks into the test channel and is expressed in decibels. Reference Voltage Temperature Coefficient Reference voltage temperature coefficient is derived from the typical shift of output voltage at 25C on a sample of parts at the maximum and minimum reference output voltage (VREF) measured at TMIN, T (25C), and TMAX. The value is expressed in ppm/C as TCV REF (ppm/C) = V REF ( Max ) - V REF ( Min) V REF (25C ) x (T MAX - T MIN ) x 10 6 where: VREF (Max) is the maximum reference output voltage at TMIN, T (25C), or TMAX. VREF (Min) is the minimum reference output voltage at TMIN, T (25C), or TMAX. VREF (25C) is the reference output voltage at 25C. TMAX = +85C. TMIN = -40C. Rev. D | Page 23 of 42 ADAS3022 Data Sheet THEORY OF OPERATION OVERVIEW Therefore, advantages of the ADAS3022 solution include reduced footprint and less complex design requirements, which also results in faster time to market and lower cost. The ADAS3022 is the first system on a single chip that integrates the typical components used in a data acquisition system in one easy to use, programmable device. This single-chip solution is capable of converting up to 1,000,000 samples per second (1 MSPS) of aggregate throughput. The ADAS3022 features * * * * * * * * OPERATION As shown in Figure 52, the ADAS3022 internal analog circuitry consists of a high impedance, low leakage multiplexer and a programmable gain instrumentation amplifier that can accept full-scale differential voltages of 0.64 V, 1.28 V, 2.56 V, 5.12 V, 10.24 V, 20.48 V, and 24.576 V. The ADAS3022 can be configured to use up to eight single-ended input channels or four pairs of channels, that is, 125 kSPS per channel for eight channels or effectively 250 kSPS for four channel pairs. The device can also provide a relative temperature measurement using the internal temperature sensor. In addition, the differential auxiliary channel pair (AUX+ and AUX-) is provided with the specified input range of VREF . This option bypasses the mux and PGIA stages, allowing direct access to the SAR ADC core. High impedance inputs High common-mode rejection 8-channel, low crosstalk multiplexer (mux) Programmable gain instrumentation amplifier (PGIA) with seven selectable differential input ranges from 0.64 V to 24.576 V 16-bit PulSAR(R) ADC with no missing codes Internal, precision, low drift 4.096 V reference and buffer Temperature sensor Channel sequencer The ADAS3022 uses an Analog Devices patented high voltage iCMOS process, allowing up to a 24.576 V differential input voltage range when using 15 V supplies, which makes the device suitable for industrial applications. Reducing the number of channels or pairs increases the throughput rate by an amount proportional to the reciprocal of the number of sampled channels multiplied by the aggregate throughput: The device is housed in a small, 6 mm x 6 mm, 40-lead LFCSP and a 7 mm x 7 mm, 48-lead LQFP and can operate over the industrial temperature range (-40C to +85C). A typical discrete multichannel data acquisition system containing similar circuitry requires at least three times more space on the printed circuit board (PCB). For a single channel or channel pair, the maximum throughput rate is 1 MSPS. For all eight channels, the AUX channel pair, and the temperature sensor, the throughput rate of a given channel decreases to 100 kSPS. VDDH IN0/IN1 DIFF TO COM AVDD VIO DVDD ADAS3022 RESET LOGIC/ INTERFACE IN0 IN1 IN2/IN3 IN4/IN5 IN4 IN6/IN7 IN6 PulSAR ADC PGIA MUX IN5 IN7 COM CNV BUSY CS IN2 IN3 PD SCK DIN SDO TEMP SENSOR REFIN BUF AUX+ REF AUX- VSSH AGND DGND REFx Figure 52. ADAS3022 Simplified Block Diagram Rev. D | Page 24 of 42 10516-005 DIFF PAIR 1/(Number of Channels or Pairs) x 1000 kSPS Data Sheet ADAS3022 When the sequencer option is used, an on-chip sequencer scans the channels in order and offers independent input voltage ranges for each channel (see the On Demand Conversion Mode section). In this mode, a single configuration word initiates the sequencer to scan repeatedly without the need to rewrite the register. After the last channel is scanned, the ADAS3022 automatically begins at IN0 again and repeats the sequence until a word is written to stop the sequencer or the asynchronous RESET is asserted. Additionally, if changes are made to certain configuration bits, the sequencer is reset to IN0. The PulSAR-based ADC core is capable of converting 1 MSPS from a single rising edge on the convert start input (CNV). The conversion results are available in twos complement format and are presented on the serial data output (SDO). The digital interface uses a dedicated chip select pin (CS) to transfer data to and from the ADAS3022 and also provides a BUSY indicator, asynchronous RESET, and power-down (PD) inputs. The ADAS3022 on-chip reference uses an internal temperature compensated 2.5 V output band gap reference and a precision buffer amplifier to provide the 4.096 V high precision system reference. tCYC tACQ PHASE HOLD 10516-006 CNV CONVERT/TRACK Figure 53. ADAS3022 System Timing Regardless of the type of signal (differential or single-ended, antiphase or nonantiphase, symmetric or asymmetric), the ADAS3022 converts all signals present on the enabled inputs in a differential fashion, like an industry-standard difference or instrumentation amplifier. The conversion result is available after the conversion completes and can be read back at any time before the end of the next conversion. Reading back data must be avoided during the quiet period, as indicated by BUSY being active high. Because the ADAS3022 has an on-board conversion clock, the serial clock (SCK) is not required for the conversion process. It is only required to present results to the user. TRANSFER FUNCTION The ideal transfer characteristics of the ADAS3022 are shown in Figure 54. With the inputs configured for differential input ranges, the data output is twos complement, as described in Table 7. TWOS COMPLEMENT All of the bits in Table 12 are configured through a serial (SPIcompatible), 16-bit configuration register (CFG). Configuration and conversion results can be read after or during a conversion, or the readback option can be disabled. The ADAS3022 requires a minimum of three power supplies: +5 V, +15 V, and -15 V. On-chip low dropout regulators provide the necessary 2.5 V system voltages and must be decoupled externally via dedicated pins (ACAP, DCAP, and RCAP). The ADAS3022 can be interfaced to any 1.8 V to 5 V digital logic family using the dedicated VIO logic level voltage supply (see Table 10). Rev. D | Page 25 of 42 011 ... 111 011 ... 110 011 ... 101 100 ... 010 100 ... 001 100 ... 000 -FSR -FSR + 1LSB -FSR + 0.5LSB +FSR - 1LSB +FSR - 1.5LSB ANALOG INPUT Figure 54. ADC Ideal Transfer Function 10516-007 The inputs are multiplexed to the PGIA using a high voltage multiplexer with low charge injection and very low leakage. The inputs can be configured for a single-ended to common point (COM) measurement or can be paired for up to four fully differential inputs with independent gain settings. This requires using the advanced sequencer or programming sequential configuration words with the desired gain for each pair. The digitally controlled, programmable gain is used to select one of seven voltage input ranges (see Table 8). A rising edge on CNV initiates a conversion and changes the state of the ADAS3022 from track to hold. In this state, the ADAS3022 performs analog signal conditioning. When the signal conditioning is complete, the ADAS3022 returns to the track state while at the same time quantizing the sample. This two-part process satisfies the necessary settling time requirement while achieving a fast throughput rate of up to 1 MSPS with 16-bit accuracy. Figure 53 shows the timing diagram and the tCYC start at the positive edge of the CNV. ADC CODE The ADAS3022 offers true high impedance inputs in a differential structure and rejects common-mode signals present on the inputs. The ADAS3022 architecture does not require any of the additional input buffers (op amps) that are usually required to condition the input signal and drive the ADC inputs when using switched capacitor-based SAR ADCs. ADAS3022 Data Sheet TYPICAL APPLICATION CONNECTION DIAGRAM Table 7. Output Codes and Ideal Input Voltages Midscale Midscale - 1 LSB -FSR + 1 LSB -FSR 0x0001 0x0000 0xFFFF 0x8001 0x8000 D2 L2 47H C2 1F + 1.78 RFILT + L1 47H VIN = +5V CIN + 1F 50k ADP1613 + COMP CC2 10pF L3 1F R C1 100k FREQ EN VIN GND SW +15V COUT1 + COUT2 + 2.2F 1F CV5 + RS2 DNI 1F VDDH IN0 IN1 IN2 IN2/IN3 IN3 IN4 IN4/IN5 IN5 IN6 IN6/IN7 IN7 AVDD DVDD MUX PGIA CNV TEMP SENSOR PulSAR ADC SCK DIN REFIN BUF REF AUX- VSSH AGND DGND REFx +5V +5V 4.096V + - RF1B 47.5k AD8031 Figure 55. Complete 5 V, Single-Supply, 8-Channel Multiplexed Data Acquisition System with PGIA Rev. D | Page 26 of 42 BUSY SDO -15V RF2 4.22k PD CS COM AUX+ Z1 DNI RESET LOGIC/ INTERFACE IN0/IN1 CSS + 1F VIO ADAS3022 DIFF DIFF PAIR COM RS1 0 SS FB +5V D1 REN ENABLE C C1 + 12nF C1 1F RB0 1 COUT3 4.7F ADR434 10516-200 Midscale + 1 LSB As shown in Figure 55, the ADP1613 is used in an inexpensive SEPIC-uk topology, which is an ideal candidate for providing the ADAS3022 with the necessary high voltage 15 V robust supplies (at 20 mA) and low output ripple (3 mV maximum) from an external 5 V supply. The ADP1613 satisfies the specification requirements of the ADAS3022 with minimal external components while achieving greater than 86% of efficiency. Refer to the CN-0201 circuit note for complete information about this test setup. Digital Output Code (Twos Complement, Hex) 0x7FFF + Description FSR - 1 LSB Differential Analog Inputs, VREF = 4.096 V (32,767 x VREF)/ (32,768 x PGIA gain) VREF/(32,768 x PGIA gain) 0 -(VREF/(32,768 x PGIA gain)) -(32,767 x VREF)/ (32,768 x PGIA gain) -VREF x PGIA gain Data Sheet ADAS3022 ANALOG INPUTS Input Structure The ADAS3022 uses a differential input structure between IN[7:0] and COM or between IN[7:0]+ and IN[7:0]- of a channel pair. The COM input is sampled identically such that the same voltages can be present on inputs IN[7:0]. Therefore, the selection of paired channels or all channels referenced to one common point is available. Because all inputs are sampled differentially, the ADAS3022 offers true high common-mode rejection, whereas a discrete system requires the use of additional instrumentation or a difference amplifier. Figure 56 shows an equivalent circuit of the analog inputs. The internal diodes provide ESD protection for the analog inputs (IN[7:0] and COM) from the high voltage supplies (VDDH and VSSH). Take care to ensure that the analog input signal does not exceed the supply rails by more than 0.3 V because this can cause the diodes to become forward-biased and to start conducting current. Note that if the auxiliary input pair (AUX) is used, the diodes provide ESD protection from only the lower voltage AVDD (5 V) supply and the system analog ground because these inputs are connected directly to the internal SAR ADC circuitry. VDDH MUX PGIA CPIN Table 8 describes each differential input range and the corresponding LSB size, PGIA bits settings, and PGIA gain. Table 8. Differential Input Ranges, LSB Size, and PGIA Settings Differential Input Ranges, INx+ - INx- (V) 24.576 20.48 10.24 5.12 2.56 1.28 0.64 PGIA Bits 000 111 001 010 011 100 101 PGIA Gain (V/V) 0.16 0.2 0.4 0.8 1.6 3.2 6.4 Common-Mode Operating Range The differential input common-mode voltage (VCM) range changes according to the maximum input range selected and the high voltage power supplies (VDDH and VSSH). Note that the specified operating input voltage of any input pin (see the Specifications section) requires 2.5 V of headroom from the VDDH and VSSH supplies; therefore, VSSH (VSSH + 2.5 V) INx/COM (VDDH - 2.5 V) AVDD This section provides some examples of setting the PGIA for various input signals. Note that the ADAS3022 always calculates the difference between the IN+ and IN- signals. AUX+ OR AUX- 10516-008 CPIN AGND LSB ( V) 750 625 312.5 156.3 78.13 39.06 19.53 Figure 56. Equivalent Analog Input Circuit Fully Differential, Antiphase Signals with a Zero Common Mode For a pair of 20.48 V p-p differential antiphase signals with a zero common mode, the maximum differential voltage across the inputs is 20.48 V, and the PGIA gain configuration must be set to 111. Voltages beyond the absolute maximum ratings may cause permanent damage to the ADAS3022 (see Table 4). Programmable Gain The ADAS3022 incorporates a programmable gain instrumentation amplifier with seven selectable ranges (0.64 V, 1.28 V, 2.56 V, 5.12 V, 10.24 V, 20.48 V, and 24.576 V), enabling the use of almost any direct sensor interface. The PGIA settings are specified in terms of the maximum absolute differential input voltage across a pair of inputs (for example, INx+ to INx- or INx+ to COM). The power-on and default conditions are preset to the 20.48 V (PGIA = 111) input range. +10.24V INx+ INx+ 20.48V p-p ADAS3022 -10.24V INx- 20.48V p-p INx- 10516-009 IN[7:0] OR COM Note that because the ADAS3022 can use any input type, such as bipolar differential (antiphase or nonantiphase), bipolar single ended, or pseudo bipolar, setting the PGIA is important to make full use of the allowable input span. Figure 57. Differential, Antiphase Inputs with a Zero Common Mode Rev. D | Page 27 of 42 ADAS3022 Data Sheet Single-Ended Signals with a 0 V DC Offset (Symmetrical) Fully Differential, Antiphase Signals with a Nonzero Common Mode Compared with the example in the Single-Ended Signals with a Nonzero DC Offset (Asymmetrical) section, a better solution for single-ended signals, if possible, is to remove as much dc offset as possible between INx+ and INx- to produce a bipolar input voltage that is symmetric around the ground sense. In this example, the differential voltage across the inputs is never greater than 0.64 V, and the PGIA gain configuration is set to 101 for the 1.28 V p-p range. This scenario uses all of the codes available for the transfer function, making full use of the allowable differential input range. INx+ INx- VCM = 7V ADAS3022 VCM 0V 5.12V p-p 10516-010 INx+ 5.12V p-p INx- +0.64V Figure 58. Differential, Antiphase Inputs with a Nonzero Common Mode Differential, Nonantiphase Signals with a Zero Common Mode -0.64V INx+ ADAS3022 0V -5.12V INx- 10.24V p-p INx- Figure 59. Differential, Nonantiphase Inputs with a Zero Common Mode Single-Ended Signals with a Nonzero DC Offset (Asymmetrical) When a 12 V p-p signal with a 6 V dc level-shift is connected to one input (INx+) and the dc ground sense of the signal is connected to INx- or COM, the PGIA gain configuration is set to 000 for the 24.576 V range because the maximum differential voltage across the inputs is 12 V p-p and only half the codes available for the transfer function are used. INx+ VOFF 0V INx- Notice that the voltages in this example are not integer values due to the 4.096 V reference and the PGIA scaling ratios. INx+ The ADAS3022 uses a high voltage, high performance, low charge injection multiplexer and a total of nine inputs (IN[7:0] and COM). Using the INx and COM bits of the configuration register, the ADAS3022 is configurable for differential inputs between any of the eight input channels (IN[7:0]) and COM or for up to four input pairs. Figure 62 shows various methods for configuring the analog inputs for the type of channel (single or paired). Refer to the Configuration Register section for more information. The analog inputs can be configured as follows: * * * 12V p-p ADAS3022 VOFF INx- ADAS3022 Figure 61. Better Single-Ended Configuration--Uses All Codes 10516-012 +12V 1.28V p-p Multiplexer 10.24V p-p 10516-011 +5.12V INx- INx- For a pair of 10.24 V p-p differential nonantiphase signals with a zero common mode, the maximum differential voltage across the inputs is 10.24 V, and the PGIA gain configuration must be set to 001. INx+ INx+ INx+ 10516-013 For a pair of 5.12 V p-p differential antiphase signals with a nonzero common mode (dc common-mode voltage of 7 V in this example), the maximum differential voltage across the inputs is 5.12 V (dc common-mode voltage is rejected), and the PGIA gain configuration must be set to 010. Figure 60. Typical Single-Ended Unipolar Input--Uses Only Half the Codes * Rev. D | Page 28 of 42 Figure 62A: IN[7:0] referenced to a system ground. Figure 62B: IN[7:0] with a common reference point. Figure 62C: IN[7:0] differential pairs. For pairs, COM = 0. The positive channel is configured with INx. If INx is even, then IN0, IN2, IN4, and IN6 are used. If INx is odd, then IN1, IN3, IN5, and IN7 are used, as indicated by the channels with parentheses in Figure 62C. For example, for the IN0/IN1 pair with the positive channel on IN0, INx = 0002. For the IN4/IN5 pair with the positive channel on IN5, INx = 1012. Note that when the channel sequencer is used, as detailed in the On Demand Conversion Mode section, the positive channels are always IN0, IN2, IN4, and IN6. Figure 62D: inputs configured in a combination of any of the preceding configurations (showing that the ADAS3022 can be configured dynamically). Data Sheet ADAS3022 IN0+ IN0 IN0+ IN0 IN1+ IN1 IN1+ IN1 IN2+ IN2 IN2+ IN2 IN3+ IN3 IN3+ IN3 IN4+ IN4 IN4+ IN4 IN5+ IN5 IN5+ IN5 IN6+ IN6 IN6+ IN6 IN7+ IN7 IN7+ IN7 COM- A--8 CHANNELS, SINGLE-ENDED B--8 CHANNELS, COMMON REFERENCE IN0+ (-) IN0 IN0+ (-) IN0 IN1 IN0- (+) IN1 IN1+ (-) IN2 IN1+ (-) IN2 IN1- (+) IN3 IN1- (+) IN3 IN2+ (-) IN4 IN2+ IN4 IN2- (+) IN5 IN3+ IN5 IN3+ (-) IN6 IN4+ IN6 IN3- (+) IN7 IN5+ IN7 C--4 CHANNELS, DIFFERENTIAL * COM IN0- (+) COM For systems that cannot drive AUX directly, a suitable op amp buffer must be used to preserve the ADAS3022 performance. The driver amplifier must meet the following requirements: COM- COM D--COMBINATION The noise generated by the driver amplifier must be kept as low as possible to preserve the SNR and the transition noise performance of the ADAS3022. The noise from the amplifier is filtered by the ADAS3022 analog input circuit or by an external filter, if one is used. Because the typical noise of the SAR ADC core of the ADAS3022 is 35 V rms (VREF = 4.096 V), the SNR degradation due to the amplifier is SNRLOSS 10516-014 COM Driver Amplifier Choice Figure 62. Multiplexed Analog Input Configurations * Channel Sequencer The ADAS3022 includes a channel sequencer that is useful for scanning channels in a repeated fashion. Refer to the On Demand Conversion Mode section for more information. * Auxiliary Input Channel The ADAS3022 includes an auxiliary input channel pair (AUX+ and AUX-) that bypasses the mux and PGIA stages, allowing direct access to the SAR ADC core for applications where the additional dedicated channel pair is required. As detailed previously, the inputs are protected only from AVDD and AGND because the high voltage supplies are used for the mux and PGIA stages but not the lower voltage ADC core. When the source impedance of the driving circuit is low, the AUX inputs can be driven directly. Large source impedances significantly affect the ac performance, especially THD. The dc performance parameters are less sensitive to the input impedance. The maximum source impedance depends on the amount of THD that can be tolerated. The THD degrades as a function of the source impedance and the maximum input frequency. 35 = 20 log 2 2 35 + f -3dB (Ne N ) 2 where: f-3dB is the input bandwidth (8 MHz) of the' SAR ADC core of the ADAS3022 expressed in megahertz or the cutoff frequency of an input filter, if one is used. N is the noise gain of the amplifier (for example, 1 in buffer configuration). eN is the equivalent input noise voltage of the op amp expressed in nV/Hz. For ac applications, the driver must have a THD performance commensurate with the ADAS3022. The analog input circuit must settle a full-scale step onto the capacitor array at a 16-bit level (0.0015%). In amplifier data sheets, settling at 0.1% to 0.01% is more commonly specified. This may differ significantly from the settling time at a 16-bit level and must be verified prior to driver selection. Table 9. Recommended Driver Amplifiers Amplifier ADA4841-1, ADA4841-2 ADA4897-1, ADA4897-2 AD8655 AD8021, AD8022 OP184 AD8605, AD8615 Rev. D | Page 29 of 42 Typical Application Very low noise, small, and low power Very low noise, low and high frequencies 5 V single supply, low noise Very low noise and high frequency Low power, low noise, and low frequency 5 V single supply, low power ADAS3022 Data Sheet The ADAS3022 allows the choice of an internal reference or an external reference using the on-chip buffer/amplifier, or an external reference. The internal reference of the ADAS3022 provides excellent performance and can be used in almost all applications. To set the reference selection mode, use the internal reference enable bit (REFEN) and the REFIN pin as described in this section. REF1 and REF2 must be tied together externally. With REFIN = 2.5 V, REF1 and REF2 output 4.096 V, which serves as the main system reference. For this configuration, connect the external source as shown in Figure 64. Any type of 2.5 V reference, including those with low power, low drift, and a small package, can be used in this configuration because the internal buffer handles the dynamics of the ADAS3022 reference. 0.1F 0.1F 10F Internal Reference 10F REFN REF2 REFN The precision internal reference is factory trimmed and is suitable for most applications. The internal reference output is trimmed to the targeted value of 4.096 V with an initial accuracy of 8 mV. The reference is also temperature compensated to provide a typical drift of 5 ppm/C. When the internal reference is used, the ADAS3022 must be decoupled as shown in Figure 63. Note that both REF1 and REF2 connections are required, along with suitable decoupling on the REFIN output and the RCAP internally regulated supply. 10F REFN REF2 REFN ADAS3022 External Reference For applications that require a precise, low drift 4.096 V reference, an external reference can also be used. This option requires disabling the internal buffer by setting REFEN to 0 and driving or connecting REFIN to AGND; therefore, both hardware and software control are necessary. Attempting to drive the REF1 and REF2 pins prior to disabling the internal buffer can cause source/sink contention in the driving amplifiers. Connect the precision 4.096 V reference, which serves as the main system reference, through a low impedance buffer (such as the AD8031 or the AD8605) to REF1 and REF2 as shown in Figure 65. Recommended references include the ADR434, ADR444, and ADR4540. REFERENCE SOURCE = 4.096V 10F 0.1F 10F REFIN BAND GAP RCAP 1F BAND GAP Figure 64. External Reference Using Internal Buffer 0.1F REF1 REFN REFIN RGND REFN RCAP 1F RGND 10516-016 10F REF1 REFN 0.1F 10F REF2 REFN ADAS3022 REFIN REF1 BAND GAP RGND Figure 63. 4.096 V Internal Reference Connection External Reference and Internal Buffer RCAP 1F 10516-018 0.1F REFERENCE SOURCE = 2.5V 10F ADAS3022 Setting the REFEN bit in the CFG register to 1 (default) enables the internal reference and produces 4.096 V on the REF1 and REF2 pins; this 4.096 V output serves as the main system reference. The unbuffered 2.5 V (typical) band gap voltage is output on the REFIN pin, which requires an external parallel decoupling using 10 F and 0.1 F capacitors to reduce the noise on the output. Because the current output of REFIN is limited, it can be used as a source if followed by a suitable buffer, such as the AD8031. Note that excessive loading of the REFIN output also lowers the 4.096 V system reference because the internal amplifier uses a fixed gain. 0.1F 0.1F 10516-017 VOLTAGE REFERENCE OUTPUT/INPUT Figure 65. External Reference The external reference and internal buffer are useful when a common system reference is used or if improved drift performance is required. Setting REFEN to 0 disables the internal band gap reference, allowing the user to provide an external voltage reference (2.5 V typical) to the REFIN pin. The internal buffer remains enabled, thus reducing the need for an external buffer amplifier to generate the main system reference. If an op amp is used as the external reference source, take note of any concerns regarding driving capacitive loads. Capacitive loading for op amps usually refers to the ability of the amplifier to remain marginally stable in ac applications but can also play a role in dc applications, such as a reference source. Keep in mind that the reference source sees the dynamics of the bit decision process on the reference pins and further analysis beyond the scope of this data sheet may be required. Rev. D | Page 30 of 42 Data Sheet ADAS3022 Reference Decoupling POWER SUPPLY With any of the reference topologies described in the Voltage Reference Input/Output section, the REF1 and REF2 reference pins of the ADAS3022 have dynamic impedances and require sufficient decoupling, regardless of whether the pins are used as inputs or outputs. This decoupling usually consists of a low equivalent series resistor (ESR) capacitor connected to each REF1 and REF2 and to the accompanying REFN return paths. Using X5R, 1206 size ceramic chip capacitors is recommended for decoupling in all the reference topologies described in the Voltage Reference Input/Output section. The ADAS3022 uses five supplies: AVDD, DVDD, VIO, VDDH, and VSSH (see Table 10). Note that ACAP, DCAP, and RCAP are included in Table 10 for informational purposes only because these supplies are outputs of the on-chip supply regulators. Refer to UG-484 for more information about how these supplies are generated on the EVAL-ADAS3022EDZ. The placement of the reference decoupling capacitors plays an important role in the system performance. Mount the decoupling capacitors on the same side as the ADAS3022, close to the REF1 and REF2 pins, with thick PCB traces. Route the return paths to the REFN inputs, which are in turn connected to the analog ground plane of the system. The resistance of the return path to ground must be minimized by using as many through vias as possible when it is necessary to connect to an internal PCB layer. The REFN and RGND inputs must be connected with the shortest distance to the analog ground plane of the system, preferably adjacent to the solder pads, using several vias. One common mistake is to route these traces to an individual trace that connects to the ground of the system. This can introduce noise, which may adversely affect LSB sensitivity. To prevent such noise, it is highly recommended to use PCBs with multiple layers, including ground planes, rather than using single- or double-sided boards. Refer to UG-484 for more information about the PCB layout of the EVAL-ADAS3022EDZ. For applications that use multiple ADAS3022 devices or other PulSAR ADCs, it is more effective to use the internal reference buffer to buffer the external reference voltage, thus reducing SAR conversion crosstalk. The voltage reference temperature coefficient (TC) directly affects the full-scale accuracy of the system; therefore, in applications where full-scale accuracy is crucial, care must be taken with the TC. For example, a 15 ppm/C TC of the reference changes the full-scale accuracy by 1 LSB/C. Table 10. Power Supplies Name AVDD DVDD Function Analog 5 V core Digital 5 V core VIO Digital input/output VDDH VSSH ACAP DCAP RCAP Positive high voltage Negative high voltage Analog 2.5 V core Digital 2.5 V core Analog 2.5 V core Required Yes Yes, or can connect to AVDD Yes, and can connect to DVDD (for 5 V level) Yes, +15 V typ Yes, -15 V typ No, on chip No, on chip No, on chip Core Supplies AVDD and DVDD supply the ADAS3022 analog and digital cores, respectively. Sufficient decoupling of these supplies is required, consisting of at least a 10 F capacitor and a 100 nF capacitor on each supply. The 100 nF capacitors must be placed as close as possible to the ADAS3022. To reduce the number of supplies needed, DVDD can be supplied from the analog supply by connecting a simple RC filter between AVDD and DVDD, as shown in Figure 66. VIO is the variable digital input/output supply and can be directly interfaced to any logic between 1.8 V and 5 V (DVDD supply maximum). To reduce the supplies needed, VIO can alternatively be connected to DVDD when DVDD is supplied from the analog supply through an RC filter. The recommended low dropout regulators are ADP3334, ADP1715, and ADP7102/ ADP7104 for the AVDD, DVDD, and VIO supplies. Rev. D | Page 31 of 42 ADAS3022 Data Sheet 20 ANALOG SUPPLY +5V 10F 100nF 10F AVDD AGND +15V 10F 100nF 1.8V TO 5V DIGITAL I/O SUPPLY VIO 100nF ADAS3022 10F DGND VSSH 10516-020 100nF 100nF DVDD DGND VDDH 10F -15V +5V DIGITAL SUPPLY Figure 66. ADAS3022 Supply Connections High Voltage Supplies The high voltage bipolar supplies (VDDH and VSSH) are required and must be at least 2.5 V larger than the maximum input. For example, the supplies must be 15 V for headroom in the 24.576 V differential input range. Sufficient decoupling of these supplies is also required, consisting of at least a 10 F capacitor and a 100 nF capacitor on each supply. Power Dissipation Modes The ADAS3022 offers two power dissipation modes: fully operational mode and power-down mode. Note that before the device can operate at the specified performance, the reference voltage must charge up the external reservoir capacitor(s) and be allowed the specified settling time. Returning PD and RESET low from high resets the ADAS3022 digital core, including the CFG register, to its default state. Therefore, the desired CFG must be rewritten to the device and two dummy conversions must be completed before the device operation is restored to the configuration programmed prior to PD assertion. CONVERSION MODES Fully Operational Mode In fully operational mode, the ADAS3022 can perform conversions as soon as all internal bias currents are established. Power-Down Mode To minimize the operating currents of the device when it is idle, place the device in full power-down mode by bringing the PD input high. This places the ADAS3022 into a deep sleep mode, in which CNV activity is ignored and the digital interface is inactive. Refer to the Reset and Power-Down (PD) Inputs section for timing details. In deep sleep mode, the internal regulators (ACAP, RCAP, and DCAP) and the voltage reference are also powered down. To reestablish operation, return PD low. The ADAS3022 offers two conversion modes to accommodate varying applications. The mode is set with the conversion mode select bit (CMS, Bit 1 of the CFG register). Warp Mode (CMS = 0) Setting CMS to 0 is useful when an aggregate throughput rate of 1 MSPS is required. However, in this mode, the maximum time between conversions is restricted. If this maximum period is exceeded, the conversion result may be corrupted. Therefore, this mode is more suitable for continually sampled applications. Normal Mode (CMS = 1, Default) Setting CMS to 1 is useful for all applications with a maximum aggregate throughput of 900 kSPS. In this mode, there is no restriction in terms of the maximum time between conversions. This mode is the default condition from the assertion of an asynchronous RESET. The main difference between normal mode and warp mode is the BUSY time; tQUIET is slightly longer in normal mode than it is in warp mode. Rev. D | Page 32 of 42 Data Sheet ADAS3022 DIGITAL INTERFACE BUSY Falling Edge--End of a Conversion (EOC) The ADAS3022 digital interface consists of asynchronous inputs, a busy indicator, and a 4-wire serial interface for conversion result readback and configuration register programming. This interface uses the three asynchronous signals (CNV, RESET, and PD) and a 4-wire serial interface composed of CS, SDO, SCK, and DIN. CS can also be tied to CNV for some applications. Conversion results are available on the serial data output pin (SDO), and the 16-bit configuration word (CFG) is programmed on the serial data input pin (DIN). This register controls settings such as the channel to be converted, the programmable gain setting, and the reference choice (see the Configuration Register section for more information). The EOC event is indicated by BUSY returning low and can be used as a host interrupt. In addition, the EOC gates data access to and from the ADAS3022. If the current conversion result is not read prior to the following EOC event, the data is lost. Furthermore, if the CFG update is not completed prior to EOC, it is discarded and the current configuration is applied to future conversions. This pipeline ensures that the ADAS3022 has sufficient time to acquire the next sample to the specified 16-bit accuracy. Conversion Timing A detailed timing diagram of the conversion process is shown in Figure 67. tCYC SOC (n) CONVERSION CONTROL SOC (n + 1) EOC (n) tCONV tCBD Conversions are initiated by the CNV input. The ADAS3022 is fully asynchronous and can perform conversions at any frequency from dc up to 1 MHz, depending on the conversion mode. CNV BUSY SAFE CONVERSION A rising edge on CNV changes the state of the ADAS3022 from track mode to hold mode and is all that is necessary to initiate a conversion. All conversion timing clocks are internally generated. After a conversion is initiated, the ADAS3022 ignores other activity on the CNV line (governed by the throughput rate) until the end of the conversion; the conversion can only be aborted by the power-down (PD) or RESET inputs. When the ADAS3022 is performing a conversion and the BUSY output is driven high, the ADAS3022 uses a unique 2-phase conversion process to allow for safe data access and quiet times. The CNV signal is decoupled from the CS pin, allowing multiple ADAS3022 devices to be controlled by the same processor. For applications where SNR is critical, the CNV source must have very low jitter. This can be achieved by using a dedicated oscillator or by clocking CNV with a high frequency, low jitter clock. For applications where jitter is more tolerable or a single device is in use, CNV can be tied to CS. For more information about sample clock jitter and aperture delay, refer to the MT-007 Tutorial, Aperture Time, Aperture Jitter, Aperture Delay Time--Removing the Confusion. Although CNV is a digital signal, it must be designed to ensure fast, clean edges with minimal overshoot, undershoot, and ringing. The CNV trace must be shielded by connecting a trace to ground, and a low value (such as 50 ) serial resistor termination must be added close to the output of the component that drives this line. In addition, take care to avoid digital activity close to the sampling instant because such activity may result in degraded SNR performance. tDAC tDDCA ACQUISITION QUIET (n + 1) (n) (n) (n + 1) XXX XXX tACQ tCCS tCCS CS DATA (n - 1) SDO DIN CFG (n + 2) x DATA (n) x CFG (n + 3) x 10516-022 CNV Rising Edge--Start of a Conversion (SOC) tQUIET tDDC tAD tCH Figure 67. Basic Conversion Timing Register Pipeline To ensure that all CFG updates are applied during a known safe instant to the various circuit elements, the asynchronous data transfer is synchronized to the ADAS3022 timing engine using the EOC event. This synchronization introduces an inherent delay between updating the CFG register setting and the application of the configuration to a conversion. This pipeline from the end of the current conversion (n) consists of a two-deep delay (shown as (n + 2) in Figure 67) before the CFG setting takes effect. This means that two SOC and EOC events must elapse before the setting (that is, new channel, gain, and so on) takes effect. Note that the nomenclature (n), (n + 1), and so on is used in the remainder of the following digital sections for simplicity. There is no pipeline after the end of a conversion, however, before data can be read back. RESET AND POWER-DOWN (PD) INPUTS The asynchronous RESET and PD inputs can be used to reset and power down the ADAS3022, respectively. Timing details are shown in Figure 68. Rev. D | Page 33 of 42 ADAS3022 Data Sheet When the device returns from power-down mode or from a reset and the default CFG is not used, there is no tACQ requirement; the first two conversions from power-up are undefined/invalid because the two-deep delay pipeline requirement must be satisfied to reconfigure the device to the desired setting. tACQ SEE NOTE CNV n-1 n n-1 CS tDIS SDO n-2 CFG x n+1 tEN n-1 x n+2 tSCKH tSCKL CS tDIS SCK tSDOH tEN tSDOD SDO (MISO) DIN (MOSI) tDINS tDINH Figure 69. Serial Timing CPHA The clock phase select bit (CPHA, Bit 0) sets the first bit of the conversion result on SDO after the end of a conversion (see Figure 70). Setting CPHA to 0 outputs the MSB when CS is asserted. Subsequent SCK falling edges clock out bits in an MSB - 1, MSB - 2, and so on fashion. This mode is useful for hosts limited to 16 clock edges where the first falling (or rising) edge can be used to latch the data. RESET/ PD BUSY tSCK x x NOTES 1. WHEN THE PART IS RELEASED FROM RESET, tACQ MUST BE MET FOR CONVERSION n IF USING THE DEFAULT CFG SETTING FOR CHANNEL IN0. WHEN THE PART IS RELEASED FROM POWER-DOWN, tACQ IS NOT REQUIRED, AND THE FIRST TWO CONVERSIONS, n AND n + 1, ARE UNDEFINED. 10516-023 SEE NOTE Setting CPHA to 1 outputs the MSB not only when CS is asserted but also after the first SCK falling edge. Subsequent SCK falling edges clock out bits in an MSB - 1, MSB - 2, and so on fashion. This mode can be useful for sign extension applications. CS Figure 68. RESET and PD Timing SCK SERIAL DATA INTERFACE The ADAS3022 uses a simple 4-wire interface and is compatible with FPGAs, DSPs, and common serial interfaces, such as serial peripheral interface (SPI), queued serial peripheral interface (QSPI), and MICROWIRETM. The interface uses the CS, SCK, SDO, and DIN signals. Timing details for the serial interface are shown in Figure 69. SDO is activated when CS is asserted. The conversion result is output on SDO and is updated on SCK falling edges. Simultaneously, the 16-bit CFG word is updated, if desired, on the serial data input (DIN). The state of the clock phase select bit (CPHA, Bit 0) determines whether the MSB is output again on the first clock or whether the MSB - 1 bit is output when SDO activates after the EOC. 2 1 15 16 SDO CPHA = 0 MSB MSB - 1 MSB - 2 LSB + 1 LSB MSB SDO CPHA = 1 MSB MSB MSB - 1 LSB + 2 LSB + 1 LSB 10516-025 tRH Note that in Figure 68 and Figure 69, SCK is shown idling high. SCK can idle high or low, requiring that the system developer design an interface that suits setup and hold times for both SDO and DIN. 10516-024 A rising edge on RESET or PD aborts the conversion process and places SDO into high impedance, regardless of the CS level. Note that RESET has a minimum pulse width (active high) time for setting the ADAS3022 into the reset state. See the Configuration Register section for the default CFG setting when the ADAS3022 returns from the reset state. If the default setting is used after RESET is deasserted (Logic 0), a period equal to the acquisition time (tACQ) must elapse before CNV can be asserted for the conversion result to be valid. If a conversion initiates, the result corrupts. In addition, the output data from the previous conversion is cleared upon a reset. Attempting to access the data result prior to initiating a new conversion results in an invalid result. Figure 70. CPHA Details Sampling on the SCK Falling Edge To achieve the fastest data transfer rate, the host must sample data on the SCK falling edge, as long as there is a sufficient hold time of tSDOH (see Figure 69). When using this method, data transfers must occur during the safe conversion time (tDDC). Because this time is fixed, extending data reading or writing into the quiet conversion phase (tQUIET) may cause data corruption. However, for systems that need slightly more time, tDDCA (data during conversion additional) can be used. Rev. D | Page 34 of 42 Data Sheet ADAS3022 SOC Sampling on the SCK Rising Edge (Alternate Edge) tAD SPI or other alternate edge transfers typically require more time to access data because the total data transfer time of these slower hosts can be >tDDC. If this is the case, the time from tQUIET to the next CNV rising edge, which is known as the data access time after conversion (tDAC) and is determined by the user, must be adjusted by lowering the throughput rate (CNV frequency), thus providing the necessary time. If this does not allow enough time, the data access can be broken up so that some data access occurs during this time followed by the remainder of data access occurring during the next tDDC and tDDCA times. CFG Readback The CFG result associated with the current conversion can be read back with an additional 16 SCK burst following the conversion result (see Figure 70). After the LSB of the conversion result clocks out, the MSB of the CFG associated with that conversion follows. Subsequent SCK falling edges repeat the conversion result and CFG word. For example, when CPHA is 0, the MSB of the conversion result is output on the 32nd falling edge. Because the time to access data is somewhat restricted, the following guidelines are useful in determining the ADAS3022 throughput, or CNV frequency, and the serial interface details. Note that in Figure 71 to Figure 73, tAD is for reference purposes only and denotes a time without digital activity because such activity must not occur prior to or just after sampling. BUSY f SCK t AD 17 34 MHz + t DDC Although additional time to access data can be attained by transferring data during tDDCA, this is not recommended because the ADAS3022 performs sensitive bit decisions during this time. If tDDCA is used, however, the minimum SCK frequency is f SCK 17 t AD + t DDC + t DDCA n EOC tQUIET n n+1 n+1 n+2 CS n-1 n DIN n+2 n+3 10516-026 SDO SCK Figure 71. Data Access During Conversion Data Access After/Spanning Conversion--Host Determined Throughput For hosts that do not have the 34 MHz or 25 MHz SCK rates available, the maximum throughput rate cannot be achieved because the data access time after conversion, tDAC, must be increased to allow more time to access data. In this case, there are three methods to access data: * Data Access During Conversion--Maximum Throughput The maximum throughput rate per channel is determined mainly by the maximum SCK period of the host. When using the maximum throughput rate of 1 MSPS, the ADAS3022 has an almost symmetric period for both safe data and quiet times (approximately 500 ns each; see Figure 71). Consequently, tDDC is basically fixed and only provides the host approximately 500 ns to access data. Note that in Figure 71, tAD is for reference purposes only and denotes a time without digital activity because such activity should not occur during the sampling edge. For 17 SCK edges (worst case), the minimum SCK frequency required to achieve a 1 MSPS (1 s between CNV rising) aggregate throughput rate is tDDC CNV * GENERAL CONSIDERATIONS tDDCA * The first method is to adjust tDAC for 17 SCK edges (worst case) and the additional CS to CNV setup and hold times. In this case, all data access occurs during tDAC. This is the only method that can be used when using a slow host that cannot break up data into bytes or other partial data bursts. A second method is to break up the data into bursts that can transfer part of the data during tDAC of the current conversion and the rest of the data during tDDC of the next conversion. Note that CS can stay low throughout the CNV rising phase; however, serial clock activity must pause while the input is being sampled. A third method is to use the second method along with the additional tDDCA, again noting that digital activity must cease after this time to prevent the current conversion from becoming corrupted. In any of these methods, if the time between conversions (tCYC) exceeds for the fastest possible throughput mode (CMS = 0), the conversion results are inaccurate. If this is the case, the fully asynchronous mode (CMS = 1) must be selected (see the Conversion Modes section for details). Figure 72 shows a basic timing diagram for all three methods. For conversion (n), the data is read back after the end of a conversion (n), with the remainder of data read into the next (n + 1) conversion. 25 MHz Rev. D | Page 35 of 42 ADAS3022 Data Sheet SOC EOC tAD tDAC tDDCA SOC GENERAL TIMING tDDC Figure 73 is a general timing diagram showing the complete register to conversion and readback pipeline delay. The figure details the timing upon power-up or upon returning from a full power-down by use of the PD input. Figure 74 and Figure 75 show the general timing diagrams when only the auxiliary ADC input channel pair is enabled for the data read during conversion (RDC) mode and the read after conversion (RAC) mode, respectively. CNV n BUSY n+1 tCCS n n+1 CS SDO x x n+2 n n+3 x n+3 10516-027 DIN n n-1 SCK Figure 72. Data Access Spanning Conversion tACQ tCYC EOC SOC SOC tQUIET tDDC POWER UP CONVERSION (n - 1) UNDEFINED NOTE 1 ACQUISITION (n + 1) UNDEFINED CONVERSION (n) UNDEFINED ACQUISITION (n) UNDEFINED tDAC NOTE 2 NOTE 1 PHASE EOC CONVERSION (n + 1) UNDEFINED CNV BUSY tDDCA NOTE 5 NOTE 2 tAD NOTE 4 CS X SCK 1 16/32 NOTE 3 1 16 DIN CFG INVALID CFG (n + 2) CFG (n + 2) CFG (n + 3) SDO DATA INVALID DATA (n - 1) INVALID DATA (n - 1) INVALID DATA (n) INVALID EOC EOC ACQUISITION (n + 2) PHASE DATA (n) INVALID EOC ACQUISITION (n + 3) CONVERSION (n + 2) CFG (n + 3) ACQUISITION (n + 4) CONVERSION (n + 3) CONVERSION (n + 4) CNV BUSY CS 1 16 1 16 1 DIN CFG (n + 4) CFG (n + 4) CFG (n + 5) CFG (n + 5) CFG (n + 6) CFG (n + 6) SDO DATA (n + 1) INVALID DATA (n + 1) INVALID DATA (n + 2) DATA (n + 2) DATA (n + 3) DATA (n + 3) NOTES 1. DATA ACCESS CAN OCCUR DURING A CONVERSION ( tDDC ), AFTER A CONVERSION (tDAC ), OR BOTH DURING AND AFTER A CONVERSION. THE CONVERSION RESULT AND THE CFG REGISTER ARE UPDATED AT THE END OF A CONVERSION (EOC). 2. DATA ACCESS CAN ALSO OCCUR UP TO tDDCA WHILE BUSY IS ACTIVE (SEE THE DIGITAL INTERFACE SECTION FOR DETAILS). ALL OF THE BUSY TIME CAN BE USED TO ACQUIRE DATA. 3. A TOTAL OF 16 SCK FALLING EDGES IS REQUIRED FOR A CONVERSION RESULT. AN ADDITIONAL 16 EDGES ARE REQUIRED TO READ BACK THE CFG RESULT ASSOCIATED WITH THE CURRENT CONVERSION. 4. CS CAN BE HELD LOW OR CONNECTED TO CNV. CS WITH FULL INDEPENDENT CONTROL IS SHOWN IN THIS FIGURE. 5. FOR OPTIMAL PERFORMANCE, DATA ACCESS SHOULD NOT OCCUR DURING THE SAMPLING EDGE. A MINIMUM TIME OF THE APERTURE DELAY (tAD) SHOULD ELAPSE PRIOR TO DATA ACCESS. Figure 73. General Timing Diagram Rev. D | Page 36 of 42 10516-228 SCK Data Sheet ADAS3022 EOC SOC tAD tQUIET CNV n BUSY n+2 n+1 n n+2 n+1 CS n n+2 DIN 1 SCK n+1 n+3 16 n+4 16 1 1 10516-252 n-1 SDO 16 Figure 74. General Timing Diagram of AUX Input Channel Pair (RDC) EOC SOC tEN tAD tQUIET CNV n BUSY n+2 n+1 n n+1 n+3 n+3 n+2 CS n+3 DIN SCK n+1 1 n+2 n+4 16 1 n+5 16 Figure 75. General Timing Diagram of AUX Input Channel Pair (RAC) Rev. D | Page 37 of 42 1 16 10516-253 n SDO ADAS3022 Data Sheet Therefore, the default value is CFG[15:0] = 0x8FCF. This sets the ADAS3022 as follows: CONFIGURATION REGISTER The configuration register, CFG, is a 16-bit, programmable register for selecting all of the ADAS3022 user-programmable options (see Table 12). The register loads when data is read back for the first 16 SCK rising edges and updates at the next EOC. Note that there is always a two-deep delay (n + 2) when writing CFG and when reading back CFG for the setting associated with the current conversion. * * * * * * * * * The default CFG setting is applied when the ADAS3022 returns from the reset state (RESET = high) to the operational state (RESET = low). However, when the ADAS3022 returns from the full power-down state (PD = high) to an enabled state (PD = low), the default CFG setting is not applied, and at least two dummy conversions are required for the user-specified CFG setting to take effect. Overwrites contents of CFG register Selects the IN0 input channel referenced to COM Configures the PGIA gain to 0.20 (20.48 V) Selects the multiplexer input Disables the internal channel sequencer Disables the temperature sensor Enables the internal reference Selects normal conversion mode Selects SPI interface mode Table 11. Configuration Register, CFG; Default Value = 0x8FCF (1000 1111 1100 1111) 15 CFG 14 INx 13 INx 12 INx 11 COM 10 RSV 9 PGIA 8 PGIA 7 PGIA 6 MUX 5 SEQ 4 SEQ 3 TEMPB 2 REFEN 1 CMS 0 CPHA Table 12. Configuration Register Bit Description Bits 15 Bit Name CFG [14:12] INx 11 COM 10 [9:7] RSV PGIA 6 MUX Description Configuration update. 0 = keep current configuration settings. 1 = overwrite contents of register (default). Input channel selection in binary fashion. See the Multiplexer section. Bit 14 Bit 13 Bit 12 Channel 0 0 0 IN0 (default) ... ... ... 1 1 1 IN7 IN[7:0] common channel input. AUX+ and AUX- are not referenced to COM. 0 = channels are referenced in differential pairs: IN0/IN1, IN2/IN3, IN4/IN5, and IN6/IN7 (see the On Demand Conversion Mode section). 1 = each channel is referenced to a common sense, COM (default). Reserved. Setting or clearing this bit has no effect. Programmable gain selection (see the Input Structure section). In basic sequencer modes, this register configures the range for all channels. In advanced sequencer mode, this register sets the range for IN0 (COM = 1) or the IN0/IN1 pair (COM = 0). See the Advanced Mode section for the PGIA configurations of individual channels or channel pairs. Bit 9 Bit 8 Bit 7 Absolute Input Voltage Range 0 0 0 24.576 V 0 0 1 10.24 V 0 1 0 5.12 V 0 1 1 2.56 V 1 0 0 1.28 V 1 0 1 0.64 V 1 1 0 Not used 1 1 1 20.48 V (default) Multiplexer/auxiliary channel input (see the Auxiliary Input Channel section). 0 = selects auxiliary channel on AUX inputs as active channel. 1 = uses the selected analog front end (AFE) channel/channel pair (default). Rev. D | Page 38 of 42 Data Sheet Bits [5:4] Bit Name SEQ 3 TEMPB 2 REFEN 1 CMS 0 CPHA ADAS3022 Description Channel sequencer. Allows for scanning channels sequentially from IN0 to INx. INx is the last channel converted prior to resetting the sequence back to IN0 and is specified by the channel selected in the INx[2:0] configuration bits (see the On Demand Conversion Mode section). Bit 5 Bit 4 Function 0 0 Disable sequencer (default) 0 1 Update configuration during basic sequence 1 0 Initialize advanced sequencer 1 1 Initialize basic sequencer Temperature sensor enable control (see the On Demand Conversion Mode section). 0 = internal temperature sensor enabled. 1 = internal temperature sensor disabled (default). Internal reference selection (see the Pin Configuration and Function Descriptions and Voltage Reference Input/Output sections for more information). 0 = disables the internal reference. The internal reference buffer is disabled by pulling REFIN to ground. 1 = enables the internal reference (default). Conversion mode select (see the Conversion Modes section). 0 = uses the warp mode for conversions with a time between conversion restriction. 1 = uses the normal mode for conversions (default). MSB select (see the CPHA section). 0 = asserting CS after the end of a conversion places the MSB on SDO, and the first SCK falling edge places (MSB - 1) on SDO. 1 = asserting CS after the end of a conversion places the MSB on SDO, and the first SCK falling edge repeats MSB on SDO (default). ON DEMAND CONVERSION MODE When the channel sequencer is disabled, the input channels can be selected for the on demand conversions based on the MUX and TEMPB bit settings, as shown in Table 13. For example, the only internal TEMP sensor channel conversions in this mode can be obtained by setting the MUX = TEMPB = 0. Table 13. Input Channel Select MUX 1 1 0 0 TEMPB 1 0 1 0 Output INx[14:12] Channels Invalid AUX Input Channels Internal Temperature Sensor Channel CHANNEL SEQUENCER DETAILS The ADAS3022 includes a channel sequencer, which is useful for scanning channels in a sequential order. Channels are scanned individually with reference to COM or as pairs and can also include the auxiliary channel pair and/or the internal temperature sensor measurement. After the last programmed measurement is sampled, the ADAS3022 sequencer is reset to the first channel (IN0) or channel pair (IN0/IN1) and repeats the sequence until the sequencer is disabled or an asynchronous RESET or PD occurs. When the channel sequencer is enabled, for all differential pairs, the positive terminals are the even channels (IN0, IN2, IN4, and IN6), and the negative terminals are, conversely, the odd channels (IN1, IN3, IN5, and IN7). When the channel sequencer is disabled, the user can assign either positive or negative terminals to even or odd channels for all differential pairs, depending on the INx[14:12] settings. For example, if INx[14:12] = 001 when using the IN0/IN1 pair, IN1 is the positive input and IN0 is the negative input. Each sequence loop always starts with IN0 or IN0/IN1 and terminates with either the last channel/channel pair set in the INx bits, the temperature sensor, or the auxiliary input channel, depending on the configuration word. Table 14 provides a quick reference for how the device responds to the programmed configuration. For the first case, the channel sequencer scans Channel IN0 through Channel IN3 in a repeated fashion. Note that the last conversion is corrupted when exiting the sequencer. Table 14. Typical Channel Sequencer Example INx[14:12] 011 111 11x 111 111 111 Rev. D | Page 39 of 42 COM 1 1 0 1 1 1 MUX 1 1 1 1 0 0 TEMPB 1 1 1 0 1 0 End of Sequence IN3 (to COM) IN7 (to COM) IN6 to IN7 TEMPB AUX AUX ADAS3022 Data Sheet INx and COM Inputs (MUX = 1, TEMPB = 1) Sequencer Modes To use individual INx channels with reference to COM or pairs of INx channels in a sequence without converting the AUX or temperature sensor channels, the MUX and TEMPB bits must be set to 1. The last channel to be converted in the sequence is specified by the channel set in the INx bits. After the last channel is scanned, the next conversion starts over at IN0 or IN0/IN1. For paired channels, the channels are paired depending on the last channel set in INx. Note that the channels are always paired with the positive input on the even channels (IN0, IN2, IN4, IN6) and the negative input on the odd channels (IN1, IN3, IN5, IN7). Therefore, setting INx to 110 or 111 scans all pairs with the positive inputs dedicated to IN0, IN2, IN4, and IN6. For example, to scan four single channels, set INx to 011, COM to 1, and MUX to 1, which results in a sequence order of IN0, IN1, IN2, IN3, IN0, IN1, IN2, and IN3. The ADAS3022 has two sequencer modes that are configured with the SEQ bits: basic mode and advanced mode. Basic mode can be used when all channels are configured with the same PGIA range. Advanced mode allows individual channel ranges to be programmed using two additional advanced sequence registers, ASR0 and ASR1. The SEQ bits are used to enable the sequencer. Setting SEQ to 01, 10, or 11 specifies which sequencer mode is used. Depending on the mode, basic or advanced sequencing determines the next data into DIN. INx and COM Inputs with AUX Inputs (MUX = 0, TEMPB = 1) To use individual INx channels with reference to COM or pairs of INx channels with the AUX inputs in a sequence, the MUX bit must be set to 0 to append the AUX channel to the end of the sequence (after the channel set in INx is scanned). Note that the AUX input is a pair, whereas the INx channel can be referenced to COM or pairs of INx channels. For example, to scan four single channels and the AUX inputs, set INx to 011, COM to 1, and MUX to 0, which results in a sequence order of IN0, IN1, IN2, IN3, AUX, IN0, IN1, IN2, IN3, AUX, and so on. INx and COM Inputs with Temperature Sensor (MUX = 1, TEMPB = 0) To append the temperature sensor conversion to the end of the input channel sequence, the TEMPB bit must be set low in the configuration word. Note that the temperature sensor requires at least 5 s between conversions. The data is output in straight binary format. INx and COM Inputs with AUX Inputs and Temperature Sensor (MUX = 0, TEMPB = 0) Both temperature sensor conversions and auxiliary channel conversions can be appended to the end of the input sequence by setting the MUX and TEMPB bits in the CFG register. For example, to scan all input channels with respect to COM, the temperature sensor, and the auxiliary channel at once, the user must set INx to 111, COM to 1, MUX to 0, and TEMPB to 0. The resulting sequence is IN0, IN1, IN2, IN3, IN4, IN5, IN6, IN7, temperature sensor, and AUX. Note that for any sequencer update there exists a two-deep delay when writing the register for the setting to take effect. Basic Sequencer Mode (SEQ = 11) The basic mode is useful for systems that use the same PGIA range on all channels. In basic sequencer mode, all that is required is a single CFG word to place the ADAS3022 in an automatically scanned mode. On the second conversion following the EOC for sequencer CFG, the sequencer starts. After the CFG for basic sequence updates, DIN must be held low for at least the MSB during the data readback or a new CFG word updates, disabling the sequencer. Update During Sequence (SEQ = 01) Some of the CFG settings, such as PGIA and CMS, can be updated during a sequence. Writing a new CFG word with the appropriate bits to be changed for the (n + 2) conversion updates the sequencer from that point; all channels then use, for example, the new PGIA value. Note that changing bits in INx for the last channel or changing COM reinitializes the sequencer at the (n + 2) conversion. A more practical method is to use the advanced sequencer mode as described in the Advanced Sequencer Mode (SEQ = 10) section. Advanced Sequencer Mode (SEQ = 10) The advanced mode is useful for systems that require different gains for different individual INx inputs or different pairs of INx inputs. In this mode, two additional registers are used to program the various gain settings. After the initial CFG word enabling the advanced sequencer mode is written, the ADAS3022 expects to receive at least one additional data transfer for the first advanced sequencer register, ASR0, or both advanced sequencer registers, depending on how many channels are in the sequence. Each ASR requires a conversion and a corresponding EOC to load the data into the device. The user cannot simply write 48 bits all at once because, as with all CFG word transfers, only the first 16 bits are latched and updated at EOC. Note that the PGIA setting for IN0 or IN0/IN1 is written in the initial CFG register, and if using pairs of INx channels, only ASR0 is required. After the CFG and the associated advanced sequencer registers are updated, DIN must be held low for at least the MSB of subsequent data transfers; otherwise, the advanced sequencer mode aborts. Rev. D | Page 40 of 42 Data Sheet ADAS3022 Table 15. Advanced Sequencer Register 0 Table 16. Advanced Sequencer Register 1 Bits 15 Bits 15 [14:11] [10:8] 7 [6:4] 3 [2:0] Function ASR0 write enable 0 = update ASR0 following CFG for advanced sequencer 1 = enters normal CFG update Reserved PGIA for IN1 or IN2/IN3 Reserved PGIA for IN2 or IN4/IN5 Reserved PGIA for IN3 or IN6/IN7 [14:12] 11 [10:8] 7 [6:4] 3 [2:0] Rev. D | Page 41 of 42 Function ASR1 write enable 0 = update ASR1 following ASR0 1 = enters normal CFG update PGIA for IN4 Reserved PGIA for IN5 Reserved PGIA for IN6 Reserved PGIA for IN7 ADAS3022 Data Sheet OUTLINE DIMENSIONS DETAIL A (JEDEC 95) 6.10 6.00 SQ 5.90 PIN 1 INDICATOR 0.30 0.25 0.18 PIN 1 INDIC ATOR AREA OPTIONS (SEE DETAIL A) 40 31 1 30 0.50 BSC 4.70 4.60 SQ 4.50 EXPOSED PAD END VIEW 20 BOTTOM VIEW 10 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 11 03-03-2017-B PKG-003653/5050 1.00 0.95 0.85 21 0.45 0.40 0.35 TOP VIEW COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-5 Figure 76. 40-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 6 mm x 6 mm Body and 0.75 mm Package Height (CP-40-15) Dimensions shown in millimeters 9.20 9.00 SQ 8.80 1.60 MAX 1 37 48 36 PIN 1 1.45 1.40 1.35 0.15 0.05 SEATING PLANE 0.20 0.09 7 3.5 0 0.08 COPLANARITY VIEW A 7.20 7.00 SQ 6.80 TOP VIEW (PINS DOWN) 12 13 VIEW A 0.50 BSC LEAD PITCH ROTATED 90 CCW COMPLIANT TO JEDEC STANDARDS MS-026-BBC 24 25 0.27 0.22 0.17 051706-A 0.75 0.60 0.45 Figure 77. 48-Lead Low Profile Quad Flat Package [LQFP] ST-48 Dimensions shown in millimeters ORDERING GUIDE Model 1 ADAS3022BCPZ ADAS3022BCPZ-RL7 ADAS3022BSTZ ADAS3022BSTZ-RL7 EVAL-ADAS3022EDZ 1 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description 40-Lead Lead Frame Chip Scale Package [LFCSP] 40-Lead Lead Frame Chip Scale Package [LFCSP] 48-Lead Low Profile Quad Flat Package [LQFP] 48-Lead Low Profile Quad Flat Package [LQFP] Evaluation Board Z = RoHS Compliant Part. (c)2012-2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10516-0-8/18(D) Rev. D | Page 42 of 42 Package Option CP-40-15 CP-40-15 ST-48 ST-48