16-Bit, 1 MSPS, 8-Channel,
Data Acquisition System
Data Sheet
ADAS3022
Rev. D Document Feedback
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FEATURES
Ease of use—16-bit, 1 MSPS complete data acquisition system
High impedance, 8-channel input: >500 MΩ
Differential input voltage range: ±24.576 V maximum
High input common-mode rejection: >100 dB
User-programmable input ranges
Channel sequencer with individual channel gains
On-chip 4.096 V reference and buffer
Auxiliary input—direct interface to PulSAR ADC inputs
No latency or pipeline delay (SAR architecture)
Serial 4-wire, 1.8 V to 5 V SPI-/SPORT-compatible interface
LFCSP package (6 mm × 6 mm)
LQFP package (7 mm × 7 mm)
−40°C to +85°C industrial temperature range
APPLICATIONS
Multichannel data acquisition and system monitoring
Process control
Power line monitoring
Automated test equipment
Instrumentation
GENERAL DESCRIPTION
The ADAS3022 is a complete 16-bit, 1 MSPS, successive approxi-
mation based analog-to-digital data acquisition system, which is
manufactured on Analog Devices, Inc., proprietary iCMOS® high
voltage industrial process technology. The device integrates an
8-channel, low leakage multiplexer; a high impedance program-
mable gain instrumentation amplifier (PGIA) stage with high
common-mode rejection; a precision, low drift 4.096 V reference
and buffer; and a 16-bit charge redistribution analog-to-digital
converter (ADC) with successive approximation register (SAR)
architecture. The ADAS3022 can resolve eight single-ended
inputs or four fully differential inputs up to ±24.576 V when
using ±15 V supplies. In addition, the device can accept the
commonly used bipolar differential, bipolar single-ended,
pseudo bipolar, or pseudo unipolar input signals, as shown
in Table 1, thus enabling the use of almost any direct sensor
interface.
The ADAS3022 simplifies design challenges by eliminating
signal buffering, level shifting, amplification/attenuation,
common-mode rejection, settling time, and any other analog
signal conditioning challenge while allowing a smaller form
factor, faster time to market, and lower cost.
Table 1. Typical Input Range Selection
Signal Input Range, VIN
Differential
±1 V ±1.28 V
±2.5 V
±2.56 V
±5 V ±5.12 V
±10 V ±10.24 V
Single Ended1
0 V to 1 V ±1.28 V
0 V to 2.5 V ±2.56 V
0 V to 5 V ±5.12 V
0 V to 10 V ±10.24 V
1 See Figure 60 and Figure 61 in the Analog Inputs section for more
information.
FUNCTIONAL BLOCK DIAGRAM
IN4
IN5
IN3
IN2
BUF
IN6
IN7
IN1
IN0
IN0/IN1
PAIR
DIFF TO
DIFF
COM
IN2/IN3
IN4/IN5
IN6/IN7
PulSAR
ADC
LOGIC/
INTERFACE
REFIN
REF
REFx
CNV
RESET PD
SCK
DIN
SDO
VSSH
VDDH
AGND
VIO
DVDD
AVDD
DGND
CS
COM
AUX+
AUX–
BUSY
ADAS3022
MUX
TEMP
SENSOR
10516-001
PGIA
Figure 1.
ADAS3022 Data Sheet
Rev. D | Page 2 of 42
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Specifications .................................................................. 7
Absolute Maximum Ratings ............................................................ 9
ESD Caution .................................................................................. 9
Pin Configuration and Function Descriptions ........................... 10
Typical Performance Characteristics ........................................... 12
Terminology .................................................................................... 22
Theory of Operation ...................................................................... 24
Overview ...................................................................................... 24
Operation ..................................................................................... 24
Transfer Function ....................................................................... 25
Typical Application Connection Diagram .............................. 26
Analog Inputs.............................................................................. 27
Voltage Reference Output/Input .............................................. 30
Power Supply ............................................................................... 31
Conversion Modes ..................................................................... 32
Digital Interface .............................................................................. 33
Conversion Control ................................................................... 33
Reset and Power-Down (PD) Inputs ....................................... 33
Serial Data Interface ................................................................... 34
General Considerations ............................................................. 35
General Timing........................................................................... 36
Configuration Register .............................................................. 38
On Demand Conversion Mode ................................................ 39
Channel Sequencer Details ....................................................... 39
Outline Dimensions ....................................................................... 42
Ordering Guide .......................................................................... 42
REVISION HISTORY
8/2018—Rev. C to Rev. D
Added LQFP Package .................................................... Throughout
Changes to Table 1 ............................................................................ 5
Changes to Table 3 ............................................................................ 7
Changes to Figure 5, Figure 5 Caption, and Table 5 .................. 11
Added Figure 6; Renumbered Sequentially and Table 6;
Renumbered Sequentially .............................................................. 13
Changed ADAS3022 Operation Section to Operation Section ..... 25
Changes to Operation Section ...................................................... 25
Updated Outline Dimensions ....................................................... 43
Changes to Ordering Guide .......................................................... 43
2/2014—Rev. B to Rev. C
Change to Figure 49 ....................................................................... 19
Change to Figure 54 ....................................................................... 24
Change to Table 7 ........................................................................... 25
Changes to Power-Down Mode Section ...................................... 30
Added On Demand Conversion Mode Section and Table 12;
Renumbered Sequentially .............................................................. 37
Change to Table 13 ......................................................................... 37
Change to JEDEC Note, Figure 75 ............................................... 40
4/2013—Rev. A to Rev. B
Changes to Table 1 ............................................................................. 1
Added Input Impedance of 500 MΩ Min, Table 2 ........................ 3
1/2013—Rev. 0 to Rev. A
Removed Endnote 3 and Added TA = 25°C to Gain Error Test
Conditions/Comments, Table 2....................................................... 3
Changes to REF1 and REF2 Description .................................... 11
Added Figure 25 to Figure 28; Renumbered Sequentially ........ 15
Changes to Figure 29 ...................................................................... 15
Added Figure 30 ............................................................................. 16
Changes to Figure 33, Figure 34, and Figure 35 ......................... 16
Changes to Figure 36 and Figure 37 ............................................ 17
Changes to Figure 50 ...................................................................... 19
Changes to Figure 54 ...................................................................... 24
Changes to Figure 56 ...................................................................... 25
Changes to Figure 57, Figure 58, Figure 59, and Figure 60 ....... 26
Changes to Voltage Reference Output/Input Section, Figure 62,
and Figure 63 ................................................................................... 28
Changes to Core Supplies Section ................................................ 29
11/2012—Revision 0: Initial Version
Data Sheet ADAS3022
Rev. D | Page 3 of 42
SPECIFICATIONS
VDDH = 15 V ± 5%, VSSH = −15 V ± 5%, AVDD = DVDD = 5 V ± 5%, VIO = 1.8 V to AVDD, internal reference, VREF = 4.096 V,
fS = 1 MSPS. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter Test Conditions/Comments Min Typ Max Unit1
RESOLUTION 16 Bits
ANALOG INPUTS—IN[7:0], COM
Operating Input Voltage Range VIN −VSSH + 2.5 VDDH − 2.5 V
Differential Input Voltage Range, VIN VIN+ − VIN−
PGIA gain = 0.16, VIN = 49.15 V p-p −6 VREF +6 VREF V
PGIA gain = 0.2, VIN = 40.96 V p-p −5 VREF +5 VREF V
PGIA gain = 0.4, VIN = 20.48 V p-p −2.5 VREF +2.5 VREF V
PGIA gain = 0.8, VIN = 10.24 V p-p −1.25 VREF +1.25 VREF V
IN
−0.625 V
REF
+0.625 V
REF
V
PGIA gain = 3.2, VIN = 2.56 V p-p −0.3125 VREF +0.3125 VREF V
PGIA gain = 6.4, VIN = 1.28 V p-p −0.1563 VREF +0.1563 VREF V
Input Impedance ZIN 500 MΩ
Channel Off Leakage ±0.6 nA
Channel On Leakage ±0.02 nA
Common-Mode Voltage Range2 VIN+, VIN−; full-scale differential inputs
PGIA gain = 0.4 −5.12 +5.12 V
PGIA gain = 0.8 −7.68 +7.68 V
PGIA gain = 1.6 −8.96 +8.96 V
PGIA gain = 3.2 −9.60 +9.60 V
PGIA gain = 6.4 −9.92 +9.92 V
ANALOG INPUTS—AUX+, AUX−
Differential Input Voltage Range −VREF +VREF V
THROUGHPUT
Conversion Rate One channel/one pair 0 1000 kSPS
0
500
kSPS
Four channels/four pairs 0 250 kSPS
Eight channels 0 125 kSPS
Transient Response Full-scale step 520 ns
DC ACCURACY
No Missing Codes 16 Bits
Integral Linearity Error PGIA gain = 0.16, 0.2, 0.4, 0.8, 1.6 −2 ±0.6 +2 LSB
PGIA gain = 3.2 −3 ±1.0 +3 LSB
PGIA gain = 6.4 −5 ±1.5 +5 LSB
Differential Linearity Error PGIA gain = 0.16, 0.2, 0.4, 0.8, 1.6 −0.9 ±0.6 +1.0 LSB
PGIA gain = 3.2 −0.9 ±0.75 +1.25 LSB
PGIA gain = 6.4 −0.9 ±0.75 +1.25 LSB
Transition Noise External reference
PGIA gain = 0.16, 0.2, 0.4, 0.8, 1.6 5 LSB
7
LSB
PGIA gain = 6.4 11 LSB
Gain Error External reference, all PGIA gains, TA = 25°C −9 +9 LSB
Gain Error Temperature Drift External reference, all PGIA gains 0.1 ppm/°C
Offset Error External reference, TA = 25°C
PGIA gain = 0.16, 0.2, 0.4, 0.8 −3.0 +0.2 +3.0 LSB
PGIA gain = 1.6 −4.0 +0.2 +4.0 LSB
PGIA gain = 3.2 −7.5 +0.2 +7.5 LSB
PGIA gain = 6.4 −12.5 +0.2 +12.5 LSB
ADAS3022 Data Sheet
Rev. D | Page 4 of 42
Parameter Test Conditions/Comments Min Typ Max Unit1
Offset Error Temperature Drift External reference
PGIA gain = 0.16, 0.2, 0.4, 0.8 0.1 0.5 ppm/°C
PGIA gain = 1.6 0.2 1.0 ppm/°C
PGIA gain = 3.2 0.4 2.0 ppm/°C
0.8
4.0
ppm/°C
Total Unadjusted Error External reference, TA = 25°C
PGIA gain = 0.16, 0.2, 0.4, 0.8, 1.6, 3.2 −9 +9 LSB
PGIA gain = 6.4 −15 +15 LSB
AC ACCURACY3
Signal-to-Noise Ratio (SNR) fIN = 10 kHz
PGIA gain = 0.16 90.0 91.5 dB
PGIA gain = 0.2 90.0 91.5 dB
PGIA gain = 0.4 89.5 91.5 dB
89.0
91.0
dB
PGIA gain = 1.6 88.0 89.7 dB
PGIA gain = 3.2 86.0 86.8 dB
PGIA gain = 6.4 83.0 84.5 dB
Signal-to-Noise-and-Distortion
(SINAD)
fIN = 10 kHz
PGIA gain = 0.16 88.0 90.0 dB
PGIA gain = 0.2 88.0 90.0 dB
PGIA gain = 0.4 88.5 91.0 dB
PGIA gain = 0.8 88.5 90.5 dB
PGIA gain = 1.6 87.5 89.5 dB
85.5
86.5
dB
PGIA gain = 6.4 82.5 84.0 dB
Dynamic Range fIN = 10 kHz, −60 dB input
PGIA gain = 0.16 91.0 92.0 dB
PGIA gain = 0.2 91.0 92.0 dB
PGIA gain = 0.4 90.5 91.5 dB
PGIA gain = 0.8 90.0 91.0 dB
PGIA gain = 1.6 89.0 90.0 dB
PGIA gain = 3.2 86.0 87.0 dB
PGIA gain = 6.4 83.5 85.0 dB
Total Harmonic Distortion (THD) fIN = 10 kHz, all PGIA gains −100 dB
Spurious-Free Dynamic Range
(SFDR)
fIN = 10 kHz, all PGIA gains 101 dB
Channel-to-Channel Crosstalk fIN = 10 kHz, all channels inactive −120 dB
Common-Mode Rejection Ratio
(CMRR)
fIN = 2 kHz
PGIA gain = 0.16, 0.2, 0.4, 0.8 90.0 110.0 dB
PGIA gain = 1.6 90.0 105.0 dB
PGIA gain = 3.2 90.0 98.0 dB
PGIA gain = 6.4 90.0 98.0 dB
−3 dB Input Bandwidth −40 dBFS 8 MHz
AUXILIARY ADC INPUT CHANNEL
DC Accuracy External reference
Integral Nonlinearity Error −1.5 ±0.5 +1.5 LSB
Differential Nonlinearity Error
−0.8
±0.6
+1.0
LSB
Gain Error
−2.5
±0.2
+2.5
LSB
Offset Error −5 ±0.2 +5 LSB
Data Sheet ADAS3022
Rev. D | Page 5 of 42
Parameter Test Conditions/Comments Min Typ Max Unit1
AC Performance Internal reference
Signal-to-Noise Ratio
LFCSP 90.0 93.0 dB
LQFP 91 dB
Signal-to-Noise-and-Distortion
LFCSP 89.5 92.5 dB
LQFP 90.5 dB
Total Harmonic Distortion −105 dB
Spurious-Free Dynamic Range 110 dB
INTERNAL REFERENCE
REFx Output Voltage TA = 25°C 4.088 4.096 4.104 V
REFx Output Current TA = 25°C 250 µA
REFx Temperature Drift REFEN = 1 ±5 ppm/°C
±1
ppm/°C
REFx Line Regulation AVDD = 5 V ± 5%
Internal Reference 20 µV/V
Buffer Only 4 µV/V
REFIN Output Voltage4 TA = 25°C 2.495 2.500 2.505 V
Turn-On Settling Time
REFIN
REF1
REF2
100
ms
EXTERNAL REFERENCE
Voltage Range REFx input 4.000 4.096 4.104 V
REFIN input (buffered) 2.5 2.505 V
Current Drain VREF = 4.096 V 100 µA
TEMPERATURE SENSOR
Output Voltage
A
275
mV
Temperature Sensitivity 800 µV/°C
DIGITAL INPUTS
Logic Levels
VIL VIO > 3 V −0.3 +0.3 × VIO V
VIH VIO > 3 V 0.7 × VIO VIO + 0.3 V
VIL VIO ≤ 3 V −0.3 +0.1 × VIO V
VIH VIO ≤ 3 V 0.9 × VIO VIO + 0.3 V
IIL −1 +1 µA
IIH −1 +1 µA
DIGITAL OUTPUTS5
Data Format
Twos complement
VOL ISINK = +500 µA 0.4 V
VOH ISOURCE = −500 µA VIO − 0.3 V
POWER SUPPLIES PD = 0
VIO 1.8 AVDD + 0.3 V
AVDD 4.75 5 5.25 V
DVDD 4.75 5 5.25 V
VDDH6 VDDH > input voltage + 2.5 V 14.25 15 15.75 V
VSSH6 VSSH < input voltage − 2.5 V −15.75 −15 −14.25 V
IVDDH PGIA gain = 0.16 3.0 3.5 mA
PGIA gain = 0.2 3.0 3.5 mA
PGIA gain = 0.4 3.5 4.0 mA
PGIA gain = 0.8 5.0 5.5 mA
PGIA gain = 1.6 8.5 9.5 mA
15.5
17.5
mA
PGIA gain = 6.4 15.5 17.5 mA
All PGIA gains, PD = 1 100 µA
ADAS3022 Data Sheet
Rev. D | Page 6 of 42
Parameter Test Conditions/Comments Min Typ Max Unit1
IVSSH PGIA gain = 0.16 −3.0 −2.5 mA
PGIA gain = 0.2 −3.0 −2.5 mA
PGIA gain = 0.4 −3.5 −3.0 mA
PGIA gain = 0.8 −5.5 −4.5 mA
−9.5
−8.0
mA
PGIA gain = 3.2 −17.5 −15 mA
PGIA gain = 6.4 −17.5 −15 mA
All PGIA gains, PD = 1 10 µA
IAVDD PGIA gain = 6.4, reference buffer enabled 18 21.0 mA
All other PGIA gains, reference buffer
enabled
16 19.0 mA
PGIA gain = 6.4, reference buffer disabled 14 17.5 mA
All other PGIA gains, reference buffer
disabled
12 16.0 mA
All PGIA gains, PD = 1 100 µA
IDVDD All PGIA gains, PD = 0 2.5 3.5 mA
All PGIA gains, PD = 1 10 µA
IVIO VIO = 3.3 V, PD = 0 0.30 1.2 mA
PD = 1 10 µA
Power Supply Sensitivity
At TA = 25°C External reference
5%
±0.5
LSB
PGIA gain = 3.2, VDDH/VSSH ± 5% ±1.0 LSB
PGIA gain = 6.4, VDDH/VSSH ± 5% ±2.0 LSB
PGIA gain = 0.16, AVDD/DVDD ± 5% ±0.6 LSB
PGIA gain = 0.2, AVDD/DVDD ± 5% ±0.8 LSB
PGIA gain = 0.4, AVDD/DVDD ± 5% ±1.0 LSB
PGIA gain = 0.8, AVDD/DVDD ± 5% ±1.5 LSB
PGIA gain = 1.6, AVDD/DVDD ± 5% ±2.0 LSB
PGIA gain = 3.2, AVDD/DVDD ± 5% ±3.5 LSB
PGIA gain = 6.4, AVDD/DVDD ± 5% ±7.0 LSB
TEMPERATURE RANGE
Specified Performance TMIN to TMAX −40 +85 °C
1 LSB means least significant bit and changes depending on the voltage range. See the Programmable Gain section for the LSB size.
2 The common-mode voltage (VCM) range for a PGIA gain of 0.16 or 0.2 is 0 V.
3 All ac accuracy specifications expressed in decibels are referred to a full-scale input FSR and tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
4 This is the output from the internal band gap reference.
5 There is no pipeline delay. Conversion results are available immediately after a conversion is complete.
6 The differential input common-mode voltage (VCM) range changes according to the maximum input range selected and the high voltage power supplies (VDDH and
VSSH). Note that the specified operating input voltage of any input pin requires 2.5 V of headroom from the VDDH and VSSH supplies; therefore, (VSSH + 2.5 V) ≤
INx/COM ≤ (VDDH − 2.5 V).
Data Sheet ADAS3022
Rev. D | Page 7 of 42
TIMING SPECIFICATIONS
VDDH = 15 V ± 5%, VSSH = −15 V ± 5%, AVDD = DVDD = 5 V ± 5%, VIO = 1.8 V to AVDD, internal reference, VREF = 4.096 V,
fS = 1 MSPS. All specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter Symbol Min Typ Max Unit
TIME BETWEEN CONVERSIONS tCYC
Warp Mode,1 CMS = 0 1 1000 µs
Normal Mode (Default), CMS = 1 1.1 µs
CONVERSION TIME: CNV RISING EDGE TO DATA AVAILABLE tCONV
Warp Mode, CMS = 0 825 ns
Normal Mode (Default), CMS = 1 925 1000 ns
AUXILIARY ADC INPUT CHANNEL ACQUISITION TIME tACQ 600 ns
CNV
Pulse Width tCH 10 ns
High to Hold Time (Aperture Delay) tAD 2 ns
High to Busy Delay tCBD 520 ns
SAFE DATA ACCESS TIME DURING CONVERSION tDDC 500 ns
QUIET CONVERSION TIME (BUSY HIGH) tQUIET
Warp Mode, CMS = 0 415 ns
Normal Mode (Default), CMS = 1 500 ns
DATA ACCESS DURING QUIET CONVERSION TIME tDDCA
Warp Mode, CMS = 0 200 ns
Normal Mode (Default), CMS = 1 300 ns
SCK
Period tSCK 15 ns
Low Time tSCKL 5 ns
High Time
t
SCKH
5
ns
Falling Edge to Data Valid tSDOH 4 ns
Falling Edge to Data Valid Delay tSDOD
VIO > 4.5 V 12 ns
VIO > 3.0 V 18 ns
VIO > 2.7 V 24 ns
VIO > 2.3 V 25 ns
VIO > 1.8 V 37 ns
CS/RESET/PD
Low to SDO tEN
VIO > 4.5 V 15 ns
VIO > 3.0 V 16 ns
VIO > 2.7 V 18 ns
VIO > 2.3 V 23 ns
VIO > 1.8 V
28
ns
High to SDO High Impedance tDIS 25 ns
DIN VALID TIME FROM SCK RISING EDGE
Setup tDINS 4 ns
Hold Time tDINH 4 ns
CNV Rising to CS tCCS 5 ns
RESET/PD High Pulse tRH 5 ns
1 Exceeding the maximum time has an effect on the accuracy of the conversion (see the Conversion Modes section).
ADAS3022 Data Sheet
Rev. D | Page 8 of 42
IOL
500µA
500µA
IOH
1.4V
TO SDO
CL
50pF
10516-002
Figure 2. Load Circuit for Digital Interface Timing
30% VIO
70% VIO
2V OR VIO – 0.5V
1
0.8V OR 0.5V
2
0.8V OR 0.5V
2
2V OR VIO – 0.5V
1
t
DELAY
t
DELAY
1
2V IF VIO > 2.5V; VIO – 0.5V IF VIO < 2.5V.
2
0.8V IF VIO > 2.5V; 0.5V IF VIO < 2.5V.
10516-003
Figure 3. Voltage Levels for Timing
ACQUISITION (n)
UNDEFINED
PHASE
POWER
UP
CONVERSION (n – 1)
UNDEFINED
CNV
BUSY
DIN
CS
SDO
NOTES
1. DATA ACCESS CAN OCCUR DURING A CONVERSION (
tDDC
), AFTER A CONVERSION (
tDAC
), OR BOTH DURING AND AFTER A CONVERSION.
THE CONVERSION RESULT AND THE CFG REGISTER ARE UPDATED AT THE END OF A CONVERSION (EOC).
2. DATA ACCESS CAN ALSO OCCUR UP TO
tDDCA
WHILE BUSY IS ACTIVE (SEE THE DIGITAL INTERFACE SECTION FOR DETAILS). ALL OF THE BUSY
TIME CAN BE USED TO ACQUIRE DATA.
3. A TOTAL OF 16 SCK FALLING EDGES IS REQUIRED FOR A CONVERSION RESULT. AN ADDITIONAL 16 EDGES ARE REQUIRED TO
READ BACK THE CFG RESULT ASSOCIATED WITH THE CURRENT CONVERSION.
4. CS CAN BE HELD LOW OR CONNECTED TO CNV. CS WITH FULL INDEPENDENT CONTROL IS SHOWN IN THIS FIGURE.
5. FOR OPTIMAL PERFORMANCE, DATA ACCESS SHOULD NOT OCCUR DURING THE SAMPLING EDGE. A MINIMUM TIME
OF THE APERTURE DELAY (
tAD
) SHOULD ELAPSE PRIOR TO DATA ACCESS.
DATA
INVALID
SCK
1 1
1
16/32
1616
X16
NOTE 3
NOTE 1
NOTE 2
NOTE 2
NOTE 1
NOTE 4
NOTE 5
CFG
INVALID CFG (n + 2)
DATA (n – 1)
INVALID
ACQUISITION (n + 1)
UNDEFINED
CONVERSION (n)
UNDEFINED
DATA (n – 1)
INVALID
CFG (n + 2) CFG (n + 3)
DATA (n)
INVALID
ACQUISITION
(n + 2)
CONVERSION (n + 1)
UNDEFINED
DATA (n)
INVALID
CFG (n + 3)
CFG (n + 4)
DATA (n + 1)
INVALID
ACQUISITION
(n + 3)
PHASE CONVERSION
(n + 2)
CNV
BUSY
DIN
CS
SDO DATA (n + 1)
INVALID
SCK
1
1
CFG (n + 4) CFG (n + 5)
DATA (n + 2)
ACQUISITION
(n + 4)
CONVERSION
(n + 3)
DATA (n + 2)
CFG (n + 5) CFG (n + 6)
DATA (n + 3)
CONVERSION
(n + 4)
DATA (n + 3)
CFG (n + 6)
EOC
EOC EOC EOC
EOC SOC
SOC
tDDC
tCYC
tQUIET tDAC
tACQ
tAD
tDDCA
10516-028
Figure 4. General Timing Diagram
Data Sheet ADAS3022
Rev. D | Page 9 of 42
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
Analog Inputs/Outputs
INx, COM to AGND VSSH − 0.3 V to VDDH + 0.3 V
AUX+, AUX− to AGND −0.3 V to AVDD + 0.3 V
REFx to AGND AGND − 0.3 V to AVDD + 0.3 V
REFIN to AGND AGND −0.3 V to +2.7 V
REFN to AGND ±0.3 V
Ground Voltage Differences
AGND, RGND, DGND
±0.3 V
Supply Voltages
VDDH to AGND −0.3 V to +16.5 V
VSSH to AGND +0.3 V to −16.5 V
AVDD, DVDD, VIO to AGND −0.3 V to +7 V
ACAP, DCAP, RCAP to GND
−0.3 V to +2.7 V
Digital Inputs/Outputs
CNV, DIN, SCK, RESET, PD, CS
to DGND
−0.3 V to VIO + 0.3 V
SDO, BUSY to DGND −0.3 V to VIO + 0.3 V
Internal Power Dissipation
2 W
Junction Temperature
125°C
Storage Temperature Range −65°C to +125°C
θJA Thermal Impedance 44.1°C/W
θJC Thermal Impedance 0.28°C/W
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
ADAS3022 Data Sheet
Rev. D | Page 10 of 42
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NOTES
1. NC = NO CONNECT. THIS PIN IS NOT INTERNALLY CONNECTED.
2. EXPOSED PADDLE. THE EXPOSED PADDLE MUST BE CONNECTED TO VSSH.
IN0 NC
AUX–
VDDH
VSSH
REFN
REFN
RGND
REF2
REF1
REFIN
RCAP
NC
AVDD
DVDD
ACAP
DCAP
AGND
AGND
DGND
DGND
IN1
IN2
IN3
AUX+
IN4
IN5
IN6
IN7
COM
CS
DIN
RESET
PD
VIO
SCK
SDO
BUSY
CNV
NC
10516-004
1
2
3
4
5
6
7
8
9
10
23
24
25
26
27
28
29
30
22
21
11
12
13
15
17
16
18
19
20
14
33
34
35
36
37
38
39
40
32
31
ADAS3022
TOP VIEW
(Not to Scale)
Figure 5. LFCSP Pin Configuration
Table 5. LFCSP Pin Function Descriptions
Pin No. Mnemonic Type 1 Description
1 to 4 IN0 to IN3 AI Input Channel 0 to Input Channel 3.
5 AUX+ AI Auxiliary Input Channel Positive Input.
6 to 9 IN4 to IN7 AI Input Channel 4 to Input Channel 7.
10 COM AI IN[7:0] Common Channel Input. The IN[7:0] input channels can be referenced to a common point. The
maximum voltage on this pin is ±10.24 V for all PGIA gains except for a PGIA gain of 0.16, in which case
the maximum voltage on this pin is ±12.228 V. AUX+ and AUX− are not referenced to COM.
11 CS DI Chip Select. Active low signal. Enables the digital interface for writing and reading data. Use this pin
when sharing the serial bus. For a dedicated ADAS3022 serial interface, CS can be tied to DGND or CNV
to simplify the interface.
12 DIN DI Data Input. Serial data input used for writing the 16-bit configuration word (CFG) that is latched on SCK
rising edges. CFG is an internal register that is updated on the rising edge of the end of a conversion, which is
the falling edge of BUSY. The configuration register can be written to during and after a conversion.
13 RESET DI Asynchronous Reset. A low-to-high transition resets the ADAS3022. The current conversion, if active, is
aborted and CFG is reset to the default state.
14, 29, 30 NC NC No Connect. This pin is not connected internally.
15 PD DI Power-Down. A low-to-high transition powers down the ADAS3022, minimizing the bias current. Note
that this pin must be held high until the user is ready to power on the device; after powering on the
device, the user must wait 100 ms until the reference is enabled and then wait for the completion of
two dummy conversions before the device is ready to convert. See the Power-Down Mode section for
more information.
16 SCK DI Serial Clock Input. The DIN and SDO data sent to and from the ADAS3022 are synchronized with SCK.
17 VIO P Digital Interface Supply. Nominally, this supply must be at the same voltage as the supply of the host
interface: 1.8 V, 2.5 V, 3.3 V, or 5 V.
18
SDO
DO
Serial Data Output. The conversion result is output on this pin and is synchronized to SCK falling edges.
The conversion result is output in twos complement format.
19 BUSY DO Busy Output. An active high signal on this pin indicates that a conversion is in process. Reading or
writing data during the quiet conversion phase (tQUIET) may cause incorrect bit decisions.
20 CNV DI Convert Input. A conversion is initiated on the rising edge of this pin.
21, 22 DGND P Digital Ground. Connect these pins to the system digital ground plane.
23, 24 AGND P Analog Ground. Connect these pins to the system analog ground plane.
25 DCAP P Internal 2.5 V Digital Regulator Output. Decouple this internally regulated output using a 10 µ F
capacitor and a 0.1 µ F local capacitor.
26 ACAP P Internal 2.5 V Analog Regulator Output. This regulator supplies power to the internal ADC core and all
of the supporting analog circuits with the exception of the internal reference. Decouple this internally
regulated output using a 10 µ F capacitor and a 0.1 µ F local capacitor.
Data Sheet ADAS3022
Rev. D | Page 11 of 42
Pin No. Mnemonic Type 1 Description
27 DVDD P Digital 5 V Supply. Decouple this supply using a 10 µ F capacitor and a 0.1 µ F local capacitor.
28 AVDD P Analog 5 V Supply. Decouple this supply using a 10 µ F capacitor and a 0.1 µ F local capacitor.
31 RCAP P Internal 2.5 V Analog Regulator Output. This regulator supplies power to the internal reference.
Decouple this pin using a 1 µ F capacitor connected to RCAP and a 0.1 µ F local capacitor.
32 REFIN AI/O Internal 2.5 V Band Gap Reference Output, Reference Buffer Input, or Reference Power-Down Input. See
the Voltage Reference Input/Output section for more information.
33, 34 REF1, REF2 AI/O Reference Input/Output. Regardless of the reference method, these pins need individual decoupling
using external 10 µ F ceramic capacitors connected as close to REF1, REF2, and REFN as possible. See
the Voltage Reference Output/Input section for more information. REF1 and REF2 must be tied
together externally.
35 RGND P Reference Supply Ground. Connect this pin to the system analog ground plane.
36, 37 REFN P Reference Input/Output Ground. Connect the 10 µ F capacitors on REF1 and REF2 to these pins, and
connect these pins to the system analog ground plane.
38 VSSH P High Voltage Analog Negative Supply. Nominally, the supply of this pin must be −15 V. Decouple this
pin using a 10 µ F capacitor and a 0.1 µ F local capacitor.
39
VDDH
P
High Voltage Analog Positive Supply. Nominally, the supply of this pin must be +15 V. Decouple this pin
using a 10 µ F capacitor and a 0.1 µ F local capacitor.
40 AUX− AI Auxiliary Input Channel Negative Input.
EPAD Exposed Paddle. The exposed paddle must be connected to VSSH.
1AI = analog input, AI/O = analog input/output, DI = digital input, DO = digital output, and P = power.
ADAS3022 Data Sheet
Rev. D | Page 12 of 42
48 47 46 45 44 43 42 41 40 39 38 37
35
34
33
30
31
32
36
29
28
27
25
26
2
3
4
7
6
5
1
8
9
10
12
11
NIC = NOT INTERNALLY CONNECTED.
13 14 15 16 17 18 19 20 21 22 23 24
10516-306
ADAS3022
(Not to Scale)
TOP VIEW
IN0
NIC
NIC
AUX–
VDDH
VSSH
REFN
RGND
REF2
NIC
NIC
NIC
REF1
REFIN
RCAP
NIC
NIC
AVDD
DVDD
ACAP
DCAP
AGND
AGND
DGND
DGND
IN1
IN2
IN3
NIC
AUX+
IN4
IN5
IN6
IN7
COM
NIC
CS
DIN
RESET
AGND
NIC
VIO
SCK
SDO
NIC
BUSY/SDO2
CNV
PD
Figure 6. LQFP Pin Configuration
Table 6. 48-Lead LQFP Pin Function Descriptions
Pin No. Mnemonic Type 1 Description
1 to 4, 7 to
10
IN0 to IN7 AI Input Channel 0 to Input Channel 7.
5, 12, 18, 22,
32, 34 to 36,
41, 44, 45
NIC
Not Internally Connected
6 AUX+ Auxiliary Input Channel Positive Input.
16, 27, 28 AGND PI Analog Ground. Connect AGND to the system analog ground plane.
11 COM AI IN0 to IN7 Common Channel Input. Input Channel IN0 to Input Channel IN7 are referenced to a
common point. The maximum input voltage on this pin is ±10.24 V for all PGIA gains.
13 CS Chip Select. Active low signal. Enables the digital interface for writing and reading data. Use the CS pin
when sharing the serial bus. For a dedicated and simplified ADAS3022 serial interface, tie CS to DGND or
CNV.
14 DIN DI Data Input. DIN is the serial data input for writing the 16-bit configuration (CFG) word that is
clocked into the device on the SCK rising edges. CFG is an internal register that is updated on the
rising edge of the next end of a conversion pulse, which coincides with the falling edge of
BUSY/SDO2. The CFG register is written into the device on the first 16 clocks after conversion. To
avoid corrupting a conversion due to digital activity on the serial bus, do not write data during a
conversion.
15 RESET DI Asynchronous Reset. A low to high transition resets the ADAS3022. The current conversion, if active,
is aborted and the CFG register is reset to the default state.
17 PD DI Power-Down. A low to high transition powers down the ADAS3022, minimizing the device
operating current. PD must be held high until the user is ready to power on the device. After
powering on the device, the user must wait 100 ms until the reference is enabled and then wait for
the completion of one dummy conversion before the device is ready to convert. The RESET pin
remains low for 100 ns after the release of PD. See the Power-Down Mode section for more
information.
19 SCK DI Serial Clock Input. The DIN and SDO data sent to and from the ADAS3022 are synchronized with
SCK.
20 VIO P Digital Interface Supply. Nominally, it is recommended that VIO be at the same voltage as the
supply of the host interface: 1.8 V, 2.5 V, 3.3 V, or 5 V.
21 SDO DO Serial Data Output. The conversion result is output on this pin and synchronized to the SCK falling
edges. The conversion results are presented on this pin in twos complement format.
Data Sheet ADAS3022
Rev. D | Page 13 of 42
Pin No. Mnemonic Type 1 Description
23 BUSY/SDO2 DO Busy/Serial Data Output 2. The converter busy signal is always output on the BUSY/SDO2 pin
when CS is logic high. If SDO2 is enabled when CS is brought low after the end of conversion (EOC),
the SDO outputs the data. The conversion result is output on this pin and synchronized to the SCK
falling edges. The conversion results are presented on this pin in twos complement format.
24 CNV DI Convert Input. A conversion initiates on the rising edge of the CNV pin.
25, 26 DGND P Digital Ground. Connect DGND to the system digital ground plane.
29 DCAP P Internal 2.5 V Digital Regulator Output. Decouple DCAP, an internally regulated output, using a 10 µ
F and a 0.1 µ F local capacitor.
30 ACAP P Internal 2.5 V Analog Regulator Output. This regulator supplies power to the internal ADC core and
to all of the supporting analog circuits, except for the internal reference. Decouple this internally
regulated output (ACAP) using a 10 µ F capacitor and a 0.1 µ F local capacitor.
31 DVDD P Digital 5 V Supply. Decouple the DVDD supply to DGND using a 10 µ F capacitor and 0.1 µ F local
capacitor.
33 AVDD P Analog 5 V Supply. Decouple the AVDD supply to AGND using a 10 µ F capacitor and 0.1 µ F local
capacitor.
37 RCAP P Internal 2.5 V Analog Regulator Output. RCAP supplies power to the internal reference. Decouple
this internally regulated output (RCAP) using a 10 µ F capacitor and a 0.1 µ F local capacitor.
38 REFIN Internal 2.5 V Band Gap Reference Output, Reference Buffer Input, or Reference Power-Down Input.
REF1 and REF2 must be tied together externally. See the Voltage Reference Output/Input section for
more information.
39, 40 REF1, REF2 AI/O Reference Input/Output. Regardless of the reference method, REF1 and REF2 require individual
decoupling using external 10 µF ceramic capacitors connected as close to REF1, REF2, and REFN as
possible. See the Voltage Reference Output/Input section for more information.
42 RGND P Reference Supply Ground. Connect RGND to the system analog ground plane.
43 REFN P Reference Input/Output Ground. Connect the 10 µ F capacitors that are on REF1 and REF2 to the
REFN pins, then connect the REFN pins to the system analog ground plane.
46 VSSH P High Voltage Analog Negative Supply. Nominally, the supply of VSSH is −15 V. Decouple VSSH using
a 10 µ F capacitor and a 0.1 µ F local capacitor. Connect the exposed pad to VSSH.
47 VDDH P High Voltage Analog Positive Supply. Nominally, the supply of VDDH is 15 V. Decouple VDDH using
a 10 µ F capacitor and a 0.1 µ F local capacitor.
48 AUX− AI Auxiliary Input Channel Negative Input.
1 AI = analog input, AI/O = analog input/output, DI = digital input, DO = digital output, and P = power.
ADAS3022 Data Sheet
Rev. D | Page 14 of 42
TYPICAL PERFORMANCE CHARACTERISTICS
VDDH = 15 V, VSSH = −15 V, AVDD = DVDD = 5 V, VIO = 1.8 V to AVDD, unless otherwise noted.
08192 16384 24576 32768
CODE
40960 49152 57344 65536
INL (LSB)
GAIN = 0.16, 0.2, 0.4, 0.8, 1.6
INL MAX = 0.649
INL MIN = –0.592
10516-101
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
Figure 7. Integral Nonlinearity vs. Code,
PGIA Gain = 0.16, 0.2, 0.4, 0.8, and 1.6
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
08192 16384 24576 32768
CODE
40960 49152 57344 65536
INL (LSB)
10516-105
GAIN = 3.2
INL MAX = 1.026
INL MIN = –0.948
Figure 8. Integral Nonlinearity vs. Code,
PGIA Gain = 3.2
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
08192 16384 24576 32768
CODE
40960 49152 57344 65536
INL (LSB)
10516-106
GAIN = 6.4
INL MAX = 0.558
INL MIN = –1.319
Figure 9. Integral Nonlinearity vs. Code,
PGIA Gain = 6.4
–1.00
–0.75
–0.50
–0.25
0
0.25
0.50
0.75
1.00
08192 16384 24576 32768
CODE
40960 49152 57344 65536
DNL (LSB)
FOR ALL GAINS
10516-108
Figure 10. Differential Nonlinearity vs. Code for All PGIA Gains
0
50,000
100,000
150,000
200,000
250,000
300,000
350,000
400,000
7FFC
7FFD
7FFE
7FFF
8000
8001
8002
8003
8004
8005
8006
8007
8008
8009
COUNT
CODE IN HEX
GAIN = 0.16, 0.2, 0.4, 0.8, 1.6
10516-117
600
52,300
300,200
152,600
6,400
Figure 11. Histogram of a DC Input at Code Center,
PGIA Gain = 0.16, 0.2, 0.4, 0.8, and 1.6
0
50,000
100,000
150,000
200,000
250,000
300,000
350,000
400,000
7FFC
7FFD
7FFE
7FFF
8000
8001
8002
8003
8004
8005
8006
8007
8008
8009
COUNT
CODE IN HEX
10516-119
GAIN = 3.2
1,400
22,700
118,400
213,200
129,000
25,500
1,600
Figure 12. Histogram of a DC Input at Code Center,
PGIA Gain = 3.2
Data Sheet ADAS3022
Rev. D | Page 15 of 42
0
50,000
100,000
150,000
200,000
250,000
300,000
350,000
400,000
7FFC
7FFD
7FFE
7FFF
8000
8001
8002
8003
8004
8005
8006
8007
8008
8009
COUNT
CODE IN HEX
10516-120
GAIN = 6.4
300
200
21,700
82,000
157,300
151,900
75,100
18,400
2,400 100
Figure 13. Histogram of a DC Input at Code Center,
PGIA Gain = 6.4
0
10
20
30
40
50
60
70
80
90
100
00.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
COUNT
OFFSET DRIFT (ppm/°C)
EXTERNAL REFERENCE
GAIN = 0.16, 0.2, 0.4, 0.8, 1.6
fS
= 1000kSPS
10516-155
Figure 14. Offset Drift,
PGIA Gain = 0.16, 0.2, 0.4, 0.8, and 1.6
0
10
20
30
40
50
60
70
80
90
100
00.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
COUNT
OFFSET DRIFT (ppm/°C)
EXTERNAL REFERENCE
GAIN = 3.2
fS
= 1000kSPS
10516-156
Figure 15. Offset Drift,
PGIA Gain = 3.2
0
10
20
30
40
50
60
70
80
90
100
00.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
COUNT
OFFSET DRIFT (ppm/°C)
EXTERNAL REFERENCE
GAIN = 6.4
f
S
= 1000kSPS
10516-157
Figure 16. Offset Drift,
PGIA Gain = 6.4
112
72
23
2
0
20
40
60
80
100
120
0 1 2 3 4 5 6 7 8 9 10
COUNT
REFERENCE BUFFER DRIFT (ppm/°C)
f
S
= 1000kSPS
EXTERNAL 2.5V REFERENCE
INTERNAL BUFFER
10516-140
Figure 17. Reference Buffer Drift, External Reference
46
35
30
15 15
11 10
6
21
0
20
40
60
80
100
120
012345678910 11 12 13 14 15
COUNT
REFERENCE BUFFER DRIFT (ppm/°C)
38
f
S = 1000kSPS
INTERNAL 2.5V REFERENCE
INTERNAL BUFFER
10516-141
Figure 18. Reference Buffer Drift, Internal Reference
ADAS3022 Data Sheet
Rev. D | Page 16 of 42
–180
–160
–140
–120
–100
–80
–60
–40
–20
0
0100 200 300 400 500
AMPLITUDE (dBFS)
FREQUENCY (kHz)
GAIN = 0.16
fS
= 1000kSPS
fIN
= 10.1kHz
SNR = 91.7dB
SINAD = 89.2dB
THD = –92.5dB
SFDR = 92.5dB
10516-121
Figure 19. 10 kHz FFT,
PGIA Gain = 0.16
–180
–160
–140
–120
–100
–80
–60
–40
–20
0
0100 200 300 400 500
AMPLITUDE (dBFS)
FREQUENCY (kHz)
GAIN = 0.2
fS = 1000kSPS
fIN = 10.1kHz
SNR = 91.4dB
SINAD = 89.9dB
THD = –94.7dB
SFDR = 94.8dB
10516-122
Figure 20. 10 kHz FFT,
PGIA Gain = 0.2
–180
–160
–140
–120
–100
–80
–60
–40
–20
0
0100 200 300 400 500
AMPLITUDE (dBFS)
FREQUENCY (kHz)
GAIN = 0.4
fS = 1000kSPS
fIN = 10.1kHz
SNR = 91.2dB
SINAD = 91.0dB
THD = –103dB
SFDR = 104dB
10516-123
Figure 21. 10 kHz FFT,
PGIA Gain = 0.4
–180
–160
–140
–120
–100
–80
–60
–40
–20
0
0100 200 300 400 500
AMPLITUDE (dBFS)
FREQUENCY (kHz)
GAIN = 0.8
fS
= 1000kSPS
fIN
= 10.1kHz
SNR = 90.7dB
SINAD = 90.6dB
THD = –107dB
SFDR = 106dB
10516-124
Figure 22. 10 kHz FFT,
PGIA Gain = 0.8
–180
–160
–140
–120
–100
–80
–60
–40
–20
0
0100 200 300 400 500
AMPLITUDE (dBFS)
FREQUENCY (kHz)
GAIN = 1.6
fS = 1000kSPS
fIN = 10.1kHz
SNR = 89.8dB
SINAD = 89.7dB
THD = –106dB
SFDR = 107dB
10516-125
Figure 23. 10 kHz FFT,
PGIA Gain = 1.6
–180
–160
–140
–120
–100
–80
–60
–40
–20
0
0100 200 300 400 500
AMPLITUDE (dBFS)
FREQUENCY (kHz)
GAIN = 3.2
fS = 1000kSPS
fIN = 10.1kHz
SNR = 87.6dB
SINAD = 87.5dB
THD = –105dB
SFDR = 106dB
10516-126
Figure 24. 10 kHz FFT,
PGIA Gain = 3.2
Data Sheet ADAS3022
Rev. D | Page 17 of 42
–180
–160
–140
–120
–100
–80
–60
–40
–20
0
0100 200 300 400 500
AMPLITUDE (dBFS)
FREQUENCY (kHz)
GAIN = 6.4
fS
= 1000kSPS
fIN
= 10.1kHz
SNR = 85.7dB
SINAD = 85.6dB
THD = –101dB
SFDR = 103dB
10516-127
Figure 25. 10 kHz FFT,
PGIA Gain = 6.4
10516-303
100
95
90
85
80
75
70
1100010010
SNR (dB)
FREQUENCY (kHz)
GAIN = 0.4, –0.5dBFS
GAIN = 0.8, –0.5dBFS
GAIN = 1.6, –0.5dBFS
GAIN = 3.2, –0.5dBFS
GAIN = 0.4, –10dBFS
GAIN = 0.8, –10dBFS
GAIN = 1.6, –10dBFS
GAIN = 3.2, –10dBFS
Figure 26. SNR vs. Frequency
10516-302
100
95
90
85
80
75
70
65
60
55
50
1100010010
SINAD (dB)
FREQUENCY (kHz)
GAIN = 0.4, –0.5dBFS
GAIN = 0.8, –0.5dBFS
GAIN = 1.6, –0.5dBFS
GAIN = 3.2, –0.5dBFS
GAIN = 0.4, –10dBFS
GAIN = 0.8, –10dBFS
GAIN = 1.6, –10dBFS
GAIN = 3.2, –10dBFS
Figure 27. SINAD vs. Frequency
10516-304
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
–105
–110
–115
–120
–125
1100010010
THD (dB)
FREQUENCY (kHz)
GAIN = 0.4, –0.5dBFS
GAIN = 0.8, –0.5dBFS
GAIN = 1.6, –0.5dBFS
GAIN = 3.2, –0.5dBFS
GAIN = 0.4, –10dBFS
GAIN = 0.8, –10dBFS
GAIN = 1.6, –10dBFS
GAIN = 3.2, –10dBFS
Figure 28. THD vs. Frequency
10516-300
–60
–70
–80
–90
–100
–110
–120
–130
–140
020 40 60 80 100 120 140 160 180 200
CROSSTALK (dB)
FREQUENCY (kHz)
INTERNAL REFERENCE
CHANNEL 4 TO COM, SEQUENCER DISABLED
VIN = –0.5dBFS ON CHANNELS 0 TO 3, 5 TO 7
fS
= 1000kSPS
Figure 29. Crosstalk vs. Frequency
60
70
80
90
100
110
120
130
110 100 1k 10k 100k
CMRR (dB)
FREQUENCY (Hz)
COMMON-MODE AMPLITUDE = 20.48V p-p
INTERNAL REFERENCE
f
S
= 1000kSPS
GAIN = 0.16
GAIN = 0.20
GAIN = 0.40
GAIN = 0.80
GAIN = 1.60
GAIN = 3.20
GAIN = 6.40
10516-139
Figure 30. CMRR vs. Frequency
ADAS3022 Data Sheet
Rev. D | Page 18 of 42
10516-301
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
0.01 10010
10.1
POWER SUPPLY REJECTION RATIO (dB)
FREQUENCY (kHz)
PSRR VDDH
AVDD, GAIN = 0.2
AVDD, GAIN = 3.2
PSRR VSSH
AVDD, GAIN = 1.6
AVDD, GAIN = 6.4
Figure 31. PSRR vs. Frequency
13
14
15
16
17
18
19
4.7 4.8 4.9 5.0 5.1 5.2 5.3
AVDD CURRENT (mA)
AVDD SUPPLY (V)
GAIN= 0.2 GAIN = 0.4 GAIN = 0.
8
GAIN= 1.6 GAIN = 3.2 GAIN = 6.4
10516-130
Figure 32. AVDD Current vs. Supply, Internal Reference
10
11
12
13
14
15
4.7 4.8 4.9 5.0 5.1 5.2 5.3
AVDD CURRENT (mA)
AVDD SUPPLY (V)
GAIN = 0.2 GAIN = 0.4 GAIN = 0.8
GAIN = 1.6 GAIN = 3.2 GAIN = 6.4
10516-131
Figure 33. AVDD Current vs. Supply, External Reference
10
12
14
16
18
20
10 100 1000
AVDD CURRENT (mA)
THROUGHPUT (kSPS)
GAIN = 0.2 GAIN = 0.4GAIN=0.8
GAIN = 1.6 GAIN =3.2GAIN=6.4
10516-134
Figure 34. AVDD Current vs. Throughput, Internal Reference
9
11
10
12
13
14
15
10 100 1000
AVDD CURRENT (mA)
THROUGHPUT (kSPS)
GAIN = 0.2 GAIN = 0.4 GAIN =0.8
GAIN = 1.6 GAIN = 3.2 GAIN = 6.4
10516-135
Figure 35. AVDD Current vs. Throughput, External Reference
0.5
1.5
2.5
3.5
4.5
1.0
2.0
3.0
4.0
10 100 1000
DVDD CURRENT (mA)
THROUGHPUT (kSPS)
GAIN = 0.2 GAIN = 0.4 GAIN = 0.8
GAIN = 1.6 GAIN = 3.2 GAIN = 6.4
10516-136
Figure 36. DVDD Current vs. Throughput
Data Sheet ADAS3022
Rev. D | Page 19 of 42
0
3
6
9
12
15
18
10 100 1000
VDDH CURRENT (mA)
THROUGHPUT (kSPS)
GAIN =0.2 GAIN = 0.4 GAIN= 0.8
GAIN = 1.6 GAIN = 3.2GAIN = 6.4
10516-137
Figure 37. VDDH Current vs. Throughput
–18
–15
–12
–9
–6
–3
0
10 100 1000
VSSH CURRENT (mA)
THROUGHPUT (kSPS)
GAIN = 0.2 GAIN = 0.4 GAIN = 0.8
GAIN = 1.6 GAIN = 3.2 GAIN = 6.4
10516-138
Figure 38. VSSH Current vs. Throughput
0
2
4
6
8
10
12
14
16
18
20
–50 –40 –30 –20 –10 010 20 30 40 50 60 70 80 90
VDDH CURRENT (mA)
TEMPERATURE (°C)
GAIN = 0.2 GAIN = 0.4 GAIN = 0.8
GAIN = 1.6 GAIN = 3.2 GAIN = 6.4
f
S = 1000kSPS
10516-142
Figure 39. VDDH Current vs. Temperature
–20
–18
–16
–14
–12
–10
–8
–6
–4
–2
0
–50 –40 –30 –20 –10 010 20 30 40 50 60 70 80 90
VSSH CURRENT (mA)
TEMPERATURE (°C)
GAIN = 0.2 GAIN = 0.4 GAIN = 0.8
GAIN = 1.6 GAIN = 3.2 GAIN = 6.4
f
S
= 1000kSPS
10516-143
Figure 40. VSSH Current vs. Temperature
16.0
16.5
17.0
17.5
18.0
18.5
19.0
19.5
–50 –40 –30 –20 –10 010 20 30 40 50 60 70 80 90
AVDD CURRENT (mA)
TEMPERATURE (°C)
GAIN = 0.2 GAIN = 0.4 GAIN = 0.8
GAIN = 1.6 GAIN = 3.2 GAIN = 6.4
f
S = 1000kSPS
10516-144
Figure 41. AVDD Current vs. Temperature
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
–50 –40 –30 –20 –10 010 20 30 40 50 60 70 80 90
DVDD CURRENT (mA)
TEMPERATURE (°C)
GAIN = 0.2 GAIN = 0.4 GAIN = 0.8
GAIN = 1.6 GAIN = 3.2 GAIN = 6.4
f
S = 1000kSPS
VIO = 3.3V
10516-146
Figure 42. DVDD Current vs. Temperature
ADAS3022 Data Sheet
Rev. D | Page 20 of 42
2.00
2.25
2.50
2.75
3.00
3.25
3.50
3.75
4.00
–50 –40 –30 –20 –10 010 20 30 40 50 60 70 80 90
VIO CURRENT (mA)
TEMPERATURE (°C)
GAIN = 0.2 GAIN = 0.4 GAIN = 0.8
GAIN = 1.6 GAIN = 3.2 GAIN = 6.4
fS
= 1000kSPS
10516-145
Figure 43. VIO Current vs. Temperature
80
82
84
86
88
90
92
94
96
98
100
–50 –40 –30 –20 –10 010 20 30 40 50 60 70 80 90
SNR (dB)
TEMPERATURE (°C)
GAIN = 0.2
GAIN = 0.16
GAIN = 0.4
GAIN= 0.8
GAIN = 1.6
GAIN = 3.2
GAIN = 6.4
fS
= 1000kSPS
10516-147
Figure 44. SNR vs. Temperature
–120
–115
–110
–105
–100
–95
–90
–85
–80
–50 –40 –30 –20 –10 010 20 30 40 50 60 70 80 90
THD (dB)
TEMPERATURE (°C)
GAIN = 0.2
GAIN = 0.16
GAIN = 0.4
GAIN = 0.8
GAIN = 1.6
GAIN = 3.2
GAIN = 6.4
10516-148
Figure 45. THD vs. Temperature
–5
–4
–3
–2
–1
0
1
2
3
4
5
–50 –40 –30 –20 –10 010 20 30 40 50 60 70 80 90
GAIN ERROR (LSB)
TEMPERATURE (°C)
GAIN= 0.2
GAIN = 0.16
GAIN = 0.4
GAIN= 0.8
GAIN =1.6
GAIN = 3.2
GAIN = 6.4
10516-149
f
S = 1000kSPS
EXTERNAL REFERENCE
Figure 46. Gain Error vs. Temperature
–12
–8
–4
0
4
8
12
–50 –40 –30 –20 –10 010 20 30 40 50 60 70 80 90
OFFSET ERROR (LSB)
TEMPERATURE (°C)
GAIN = 0.2
GAIN= 0.16
GAIN =0.4
GAIN = 0.8
GAIN = 1.6
GAIN =3.2
GAIN = 6.4
f
S = 1000kSPS
EXTERNAL REFERENCE
10516-150
Figure 47. Offset Error vs. Temperature
–5
–4
–3
–2
–1
0
1
2
3
4
5
–50 –40 –30 –20 –10 010 20 30 40 50 60 70 80 90
ERROR (LSB)
TEMPERATURE (°C)
fS
= 1000kSPS
EXTERNAL REFERENCE
GAIN ERROR
OFFSET ERROR
10516-151
Figure 48. Offset and Gain Errors of the AUX ADC Channel Pair vs. Temperature
Data Sheet ADAS3022
Rev. D | Page 21 of 42
3400
3600
3800
4000
4200
4400
4600
4800
5000
5200
5400
5600
–50 –40 –30 –20 –10 010 20 30 40 50 60 70 80 90
TEMP SENSOR OUTPUT CODE (LSB)
TEMPERATURE (°C)
10516-152
Figure 49. Temperature Sensor Output Code vs. Temperature
–4.5
–4.0
–3.5
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
0.5
10k 100k 1M 10M
NORMALIZED CLOSED-LOOP GAIN (dB)
FREQUENCY (Hz)
GAIN = 0.2
–0.5dBFS
GAIN = 0.4
GAIN = 0.8 GAIN = 1.6
GAIN = 3.2 GAIN = 6.4
10516-153
fS
= 1000 kSPS
Figure 50. Large Signal Frequency Response vs. Gain
0
4
8
12
16
20
24
28
32
0
5
10
15
20
25
0100 200 300 400 500 600 700 800 900 1000
TEMPERATURE SENSOR OUTPUT ERROR (°C)
TEMPERATURE SENSOR OUTPUT ERROR (mV)
THROUGHPUT (kSPS)
T
A
= 25°C
INTERNAL REFERENCE
10516-154
Figure 51. Temperature Sensor Output Error vs. Throughput
ADAS3022 Data Sheet
Rev. D | Page 22 of 42
TERMINOLOGY
Operating Input Voltage Range
Operating input voltage range is the maximum input voltage
range, including the common-mode voltage, allowed on the
input channels IN[7:0] and COM.
Differential Input Voltage Range
Differential input voltage range is the maximum differential
full-scale input range. The value changes according to the
programmable gain setting.
Channel Off Leakage
Channel off leakage is the leakage current with the channel off.
Channel On Leakage
Channel on leakage is the leakage current with the channel on.
Charge Injection
Charge injection is a measure of the glitch impulse that is
transferred through the analog input pin into the source when
the sample is taken and/or the multiplexer is switched.
Common-Mode Rejection Ratio
CMRR is the ratio of the amplitude of a signal referred to input in
the converted result to the amplitude of the modulation common
to a pair of inputs and is expressed in decibels. CMRR is a measure
of the ability of the ADAS3022 to reject signals, such as power
line noise, that are common to the inputs. This specification is
for a 2 kHz sine wave of 20.48 V p-p applied to both channels of
an input pair.
Transient Response
Transient response is a measure of the time required for the
ADAS3022 to properly acquire the input after a full-scale step
function is applied to the system.
Least Significant Bit
LSB is the smallest increment that can be represented by a
converter. For a fully differential input ADC with N bits of
resolution, the LSB expressed in volts is
N
REF
V
LSB 2
2
(V) =
Integral Nonlinearity Error
INL refers to the deviation of each individual code from a line
drawn from negative full scale to positive full scale. The point
used as negative full scale occurs ½ LSB before the first code
transition. Positive full scale is defined as a level 1½ LSB beyond
the last code transition. The deviation is measured from the
middle of each code to the true straight line (see Figure 54).
Differential Nonlinearity (DNL) Error
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.
Offset Error
Offset error is the deviation of the actual MSB transition from
the ideal MSB transition point. The ideal MSB transition occurs
at an input level ½ LSB above analog ground.
Gain Error
The last transition (from 111 … 10 to 111 … 11) for an analog
voltage must occur 1½ LSB below the nominal full scale. The
gain error is the deviation expressed in LSB (or as a percentage
of the full-scale range) of the actual level of the last transition
from the ideal level after the offset error is removed. Closely
related to this parameter is the full-scale error (also expressed in
LSB or as a percentage of the full-scale range), which includes
the effects of the offset error.
Total Unadjusted Error (TUE)
TUE is the deviation of each code from an ideal transfer function
and is a combination of all error contributors, including non-
linearity, offset error, and gain error. TUE for the ADAS3022 is
expressed as the maximum deviation in LSB or as a percentage
of the full-scale range.
Aperture Delay
Aperture delay is a measure of the acquisition performance. It is
the time between the rising edge of the CNV input and the point
at which the input signal is held for a conversion.
Dynamic Range
Dynamic range is the ratio of the rms value of the full-scale signal
to the total rms noise measured with the inputs shorted together.
The value for the dynamic range is expressed in decibels.
Signal-to-Noise Ratio
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Signal-to-Noise-and-Distortion Ratio
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.
Data Sheet ADAS3022
Rev. D | Page 23 of 42
Total Harmonic Distortion
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in decibels.
Spurious-Free Dynamic Range
SFDR is the difference, expressed in decibels, between the rms
amplitude of the input signal and the peak spurious signal.
Channel-to-Channel Crosstalk
Channel-to-channel crosstalk is a measure of the level of crosstalk
between any channel and all other channels. The crosstalk is
measured by applying a dc input to the channel under test and
applying a full-scale, 10 kHz sine wave signal to all other channels.
The crosstalk is the amount of signal that leaks into the test channel
and is expressed in decibels.
Reference Voltage Temperature Coefficient
Reference voltage temperature coefficient is derived from the
typical shift of output voltage at 25°C on a sample of parts at the
maximum and minimum reference output voltage (VREF) measured
at TMIN, T (25°C), and TMAX. The value is expressed in ppm/°C as
6
10
)–()(
)(–)(
)Cppm/(×
×°
=°
MIN
MAX
REF
REFREF
REF
TTC25V
MinVMaxV
TCV
where:
VREF (Max) is the maximum reference output voltage at TMIN,
T (25°C), or TMAX.
VREF (Min) is the minimum reference output voltage at TMIN,
T (25°C), or TMAX.
VREF (25°C) is the reference output voltage at 25°C.
TMAX = +85°C.
TMIN = −40°C.
ADAS3022 Data Sheet
Rev. D | Page 24 of 42
THEORY OF OPERATION
OVERVIEW
The ADAS3022 is the first system on a single chip that integrates
the typical components used in a data acquisition system in one
easy to use, programmable device. This single-chip solution is
capable of converting up to 1,000,000 samples per second
(1 MSPS) of aggregate throughput. The ADAS3022 features
• High impedance inputs
• High common-mode rejection
• 8-channel, low crosstalk multiplexer (mux)
• Programmable gain instrumentation amplifier (PGIA) with
seven selectable differential input ranges from ±0.64 V to
±24.576 V
• 16-bit PulSAR® ADC with no missing codes
• Internal, precision, low drift 4.096 V reference and buffer
• Temperature sensor
• Channel sequencer
The ADAS3022 uses an Analog Devices patented high voltage
iCMOS process, allowing up to a ±24.576 V differential input
voltage range when using ±15 V supplies, which makes the
device suitable for industrial applications.
The device is housed in a small, 6 mm × 6 mm, 40-lead LFCSP
and a 7 mm × 7 mm, 48-lead LQFP and can operate over the
industrial temperature range (−40°C to +85°C). A typical
discrete multichannel data acquisition system containing
similar circuitry requires at least three times more space on the
printed circuit board (PCB).
Therefore, advantages of the ADAS3022 solution include
reduced footprint and less complex design requirements, which
also results in faster time to market and lower cost.
OPERATION
As shown in Figure 52, the ADAS3022 internal analog circuitry
consists of a high impedance, low leakage multiplexer and a
programmable gain instrumentation amplifier that can accept
full-scale differential voltages of ±0.64 V, ±1.28 V, ±2.56 V, ±5.12 V,
±10.24 V, ±20.48 V, and ±24.576 V. The ADAS3022 can be con-
figured to use up to eight single-ended input channels or four
pairs of channels, that is, 125 kSPS per channel for eight channels
or effectively 250 kSPS for four channel pairs. The device can also
provide a relative temperature measurement using the internal
temperature sensor. In addition, the differential auxiliary channel
pair (AUX+ and AUX−) is provided with the specified input
range of ±VREF . This option bypasses the mux and PGIA stages,
allowing direct access to the SAR ADC core.
Reducing the number of channels or pairs increases the throughput
rate by an amount proportional to the reciprocal of the number
of sampled channels multiplied by the aggregate throughput:
1/(Number of Channels or Pairs) × 1000 kSPS
For a single channel or channel pair, the maximum throughput
rate is 1 MSPS. For all eight channels, the AUX channel pair, and
the temperature sensor, the throughput rate of a given channel
decreases to 100 kSPS.
IN4
IN5
IN3
IN2
BUF
IN6
IN7
IN1
IN0
IN0/IN1
PAIR
DIFF TO
DIFF
COM
IN2/IN3
IN4/IN5
IN6/IN7
PulSAR
ADC
LOGIC/
INTERFACE
REFIN
REF
REFx
CNV
RESET PD
SCK
DIN
SDO
VSSH
VDDH
AGND
VIO
DVDD
AVDD
DGND
CS
COM
AUX+
AUX–
BUSY
ADAS3022
MUX
TEMP
SENSOR
10516-005
PGIA
Figure 52. ADAS3022 Simplified Block Diagram
Data Sheet ADAS3022
Rev. D | Page 25 of 42
The ADAS3022 offers true high impedance inputs in a differential
structure and rejects common-mode signals present on the inputs.
The ADAS3022 architecture does not require any of the additional
input buffers (op amps) that are usually required to condition
the input signal and drive the ADC inputs when using switched
capacitor-based SAR ADCs.
The inputs are multiplexed to the PGIA using a high voltage
multiplexer with low charge injection and very low leakage. The
inputs can be configured for a single-ended to common point
(COM) measurement or can be paired for up to four fully
differential inputs with independent gain settings. This requires
using the advanced sequencer or programming sequential
configuration words with the desired gain for each pair. The
digitally controlled, programmable gain is used to select one of
seven voltage input ranges (see Table 8).
When the sequencer option is used, an on-chip sequencer scans
the channels in order and offers independent input voltage
ranges for each channel (see the On Demand Conversion Mode
section). In this mode, a single configuration word initiates the
sequencer to scan repeatedly without the need to rewrite the
register. After the last channel is scanned, the ADAS3022
automatically begins at IN0 again and repeats the sequence
until a word is written to stop the sequencer or the
asynchronous RESET is asserted. Additionally, if changes are
made to certain configuration bits, the sequencer is reset to
IN0.
The PulSAR-based ADC core is capable of converting 1 MSPS
from a single rising edge on the convert start input (CNV). The
conversion results are available in twos complement format and
are presented on the serial data output (SDO). The digital interface
uses a dedicated chip select pin (CS) to transfer data to and from
the ADAS3022 and also provides a BUSY indicator, asynchronous
RESET, and power-down (PD) inputs.
The ADAS3022 on-chip reference uses an internal temperature
compensated 2.5 V output band gap reference and a precision
buffer amplifier to provide the 4.096 V high precision system
reference.
All of the bits in Table 12 are configured through a serial (SPI-
compatible), 16-bit configuration register (CFG). Configuration
and conversion results can be read after or during a conversion,
or the readback option can be disabled.
The ADAS3022 requires a minimum of three power supplies: +5 V,
+15 V, and −15 V. On-chip low dropout regulators provide the
necessary 2.5 V system voltages and must be decoupled externally
via dedicated pins (ACAP, DCAP, and RCAP). The ADAS3022
can be interfaced to any 1.8 V to 5 V digital logic family using
the dedicated VIO logic level voltage supply (see Table 10).
A rising edge on CNV initiates a conversion and changes the
state of the ADAS3022 from track to hold. In this state, the
ADAS3022 performs analog signal conditioning. When the
signal conditioning is complete, the ADAS3022 returns to the
track state while at the same time quantizing the sample. This
two-part process satisfies the necessary settling time requirement
while achieving a fast throughput rate of up to 1 MSPS with 16-bit
accuracy. Figure 53 shows the timing diagram and the tCYC start
at the positive edge of the CNV.
PHASE
CNV
HOLD CONVERT/TRACK
t
CYC
t
ACQ
10516-006
Figure 53. ADAS3022 System Timing
Regardless of the type of signal (differential or single-ended,
antiphase or nonantiphase, symmetric or asymmetric), the
ADAS3022 converts all signals present on the enabled inputs in
a differential fashion, like an industry-standard difference or
instrumentation amplifier.
The conversion result is available after the conversion completes
and can be read back at any time before the end of the next
conversion. Reading back data must be avoided during the quiet
period, as indicated by BUSY being active high. Because the
ADAS3022 has an on-board conversion clock, the serial clock
(SCK) is not required for the conversion process. It is only
required to present results to the user.
TRANSFER FUNCTION
The ideal transfer characteristics of the ADAS3022 are shown in
Figure 54. With the inputs configured for differential input ranges,
the data output is twos complement, as described in Table 7.
100 ... 000
100 ... 001
100 ... 010
011 ... 101
011 ... 110
011 ... 111
TWOS
COMPLEMENT
ADC CODE
ANALOG INPUT
+FSR – 1.5LSB
+FSR – 1LSB
–FSR + 1LSB
–FSR
–FSR + 0.5LSB
10516-007
Figure 54. ADC Ideal Transfer Function
ADAS3022 Data Sheet
Rev. D | Page 26 of 42
Table 7. Output Codes and Ideal Input Voltages
Description
Differential Analog
Inputs, VREF = 4.096 V
Digital Output
Code (Twos
Complement, Hex)
FSR − 1 LSB (32,767 × VREF)/
(32,768 × PGIA gain)
0x7FFF
Midscale + 1 LSB VREF/(32,768 × PGIA
gain)
0x0001
Midscale 0 0x0000
Midscale − 1 LSB −(VREF/(32,768 ×
PGIA gain))
0xFFFF
−FSR + 1 LSB −(32,767 × VREF)/
(32,768 × PGIA gain)
0x8001
−FSR −VREF × PGIA gain 0x8000
TYPICAL APPLICATION CONNECTION DIAGRAM
As shown in Figure 55, the ADP1613 is used in an inexpensive
SEPIC-Ćuk topology, which is an ideal candidate for providing
the ADAS3022 with the necessary high voltage ±15 V robust
supplies (at 20 mA) and low output ripple (3 mV maximum)
from an external 5 V supply. The ADP1613 satisfies the
specification requirements of the ADAS3022 with minimal
external components while achieving greater than 86% of
efficiency. Refer to the CN-0201 circuit note for complete
information about this test setup.
IN0
IN0/IN1
IN2/IN3
IN4/IN5
IN6/IN7
IN1
IN2
IN3
IN4
IN5
IN6
IN7
DIFF
PAIR
DIFF
COM
LOGIC/
INTERFACE
REFIN
REF
MUX
CNV
RESET
SCK
DIN
SDO
VDDH AVDD DVDD VIO
CS
COM
AUX+
AUX–
BUSY
+
+
+
ENABLE
ADP1613
ADAS3022
COMP
FB FREQ
EN VIN
GND
SS
SW
++
V
IN
= +5V
+
++
+
VSSH
RF2
4.22kΩ
RF1B
47.5kΩ
R
C
1
100kΩ
C
C
1
12nF C
C
2
10pF
C
V
5
1µF
R
EN
R
B
0
1Ω
R
S
1
0Ω
R
S
2
DNI
C
SS
1µF Z1
C
IN
1µF
D1
D2
C1
1µF
C2
1µF
L3
1µF
C
OUT
3
4.7µF
C
OUT
1
1µF
C
OUT
2
2.2µF
+15V
–15V
+5V
ADR434
REFx
PD
AGND DGND
AD8031
4.096V
+
–
1.78Ω
R
FILT
DNI
50kΩ
L1
47µH
L2
47µH
+
+5V
+5V
BUF
PulSAR
ADC
10516-200
TEMP
SENSOR
PGIA
Figure 55. Complete 5 V, Single-Supply, 8-Channel Multiplexed Data Acquisition System with PGIA
Data Sheet ADAS3022
Rev. D | Page 27 of 42
ANALOG INPUTS
Input Structure
The ADAS3022 uses a differential input structure between
IN[7:0] and COM or between IN[7:0]+ and IN[7:0]− of a
channel pair. The COM input is sampled identically such that
the same voltages can be present on inputs IN[7:0]. Therefore,
the selection of paired channels or all channels referenced to
one common point is available. Because all inputs are sampled
differentially, the ADAS3022 offers true high common-mode
rejection, whereas a discrete system requires the use of
additional instrumentation or a difference amplifier.
Figure 56 shows an equivalent circuit of the analog inputs. The
internal diodes provide ESD protection for the analog inputs
(IN[7:0] and COM) from the high voltage supplies (VDDH and
VSSH). Take care to ensure that the analog input signal does not
exceed the supply rails by more than 0.3 V because this can
cause the diodes to become forward-biased and to start conducting
current. Note that if the auxiliary input pair (AUX±) is used, the
diodes provide ESD protection from only the lower voltage AVDD
(5 V) supply and the system analog ground because these inputs
are connected directly to the internal SAR ADC circuitry.
C
PIN
C
PIN
IN[7:0]
OR COM
VSSH
AUX+
OR AUX–
AGND
VDDH
AVDD
MUX PGIA
10516-008
Figure 56. Equivalent Analog Input Circuit
Voltages beyond the absolute maximum ratings may cause
permanent damage to the ADAS3022 (see Table 4).
Programmable Gain
The ADAS3022 incorporates a programmable gain instru-
mentation amplifier with seven selectable ranges (±0.64 V,
±1.28 V, ±2.56 V, ±5.12 V, ±10.24 V, ±20.48 V, and ±24.576 V),
enabling the use of almost any direct sensor interface. The PGIA
settings are specified in terms of the maximum absolute differential
input voltage across a pair of inputs (for example, INx+ to INx−
or INx+ to COM). The power-on and default conditions are
preset to the ±20.48 V (PGIA = 111) input range.
Note that because the ADAS3022 can use any input type, such
as bipolar differential (antiphase or nonantiphase), bipolar single
ended, or pseudo bipolar, setting the PGIA is important to
make full use of the allowable input span.
Table 8 describes each differential input range and the
corresponding LSB size, PGIA bits settings, and PGIA gain.
Table 8. Differential Input Ranges, LSB Size, and PGIA
Settings
Differential Input Ranges,
INx+ − INx− (V)
LSB (µ
V) PGIA Bits
PGIA Gain
(V/V)
±24.576 750 000 0.16
±20.48 625 111 0.2
±10.24
312.5
001
0.4
±5.12 156.3 010 0.8
±2.56 78.13 011 1.6
±1.28 39.06 100 3.2
±0.64 19.53 101 6.4
Common-Mode Operating Range
The differential input common-mode voltage (VCM) range
changes according to the maximum input range selected and
the high voltage power supplies (VDDH and VSSH). Note that
the specified operating input voltage of any input pin (see the
Specifications section) requires 2.5 V of headroom from the
VDDH and VSSH supplies; therefore,
(VSSH + 2.5 V) ≤ INx/COM ≤ (VDDH − 2.5 V)
This section provides some examples of setting the PGIA for
various input signals. Note that the ADAS3022 always calculates
the difference between the IN+ and IN− signals.
Fully Differential, Antiphase Signals with a
Zero Common Mode
For a pair of 20.48 V p-p differential antiphase signals with a
zero common mode, the maximum differential voltage across
the inputs is ±20.48 V, and the PGIA gain configuration must be
set to 111.
ADAS3022
INx+
INx+
+10.24V 20.48V p-p
20.48V p-p
–10.24V
INx–
INx–
10516-009
Figure 57. Differential, Antiphase Inputs with a Zero Common Mode
ADAS3022 Data Sheet
Rev. D | Page 28 of 42
Fully Differential, Antiphase Signals with a
Nonzero Common Mode
For a pair of 5.12 V p-p differential antiphase signals with a
nonzero common mode (dc common-mode voltage of 7 V in
this example), the maximum differential voltage across the
inputs is ±5.12 V (dc common-mode voltage is rejected), and
the PGIA gain configuration must be set to 010.
ADAS3022
INx+
INx+
0V
5.12V p-p
5.12V p-p
INx–
INx–
V
CM
= 7V
V
CM
10516-010
Figure 58. Differential, Antiphase Inputs with a Nonzero Common Mode
Differential, Nonantiphase Signals with a
Zero Common Mode
For a pair of 10.24 V p-p differential nonantiphase signals with
a zero common mode, the maximum differential voltage across
the inputs is ±10.24 V, and the PGIA gain configuration must be
set to 001.
ADAS3022
INx+
+5.12V 10.24V p-p
0V
INx–
–5.12V 10.24V p-p
10516-011
INx+
INx–
Figure 59. Differential, Nonantiphase Inputs with a Zero Common Mode
Single-Ended Signals with a Nonzero DC Offset
(Asymmetrical)
When a 12 V p-p signal with a 6 V dc level-shift is connected to
one input (INx+) and the dc ground sense of the signal is
connected to INx− or COM, the PGIA gain configuration is set
to 000 for the ±24.576 V range because the maximum differential
voltage across the inputs is 12 V p-p and only half the codes
available for the transfer function are used.
ADAS3022
INx+
INx+
+12V 12V p-p
0V
V
OFF
V
OFF
INx–
INx–
10516-012
Figure 60. Typical Single-Ended Unipolar Input—Uses Only Half the Codes
Single-Ended Signals with a 0 V DC Offset (Symmetrical)
Compared with the example in the Single-Ended Signals with a
Nonzero DC Offset (Asymmetrical) section, a better solution
for single-ended signals, if possible, is to remove as much dc
offset as possible between INx+ and INx− to produce a bipolar
input voltage that is symmetric around the ground sense. In this
example, the differential voltage across the inputs is never greater
than ±0.64 V, and the PGIA gain configuration is set to 101 for
the 1.28 V p-p range. This scenario uses all of the codes available
for the transfer function, making full use of the allowable differential
input range.
ADAS3022
INx+
INx+
+0.64V
1.28V p-p
–0.64V
INx–
INx–
10516-013
Figure 61. Better Single-Ended Configuration—Uses All Codes
Notice that the voltages in this example are not integer values
due to the 4.096 V reference and the PGIA scaling ratios.
Multiplexer
The ADAS3022 uses a high voltage, high performance, low
charge injection multiplexer and a total of nine inputs (IN[7:0]
and COM). Using the INx and COM bits of the configuration
register, the ADAS3022 is configurable for differential inputs
between any of the eight input channels (IN[7:0]) and COM or
for up to four input pairs. Figure 62 shows various methods for
configuring the analog inputs for the type of channel (single or
paired). Refer to the Configuration Register section for more
information.
The analog inputs can be configured as follows:
• Figure 62A: IN[7:0] referenced to a system ground.
• Figure 62B: IN[7:0] with a common reference point.
• Figure 62C: IN[7:0] differential pairs. For pairs, COM = 0.
The positive channel is configured with INx. If INx is even,
then IN0, IN2, IN4, and IN6 are used. If INx is odd, then
IN1, IN3, IN5, and IN7 are used, as indicated by the channels
with parentheses in Figure 62C. For example, for the IN0/IN1
pair with the positive channel on IN0, INx = 0002. For the
IN4/IN5 pair with the positive channel on IN5, INx = 1012.
Note that when the channel sequencer is used, as detailed in
the On Demand Conversion Mode section, the positive
channels are always IN0, IN2, IN4, and IN6.
• Figure 62D: inputs configured in a combination of any of
the preceding configurations (showing that the ADAS3022
can be configured dynamically).
Data Sheet ADAS3022
Rev. D | Page 29 of 42
IN0+
COM–
IN0
IN1+
IN2+
IN3+
IN4+
IN5+
IN6+
IN7+
IN0+
IN1+
IN2+
IN3+
IN4+
IN5+
IN6+
IN7+
IN1
IN2
IN3
IN4
IN5
IN6
IN7
COM
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
COM
A—8 CHANNELS,
SINGLE-ENDED
B—8 CHANNELS,
COMMON REFERENCE
10516-014
IN2+
IN3+
IN4+
IN5+
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
COM
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
COM
IN0+ (–)
C—4 CHANNELS,
DIFFERENTIAL
D—COMBINATION
COM–
IN0– (+)
IN1+ (–)
IN1– (+)
IN0+ (–)
IN0– (+)
IN1+ (–)
IN1– (+)
IN2+ (–)
IN2– (+)
IN3+ (–)
IN3– (+)
Figure 62. Multiplexed Analog Input Configurations
Channel Sequencer
The ADAS3022 includes a channel sequencer that is useful for
scanning channels in a repeated fashion. Refer to the On
Demand Conversion Mode section for more information.
Auxiliary Input Channel
The ADAS3022 includes an auxiliary input channel pair (AUX+
and AUX−) that bypasses the mux and PGIA stages, allowing direct
access to the SAR ADC core for applications where the additional
dedicated channel pair is required. As detailed previously, the
inputs are protected only from AVDD and AGND because the high
voltage supplies are used for the mux and PGIA stages but not
the lower voltage ADC core.
When the source impedance of the driving circuit is low, the
AUX± inputs can be driven directly. Large source impedances
significantly affect the ac performance, especially THD. The dc
performance parameters are less sensitive to the input impedance.
The maximum source impedance depends on the amount of
THD that can be tolerated. The THD degrades as a function of
the source impedance and the maximum input frequency.
Driver Amplifier Choice
For systems that cannot drive AUX± directly, a suitable op amp
buffer must be used to preserve the ADAS3022 performance.
The driver amplifier must meet the following requirements:
• The noise generated by the driver amplifier must be kept as
low as possible to preserve the SNR and the transition noise
performance of the ADAS3022. The noise from the amplifier
is filtered by the ADAS3022 analog input circuit or by an
external filter, if one is used. Because the typical noise of the
SAR ADC core of the ADAS3022 is 35 µV rms (VREF = 4.096
V), the SNR degradation due to the amplifier is
+
=
−22 )(
2
π
35
35
log20
N
3dB
LOSS
Nef
SNR
where:
f−3dB is the input bandwidth (8 MHz) of the’ SAR ADC core of
the ADAS3022 expressed in megahertz or the cutoff
frequency of an input filter, if one is used.
N is the noise gain of the amplifier (for example, 1 in buffer
configuration).
eN is the equivalent input noise voltage of the op amp
expressed in nV/√Hz.
• For ac applications, the driver must have a THD performance
commensurate with the ADAS3022.
• The analog input circuit must settle a full-scale step onto
the capacitor array at a 16-bit level (0.0015%). In amplifier
data sheets, settling at 0.1% to 0.01% is more commonly
specified. This may differ significantly from the settling
time at a 16-bit level and must be verified prior to driver
selection.
Table 9. Recommended Driver Amplifiers
Amplifier Typical Application
ADA4841-1, ADA4841-2 Very low noise, small, and low power
ADA4897-1, ADA4897-2 Very low noise, low and high frequencies
AD8655 5 V single supply, low noise
AD8021, AD8022 Very low noise and high frequency
OP184 Low power, low noise, and low frequency
AD8605, AD8615
5 V single supply, low power
ADAS3022 Data Sheet
Rev. D | Page 30 of 42
VOLTAGE REFERENCE OUTPUT/INPUT
The ADAS3022 allows the choice of an internal reference or an
external reference using the on-chip buffer/amplifier, or an
external reference.
The internal reference of the ADAS3022 provides excellent
performance and can be used in almost all applications. To set
the reference selection mode, use the internal reference enable bit
(REFEN) and the REFIN pin as described in this section. REF1
and REF2 must be tied together externally.
Internal Reference
The precision internal reference is factory trimmed and is
suitable for most applications.
Setting the REFEN bit in the CFG register to 1 (default) enables the
internal reference and produces 4.096 V on the REF1 and REF2
pins; this 4.096 V output serves as the main system reference. The
unbuffered 2.5 V (typical) band gap voltage is output on the REFIN
pin, which requires an external parallel decoupling using 10 µF and
0.1 µF capacitors to reduce the noise on the output. Because the
current output of REFIN is limited, it can be used as a source if
followed by a suitable buffer, such as the AD8031. Note that
excessive loading of the REFIN output also lowers the 4.096 V
system reference because the internal amplifier uses a fixed gain.
The internal reference output is trimmed to the targeted value of
4.096 V with an initial accuracy of ±8 mV. The reference is also
temperature compensated to provide a typical drift of ±5 ppm/°C.
When the internal reference is used, the ADAS3022 must be
decoupled as shown in Figure 63. Note that both REF1 and
REF2 connections are required, along with suitable decoupling
on the REFIN output and the RCAP internally regulated supply.
REF2 REF1
RCA
P
REFN
RGND
BAND
GAP
ADAS3022
0.1
µ
F
REFIN
REFN
10
µ
F10
µ
F
0.1
µ
F
10
µ
F
0.1
µ
F
1
µ
F
REFN
10516-016
Figure 63. 4.096 V Internal Reference Connection
External Reference and Internal Buffer
The external reference and internal buffer are useful when a com-
mon system reference is used or if improved drift performance
is required.
Setting REFEN to 0 disables the internal band gap reference,
allowing the user to provide an external voltage reference (2.5 V
typical) to the REFIN pin.
The internal buffer remains enabled, thus reducing the need for an
external buffer amplifier to generate the main system reference.
With REFIN = 2.5 V, REF1 and REF2 output 4.096 V, which
serves as the main system reference.
For this configuration, connect the external source as shown
in Figure 64. Any type of 2.5 V reference, including those with
low power, low drift, and a small package, can be used in this
configuration because the internal buffer handles the dynamics
of the ADAS3022 reference.
REF2 REF1
RCAP
REFN
RGND
BAND
GAP
ADAS3022
0.1
µ
F
REFIN
REFN
10
µ
F10
µ
F
0.1
µ
F
10
µ
F
0.1
µ
F
1
µ
F
REFN
REFERENCE
SOURCE = 2.5V
10516-017
Figure 64. External Reference Using Internal Buffer
External Reference
For applications that require a precise, low drift 4.096 V reference,
an external reference can also be used.
This option requires disabling the internal buffer by setting
REFEN to 0 and driving or connecting REFIN to AGND; therefore,
both hardware and software control are necessary. Attempting
to drive the REF1 and REF2 pins prior to disabling the internal
buffer can cause source/sink contention in the driving amplifiers.
Connect the precision 4.096 V reference, which serves as the
main system reference, through a low impedance buffer (such as
the AD8031 or the AD8605) to REF1 and REF2 as shown in
Figure 65. Recommended references include the ADR434,
ADR444, and ADR4540.
REF2 REF1
RCAP
REFN
RGND
BAND
GAP
ADAS3022
0.1
µ
F
REFINREFN
10
µ
F10
µ
F
0.1
µ
F
1µF
REFERENCE
SOURCE = 4.096V
10516-018
Figure 65. External Reference
If an op amp is used as the external reference source, take note
of any concerns regarding driving capacitive loads. Capacitive
loading for op amps usually refers to the ability of the amplifier
to remain marginally stable in ac applications but can also play
a role in dc applications, such as a reference source. Keep in
mind that the reference source sees the dynamics of the bit
decision process on the reference pins and further analysis
beyond the scope of this data sheet may be required.
Data Sheet ADAS3022
Rev. D | Page 31 of 42
Reference Decoupling
With any of the reference topologies described in the Voltage
Reference Input/Output section, the REF1 and REF2 reference
pins of the ADAS3022 have dynamic impedances and require
sufficient decoupling, regardless of whether the pins are used as
inputs or outputs. This decoupling usually consists of a low
equivalent series resistor (ESR) capacitor connected to each
REF1 and REF2 and to the accompanying REFN return paths.
Using X5R, 1206 size ceramic chip capacitors is recommended
for decoupling in all the reference topologies described in the
Voltage Reference Input/Output section.
The placement of the reference decoupling capacitors plays an
important role in the system performance. Mount the decoupling
capacitors on the same side as the ADAS3022, close to the REF1
and REF2 pins, with thick PCB traces. Route the return paths to the
REFN inputs, which are in turn connected to the analog ground
plane of the system. The resistance of the return path to ground
must be minimized by using as many through vias as possible
when it is necessary to connect to an internal PCB layer.
The REFN and RGND inputs must be connected with the
shortest distance to the analog ground plane of the system,
preferably adjacent to the solder pads, using several vias. One
common mistake is to route these traces to an individual trace
that connects to the ground of the system. This can introduce
noise, which may adversely affect LSB sensitivity. To prevent
such noise, it is highly recommended to use PCBs with multiple
layers, including ground planes, rather than using single- or
double-sided boards. Refer to UG-484 for more information
about the PCB layout of the EVA L-ADAS3022EDZ.
For applications that use multiple ADAS3022 devices or other
PulSAR ADCs, it is more effective to use the internal reference
buffer to buffer the external reference voltage, thus reducing
SAR conversion crosstalk.
The voltage reference temperature coefficient (TC) directly
affects the full-scale accuracy of the system; therefore, in
applications where full-scale accuracy is crucial, care must be
taken with the TC. For example, a ±15 ppm/°C TC of the
reference changes the full-scale accuracy by ±1 LSB/°C.
POWER SUPPLY
The ADAS3022 uses five supplies: AVDD, DVDD, VIO, VDDH,
and VSSH (see Table 10). Note that ACAP, DCAP, and RCAP
are included in Table 10 for informational purposes only because
these supplies are outputs of the on-chip supply regulators.
Refer to UG-484 for more information about how these supplies
are generated on the EVAL-ADAS3022EDZ.
Table 10. Power Supplies
Name Function Required
AVDD Analog 5 V core Yes
DVDD
Digital 5 V core
Yes, or can connect to
AVDD
VIO Digital input/output Yes, and can connect
to DVDD (for 5 V level)
VDDH Positive high voltage Yes, +15 V typ
VSSH Negative high voltage Yes, −15 V typ
ACAP
Analog 2.5 V core
No, on chip
DCAP Digital 2.5 V core No, on chip
RCAP Analog 2.5 V core No, on chip
Core Supplies
AVDD and DVDD supply the ADAS3022 analog and digital
cores, respectively. Sufficient decoupling of these supplies is
required, consisting of at least a 10 µ F capacitor and a 100 nF
capacitor on each supply. The 100 nF capacitors must be placed
as close as possible to the ADAS3022. To reduce the number of
supplies needed, DVDD can be supplied from the analog supply
by connecting a simple RC filter between AVDD and DVDD, as
shown in Figure 66.
VIO is the variable digital input/output supply and can be
directly interfaced to any logic between 1.8 V and 5 V (DVDD
supply maximum). To reduce the supplies needed, VIO can
alternatively be connected to DVDD when DVDD is supplied
from the analog supply through an RC filter. The recommended
low dropout regulators are ADP3334, ADP1715, and ADP7102/
ADP7104 for the AVDD, DVDD, and VIO supplies.
ADAS3022 Data Sheet
Rev. D | Page 32 of 42
AVDD
10µF
100nF 100 nF
AGND DGND
DGND
DVDD
ADAS3022
VIO
1.8V TO 5V
DIGITAL I/O
SUPPLY
ANALOG
SUPPLY
+5V
+5V DIGITAL
SUPPLY
10µF
10µF
20
Ω
VDDH
VSSH
10µF
100nF
+15V
–15V
10µF 100nF
100nF
10516-020
Figure 66. ADAS3022 Supply Connections
High Voltage Supplies
The high voltage bipolar supplies (VDDH and VSSH) are
required and must be at least 2.5 V larger than the maximum
input. For example, the supplies must be ±15 V for headroom in
the ±24.576 V differential input range. Sufficient decoupling of
these supplies is also required, consisting of at least a 10 µ F
capacitor and a 100 nF capacitor on each supply.
Power Dissipation Modes
The ADAS3022 offers two power dissipation modes: fully
operational mode and power-down mode.
Fully Operational Mode
In fully operational mode, the ADAS3022 can perform
conversions as soon as all internal bias currents are established.
Power-Down Mode
To minimize the operating currents of the device when it is idle,
place the device in full power-down mode by bringing the PD
input high. This places the ADAS3022 into a deep sleep mode, in
which CNV activity is ignored and the digital interface is inactive.
Refer to the Reset and Power-Down (PD) Inputs section for timing
details. In deep sleep mode, the internal regulators (AC A P,
RCAP, and DCAP) and the voltage reference are also powered
down. To reestablish operation, return PD low.
Note that before the device can operate at the specified
performance, the reference voltage must charge up the external
reservoir capacitor(s) and be allowed the specified settling time.
Returning PD and RESET low from high resets the ADAS3022
digital core, including the CFG register, to its default state.
Therefore, the desired CFG must be rewritten to the device and
two dummy conversions must be completed before the device
operation is restored to the configuration programmed prior to
PD assertion.
CONVERSION MODES
The ADAS3022 offers two conversion modes to accommodate
varying applications. The mode is set with the conversion mode
select bit (CMS, Bit 1 of the CFG register).
Warp Mode (CMS = 0)
Setting CMS to 0 is useful when an aggregate throughput rate of
1 MSPS is required. However, in this mode, the maximum time
between conversions is restricted. If this maximum period is
exceeded, the conversion result may be corrupted. Therefore,
this mode is more suitable for continually sampled applications.
Normal Mode (CMS = 1, Default)
Setting CMS to 1 is useful for all applications with a maximum
aggregate throughput of 900 kSPS. In this mode, there is no
restriction in terms of the maximum time between conversions.
This mode is the default condition from the assertion of an
asynchronous RESET. The main difference between normal
mode and warp mode is the BUSY time; tQUIET is slightly longer
in normal mode than it is in warp mode.
Data Sheet ADAS3022
Rev. D | Page 33 of 42
DIGITAL INTERFACE
The ADAS3022 digital interface consists of asynchronous
inputs, a busy indicator, and a 4-wire serial interface for
conversion result readback and configuration register
programming.
This interface uses the three asynchronous signals (C N V,
RESET, and PD) and a 4-wire serial interface composed of CS,
SDO, SCK, and DIN. CS can also be tied to CNV for some
applications.
Conversion results are available on the serial data output pin
(SDO), and the 16-bit configuration word (CFG) is program-
med on the serial data input pin (DIN). This register controls
settings such as the channel to be converted, the programmable
gain setting, and the reference choice (see the Configuration
Register section for more information).
CONVERSION CONTROL
Conversions are initiated by the CNV input. The ADAS3022 is
fully asynchronous and can perform conversions at any frequency
from dc up to 1 MHz, depending on the conversion mode.
CNV Rising Edge—Start of a Conversion (SOC)
A rising edge on CNV changes the state of the ADAS3022 from
track mode to hold mode and is all that is necessary to initiate a
conversion. All conversion timing clocks are internally generated.
After a conversion is initiated, the ADAS3022 ignores other
activity on the CNV line (governed by the throughput rate) until
the end of the conversion; the conversion can only be aborted
by the power-down (PD) or RESET inputs.
When the ADAS3022 is performing a conversion and the BUSY
output is driven high, the ADAS3022 uses a unique 2-phase
conversion process to allow for safe data access and quiet times.
The CNV signal is decoupled from the CS pin, allowing
multiple ADAS3022 devices to be controlled by the same
processor. For applications where SNR is critical, the CNV
source must have very low jitter. This can be achieved by using
a dedicated oscillator or by clocking CNV with a high
frequency, low jitter clock. For applications where jitter is more
tolerable or a single device is in use, CNV can be tied to CS. For
more information about sample clock jitter and aperture delay,
refer to the MT-007 Tutorial, Aperture Time, Aperture Jitter,
Aperture Delay Time—Removing the Confusion.
Although CNV is a digital signal, it must be designed to ensure
fast, clean edges with minimal overshoot, undershoot, and
ringing. The CNV trace must be shielded by connecting a trace
to ground, and a low value (such as 50 Ω) serial resistor
termination must be added close to the output of the component
that drives this line. In addition, take care to avoid digital activity
close to the sampling instant because such activity may result in
degraded SNR performance.
BUSY Falling Edge—End of a Conversion (EOC)
The EOC event is indicated by BUSY returning low and can be
used as a host interrupt. In addition, the EOC gates data access
to and from the ADAS3022. If the current conversion result is
not read prior to the following EOC event, the data is lost.
Furthermore, if the CFG update is not completed prior to EOC, it
is discarded and the current configuration is applied to future con-
versions. This pipeline ensures that the ADAS3022 has sufficient
time to acquire the next sample to the specified 16-bit accuracy.
Conversion Timing
A detailed timing diagram of the conversion process is shown
in Figure 67.
CONVER-
SION
ACQUI-
SITION
CNV
CS
SDO
DIN
BUSY
(n)
SAFE
XXX
XXX
QUIET
DATA
(n – 1)
CFG
(n + 2) x
xCFG
(n + 3)
DATA
(n)
x
(n + 1)
(n + 1)
(n)
EOC
(n)
SOC
(n)
t
DDC
t
CH
t
CYC
t
QUIET
t
DAC
t
AD
t
ACQ
t
CCS
t
CBD
t
CONV
t
CCS
t
DDCA
SOC
(n + 1)
10516-022
Figure 67. Basic Conversion Timing
Register Pipeline
To ensure that all CFG updates are applied during a known safe
instant to the various circuit elements, the asynchronous data
transfer is synchronized to the ADAS3022 timing engine using
the EOC event. This synchronization introduces an inherent delay
between updating the CFG register setting and the application
of the configuration to a conversion. This pipeline from the end
of the current conversion (n) consists of a two-deep delay (shown
as (n + 2) in Figure 67) before the CFG setting takes effect. This
means that two SOC and EOC events must elapse before the
setting (that is, new channel, gain, and so on) takes effect. Note
that the nomenclature (n), (n + 1), and so on is used in the
remainder of the following digital sections for simplicity.
There is no pipeline after the end of a conversion, however,
before data can be read back.
RESET AND POWER-DOWN (PD) INPUTS
The asynchronous RESET and PD inputs can be used to reset
and power down the ADAS3022, respectively. Timing details
are shown in Figure 68.
ADAS3022 Data Sheet
Rev. D | Page 34 of 42
A rising edge on RESET or PD aborts the conversion process and
places SDO into high impedance, regardless of the CS level. Note
that RESET has a minimum pulse width (active high) time for
setting the ADAS3022 into the reset state. See the Configuration
Register section for the default CFG setting when the ADAS3022
returns from the reset state. If the default setting is used after
RESET is deasserted (Logic 0), a period equal to the acquisition
time (tACQ) must elapse before CNV can be asserted for the
conversion result to be valid. If a conversion initiates, the result
corrupts. In addition, the output data from the previous
conversion is cleared upon a reset. Attempting to access the data
result prior to initiating a new conversion results in an invalid
result.
When the device returns from power-down mode or from a reset
and the default CFG is not used, there is no tACQ requirement;
the first two conversions from power-up are undefined/invalid
because the two-deep delay pipeline requirement must be satisfied
to reconfigure the device to the desired setting.
CS
SDO
CNV
n– 1
n – 1
n
SEE NOTE
SEE NOTE
n – 1
n – 2
x x
x
BUSY
RESET/
PD
t
ACQ
t
DIS
tEN
t
RH
CFG n + 1x n+ 2
NOTES
1. WHEN THE PART IS RELEASED FROM RESET, tACQ MUST BE MET FOR
CONVERSION n IF USING THE DEFAULT CFG SETTING FOR CHANNEL IN0.
WHEN THE PART IS RELEASED FROM POWER-DOWN, tACQ IS NOT REQUIRED,
AND THE FIRST TWO CONVERSIONS, n AND n + 1, ARE UNDEFINED.
10516-023
Figure 68. RESET and PD Timing
SERIAL DATA INTERFACE
The ADAS3022 uses a simple 4-wire interface and is compatible
with FPGAs, DSPs, and common serial interfaces, such as serial
peripheral interface (SPI), queued serial peripheral interface
(QSPI), and MICROWIRE™. The interface uses the CS, SCK,
SDO, and DIN signals. Timing details for the serial interface are
shown in Figure 69. SDO is activated when CS is asserted. The
conversion result is output on SDO and is updated on SCK
falling edges. Simultaneously, the 16-bit CFG word is updated, if
desired, on the serial data input (DIN). The state of the clock
phase select bit (CPHA, Bit 0) determines whether the MSB is
output again on the first clock or whether the MSB − 1 bit is
output when SDO activates after the EOC.
Note that in Figure 68 and Figure 69, SCK is shown idling high.
SCK can idle high or low, requiring that the system developer
design an interface that suits setup and hold times for both SDO
and DIN.
DIN
(MOSI)
SDO
(MISO)
CS
SCK
t
EN
t
SDOD
t
SDOH
t
SCK
t
DIS
t
DINH
t
DINS
t
SCKH
t
SCKL
10516-024
Figure 69. Serial Timing
CPHA
The clock phase select bit (CPHA, Bit 0) sets the first bit of the
conversion result on SDO after the end of a conversion (see
Figure 70).
Setting CPHA to 0 outputs the MSB when CS is asserted. Sub-
sequent SCK falling edges clock out bits in an MSB − 1, MSB − 2,
and so on fashion. This mode is useful for hosts limited to 16 clock
edges where the first falling (or rising) edge can be used to latch
the data.
Setting CPHA to 1 outputs the MSB not only when CS is asserted
but also after the first SCK falling edge. Subsequent SCK falling
edges clock out bits in an MSB − 1, MSB − 2, and so on fashion.
This mode can be useful for sign extension applications.
SDO
CPHA = 1
SDO
CPHA = 0
CS
SCK
MSB MSBLSBLSB + 1MSB – 1 MSB – 2
MSB
121615
LSB + 1 LSBLSB + 2MSB MSB – 1
10516-025
Figure 70. CPHA Details
Sampling on the SCK Falling Edge
To achieve the fastest data transfer rate, the host must sample
data on the SCK falling edge, as long as there is a sufficient hold
time of ≤tSDOH (see Figure 69). When using this method, data
transfers must occur during the safe conversion time (tDDC).
Because this time is fixed, extending data reading or writing into
the quiet conversion phase (tQUIET) may cause data corruption.
However, for systems that need slightly more time, tDDCA (data
during conversion additional) can be used.
Data Sheet ADAS3022
Rev. D | Page 35 of 42
Sampling on the SCK Rising Edge (Alternate Edge)
SPI or other alternate edge transfers typically require more time
to access data because the total data transfer time of these slower
hosts can be >tDDC. If this is the case, the time from tQUIET to the next
CNV rising edge, which is known as the data access time after
conversion (tDAC) and is determined by the user, must be
adjusted by lowering the throughput rate (CNV frequency),
thus providing the necessary time. If this does not allow enough
time, the data access can be broken up so that some data access
occurs during this time followed by the remainder of data
access occurring during the next tDDC and tDDCA times.
CFG Readback
The CFG result associated with the current conversion can be read
back with an additional 16 SCK burst following the conversion
result (see Figure 70). After the LSB of the conversion result
clocks out, the MSB of the CFG associated with that conversion
follows. Subsequent SCK falling edges repeat the conversion
result and CFG word. For example, when CPHA is 0, the MSB
of the conversion result is output on the 32nd falling edge.
GENERAL CONSIDERATIONS
Because the time to access data is somewhat restricted, the
following guidelines are useful in determining the ADAS3022
throughput, or CNV frequency, and the serial interface details.
Note that in Figure 71 to Figure 73, tAD is for reference purposes
only and denotes a time without digital activity because such
activity must not occur prior to or just after sampling.
Data Access During Conversion—Maximum Throughput
The maximum throughput rate per channel is determined
mainly by the maximum SCK period of the host. When using
the maximum throughput rate of 1 MSPS, the ADAS3022 has
an almost symmetric period for both safe data and quiet times
(approximately 500 ns each; see Figure 71). Consequently, tDDC
is basically fixed and only provides the host approximately
500 ns to access data. Note that in Figure 71, tAD is for reference
purposes only and denotes a time without digital activity
because such activity should not occur during the sampling edge.
For 17 SCK edges (worst case), the minimum SCK frequency
required to achieve a 1 MSPS (1 µs between CNV rising)
aggregate throughput rate is
MHz34
17 ≥
+
≥
DDCAD
tt
SCK
f
Although additional time to access data can be attained by trans-
ferring data during tDDCA, this is not recommended because the
ADAS3022 performs sensitive bit decisions during this time. If
tDDCA is used, however, the minimum SCK frequency is
MHz25
17 ≥
++
≥
DDCADDCAD
tt
t
SCK
f
CS
n
n
nn – 1
n + 2
n + 2 n + 3
n + 1
n + 1
SDO
DIN
SCK
CNV
BUSY
SOC EOC
t
DDC
t
AD
t
DDCA
t
QUIET
10516-026
Figure 71. Data Access During Conversion
Data Access After/Spanning Conversion—Host Determined
Throughput
For hosts that do not have the 34 MHz or 25 MHz SCK rates
available, the maximum throughput rate cannot be achieved
because the data access time after conversion, tDAC, must be
increased to allow more time to access data. In this case, there
are three methods to access data:
• The first method is to adjust tDAC for 17 SCK edges (worst
case) and the additional CS to CNV setup and hold times.
In this case, all data access occurs during tDAC. This is the
only method that can be used when using a slow host that
cannot break up data into bytes or other partial data bursts.
• A second method is to break up the data into bursts that
can transfer part of the data during tDAC of the current
conversion and the rest of the data during tDDC of the next
conversion. Note that CS can stay low throughout the CNV
rising phase; however, serial clock activity must pause
while the input is being sampled.
• A third method is to use the second method along with the
additional tDDCA, again noting that digital activity must cease
after this time to prevent the current conversion from
becoming corrupted.
In any of these methods, if the time between conversions (tCYC)
exceeds for the fastest possible throughput mode (CMS = 0), the
conversion results are inaccurate. If this is the case, the fully
asynchronous mode (CMS = 1) must be selected (see the
Conversion Modes section for details).
Figure 72 shows a basic timing diagram for all three methods.
For conversion (n), the data is read back after the end of a
conversion (n), with the remainder of data read into the next
(n + 1) conversion.
ADAS3022 Data Sheet
Rev. D | Page 36 of 42
10516-027
CS
n
n
x x
n
n – 1
n + 2 n + 3
SDO
DIN
SCK
CNV
BUSY
SOC SOC
EOC
t
CCS
tDDC
tDDCA
tAD
n + 1
x
n + 1
n
n + 3
tDAC
Figure 72. Data Access Spanning Conversion
GENERAL TIMING
Figure 73 is a general timing diagram showing the complete
register to conversion and readback pipeline delay. The figure
details the timing upon power-up or upon returning from a full
power-down by use of the PD input. Figure 74 and Figure 75 show
the general timing diagrams when only the auxiliary ADC input
channel pair is enabled for the data read during conversion (RDC)
mode and the read after conversion (RAC) mode, respectively.
10516-228
ACQUISITION (n)
UNDEFINED
PHASE
POWER
UP
CONVERSION (n – 1)
UNDEFINED
CNV
BUSY
DIN
CS
SDO
NOTES
1. DATA ACCESS CAN OCCUR DURING A CONVERSION (
tDDC
), AFTER A CONVERSION (
tDAC
), OR BOTH DURING AND AFTER A CONVERSION.
THE CONVERSION RESULT AND THE CFG REGISTER ARE UPDATED AT THE END OF A CONVERSION (EOC).
2. DATA ACCESS CAN ALSO OCCUR UP TO
tDDCA
WHILE BUSY IS ACTIVE (SEE THE DIGITAL INTERFACE SECTION FOR DETAILS). ALL OF THE BUSY
TIME CAN BE USED TO ACQUIRE DATA.
3. A TOTAL OF 16 SCK FALLING EDGES IS REQUIRED FOR A CONVERSION RESULT. AN ADDITIONAL 16 EDGES ARE REQUIRED TO
READ BACK THE CFG RESULT ASSOCIATED WITH THE CURRENT CONVERSION.
4. CS CAN BE HELD LOW OR CONNECTED TO CNV. CS WITH FULL INDEPENDENT CONTROL IS SHOWN IN THIS FIGURE.
5. FOR OPTIMAL PERFORMANCE, DATA ACCESS SHOULD NOT OCCUR DURING THE SAMPLING EDGE. A MINIMUM TIME
OF THE APERTURE DELAY (
tAD
) SHOULD ELAPSE PRIOR TO DATA ACCESS.
DATA
INVALID
SCK
1 1
1
16/32
1616
X16
NOTE 3
NOTE 1
NOTE 2
NOTE 2
NOTE 1
NOTE 4
NOTE 5
CFG
INVALID CFG (n + 2)
DATA (n – 1)
INVALID
ACQUISITION (n + 1)
UNDEFINED
CONVERSION (n)
UNDEFINED
DATA (n – 1)
INVALID
CFG (n + 2) CFG (n + 3)
DATA (n)
INVALID
ACQUISITION
(n + 2)
CONVERSION (n + 1)
UNDEFINED
DATA (n)
INVALID
CFG (n + 3)
CFG (n + 4)
DATA (n + 1)
INVALID
ACQUISITION
(n + 3)
PHASE CONVERSION
(n + 2)
CNV
BUSY
DIN
CS
SDO DATA (n + 1)
INVALID
SCK
1
1
CFG (n + 4) CFG (n + 5)
DATA (n + 2)
ACQUISITION
(n + 4)
CONVERSION
(n + 3)
DATA (n + 2)
CFG (n + 5) CFG (n + 6)
DATA (n + 3)
CONVERSION
(n + 4)
DATA (n + 3)
CFG (n + 6)
EOC
EOC EOC EOC
EOC SOC
SOC
tDDC
tCYC
tQUIET tDAC
tACQ
tAD
tDDCA
Figure 73. General Timing Diagram
Data Sheet ADAS3022
Rev. D | Page 37 of 42
CS
n
n
n – 1
n + 2
n + 2
n + 1
n + 1
SDO
DIN
SCK
CNV
BUSY
SOC EOC
t
AD
t
QUIET
116
n
n + 3
n + 2
n + 1
n + 4
116
116
10516-252
Figure 74. General Timing Diagram of AUX Input Channel Pair (RDC)
CS
n
n
n
n + 2
n + 3
n + 1
n + 1
SDO
DIN
SCK
CNV
BUSY
SOC EOC
tAD
tQUIET
116 116
n + 1
n + 4
tEN
n + 2
116
n + 2
n + 5
n + 3
n + 3
10516-253
Figure 75. General Timing Diagram of AUX Input Channel Pair (RAC)
ADAS3022 Data Sheet
Rev. D | Page 38 of 42
CONFIGURATION REGISTER
The configuration register, CFG, is a 16-bit, programmable
register for selecting all of the ADAS3022 user-programmable
options (see Table 12). The register loads when data is read back
for the first 16 SCK rising edges and updates at the next EOC.
Note that there is always a two-deep delay (n + 2) when writing
CFG and when reading back CFG for the setting associated
with the current conversion.
The default CFG setting is applied when the ADAS3022 returns
from the reset state (RESET = high) to the operational state
(RESET = low). However, when the ADAS3022 returns from the
full power-down state (PD = high) to an enabled state (PD = low),
the default CFG setting is not applied, and at least two dummy
conversions are required for the user-specified CFG setting to
take effect.
Therefore, the default value is CFG[15:0] = 0x8FCF. This sets
the ADAS3022 as follows:
• Overwrites contents of CFG register
• Selects the IN0 input channel referenced to COM
• Configures the PGIA gain to 0.20 (±20.48 V)
• Selects the multiplexer input
• Disables the internal channel sequencer
• Disables the temperature sensor
• Enables the internal reference
• Selects normal conversion mode
• Selects SPI interface mode
Table 11. Configuration Register, CFG; Default Value = 0x8FCF (1000 1111 1100 1111)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFG INx INx INx COM RSV PGIA PGIA PGIA MUX SEQ SEQ TEMPB REFEN CMS CPHA
Table 12. Configuration Register Bit Description
Bits Bit Name Description
15 CFG Configuration update.
0 = keep current configuration settings.
1 = overwrite contents of register (default).
[14:12] INx Input channel selection in binary fashion. See the Multiplexer section.
Bit 14 Bit 13 Bit 12 Channel
0 0 0 IN0 (default)
… … …
1
1
1
IN7
11 COM IN[7:0] common channel input. AUX+ and AUX− are not referenced to COM.
0 = channels are referenced in differential pairs: IN0/IN1, IN2/IN3, IN4/IN5, and IN6/IN7 (see the On Demand
Conversion Mode section).
1 = each channel is referenced to a common sense, COM (default).
10 RSV Reserved. Setting or clearing this bit has no effect.
[9:7] PGIA Programmable gain selection (see the Input Structure section). In basic sequencer modes, this register configures
the range for all channels. In advanced sequencer mode, this register sets the range for IN0 (COM = 1) or the IN0/IN1
pair (COM = 0). See the Advanced Mode section for the PGIA configurations of individual channels or channel pairs.
Bit 9 Bit 8 Bit 7 Absolute Input Voltage Range
0 0 0 ±24.576 V
0 0 1 ±10.24 V
0 1 0 ±5.12 V
0 1 1 ±2.56 V
1 0 0 ±1.28 V
1 0 1 ±0.64 V
1 1 0 Not used
1 1 1 ±20.48 V (default)
6 MUX Multiplexer/auxiliary channel input (see the Auxiliary Input Channel section).
0 = selects auxiliary channel on AUX± inputs as active channel.
1 = uses the selected analog front end (AFE) channel/channel pair (default).
Data Sheet ADAS3022
Rev. D | Page 39 of 42
Bits Bit Name Description
[5:4] SEQ Channel sequencer. Allows for scanning channels sequentially from IN0 to INx. INx is the last channel converted prior
to resetting the sequence back to IN0 and is specified by the channel selected in the INx[2:0] configuration bits (see
the On Demand Conversion Mode section).
Bit 5 Bit 4 Function
0 0 Disable sequencer (default)
0 1 Update configuration during basic sequence
1 0 Initialize advanced sequencer
1 1 Initialize basic sequencer
3 TEMPB Temperature sensor enable control (see the On Demand Conversion Mode section).
0 = internal temperature sensor enabled.
1 = internal temperature sensor disabled (default).
2 REFEN Internal reference selection (see the Pin Configuration and Function Descriptions and Voltage Reference
Input/Output sections for more information).
0 = disables the internal reference. The internal reference buffer is disabled by pulling REFIN to ground.
1 = enables the internal reference (default).
1 CMS Conversion mode select (see the Conversion Modes section).
0 = uses the warp mode for conversions with a time between conversion restriction.
1 = uses the normal mode for conversions (default).
0 CPHA MSB select (see the CPHA section).
0 = asserting CS after the end of a conversion places the MSB on SDO, and the first SCK falling edge places (MSB − 1) on SDO.
1 = asserting CS after the end of a conversion places the MSB on SDO, and the first SCK falling edge repeats MSB on SDO
(default).
ON DEMAND CONVERSION MODE
When the channel sequencer is disabled, the input channels can
be selected for the on demand conversions based on the MUX
and TEMPB bit settings, as shown in Table 13. For example, the
only internal TEMP sensor channel conversions in this mode
can be obtained by setting the MUX = TEMPB = 0.
Table 13. Input Channel Select
MUX TEMPB Output
1 1 INx[14:12] Channels
1 0 Invalid
0 1 AUX± Input Channels
0 0 Internal Temperature Sensor Channel
CHANNEL SEQUENCER DETAILS
The ADAS3022 includes a channel sequencer, which is useful for
scanning channels in a sequential order. Channels are scanned
individually with reference to COM or as pairs and can also
include the auxiliary channel pair and/or the internal temperature
sensor measurement. After the last programmed measurement
is sampled, the ADAS3022 sequencer is reset to the first channel
(IN0) or channel pair (IN0/IN1) and repeats the sequence until
the sequencer is disabled or an asynchronous RESET or PD occurs.
When the channel sequencer is enabled, for all differential
pairs, the positive terminals are the even channels (IN0, IN2,
IN4, and IN6), and the negative terminals are, conversely, the
odd channels (IN1, IN3, IN5, and IN7). When the channel
sequencer is disabled, the user can assign either positive or
negative terminals to even or odd channels for all differential
pairs, depending on the INx[14:12] settings. For example, if
INx[14:12] = 001 when using the IN0/IN1 pair, IN1 is the
positive input and IN0 is the negative input.
Each sequence loop always starts with IN0 or IN0/IN1 and
terminates with either the last channel/channel pair set in the
INx bits, the temperature sensor, or the auxiliary input channel,
depending on the configuration word. Table 14 provides a quick
reference for how the device responds to the programmed configu-
ration. For the first case, the channel sequencer scans Channel IN0
through Channel IN3 in a repeated fashion. Note that the last
conversion is corrupted when exiting the sequencer.
Table 14. Typical Channel Sequencer Example
INx[14:12] COM MUX TEMPB End of Sequence
011 1 1 1 IN3 (to COM)
111 1 1 1 IN7 (to COM)
11x
0
1
1
IN6 to IN7
111 1 1 0 TEMPB
111 1 0 1 AUX±
111 1 0 0 AUX±
ADAS3022 Data Sheet
Rev. D | Page 40 of 42
INx and COM Inputs (MUX = 1, TEMPB = 1)
To use individual INx channels with reference to COM or pairs
of INx channels in a sequence without converting the AUX or
temperature sensor channels, the MUX and TEMPB bits must
be set to 1. The last channel to be converted in the sequence is
specified by the channel set in the INx bits. After the last channel is
scanned, the next conversion starts over at IN0 or IN0/IN1. For
paired channels, the channels are paired depending on the last
channel set in INx. Note that the channels are always paired
with the positive input on the even channels (IN0, IN2, IN4,
IN6) and the negative input on the odd channels (IN1, IN3, IN5,
IN7). Therefore, setting INx to 110 or 111 scans all pairs with
the positive inputs dedicated to IN0, IN2, IN4, and IN6. For
example, to scan four single channels, set INx to 011, COM to 1,
and MUX to 1, which results in a sequence order of IN0, IN1,
IN2, IN3, IN0, IN1, IN2, and IN3.
INx and COM Inputs with AUX Inputs (MUX = 0, TEMPB = 1)
To use individual INx channels with reference to COM or pairs
of INx channels with the AUX inputs in a sequence, the MUX
bit must be set to 0 to append the AUX channel to the end of the
sequence (after the channel set in INx is scanned). Note that the
AUX input is a pair, whereas the INx channel can be referenced to
COM or pairs of INx channels. For example, to scan four single
channels and the AUX inputs, set INx to 011, COM to 1, and
MUX to 0, which results in a sequence order of IN0, IN1, IN2,
IN3, AUX, IN0, IN1, IN2, IN3, AUX, and so on.
INx and COM Inputs with Temperature Sensor
(MUX = 1, TEMPB = 0)
To append the temperature sensor conversion to the end of the
input channel sequence, the TEMPB bit must be set low in the
configuration word. Note that the temperature sensor requires
at least 5 µs between conversions. The data is output in straight
binary format.
INx and COM Inputs with AUX Inputs and Temperature
Sensor (MUX = 0, TEMPB = 0)
Both temperature sensor conversions and auxiliary channel
conversions can be appended to the end of the input sequence
by setting the MUX and TEMPB bits in the CFG register. For
example, to scan all input channels with respect to COM, the
temperature sensor, and the auxiliary channel at once, the user
must set INx to 111, COM to 1, MUX to 0, and TEMPB to 0.
The resulting sequence is IN0, IN1, IN2, IN3, IN4, IN5, IN6,
IN7, temperature sensor, and AUX.
Sequencer Modes
The ADAS3022 has two sequencer modes that are configured
with the SEQ bits: basic mode and advanced mode. Basic mode
can be used when all channels are configured with the same
PGIA range. Advanced mode allows individual channel ranges
to be programmed using two additional advanced sequence
registers, ASR0 and ASR1. The SEQ bits are used to enable the
sequencer. Setting SEQ to 01, 10, or 11 specifies which sequencer
mode is used. Depending on the mode, basic or advanced
sequencing determines the next data into DIN.
Note that for any sequencer update there exists a two-deep
delay when writing the register for the setting to take effect.
Basic Sequencer Mode (SEQ = 11)
The basic mode is useful for systems that use the same PGIA
range on all channels. In basic sequencer mode, all that is
required is a single CFG word to place the ADAS3022 in an
automatically scanned mode. On the second conversion
following the EOC for sequencer CFG, the sequencer starts.
After the CFG for basic sequence updates, DIN must be held
low for at least the MSB during the data readback or a new CFG
word updates, disabling the sequencer.
Update During Sequence (SEQ = 01)
Some of the CFG settings, such as PGIA and CMS, can be updated
during a sequence. Writing a new CFG word with the appropriate
bits to be changed for the (n + 2) conversion updates the sequencer
from that point; all channels then use, for example, the new PGIA
value. Note that changing bits in INx for the last channel or chang-
ing COM reinitializes the sequencer at the (n + 2) conversion. A
more practical method is to use the advanced sequencer mode as
described in the Advanced Sequencer Mode (SEQ = 10) section.
Advanced Sequencer Mode (SEQ = 10)
The advanced mode is useful for systems that require different
gains for different individual INx inputs or different pairs of
INx inputs. In this mode, two additional registers are used to
program the various gain settings. After the initial CFG word
enabling the advanced sequencer mode is written, the ADAS3022
expects to receive at least one additional data transfer for the
first advanced sequencer register, ASR0, or both advanced
sequencer registers, depending on how many channels are in the
sequence. Each ASR requires a conversion and a corresponding
EOC to load the data into the device. The user cannot simply
write 48 bits all at once because, as with all CFG word transfers,
only the first 16 bits are latched and updated at EOC.
Note that the PGIA setting for IN0 or IN0/IN1 is written in the
initial CFG register, and if using pairs of INx channels, only
ASR0 is required. After the CFG and the associated advanced
sequencer registers are updated, DIN must be held low for at
least the MSB of subsequent data transfers; otherwise, the
advanced sequencer mode aborts.
Data Sheet ADAS3022
Rev. D | Page 41 of 42
Table 15. Advanced Sequencer Register 0
Bits Function
15 ASR0 write enable
0 = update ASR0 following CFG for advanced sequencer
1 = enters normal CFG update
[14:11] Reserved
[10:8] PGIA for IN1 or IN2/IN3
7 Reserved
[6:4] PGIA for IN2 or IN4/IN5
3 Reserved
[2:0] PGIA for IN3 or IN6/IN7
Table 16. Advanced Sequencer Register 1
Bits Function
15 ASR1 write enable
0 = update ASR1 following ASR0
1 = enters normal CFG update
[14:12] PGIA for IN4
11 Reserved
[10:8] PGIA for IN5
7 Reserved
[6:4] PGIA for IN6
3 Reserved
[2:0] PGIA for IN7
ADAS3022 Data Sheet
Rev. D | Page 42 of 42
OUTLINE DIMENSIONS
03-03-2017-B
0.50
BSC
BOTTOM VIEW
TOP VIEW
PIN 1
INDICATOR
0.05 MAX
0.02 NOM
0.20 REF
COPLANARITY
0.08
0.30
0.25
0.18
6.10
6.00 SQ
5.90
1.00
0.95
0.85
0.45
0.40
0.35
0.25 MIN
4.70
4.60 SQ
4.50
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-5
40
1
11 10
20
21
30
31
END VIEW
EXPOSED
PAD
PKG-003653/5050
SEATING
PLANE
PIN 1
INDIC AT OR AREA OPTIONS
(SEE DETAIL A)
DETAIL A
(JEDEC 95)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 76. 40-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
6 mm × 6 mm Body and 0.75 mm Package Height
(CP-40-15)
Dimensions shown in millimeters
COMPLIANT TO JEDEC STANDARDS MS-026-BBC
TOP VIEW
(PINS DOWN)
1
12
13
25
24
36
37
48
0.27
0.22
0.17
0.50
BSC
LEAD PITCH
1.60
MAX
0.75
0.60
0.45
VIEW A
PIN 1
0.20
0.09
1.45
1.40
1.35
0.08
COPLANARITY
VIEW A
ROTATED 90° CCW
SEATING
PLANE
7°
3.5°
0°
0.15
0.05
9.20
9.00 SQ
8.80
7.20
7.00 SQ
6.80
051706-A
Figure 77. 48-Lead Low Profile Quad Flat Package [LQFP]
ST-48
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADAS3022BCPZ −40°C to +85°C 40-Lead Lead Frame Chip Scale Package [LFCSP] CP-40-15
ADAS3022BCPZ-RL7 −40°C to +85°C 40-Lead Lead Frame Chip Scale Package [LFCSP] CP-40-15
ADAS3022BSTZ −40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48
ADAS3022BSTZ-RL7 −40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48
EVAL-ADAS3022EDZ Evaluation Board
1 Z = RoHS Compliant Part.
©2012–2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10516-0-8/18(D)