February 2013 Revision 3.3
Intel® 82574 GbE Controller Family
Datasheet
Product Features
PCI Express* (PCIe*)
— 64-bit address master support for systems
using more than 4 GB of physical memory
— Programmable host memory receive buffers
(256 bytes to 16 KB)
— Intelligent interrupt generation features to
enhance driver performance
— Descriptor ring management hardware for
transmit and receive software controlled reset
(resets everything except the configuration
space)
— Message Signaled Interrupts (MSI and MSI-X)
— Configurable receive and transmit data FIFO,
programmable in 1 KB increments
MAC
— Flow Control Support compliant with the
802.3X Specification
— VLAN support compliant with the 802.1Q
Specification
— MAC Address filters: perfect match unicast
— filters; multicast hash filtering, broadcast filter
— and promiscuous mode
— Statistics for management and RMOM
— MAC loopback
PHY
— Compliant with the 1 Gb/s IEEE 802.3 802.3u
802.3ab Specifications
— IEEE 802.3ab auto negotiation support
— Full duplex operation at 10/100/1000 Mb/s
— Half duplex at 10/100 Mb/s
— Auto MDI, MDI-X crossover at all speeds
High Performance
— TCP segmentation capability compatible with
Large Send offloading features
— Support up to 64 KB TCP segmentation (TSO
v2)
— Fragmented UDP checksum offload for packet
reassemble
— IPv4 and IPv6 checksum offload support
(receive, transmit, and large send)
— Split header support
— Receive Side Scaling (RSS) with two hardware
receive queues
— 9 KB jumbo frame support
— 40 KB packet buffer size
Manageability
— NC-SI for remote management core
— SMBus advanced pass through interface
Low Power
— Magic Packet* wake-up enable with unique
MAC address
— ACPI register set and power down functionality
supporting D0 andD3 states
— Full wake up support (APM and ACPI 2.0)
— Smart power down at S0 no link and Sx no link
— LAN disable function
Technology
— 9 mm x 9 mm 64-pin QFN package with
Exposed Pad*
— Configurable LED operation for customization
of LED displays
— TimeSync offload compliant with the 802.1as
specification
— Wider operating temperature range; -40 °C to
85 °C (82574IT only)
2
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Copyright © 2013, Intel Corporation. All Rights Reserved.
3
Datasheet—82574 GbE Controller
Contents
1.0 Introduction ............................................................................................................ 12
1.1 Scope .............................................................................................................. 12
1.2 Number Conventions ......................................................................................... 12
1.3 Acronyms......................................................................................................... 13
1.4 Reference Documents ........................................................................................ 14
1.5 82574L Architecture Block Diagram ..................................................................... 15
1.6 System Interface............................................................................................... 15
1.7 Features Summary ............................................................................................ 15
1.8 Product Codes................................................................................................... 18
2.0 Pin Interface ........................................................................................................... 20
2.1 Pin Assignments................................................................................................ 20
2.2 Pull-Up/Pull-Down Resistors and Strapping Options................................................ 21
2.3 Signal Type Definition ........................................................................................ 21
2.3.1 PCIe ..................................................................................................... 21
2.3.2 NVM Port............................................................................................... 22
2.3.3 System Management Bus (SMBus) Interface .............................................. 23
2.3.4 NC-SI and Testability.............................................................................. 23
2.3.5 LEDs .................................................................................................... 24
2.3.6 PHY Pins ............................................................................................... 24
2.3.7 Miscellaneous Pin ................................................................................... 25
2.3.8 Power Supplies and Support Pins.............................................................. 26
2.4 Package ........................................................................................................... 27
3.0 Interconnects .......................................................................................................... 28
3.1 PCIe ................................................................................................................ 28
3.1.1 Architecture, Transaction, and Link Layer Properties ................................... 29
3.1.2 General Functionality .............................................................................. 30
3.1.3 Transaction Layer................................................................................... 30
3.1.4 Flow Control .......................................................................................... 35
3.1.5 Host I/F ................................................................................................ 37
3.1.6 Error Events and Error Reporting.............................................................. 38
3.1.7 Link Layer ............................................................................................. 41
3.1.8 PHY ...................................................................................................... 42
3.1.9 Performance Monitoring .......................................................................... 43
3.2 Ethernet Interface ............................................................................................. 43
3.2.1 MAC/PHY GMII/MII Interface ................................................................... 43
3.2.2 Duplex Operation for Copper PHY/GMII/MII Operation................................. 44
3.2.3 Auto-Negotiation & Link Setup Features .................................................... 45
3.2.4 Loss of Signal/Link Status Indication......................................................... 48
3.2.5 10/100 Mb/s Specific Performance Enhancements....................................... 49
3.2.6 Flow Control .......................................................................................... 50
3.3 SPI Non-Volatile Memory Interface ...................................................................... 53
3.3.1 General Overview................................................................................... 53
3.3.2 Supported NVM Devices .......................................................................... 53
3.3.3 NVM Device Detection............................................................................. 54
3.3.4 Device Operation with an External EEPROM................................................ 55
3.3.5 Device Operation with Flash..................................................................... 55
3.3.6 Shadow RAM ......................................................................................... 55
3.3.7 NVM Clients and Interfaces...................................................................... 57
3.3.8 NVM Write and Erase Sequence................................................................ 58
82574 GbE Controller—Datasheet
4
3.4 System Management Bus (SMBus).......................................................................60
3.5 NC-SI...............................................................................................................60
3.5.1 Interface Specification.............................................................................61
3.5.2 Electrical Characteristics ..........................................................................61
4.0 Initialization ............................................................................................................62
4.1 Introduction......................................................................................................62
4.2 Reset Operation.................................................................................................62
4.3 Power Up..........................................................................................................64
4.3.1 Power-Up Sequence ................................................................................64
4.3.2 Timing Diagram......................................................................................72
4.4 Global Reset (PE_RST_N, PCIe In-Band Reset) ......................................................73
4.4.1 Reset Sequence......................................................................................73
4.4.2 Timing Diagram......................................................................................74
4.5 Timing Parameters.............................................................................................76
4.5.1 Timing Requirements ..............................................................................76
4.5.2 MDIO and NVM Semaphore ......................................................................76
4.6 Software Initialization Sequence ..........................................................................77
4.6.1 Interrupts During Initialization..................................................................78
4.6.2 Global Reset and General Configuration .....................................................78
4.6.3 Link Setup Mechanisms and Control/Status Bit Summary .............................78
4.6.4 Initialization of Statistics..........................................................................80
4.6.5 Receive Initialization ...............................................................................80
4.6.6 Transmit Initialization..............................................................................81
5.0 Power Management and Delivery .............................................................................84
5.1 Assumptions .....................................................................................................84
5.2 Power Consumption ...........................................................................................84
5.3 Power Delivery ..................................................................................................85
5.3.1 The 1.9 V dc Rail ....................................................................................85
5.3.2 The 1.05 V dc Rail ..................................................................................85
5.4 Power Management............................................................................................85
5.4.1 82574L Power States ..............................................................................85
5.4.2 Auxiliary Power Usage .............................................................................86
5.4.3 Power Limits by Certain Form Factors........................................................87
5.4.4 Power States..........................................................................................87
5.4.5 Timing of Power-State Transitions.............................................................91
5.5 Wake Up ..........................................................................................................94
5.5.1 Advanced Power Management Wake Up.....................................................94
5.5.2 PCIe Power Management Wake Up............................................................95
5.5.3 Wake-Up Packets....................................................................................95
6.0 Non-Volatile Memory (NVM) Map ...........................................................................102
6.1 Basic Configuration Table..................................................................................102
6.1.1 Hardware Accessed Words .....................................................................104
6.1.2 Software Accessed Words ......................................................................117
6.2 Manageability Configuration Words.....................................................................125
6.2.1 SMBus APT Configuration Words .............................................................125
6.2.2 NC-SI Configuration Words ....................................................................127
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Datasheet—82574 GbE Controller
7.0 Inline Functions .................................................................................................... 130
7.1 Packet Reception............................................................................................. 130
7.1.1 Packet Address Filtering ........................................................................ 130
7.1.2 Receive Data Storage ........................................................................... 131
7.1.3 Legacy Receive Descriptor Format .......................................................... 131
7.1.4 Extended Rx Descriptor......................................................................... 134
7.1.5 Packet Split Receive Descriptor .............................................................. 140
7.1.6 Receive Descriptor Fetching................................................................... 143
7.1.7 Receive Descriptor Write Back................................................................ 143
7.1.8 Receive Descriptor Queue Structure........................................................ 144
7.1.9 Receive Interrupts................................................................................ 146
7.1.10 Receive Packet Checksum Offloading ...................................................... 149
7.1.11 Multiple Receive Queues and Receive-Side Scaling (RSS)........................... 151
7.2 Packet Transmission ........................................................................................ 157
7.2.1 Transmit Functionality........................................................................... 157
7.2.2 Transmission Flow Using Simplified Legacy Descriptors.............................. 158
7.2.3 Transmission Process Flow Using Extended Descriptors.............................. 158
7.2.4 Transmit Descriptor Ring Structure ......................................................... 159
7.2.5 Multiple Transmit Queues ...................................................................... 161
7.2.6 Overview of On-Chip Transmit Modes...................................................... 161
7.2.7 Pipelined Tx Data Read Requests............................................................ 162
7.2.8 Transmit Interrupts .............................................................................. 163
7.2.9 Transmit Data Storage.......................................................................... 163
7.2.10 Transmit Descriptor Formats.................................................................. 164
7.2.11 Extended Data Descriptor Format ........................................................... 172
7.3 TCP Segmentation........................................................................................... 176
7.3.1 TCP Segmentation Performance Advantages ............................................ 176
7.3.2 Ethernet Packet Format......................................................................... 176
7.3.3 TCP Segmentation Data Descriptors........................................................ 177
7.3.4 TCP Segmentation Source Data.............................................................. 178
7.3.5 Hardware Performed Updating for Each Frame ......................................... 178
7.3.6 TCP Segmentation Use of Multiple Data Descriptors .................................. 179
7.4 Interrupts ...................................................................................................... 182
7.4.1 Legacy and MSI Interrupt Modes ............................................................ 182
7.4.2 MSI-X Mode......................................................................................... 182
7.4.3 Registers............................................................................................. 183
7.4.4 Interrupt Moderation ............................................................................ 185
7.4.5 Clearing Interrupt Causes...................................................................... 187
7.5 802.1q VLAN Support ...................................................................................... 188
7.5.1 802.1q VLAN Packet Format .................................................................. 188
7.5.2 Transmitting and Receiving 802.1q Packets ............................................. 189
7.5.3 802.1q VLAN Packet Filtering ................................................................. 189
7.6 LED's............................................................................................................. 190
7.7 Time SYNC (IEEE1588 and 802.1AS) ................................................................. 191
7.7.1 Overview ............................................................................................ 191
7.7.2 Flow and Hardware/Software Responsibilities ........................................... 192
7.7.3 Hardware Time Sync Elements ............................................................... 194
7.7.4 PTP Packet Structure ............................................................................ 197
82574 GbE Controller—Datasheet
6
8.0 System Manageability ............................................................................................200
8.1 Scope ............................................................................................................200
8.2 Pass-Through (PT) Functionality......................................................................... 200
8.3 Components of a Sideband Interface ..................................................................201
8.4 SMBus Pass-Through Interface ..........................................................................201
8.4.1 General ...............................................................................................202
8.4.2 Pass-Through Capabilities ...................................................................... 202
8.4.3 Manageability Receive Filtering ...............................................................202
8.4.4 SMBus Transactions ..............................................................................210
8.4.5 SMBus Notification Methods ...................................................................214
8.5 Receive TCO Flow ............................................................................................217
8.6 Transmit TCO Flow...........................................................................................217
8.6.1 Transmit Errors in Sequence Handling .....................................................218
8.6.2 TCO Command Aborted Flow..................................................................218
8.7 SMBus ARP Transactions...................................................................................219
8.7.1 Prepare to ARP .....................................................................................219
8.7.2 Reset Device (General)..........................................................................219
8.7.3 Reset Device (Directed).........................................................................219
8.7.4 Assign Address..................................................................................... 219
8.7.5 Get UDID (General and Directed)............................................................220
8.8 SMBus Pass-Through Transactions .....................................................................222
8.8.1 Write Transactions ................................................................................222
8.8.2 Read Transactions (82574L to MC).......................................................... 227
8.9 SMBus Troubleshooting ....................................................................................237
8.9.1 SMBus Commands are Always NACK'd by the 82574L ................................237
8.9.2 SMBus Clock Speed is 16.6666 KHz.........................................................237
8.9.3 A Network Based Host Application is not Receiving any Network Packets ...... 237
8.9.4 Status Registers ...................................................................................238
8.9.5 Unable to Transmit Packets from the MC.................................................. 238
8.9.6 SMBus Fragment Size............................................................................238
8.9.7 Enable XSum Filtering ...........................................................................239
8.9.8 Still Having Problems?...........................................................................239
8.10 NC-SI Interface ............................................................................................... 240
8.11 Overview........................................................................................................ 240
8.11.1 Terminology......................................................................................... 240
8.11.2 System Topology ..................................................................................242
8.11.3 Data Transport.....................................................................................243
8.12 NC-SI Support.................................................................................................245
8.12.1 Supported Features...............................................................................245
8.12.2 NC-SI Mode - Intel Specific Commands....................................................246
8.13 Basic NC-SI Workflows .....................................................................................251
8.13.1 Package States.....................................................................................251
8.13.2 Channel States.....................................................................................252
8.13.3 Discovery ............................................................................................252
8.13.4 Configurations......................................................................................252
8.13.5 Pass-Through Traffic States....................................................................254
8.13.6 Asynchronous Event Notifications............................................................255
8.13.7 Querying Active Parameters ...................................................................255
8.14 Resets............................................................................................................256
8.15 Advanced Workflows ........................................................................................256
8.15.1 Multi-NC Arbitration ..............................................................................256
8.15.2 External Link Control.............................................................................257
8.15.3 Statistics ............................................................................................. 258
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Datasheet—82574 GbE Controller
9.0 Programming Interface ......................................................................................... 260
9.1 PCIe Configuration Space ................................................................................. 260
9.1.1 PCIe Compatibility................................................................................ 260
9.1.2 Mandatory PCI Configuration Registers.................................................... 261
9.1.3 PCI Power Management Registers........................................................... 266
9.1.4 Message Signaled Interrupt (MSI) Configuration Registers ......................... 269
9.1.5 MSI-X Configuration ............................................................................. 270
9.1.6 PCIe Configuration Registers.................................................................. 273
10.0 Driver Programming Interface............................................................................... 284
10.1 Introduction ................................................................................................... 284
10.1.1 Memory and I/O Address Decoding......................................................... 284
10.1.2 Registers Byte Ordering ........................................................................ 287
10.1.3 Register Conventions ............................................................................ 288
10.2 Configuration and Status Registers - CSR Space .................................................. 288
10.2.1 Register Summary Table ....................................................................... 288
10.2.2 General Register Descriptions ................................................................ 295
10.2.3 PCIe Register Descriptions..................................................................... 314
10.2.4 Interrupt Register Descriptions............................................................... 322
10.2.5 Receive Register Descriptions ................................................................ 329
10.2.6 Transmit Register Descriptions ............................................................... 346
10.2.7 Statistic Register Descriptions ................................................................ 354
10.2.8 Management Register Descriptions ......................................................... 369
10.2.9 Time Sync Register Descriptions............................................................. 380
10.2.10MSI-X Register Descriptions................................................................... 383
10.2.11PHY Registers ...................................................................................... 385
10.2.12Diagnostic Register Descriptions............................................................. 414
11.0 Diagnostics............................................................................................................ 420
11.1 Introduction ................................................................................................... 420
11.2 FIFO Pointer Accessibility.................................................................................. 420
11.3 FIFO Data Accessibility..................................................................................... 420
11.4 Loopback Operations ....................................................................................... 421
12.0 Electrical Specifications ......................................................................................... 422
12.1 Introduction ................................................................................................... 422
12.2 Voltage Regulator Power Supply Specification ..................................................... 422
12.2.1 3.3 V dc Rail........................................................................................ 422
12.2.2 1.9 V dc Rail....................................................................................... 422
12.2.3 1.05 V dc Rail ...................................................................................... 423
12.2.4 PNP Specifications ............................................................................... 423
12.3 Power Sequencing ........................................................................................... 424
12.4 Power-On Reset .............................................................................................. 424
12.5 Power Scheme Solutions .................................................................................. 425
12.6 Flash AC Specifications..................................................................................... 428
12.7 EEPROM AC Specifications ................................................................................ 429
12.8 Discrete/Integrated Magnetics Specifications....................................................... 430
12.9 Oscillator/Crystal Specifications......................................................................... 431
12.10 I/O DC Parameters .......................................................................................... 432
12.10.1Test, JTAG and NC-SI ........................................................................... 433
12.10.2LEDs .................................................................................................. 433
12.10.3SMBus ................................................................................................ 434
82574 GbE Controller—Datasheet
8
13.0 Design Considerations ...........................................................................................436
13.1 PCIe ..............................................................................................................436
13.1.1 Port Connection to the 82574 .................................................................436
13.1.2 PCIe Reference Clock ............................................................................436
13.1.3 Other PCIe Signals................................................................................436
13.1.4 PCIe Routing........................................................................................437
13.2 Clock Source................................................................................................... 437
13.2.1 Frequency Control Device Design Considerations.......................................437
13.2.2 Frequency Control Component Types....................................................... 437
13.3 Crystal Support ...............................................................................................439
13.3.1 Crystal Selection Parameters..................................................................439
13.3.2 Crystal Placement and Layout Recommendations ......................................442
13.4 Oscillator Support ............................................................................................443
13.4.1 Oscillator Placement and Layout Recommendations ...................................445
13.5 Ethernet Interface ...........................................................................................446
13.5.1 Magnetics for 1000 BASE-T ....................................................................446
13.5.2 Magnetics Module Qualification Steps ......................................................446
13.5.3 Third-Party Magnetics Manufacturers.......................................................446
13.5.4 Designing the 82574 as a 10/100 Mb/s Only Device ..................................447
13.5.5 Layout Considerations for the Ethernet Interface.......................................448
13.5.6 Physical Layer Conformance Testing........................................................ 454
13.5.7 Troubleshooting Common Physical Layout Issues ...................................... 454
13.6 SMBus and NC-SI ............................................................................................455
13.6.1 NC-SI Electrical Interface Requirements...................................................456
13.7 82574L Power Supplies.....................................................................................460
13.7.1 82574 GbE Controller Power Sequencing.................................................. 460
13.7.2 Power and Ground Planes ......................................................................462
13.8 Device Disable................................................................................................. 462
13.8.1 BIOS Handling of Device Disable............................................................. 463
13.9 82574L Exposed Pad* ......................................................................................463
13.9.1 Introduction.........................................................................................463
13.9.2 Component Pad, Solder Mask and Solder Paste......................................... 464
13.9.3 Landing Pattern A (No Via In Pad)...........................................................465
13.9.4 Landing Pattern B (Thermal Relief; No Via In Pad).....................................466
13.10 Assembly Process Flow .....................................................................................467
13.11 Reflow Guidelines ............................................................................................467
13.12 XOR Testing.................................................................................................... 469
14.0 Thermal Design Considerations..............................................................................472
14.1 Introduction....................................................................................................472
14.2 Intended Audience ...........................................................................................472
14.3 Measuring the Thermal Conditions .....................................................................472
14.4 Thermal Considerations ....................................................................................472
14.5 Packaging Terminology.....................................................................................473
14.6 Product Package Thermal Specification ............................................................... 473
14.7 Thermal Specifications......................................................................................474
14.7.1 Case Temperature ................................................................................474
14.7.2 Designing for Thermal Performance......................................................... 474
14.8 Thermal Attributes...........................................................................................475
14.8.1 Typical System Definitions .....................................................................475
14.9 82574L Package Thermal Characteristics............................................................. 476
14.10 Reliability .......................................................................................................476
14.11 Measurements for Thermal Specifications............................................................477
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Datasheet—82574 GbE Controller
14.12 Case Temperature Measurements...................................................................... 477
14.12.1Attaching the Thermocouple .................................................................. 478
14.13 Conclusion ..................................................................................................... 478
14.14 PCB Guidelines................................................................................................ 479
15.0 Board Layout and Schematic Checklists ................................................................. 480
16.0 Models................................................................................................................... 490
17.0 Reference Schematics ........................................................................................... 492
82574 GbE Controller—Datasheet
10
Revision History
Date Revision Description
February 2013 3.3
• Added PXE VLAN Configuration Pointer (0x003C) bit descriptions; Section 6.
• Updated section 9.1.6.1.7 - Link CAP, Offset 0xEC, (RO); bit 11:10 descriptions.
• Updated section 8.6.1 (Transmit Errors in Sequence Handling); (changed “F and L flags off” to “F and L flags on” in the
note after table 59.
June 2012 3.2
• Revised table 36 - NVM Map of Address Range 0x00-0x3F (Word 0x05).
• Revised section 15.0 - Board Layout and Schematic Checklists (Magnetics, both discrete and integrated).
• Revised section 10.2.5.11 - Receive Descriptor Control - RXDCTL (0x02828 + n*0x100[n=0..1]; RW).
January 2012 3.1
• Updated section 10.2.2.1 (removed footnote for bit ASDE).
• Updated section 10.2.6.11 (changed bit 22 value to 1b).
• Updated section 10.2.1 (changed packet buffer memory to 0x19FFF).
• Updated section 10.2.12.12 (Rx and Tx FIFO values).
• Revised Table 68 (Optional NC-SI Features Support).
• Revised Table 26 (Compatible EEPROM Parts).
• Removed the footnote reference from section 10.2.2.3 (EEPROM/FLASH control Register; bit 23).
February 2011 3.0
• Revised section 14.6 “Product Package Thermal Specification” (added a Psi JT note after table 94).
• Revised section 6.1.1.16 (PCIe Init Configuration 3 Word (Word 0x1A); bits 3:2).
• Revised section 9.1.6.1.7 (Link CAP, Offset 0xEC, (RO); bits 11:10).
January 2011 2.9
• Updated section 6 to reflect latest NVM dev start image.
• Updated section 8.8.1.3 (CBDM bit description).
• Updated section 8.8.1.6 (MAC Filters description).
• Updated section 8.8.2.2 (status data byte 1 bit 4 name changed to reserved).
• Updated section 8.8.2.5 (MAC Filters description).
• Updated section 13.5.5.3.
• Removed section 13.5.5.7.1 (Signal Detect).
• Changed support of up to 256 KB TCP segmentation (TSO v2) to 64 KB.
• Removed note from section 14.6.
• Added new section 13.10 (Assembly Process Flow).
• Added supported Flash devices under Table 25.
• Revised section 4.6.2 (MDIO and NVM Semaphore).
• Revised table 51 (MAC Address Functionality).
• Revised table 64 (bit 4 is now a reserved bit).
• Revised section 10.2.2.5 (bits 7:5 descriptions).
• Revised section 10.2.3.11 (bits 1:0 descriptions).
• Revised section 13.5.5.3 (Layer 1 signal layer).
• Revised section 13.8 (Device Disable).
• Revised section 14 (removed heat sink information).
• Revised section 3.3.2 (Supported NVM Devices).
• Added new sections 12.6 (Flash AC specifications) and 12.7 (EEPROM AC specifications).
January 2010 2.8
• Updated section 7.1.11.3 (IPv6 table).
• Updated section 12.7 “Oscillator/Crystal Specifications” (added Cload note).
• Updated section 13.3.1.6 “Load Capacitance and Discrete Capacitors” (new crystal load capacitance formula).
• Updated table 97 (Cload value).
October 2009 2.7
• Changed the pull-up value of AUX_PWR from 1 KΩ to 10 KΩ. in the schematic checklist.
• Changed “calibration load” to “Cload” in the schematic checklist.
• Updated Section 8 “System Manageability”.
August 2009 2.6
• Removed section 8.9.4.1.
• Updated section 13.3.1.6.
• Removed reference schematics.
April 2009 2.5 • Updated sections 4.5.2, 7.1, 10.2.2.15, 12.6, 13.5.1, and 13.5.5.4.
February 2009 2.4 • Updated sections 6.3.1.3, 10.2.3.11, and 10.2.8.8.
• Updated table 66.
December 2008 2.3
• Added section 8.12.2.3 - Set Intel Management Control Formats.
• Added section 8.12.3.4 - Get Intel Management Control Formats.
• Added section 10.2.3.12 - 3GPIO Control Register 2 - GCR2.
• Updated section 13.1.4 - PCIe Routing.
• Updated section 13.10 - Added “The XOR tree is output on the LED1 pin”.
• Updated table 97 - Schematic Checklist.
October 2008 2.2 • Changed PCIe Rev. 2.0 (2.5 GHz) x1 to PCIe Rev. 1.1 (2.5 GHz) x1 in Section 1.0.
• Added multi-drop application connectivity requirements to Section 13.6.1.2.
August 2008 2.1
• Updated title page - changed packet buffer size from 32 KB to 40 KB.
• Updated section 15 - corrected NC-SI schematic checklist information.
• Updated reference schematics - corrected NC-SI schematic information.
June 2008 2.0 Initial public release.
February 2008 1.7
• Updated section 5.2.
• Added a note to Table 31.
• Updated section 13.5.5.13.
• Added 82574IT ordering information.
February 2008 1.6 • Quick fix provided which added Measured Power Consumption (Section 5.2). This is a temporary patch. Note that the fix
does not appear in the TOC or list of tables yet. This will be corrected next week.
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Datasheet—82574 GbE Controller
January 2008 1.5
• Changed section 10.2.2.2 bit 31 assignment from 1b to 0b.
• Changed word 0x0F bit 7 bit assignment (1b to 0b).
• Added new Section 14 “Thermal Design Considerations”.
• Updated MNG Mode description (loads from NVM work 0xF instead of word 10.
• Updated the 82574L Resets table.
• Added note “The 82574L requests I/O resources to support pre-boot operation (prior to the allocation of physical
memory base addresses”.
• Updated CAP Offset 0xE4 bit 15 description.
• Updated default values for Uncorrectable Error Severity and Correctable Error Mask registers.
• Updated Figure 52.
• Updated VALUE1 and VALUE2 byte numbers in Section 10.2.8.19.
• Changed crystal drive level to 300 μW.
• Changed all 1.0 V dc references to 1.05 V dc.
• Changed all 1.8 V dc references to 1.9 V dc.
• Deleted “Default value of 0x5F20 and 0x5F28 are loaded from the NVM at power up" from the FFLT register description.
• Added a note for EITR that in 10/100 Mb/s mode, the interval time is multiplied by four.
• Updated the type and internal/external PU/PD for NC-SI pins.
• Updated the NVMT pinout description.
• Updated MNG_Mode to be loaded from NVM word 0x0F (instead of NVM word 0x10).
• Updated default values for Uncorrectable Error Severity and Correctable Error Mask registers.
• Updated section 9.1.6.1.7. Where applicable, changed milliseconds to micro seconds (bits 14:12 and 17:15).
• Removed WUPL register information.
• Noted that manageability can be supported with a 32 Kb EEPROM.
November 2007 1.1 • Updated NVMT symbol description in Section 2.3.4, Table 10.
October 2007 1.0 • Updated Sections 2, 3, 4, 5, 9, 12, and 13; as indicated by the change bars in the left margin.
August 2007 0.7 • Updated Sections 2, 3, 5, 6, 8, 10, and 12.
• Added Sections 13, 14, 15, and 16.
July 2007 0.6 • Added Section 12.0 “Electrical Specifications”.
• Updated Section 2.0 “Pin Interface”.
June 2007 0.5 Initial release (Intel Confidential).
Date Revision Description
82574 GbE Controller—Datasheet
12
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13
Datasheet—82574 GbE Controller
82574 GbE Controller—Introduction
12
1.0 Introduction
The 82574 family (82574L and 82574IT) are single, compact, low power components
that offer a fully-integrated Gigabit Ethernet Media Access Control (MAC) and Physical
Layer (PHY) port. The 82574L uses the PCI Express* (PCIe*) architecture and provides
a single-port implementation in a relatively small area so it can be used for server and
client configurations as a LAN on Motherboard (LOM) design. The 82574 family can also
be used in embedded applications such as switch add-on cards and network appliances.
External interfaces provided on the 82574:
• PCIe Rev. 1.1 (2.5 GHz) x1
• MDI (Copper) standard IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE-
TX, and 10BASE-T applications (802.3, 802.3u, and 802.3ab)
• NC-SI or SMBus connection to a Manageability Controller (MC)
• IEEE 1149.1 JTAG (note that BSDL testing is NOT supported)
Additional product details:
• 9 mm x 9 mm 64-pin QFN package
• Support for PCI 3.0 Vital Product Data (VPD)
• IPMI MC pass through; multi-drop NC-SI
• TimeSync offload compliant with 802.1as specification
1.1 Scope
This document presents the architecture (including device operation, pin descriptions,
register definitions, etc.) for the 82574. This document is intended to be a reference for
software device driver developers, board designers, test engineers, or others who
might need specific technical or programming information about the 82574.
1.2 Number Conventions
Unless otherwise specified, numbers are represented as follows:
• Hexadecimal numbers are identified by an "0x" suffix on the number (0x2A, 0x12).
• Binary numbers are identified by a "b" suffix on the number (0011b). However,
values for SMBus transactions in diagrams are listed in binary without the "b" or in
hexadecimal without the "0x".
Any other numbers without a suffix are intended as decimal numbers.
13
Introduction—82574 GbE Controller
1.3 Acronyms
Following are a list of acronyms that are used throughout this document.
Acronym Definition
ACK Acknowledge.
ARA SMBus Alert Response Address.
ARP Address Resolution Protocol.
ASF Alert Standard Format. The manageability protocol specification defined by the DMTF.
MC Manageability Controller. The general name for an external TCO controller, relevant
only in TCO mode.
CSR Control and Status Register. Usually refers to a hardware register.
DHCP Dynamic Host Configuration Protocol. A TCP/IP protocol that enables a client to
receive a temporary IP address over the network from a remote server.
DMTF The international organization responsible for managing and maintaining the ASF
specification.
IEEE Institute of Electrical and Electronics Engineers.
IP Internet Protocol. The protocol within TCP/IP that governs the breakup and
reassembly of data messages into packets and the packet routing within the network.
IP Address The 4-byte or 16-byte address that designates the Ethernet controller within the IP
communication protocol. This address is dynamic and can be updated frequently
during runtime.
IPMI Intelligent Platform Management Interface Specification.
LAN Local Area Network. Also known as the Ethernet.
MAC Address The 6-byte address that designates Ethernet controller within the Ethernet protocol.
This address is constant and unique per Ethernet controller.
NA Not Applicable.
NACK Not Acknowledged.
NC-SI Network Controller Sideband Interface. New DMTF industry standard sideband
interface.
NIC Network Interface Card. Generic name for a Ethernet controller that resides on a
Printed Circuit Board (PCB).
OS Operating System. Usually designates the PC system’s software.
PEC The SMBus checksum signature, sent at the end of an SMBus packet. An SMBus
device can be configured either to require or not require this signature.
PET Platform Event Trap.
PT Pass-Through. Also known as TCO mode.
PSA SMBus Persistent Slave Address device. In the SMBus 2.0 specification, this
designates an SMBus device whose address is stored in non-volatile memory.
RMCP Remote Management and Control Protocol.
RSP RMCP Security Extensions Protocol.
SA Security Association.
82574 GbE Controller—Introduction
14
1.4 Reference Documents
Other reference documents include:
• Intel® 82574 Family GbE Controller Specification Update, Intel Corporation.
• PCI Express* Specification v2.0 (2.5 GT/s)
• Advanced Configuration and Power Interface Specification
• PCI Bus Power Management Interface Specification
SMBus System Management Bus.
SNMP Simple Network Management Protocol.
TCO Total Cost of Ownership.
TBD To Be Defined.
Acronym Definition
Document Name Version Owner Location
SMBus
Specification 2.0 SBS Forum http://www.smbus.org/
I2C Specification 2.1 Phillips
Semiconductors http://www.philipslogic.com/
NC-SI
Specification 1.0 DMTF http://www.dmtf.org/
Search for NC-SI.
15
Introduction—82574 GbE Controller
1.5 82574L Architecture Block Diagram
Figure 1 shows a high-level architecture block diagram for the 82574.
Figure 1. 82574L Architecture Block Diagram
1.6 System Interface
The 82574L provides one PCIe lane operating at 2.5 GHz with sufficient bandwidth to
support 1000 Mb/s transfer rate. 40 KB of on-chip buffering mitigates instantaneous
receive bandwidth demands and eliminates transmit under–runs by buffering the entire
outgoing packet prior to transmission.
1.7 Features Summary
This section describes the 82574’s features that were present in previous Intel client
GbE controllers and those features that are new to the 82574.
PCIe I/F
Rx/Tx DMA
Rx/Tx FIFO
Transmit
Switch Filter
MAC
PHY
RMII I/F
SMBus
I/F
NC-SI
Rx/Tx FIFO
RMII SMBus PCIe
Link
82574 GbE Controller—Introduction
16
Table 1. Network Features
Table 2. Host Interface Features
Feature 82574L Zoar
Compliant with the 1 Gb/s Ethernet 802.3
802.3u 802.3ab specifications YY
Multi-speed operation: 10/100/1000 Mb/s Y Y
Full-duplex operation at 10/100/1000 Mb/s Y Y
Half-duplex operation at 10/100 Mb/s Y Y
Flow control support compliant with the 802.3X
specification YY
VLAN support compliant with the 802.3q
specification YY
MAC address filters: perfect match unicast
filters; multicast hash filtering, broadcast filter
and promiscuous mode YY
Configurable LED operation for OEM
customization of LED displays YY
Statistics for management and RMON Y Y
MAC loopback Y Y
Feature 82574L Zoar
PCIe interface to chipset Y Y
64-bit address master support for systems using
more than 4 GB of physical memory YY
Programmable host memory receive buffers (256
bytes to 16 KB) YY
Intelligent interrupt generation features to
enhance software device driver performance YY
Descriptor ring management hardware for
transmit and receive YY
Software controlled reset (resets everything
except the configuration space) YY
Message Signaled Interrupts (MSI) Y Y
MSI-X Y N
17
Introduction—82574 GbE Controller
Table 3. Manageability Features
Table 4. Performance Features
Table 5. Power Management Features
Feature 82574L Zoar
NC-SI over RMII for remote management core Y N
SMBus advanced pass through Y N
Feature 82574L Zoar
Configurable receive and transmit data FIFO;
programmable in 1 KB increments YY
TCP segmentation capability compatible with NT
5.x TCP Segmentation Offload (TSO) features YY
Supports up to 64 KB TSO (TSO v2) Y N
Fragmented UDP checksum offload for packet re-
assembly YY
IPv4 and IPv6 checksum offload support (receive,
transmit, and TSO) YY
Split header support Y Y
Receive Side Scaling (RSS) with two hardware
receive queues YN
Supports 9018-byte jumbo packets Y Y
Packet buffer size 40 KB 32 KB
TimeSync offload compliant with 802.1as
specification YN
Feature 82574L Zoar
Magic packet wake-up enable with unique MAC
address YY
ACPI register set and power down functionality
supporting D0 and D3 states YY
Full wake-up support (APM and ACPI 2.0) Y Y
Smart power down at S0 no link and Sx no link Y Y
LAN disable functionality Y Y
82574 GbE Controller—Introduction
18
1.8 Product Codes
Table 6 lists the product ordering codes for the 82574 family.
Table 6. Product Ordering Codes
Part Number Product Name Description
WG82574L Intel® 82574L Gigabit Network
Connection
• Embedded and Entry Server GbE LAN.
• Operates using a standard temperature
range (0 °C to 85 °C).
WG82574IT Intel® 82574IT Gigabit Network
Connection
• Embedded and Entry Server GbE LAN.
• Operates using a wider temperature
range (-40 °C to 85 °C).
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Introduction—82574 GbE Controller
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82574 GbE Controller—Pin Interface
20
2.0 Pin Interface
2.1 Pin Assignments
The 82574L supports a 64-pin, 9 x 9 QFN package with an Exposed Pad* (e-Pad*).
Note that the e-Pad is ground.
Figure 2. 82574L 64-Pin, 9 x 9 QFN Package With e-Pad
CTRL19
AVDD3p3/VDD3p3
NC_SI_CLK_IN
NC_SI_CRS_DV
VDD1p0
NC_SI_RXD1
NC_SI_RXD0
NC_SI_TX_EN
NC_SI_TXD1
NC_SI_TXD0
VDD3p3
VDD1p0
NVM_SI
NVM_SK
NVM_SO
NVM_CS_N
RSET
AVDD1p9
CTRL10
AVDD1p9
SMB_DAT
NVMT/JTAG_TMS
DIS_REG10
AUX_PWR/JTAG_TCK
VDD1p0
VDD1p9
JTAG_TDI
XTAL1
ATEST_N
AVDD1p9
MDI_MINUS[0]
MDI_PLUS[0]
MDI_MINUS[1]
MDI_PLUS[1]
MDI_MINUS[2]
MDI_PLUS[2]
MDI_MINUS[3]
MDI_PLUS[3]
AVDD1p9
AVDD1p9
12345678910111213141516
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
3334353637383940
41
42
43444546
4748
49
51
50
52
53
54
55
56
57
58
59
60
61
62
63
64
LED2
ATEST_P
AVDD1p9
XTAL2
VDD1p0
SMB_CLK
SMB_ALRT_N
PE_WAKE_N/JTAG_TDO
LED0
LED1
VDD3p3
PE_Tp
AVDD1p9
PE_Rn
PE_Rp
PECLKn
PECLKp
VDD1p0
DEV_OFF_N
TEST_EN
PE_RST_N
VDD1p0
PE_Tn
82574
64 Pin QFN
9 mm x 9 mm
0.5 mm pin pitch
with Exposed Pad*
VDD1p0
21
Pin Interface—82574 GbE Controller
2.2 Pull-Up/Pull-Down Resistors and Strapping Options
• As stated in the Name and Function table columns, the internal Pull-Up/Pull-Down
(PU/PD) resistor values are 30 KΩ ± 50%.
• Only relevant (digital) pins are listed; analog or bias and power pins have specific
considerations listed in Section 12.0.
• NVMT and AUX_PWR are used for a static configuration. They are sampled while
PE_RST_N is active and latched when PE_RST_N is deasserted. At other times,
they revert to their standard usage.
2.3 Signal Type Definition
2.3.1 PCIe
In Input is a standard input-only signal.
Out (O) Totem pole output is a standard active driver.
T/s Tri-State is a bi-directional, tri-state input/output pin.
S/t/s
Sustained tri-state is an active low tri-state signal owned and driven by one and only one agent
at a time. The agent that drives an s/t/s pin low must drive it high for at least one clock before
letting it float. A new agent cannot start driving an s/t/s signal any sooner than one clock after
the previous owner tri-states it.
O/d Open drain enables multiple devices to share as a wire-OR.
A-in Analog input signals.
A-out Analog output signals.
B Input bias.
NC-SI_in NC-SI input signal.
NC-SI_out NC-SI output signal
Table 7. PCIe
Symbol Lead # Type Op
Mode Name and Function
PECLKp
PECLKn
26
25 A-in Input
PCIe Differential Reference Clock In
This pin receives a 100 MHz differential clock input. This clock
is used as the reference clock for the PCIe Tx/Rx circuitry and
by the PCIe core PLL to generate a 125 MHz clock and 250
MHz clock for the PCIe core logic.
PE_Tp
PE_Tn 21
20 A-out Output
PCIe Serial Data Output
Serial differential output link in the PCIe interface running at
2.5 Gb/s. This output carries both data and an embedded 2.5
GHz clock that is recovered along with data at the receiving
end.
82574 GbE Controller—Pin Interface
22
2.3.2 NVM Port
PE_Rp
PE_Rn
24
23 A-in Input
PCIe Serial Data Input
Serial differential input link in the PCIe interface running at
2.5 Gb/s. The embedded clock present in this input is
recovered along with the data.
PE_WAKE_N/
JTAG_TDO 16 O/d Output
Wake
The 82574L drives this signal to zero when it detects a wake-
up event and either:
• The PME_en bit in PMCSR is 1b or
• The APME bit of the Wake Up Control (WUC) register is
1b.
JTAG TDO Output.
PE_RST_N 17 In Input
Power and Clock Good Indication
The PE_RST_N signal indicates that both PCIe power and
clock are available.
Table 8. NVM Port
Symbol Lead # Type Op
Mode Name and Function
NVM_SI 12 T/s Output
Serial Data Output
Connect this lead to the input of the Non-Volatile Memory
(NVM).
Note: The NVM_SI port pin includes an internal pull-up
resistor.
NVM_SO 14 T/s Input
Serial Data Input
Connect this lead to the output of the NVM.
Note: The NVM_SO port pin includes an internal pull-up
resistor.
NVM_SK 13 T/s Output
Non-Volatile Memory Serial Clock
Note: The NVM_SK port pin includes an internal pull-up
resistor.
NVM_CS_N 15 T/s Output
Non-Volatile Memory Chip Select Output
Note: The NVM_CS port pin includes an internal pull-up
resistor.
Table 7. PCIe
Symbol Lead # Type Op
Mode Name and Function
23
Pin Interface—82574 GbE Controller
2.3.3 System Management Bus (SMBus) Interface
Note: If the SMBus is disconnected, an external pull-up should be used for these pins, unless
it is guaranteed that manageability is disabled in the 82574.
2.3.4 NC-SI and Testability
Table 9. SMBus Interface
Symbol Lead # Type Op Mode Name and Function
SMB_DAT 36 T/s, o/d Bi-dir
SMBus Data
Stable during the high period of the clock (unless it
is a start or stop condition).
SMB_CLK 34 T/s, o/d Bi-dir
SMBus Clock
One clock pulse is generated for each data bit
transferred.
SMB_ALRT_N 35 T/s, o/d Output
SMBus Alert
Acts as an interrupt pin of a slave device on the
SMBus in pass-through mode.
Table 10. NC-SI and Testability
Symbol Lead # Type Op
Mode Name and Function
NC_SI_CLK_IN 2 NC-SI_
in Input
NC-SI Reference Clock Input
Synchronous clock reference for receive, transmit, and control
interface. This signal is a 50 MHz clock +/- 50 ppm.
Note: If not used, should have an external pull-down resistor.
Also, this clock is in addition to and separate from the XTAL
clock.
NC_SI_CRS_DV 3 NC-SI_
out Output NC-SI Carrier Sense/Receive Data Valid (CRS/DV).
NC_SI_RXD0 6 NC-SI_
out Output NC-SI Receive Data 0
Data signals to the Manageability Controller (MC).
NC_SI_RXD1 5 NC-SI_
out Output NC-SI Receive Data 1
Data signals to the MC.
NC_SI_TX_EN 7 NC-SI_
in Input NC-SI Transmit Enable
Note: If not used, should have an external pull-down resistor.
NC_SI_TXD0 9 NC-SI_
in Input
NC-SI Transmit Data 0
Data signals from the MC
Note: If not used, should have an external pull-up resistor.
NC_SI_TXD1 8 NC-SI_
in Input
NC-SI Transmit Data 1
Data signal from the MC
Note: If not used, should have an external pull-up resistor.
TEST_EN 29 In Input
Enables Test Mode
Test pins are overloaded on the functional signals as described
in the pin description text of this section. The pin is active
high.
Note: This pin should be externally pulled down for normal
operation.
82574 GbE Controller—Pin Interface
24
2.3.5 LEDs
Table 1 1 lists the functionality of each LED output pin. The default activity of each LED
can be modified in the NVM. The LED functionality is reflected and can be further
modified in the configuration registers (LEDCTL).
2.3.6 PHY Pins
Note: The 82574L has built in termination resistors. As a result, external termination resistors
should not be used.
AUX_PWR/
JTAG_TCK 39 In Input
Auxiliary Power Indication.
AUX_PWR is supported when sampled high and should be
connected using a resistor
JTAG Clock Input
Note: The AUX_PWR/JTAG_TCK port pin includes an internal
pull-down resistor.
NVMT/JTAG_TMS 38 In Input
NVM Type
The NVM is Flash when sampled LOW and EEPROM when
sampled HIGH.
JTAG TMS Input.
Note: The NVMT/JTAG_TMS port pin includes an internal pull-
up resistor. Also note that the internal pull-up is disconnected
during startup. As a result, NVMT MUST be connected
externally.
JTAG_TDI 40 In Input
JTAG TDI Input
Note: The JTAG_TDI port pin includes an internal pull-up
resistor.
Table 10. NC-SI and Testability
Symbol Lead # Type Op
Mode Name and Function
Table 11. LEDs
Symbol Lead # Type Op
Mode Name and Function
LED0 31 Out Output LED0
Programmable LED.
LED1 30 Out Output LED1
Programmable LED.
LED2 33 Out Output LED2
Programmable LED.
25
Pin Interface—82574 GbE Controller
2.3.7 Miscellaneous Pin
Table 12. PHY Pins
Symbol Lead # Type Op
Mode Name and Function
MDI_PLUS[0]
MDI_MINUS[0] 58
57 ABi-dir
Media Dependent Interface[0]:
1000BASE-T:
In MDI configuration, MDI[0]+/-corresponds to BI_DA+/-
and in MDI-X configuration MDI[0]+/- corresponds to
BI_DB+/-.
100BASE-TX:
In MDI configuration, MDI[0]+/- is used for the transmit
pair and in MDIX configuration MDI[0]+/- is used for the
receive pair.
10BASE-T:
In MDI configuration, MDI[0]+/- is used for the transmit
pair and in MDI-X configuration MDI[0]+/- is used for the
receive pair.
MDI_PLUS[1]
MDI_MINUS[1] 55
54 ABi-dir
Media Dependent Interface[1]:
1000BASE-T:
In MDI configuration, MDI[1]+/- corresponds to BI_DB+/-
and in MDI-X configuration MDI[1]+/- corresponds to
BI_DA+/-.
100BASE-TX:
In MDI configuration, MDI[1]+/- is used for the receive
pair and in MDI-X configuration MDI[1]+/- is used for the
transmit pair.
10BASE-T:
In MDI configuration, MDI[1]+/- is used for the receive
pair and in MDI-X configuration MDI[1]+/- is used for the
transmit pair.
MDI_PLUS[2]
MDI_MINUS[2]
MDI_PLUS[3]
MDI_MINUS[3]
53
52
50
49
ABi-dir
Media Dependent Interface[3:2]:
1000BASE-T:
In MDI and in MDI-X configuration, MDI[2]+/-
corresponds to BI_DC+/- and MDI[3]+/- corresponds to
BI_DD+/-.
100BASE-TX: Unused.
10BASE-T:Unused.
XTAL1
XTAL2 43
42
A-In
A-Out
Input/
Output
XTAL In/Out
These pins can be driven by an external 25 MHz crystal or
driven by an external MOS level 25 MHz oscillator. Used to
drive the PHY.
ATEST_P
ATEST_N 45
46 A-out Output Positive side of the high speed differential debug port for
the PHY.
RSET 48 A Bias
PHY Termination
This pin should be connected through a 4.99 KΩ +-1%
resister to ground.
Table 13. Miscellaneous Pin
Symbol Lead # Type Op
Mode Name and Function
DEV_OFF_N 28 In Input This is a 3.3 V dc input signal. Asserting DEV_OFF_N
puts the 82574 in device disable mode. Note that this
pin is asynchronous.
82574 GbE Controller—Pin Interface
26
2.3.8 Power Supplies and Support Pins
2.3.8.1 Power Support
2.3.8.2 Power Supply
Table 14. Power Support
Symbol Lead # Type /
Voltage Name and Function
CTRL10 62 A-out 1.05 V dc Control
Voltage control for an external 1.05 V dc PNP.
CTRL19 64 A-out 1.9 V dc Control
Voltage control for an external 1.9 V dc PNP.
DIS_REG10 59 A-in
Disable 1.05 V dc Regulator
When high, the internal 1.05 V dc regulator is disabled and the
CTRL10 signal is active. When low, the internal 1.05 V dc
regulator is enabled using its internal power transistor. In this
case, the CTRL10 signal is inactive.
Table 15. Power Supply
Symbol Lead # Type /
Voltage Name and Function
VDD1p0 4, 11, 18, 27,
37, 41, 60 1.05 V
dc 1.05 V dc power supply (7).
AVDD1p9 22, 44, 47,
51, 56, 61, 63 1.9 V dc 1.9 V dc power supply (7).
VDD3p3 10, 32 3.3 V dc 3.3 V dc power supply (2).
AVDD3p3/
VDD3p3 1 3.3 V dc 3.3 V dc power supply (1).
VDD1p9 19 1.9 V dc Fuse voltage for programming on-die fuses. Connect to 1.9 V dc for
normal operation.
GND e-Pad Ground The e-Pad metal connection on the bottom of the package. Should be
connected to ground.
82574 GbE Controller—Interconnects
28
3.0 Interconnects
3.1 PCIe
PCIe is a third generation I/O architecture that enables cost competitive, next
generation I/O solutions providing industry leading price/performance and feature
richness. It is an industry-driven specification.
PCIe defines a basic set of requirements that comprehends the majority of the targeted
application classes. High-end application requirements such as Enterprise class servers
and high-end communication platforms are delivered by a set of advanced extensions
that compliment the baseline requirements.
To guarantee headroom for future applications of PCIe, a software-managed
mechanism for introducing new, enhanced capabilities in the platform is provided.
Figure 4 shows the PCIe architecture.
Figure 4. PCIe Stack Structure
The PCIe physical layer consists of a differential transmit pair and a differential receive
pair. Full-duplex data on these two point-to-point connections is self-clocked such that
no dedicated clock signals are required.
Note: The bandwidth of this interface increases linearly with frequency.
2.5+
2.5+ Gb
Gb/s
/s
Configurable widths 1 .. 32
Configurable widths 1 .. 32
Preserve Driver Model
Config/OS
S/W
Protocol
Link
Physical
Common Base Protocol
Common Base Protocol
Advanced
Advanced Xtensions
Xtensions
Physical
(electrical
Mechanical)
Point to point, serial, differential,
Point to point, serial, differential,
hot
hot-
-plug, inter
plug, inter-
-op
op formfactors
formfactors
PCI Compliant Block
29
Interconnects—82574 GbE Controller
A packet is the fundamental unit of information exchange and the protocol includes a
message space to replace the number of side-band signals found on many of today’s
buses. This movement of hard-wired signals from the physical layer to messages within
the transaction layer enables easy and linear physical layer width expansion for
increased bandwidth.
The common base protocol uses split transactions along with several mechanisms that
are included to eliminate wait states and to optimize the reordering of transactions to
further improve system performance.
3.1.1 Architecture, Transaction, and Link Layer Properties
• Split transaction, packet-based protocol
• Common flat address space for load/store access (such as a PCI addressing
model):
— Memory address space of 32 bits to enable compact packet header (must be
used to access addresses below 4 GB)
— Memory address space of 64 bits using extended packet header
• Transaction layer mechanisms:
— PCI-X style relaxed ordering
— Optimizations for no-snoop transactions
• Credit-based flow control
• Packet sizes/formats:
— Maximum packet size supports 128- and 256-byte data payload
— Maximum read request size of 4 KB
• Reset/initialization:
— Frequency/width/profile negotiation performed by hardware
• Data integrity support:
— Using CRC-32 for transaction layer packets
• Link layer retry for recovery following error detection:
— Using CRC-16 for link layer messages
• No retry following error detection:
— 8b/10b encoding with running disparity
• Software configuration mechanism:
— Uses PCI configuration and bus enumeration model
— PCIe-specific configuration registers mapped via PCI extended capability
mechanism
• Baseline messaging:
— In-band messaging of formerly side-band legacy signals (such as interrupts)
— System-level power management supported via messages
• Power Management (PM):
— Full PCI PM support
— Wake capability from D3cold state
— Compliant with ACPI 2.0, PCI PM software model
— Active state power management (transparent to software including ACPI)
82574 GbE Controller—Interconnects
30
3.1.1.1 Physical Interface Properties
• Point to point interconnect
— Full-duplex; no arbitration
• Signaling technology:
— Low voltage differential
— Embedded clock signaling using 8b/10b encoding scheme
• Serial frequency of operation: 2.5 GHz.
• Interface width of one lane per direction
• DFT and DFM support for high volume manufacturing
3.1.1.2 Advanced Extensions
PCIe defines a set of optional features to enhance platform capabilities for specific
usage modes. The 82574L supports the following optional features:
• Extended error reporting – messaging support to communicate multiple types/
severity of errors
• Serial number
3.1.2 General Functionality
• Native/legacy:
— The PCIe capability register states the device/port type.
— The 82574L is a native device by default.
• Locked transactions:
— The 82574L does not support locked requests as a target or master.
• End to End CRC (ECRC):
— Not supported by the 82574
3.1.3 Transaction Layer
The upper layer of the PCIe architecture is the transaction layer. The transaction layer
connects to the 82574’s core using an implementation-specific protocol. Through this
core-to-transaction-layer protocol, the application-specific parts of the 82574 interact
with the PCIe subsystem and transmit and receive requests to or from the remote PCIe
agent, respectively.
3.1.3.1 Transaction Types Received by the Transaction Layer
Table 16. Transaction Types at the Rx Transaction Layer
Transaction Type FC Type Tx Later
Reaction
Hardware Should Keep
Data From Original Packet For Client
Configuration Read
Request NPH CPLH + CPLD Requester ID, TAG, Attribute Configuration space
Configuration Write
Request NPH +
NPD CPLH Requester ID, TAG, Attribute Configuration space
Memory Read
Request NPH CPLH + CPLD Requester ID, TAG, Attribute CSR
31
Interconnects—82574 GbE Controller
Flow control types:
• PH - Posted request headers
• PD - Posted request data payload
• NPH - Non-posted request headers
• NPD - Non-posted request data payload
• CPLH - Completion headers
• CPLD - Completion data payload
3.1.3.2 Transaction Types Initiated by The 82574L
Table 17. Transaction Types at the Tx Transaction Layer
3.1.3.3 Message Handling by The 82574L (as a Receiver)
Message packets are special packets that carry a message code.
The upstream device transmits special messages to the 82574 by using this
mechanism.
The transaction layer decodes the message code and responds to the message
accordingly.
Memory Write
Request
PH +
PD - - CSR
I/O Read Request NPH CPLH + CPLD Requester ID, TAG, Attribute CSR
I/O Write Request NPH +
NPD CPLH Requester ID, TAG, Attribute CSR
Read Completions CPLH +
CPLD -- DMA
Message PH - - Message Unit / INT / PM
/ Error Unit
Transaction Type FC Type Tx Later
Reaction
Hardware Should Keep
Data From Original Packet For Client
Transaction Type Payload Size FC Type From Client
Configuration Read Request
Completion Dword CPLH + CPLD Configuration space
Configuration Write Request
Completion - CPLH Configuration space
I/O Read Request Completion Dword CPLH + CPLD CSR
I/O Write Request Completion - CPLH CSR
Read Request Completion Dword/Qword CPLH + CPLD CSR
Memory Read Request - NPH DMA
Memory Write Request <= MAX_PAYLOAD_SIZE1
1. The MAX_PAYLOAD_SIZE supported is loaded from the NVM (either 128 bytes or 256 bytes). Effective
MAX_PAYLOAD_SIZE is according to configuration space register.
PH + PD DMA
Message - PH Message Unit / INT /
PM / Error Unit
82574 GbE Controller—Interconnects
32
Table 18. Supported Message in The 82574L (As a Receiver)
3.1.3.4 Message Handling by The 82574L (As a Transmitter)
The transaction layer is also responsible for transmitting specific messages to report
internal/external events (such as interrupts and PMEs).
Table 19. Supported Message in The 82574L (As a Transmitter)
Message
code [7:0]
Routing
r2r1r0 Message Device’s Later Response
0x14 100 PM_Active_State_NAK Internal signal set
0x19 011 PME_Turn_Off Internal signal set
0x41 100 Attention_Indicator_On Silently drop
0x43 100 Attention_Indicator_Blink Silently drop
0x40 100 Attention_Indicator_Off Silently drop
0x45 100 Power_Indicator_On Silently drop
0x47 100 Power_Indicator_Blink Silently drop
0x44 100 Power_Indicator_Off Silently drop
0x50 100 Slot power limit support (has one Dword data) Silently drop
0x7E 010,011,100 Vendor_defined Type 0 no data Unsupported request - NEC*
0x7E 010,011,100 Vendor_defined Type 0 data Unsupported request - NEC*
0x7F 010,011,100 Vendor_defined Type 1 no data Silently drop
0x7F 010,011,100 Vendor_defined Type 1 data Silently drop
0x00 011 Unlock Silently drop
Message
code [7:0]
Routing
r2r1r0 Message
0x20 100 Assert INT A
0x21 100 Assert INT B
0x22 100 Assert INT C
0x23 100 Assert INT D
0x24 100 DE- Assert INT A
0x25 100 DE- Assert INT B
0x26 100 DE- Assert INT C
0x27 100 DE- Assert INT D
0x30 000 ERR_COR
0x31 000 ERR_NONFATAL
0x33 000 ERR_FATAL
0x18 000 PM_PME
0x1B 101 PME_TO_Ack
33
Interconnects—82574 GbE Controller
3.1.3.5 Data Alignment
4 KB Boundary:
Requests must never specify an address/length combination that causes a memory
space access to cross a 4 KB boundary. It is hardware’s responsibility to break requests
into 4 KB-aligned requests (if needed). This does not pose any requirement on
software. However, if software allocates a buffer across a 4 KB boundary, hardware
then issues multiple requests for the buffer. Software should consider aligning buffers
to a 4 KB boundary in cases where it improves performance.
The alignment to the 4 KB boundaries is done in the core. The transaction layer does
not do any alignment according to these boundaries.
64 Bytes:
It is also recommended that requests are multiples of 64 bytes and aligned to make
better use of memory controller resources. This is also done in the core.
3.1.3.6 Configuration Request Retry Status
The 82574L might have a delay in initialization due to an NVM read. The PCIe defined a
mechanism for devices that require completion of a lengthy self-initialization sequence
before being able to service configuration requests.
If the read of the PCIe section in the NVM was not completed before the 82574
received a configuration request, then the 82574 responds with a configuration request
retry completion status to terminate the request, and effectively stalls the configuration
request until such time that the subsystem has completed local initialization and is
ready to communicate with the host.
3.1.3.7 Ordering Rules
The 82574L meets the PCIe ordering rules (PCI-X rules) by following the PCI simple
device model:
• Deadlock avoidance - Master and target accesses are independent - The response
to a target access does not depend on the status of a master request to the bus. If
master requests are blocked (such as due to no credits), target completions can
still proceed (if credits are available).
• Descriptor/data ordering - the 82574 does not proceed with some internal actions
until respective data writes have ended on the PCIe link:
— The 82574L does not update an internal header pointer until the descriptors
that the header pointer relates to are written to the PCIe link.
— The 82574L does not issue a descriptor write until the data that the descriptor
relates to is written to the PCIe link.
The 82574L can issue the following master read request from each of the following
clients:
• Rx descriptor read (one per queue)
• Tx descriptor read (one per queue)
• Tx data read (up to four including one for manageability)
Completed separate read requests are not guaranteed to return in order. Completions
for a single read request are guaranteed to return in address order.
82574 GbE Controller—Interconnects
34
3.1.3.8 Transaction Attributes
3.1.3.8.1 Traffic Class (TC) and Virtual Channels (VC)
The 82574L supports only TC = 0 and VC = 0 (default).
3.1.3.8.2 Relaxed Ordering
The 82574L takes advantage of the relaxed ordering rules in PCIe by setting the
relaxed ordering bit in the packet header. The 82574L also enables the system to
optimize performance in the following cases:
• Relaxed ordering for descriptor and data reads: When the 82574 is a master in a
read transaction, its split completion has no relationship with the writes from the
CPUs (same direction). It should be allowed to bypass the writes from the CPUs.
• Relaxed ordering for receiving data writes: When the 82574 masters receive data
writes, it also enables them to bypass each other in the path to system memory
because the software does not process this data until their associated descriptor
writes have been completed.
• The 82574L cannot perform relax ordering for descriptor writes or an MSI write.
Relaxed ordering can be used in conjunction with the no-snoop attribute to enable the
memory controller to advance non-snoop writes ahead of earlier snooped writes.
Relaxed ordering is enabled in the 82574 by setting the RO_DIS bit to 0b in the
CTRL_EXT register.
3.1.3.8.3 Snoop Not Required
The 82574L sets the Snoop Not Required attribute bit for master data writes. System
logic can provide a separate path into system memory for non-coherent traffic. The
non-coherent path to system memory provides higher, more uniform, bandwidth for
write requests.
The Snoop Not Required attribute bit does not alter transaction ordering. Therefore, to
achieve maximum benefit from snoop not required transactions, it is advisable to set
the relaxed ordering attribute as well (assuming that system logic supports both
attributes).
Software configures no-snoop support through the 82574’s control register and a set of
NONSNOOP bits in the GCR register in the CSR space. The default value for all bits is
disabled.
The 82574L supports a No-Snoop bit for each relevant DMA client:
1. TXDSCR_NOSNOOP - Transmit descriptor read.
2. TXDSCW_NOSNOOP - Transmit descriptor write.
3. TXD_NOSNOOP - Transmit data read.
4. RXDSCR_NOSNOOP - Receive descriptor read.
5. RXDSCW_NOSNOOP - Receive descriptor write.
6. RXD_NOSNOOP - Receive data write.
All PCIe functions in the 82574 are controlled by this register.
35
Interconnects—82574 GbE Controller
3.1.3.9 Error Forwarding
If a Transaction Layer Protocol (TLP) is received with an error-forwarding trailer, the
packet is dropped and not delivered to its destination. The 82574L does not initiate any
additional master requests for that PCI function until it detects an internal reset or
software. Software is able to access device registers after such a fault.
System logic is expected to trigger a system-level interrupt to inform the operating
system of the problem. The operating system can then stop the process associated
with the transaction, re-allocate memory instead of the faulty area, etc.
3.1.3.10 Master Disable
System software can disable master accesses on the PCIe link by either clearing the
PCI Bus Master bit or by bringing the function into a D3 state. From that time on, the
82574 must not issue master accesses for this function. Due to the full-duplex nature
of PCIe, and the pipelined design in the 82574, it might happen that multiple requests
from several functions are pending when the master disable request arrives. The
protocol described in this section insures that a function does not issue master requests
to the PCIe link after its master enable bit is cleared (or after entry to D3 state).
Two configuration bits are provided for the handshake between the device function and
its driver:
•PCIe Master Disable bit in the Device Control (CTRL) register - When the PCIe
Master Disable bit is set, the 82574 blocks new master requests, including
manageability requests. The 82574L then proceeds to issue any pending requests
by this function. This bit is cleared on master reset (Internal Power On Reset all the
way to a software reset) to enable master accesses.
•PCIe Master Enable Status bits in the Device Status register - Cleared by the 82574
when the PCIe Master Disable bit is set and no master requests are pending by the
relevant function, set otherwise.
Software Note:
— The software device driver sets the PCIe Master Disable bit when notified of a
pending master disable (or D3 entry). The 82574L then blocks new requests
and proceeds to issue any pending requests by this function. The software
device driver then polls the PCIe Master Enable Status bit. Once the bit is
cleared, it is guaranteed that no requests are pending from this function. The
software device driver might time out if the PCIe Master Enable Status bit is not
cleared within a given time.
—The PCIe Master Disable bit must be cleared to enable a master request to the
PCIe link. This can be done either through reset or by the software device
driver.
3.1.4 Flow Control
3.1.4.1 Flow Control Rules
The 82574L only implements the default Virtual Channel (VC0). A single set of credits is
maintained for VC0.
82574 GbE Controller—Interconnects
36
Table 20. Allocation of FC Credits
Rules for FC updates:
• The 82574L maintains two credits for NPD at any given time. It increments the
credit by one after the credit is consumed and sends an UpdateFC packet as soon
as possible. UpdateFC packets are scheduled immediately after a resource is
available.
• The 82574L provides two credits for PH (such as for two concurrent target writes)
and two credits for NPH (such as for two concurrent target reads). UpdateFC
packets are scheduled immediately after a resource becomes available.
• The 82574L follows the PCIe recommendations for frequency of UpdateFC FCPs.
3.1.4.2 Upstream Flow Control Tracking
The 82574L issues a master transaction only when the required FC credits are
available. Credits are tracked for posted, non-posted, and completions (the later to
operate against a switch).
3.1.4.3 Flow Control Update Frequency
In any case, UpdateFC packets are scheduled immediately after a resource becomes
available.
When the link is in the L0 or L0s link state, update FCPs for each enabled type of non-
infinite FC credit must be scheduled for transmission at least once every 30 µs (-0%/
+50%), except when the Extended Sync bit of the Control Link register is set, in which
case the limit is 120 µs (-0%/+50%).
3.1.4.4 Flow Control Timeout Mechanism
The 82574L implements the optional FC update timeout mechanism. The mechanism is
activated when the link is in L0 or L0s link state. It uses a timer with a limit of 200 µs (-
0%/+50%), where the timer is reset by the receipt of any init or update FCP.
Alternately, the timer can be reset by the receipt of any DLLP.
After timer expiration, the mechanism instructs the PHY to retrain the link (via the
LTSSM recovery state).
Credit Type Operations Number Of Credits
Posted Request Header (PH) Target write (1 unit)
Message (1 unit) 2 units
Posted Request Data (PD) Target write (Length/16B=1)
Message (1 unit) 16 credits (for 256 bytes)
Non-Posted Request Header (NPH)
Target read (1 unit)
Configuration read (1 unit)
Configuration write (1 unit)
2 units
Non-Posted Request Data (NPD) Configuration write (1 unit) 2 units
Completion Header (CPLH) Read completion (N/A) Infinite (accepted immediately)
Completion Data (CPLD) Read completion (N/A) Infinite (accepted immediately)
37
Interconnects—82574 GbE Controller
3.1.5 Host I/F
3.1.5.1 Tag IDs
PCIe device numbers identify logical devices within the physical device (the 82574 is a
physical device). The 82574L implements a single logical device with one PCI function -
LAN. The device number is captured from each type 0 configuration write transaction.
Each of the PCIe functions interface with the PCIe unit through one or more clients. A
client ID identifies the client and is included in the Tag field of the PCIe packet header.
Completions always carry the tag value included in the request to enable routing of the
completion to the appropriate client.
Client IDs are assigned as follows:
Table 21. Assignment of Client IDs
TAG Code
in Hex Flow: TLP TYPE – Usage
00 RX: WR REQ (data from Ethernet to main memory)
01 RX: RD REQ to read descriptor to core
02 RX: WR REQ to write back descriptor from core to memory
04 TX: RD REQ to read descriptor to core
05 TX: WR REQ to write back descriptor from core to memory
06 TX: RD REQ to read descriptor to core second queue
07 TX: WR REQ to write back descriptor from core to memory (second queue)
08 TX: RD REQ data 0 from main memory to Ethernet
09 TX: RD REQ data 1 from main memory to Ethernet
0A TX: RD REQ data 2 from main memory to Ethernet
0B TX: RD REQ data 3 from main memory to Ethernet
0C RX: RD REQ to bring Descriptor to core second Queue
0E RX: WR REQ to write back descriptor from core to memory (second queue)
10 MNG: RD REQ: Read data
11 MNG: WR REQ: Write data
1E MSI and MSI-X
1F Message unit
Others Reserved
82574 GbE Controller—Interconnects
38
3.1.5.1.1 Completion Timeout Mechanism
In any split transaction protocol, there is a risk associated with the failure of a
requester to receive an expected completion. To enable requesters to attempt recovery
from this situation in a standard manner, the completion timeout mechanism is defined.
• The completion timeout mechanism is activated for each request that requires one
or more completions when the request is transmitted.
• The completion timeout timer should not expire in less than 10 ms.
• The completion timeout timer must expire if a request is not completed in 50 ms.
• A completion timeout is a reported error associated with the requestor device/
function.
A Memory Read Request for which there are multiple completions are considered
completed only when all completions are received by the requester. If some, but not all,
requested data is returned before the completion timeout timer expires, the requestor
is permitted to keep or discard the data that was returned prior to timer expiration.
3.1.5.1.2 Out of Order Completion Handling
In a split transaction protocol, when using multiple read requests in a multi processor
environment, there is a risk that the completions might arrive from the host memory
out of order and interleave. In this case the host interface role is to sort the request
completions and transfer them to the Ethernet core in the correct order.
3.1.6 Error Events and Error Reporting
3.1.6.1 Mechanism in General
PCIe defines two error reporting paradigms: the baseline capability and the Advanced
Error Reporting (AER) capability. The baseline error reporting capabilities are required
of all PCIe devices and define the minimum error reporting requirements. The AER
capability is defined for more robust error reporting and is implemented with a specific
PCIe capability structure.
Both mechanisms are supported by the 82574.
Also the SERR# Enable and the Parity Error bits from the legacy command register take
part in the error reporting and logging mechanism.
Figure 5 shows, in detail, the flow of error reporting in the 82574.
39
Interconnects—82574 GbE Controller
Figure 5. Error Reporting Flow
3.1.6.1.1 Error Events
Table 22 lists error events identified by the 82574 and the response in terms of logging,
reporting, and actions taken. Consult the PCIe specification for the affect on the PCI
Status register.
Table 22. Response and Reporting of Error Events
Command ::
SERR# Enable
Command ::
Parity Error Response
Status ::
Signaled Target Abort
Status ::
Received Target Abort
Status ::
Received Master Abort
Status ::
Detected Parity Error
Device Control ::
Correctable Error Reporting Enable
Device Control ::
Non-Fatal Error Reporting Enable
Device Control ::
Fatal Error Reporting Enable
Device Control ::
Unsupported Request Reporting Enable
Device Status ::
Correctable Error Detected
Device Status ::
Non-Fatal Error Detected
Device Status ::
Fatal Error Detected
Device Status ::
Unsupported Request Detected
Uncorrectable Error Severity
Uncorrectable Error Mask
Correctable Error Mask
Uncorrectable Error Status
Correctable Error Status
Status Reporting - Not Gated
Secondary Status ::
Detected Parity Error
Secondary Status ::
Signaled Target Abort
Secondary Status ::
Received System Error
(Eith er im plementation acceptable - th e
unqualified version is more lik e PCI P 2P
bridge spec)
Secondary Status ::
Received Target Abort
Secondary Status ::
Received Master Abort Secondary Status ::
Master Data Parity Error
Bridge Control ::
SERR Enable
Bridge Control ::
Parity Error Response Enable
Root Control ::
System Error on Correctable Error Enable
Root Control ::
System Error on Non-Fatal Error Enable
Root Control ::
System Error on Fatal Error Enable
Root Error Command ::
Correctable Error Reporting Enable
Root Error Command ::
Non-Fatal Error Reporting Enable
Root Error Command ::
Fatal Error Reporting Enable
Root Error Status
Rcv Msg
System Error
Interrupt
Status ::
Signaled System Error
Secondary Side Error Sources
Error Sources
(Associated with Port)
Error Message
Processing
Status ::
Master Data Parity Error
Error Name Error Events Default Severity Action
PHY errors
Receiver error • 8b/10b Decode errors
• Packet framing error
Correctable
Send ERR_CORR
TLP to initiate NAK, drop data
DLLP to Drop
Data link errors
Bad TLP
• Bad CRC
• Not legal EDB
• Wrong sequence number
Correctable
Send ERR_CORR TLP to initiate NAK, drop data
Bad DLLP Bad CRC Correctable
Send ERR_CORR DLLP to drop
Replay timer
timeout REPLAY_TIMER expiration Correctable
Send ERR_CORR Follow LL rules
REPLAY NUM
rollover REPLAY NUM rollover Correctable
Send ERR_CORR Follow LL rules
82574 GbE Controller—Interconnects
40
Data link layer
protocol error Violations of Flow Control
initialization protocol
Uncorrectable
Send ERR_FATAL
TLP errors
Poisoned TLP
received TLP with Error Forwarding
Uncorrectable
ERR_NONFATAL
Log header
In case of poisoned completion,
no more requests from this client.
Unsupported
Request (UR)
• Wrong config access
•MRdLk
• Config Request Type1
• Unsupported vendor
defined type 0 message
•Not valid MSG code
• Not supported TLP type
• Wrong function number
•Wrong TC/VC
• Received target access
with data size > 64-bit
• Received TLP outside
address range
Uncorrectable
ERR_NONFATAL
Log header
Send completion with UR
Completion
Timeout Completion timeout timer
expired
Uncorrectable
ERR_NONFATAL Send the read request again
Completer abort Attempts to write to the Flash
device when writes are
disabled (FWE=10b)
Uncorrectable
ERR_NONFATAL
Log header
Send completion with CA
Unexpected
completion Received completion without
a request for it (tag, ID, etc.)
Uncorrectable
ERR_NONFATAL
Log header
Discard TLP
Receiver
Overflow Received TLP beyond
allocated credits
Uncorrectable
ERR_FATAL Receiver behavior is undefined
Flow control
protocol error
• Minimum Initial Flow
Control Advertisements
• Flow control update for
Infinite Credit
advertisement
Uncorrectable
ERR_FATAL Receiver behavior is undefined
Malformed TLP
(MP)
• Data payload exceed
Max_Payload_Size
•Received TLP data size
does not match length
field
• TD field value does not
correspond with the
observed size
• Byte enables violations.
• PM messages that don’t
use TC0.
• Usage of unsupported VC
Uncorrectable
ERR_FATAL
Log header
Drop the packet, free FC credits
Completion with
unsuccessful
completion status
No action (already
done by originator of
completion) Free FC credits
Error Name Error Events Default Severity Action
41
Interconnects—82574 GbE Controller
3.1.6.1.2 Error Pollution
Error pollution can occur if error conditions for a given transaction are not isolated to
the error's first occurrence. If the PHY detects and reports a receiver error, to avoid
having this error propagate and cause subsequent errors at upper layers, the same
packet is not signaled at the data link or transaction layers.
Similarly, when the data link layer detects an error, subsequent errors that occur for the
same packet is not signaled at the transaction layer.
3.1.6.1.3 Completion With Unsuccessful Completion Status
A completion with unsuccessful completion status is dropped and not delivered to its
destination. The request that corresponds to the unsuccessful completion is retried by
sending a new request for the undeliverable data.
3.1.7 Link Layer
3.1.7.1 ACK/NAK Scheme
The 82574L supports two alternative schemes for ACK/NAK rate:
1. ACK/NAK is scheduled for transmission following any TLP.
2. ACK/NAK is scheduled for transmission according to timeouts specified in the PCIe
specification.
The PCIe Error Recovery bit, loaded from NVM, determines which of the two schemes is
used.
3.1.7.2 Supported DLLPs
The following DLLPs are supported by the 82574 as a receiver:
Table 23. DLLPs Received by The 82574L
The following DLLPs are supported by the 82574 as a transmitter:
Remarks Remarks
ACK
NAK
PM_Request_Ack
InitFC1-P v2v1v0 = 000
InitFC1-NP v2v1v0 = 000
InitFC1-Cpl v2v1v0 = 000
InitFC2-P v2v1v0 = 000
InitFC2-NP v2v1v0 = 000
InitFC2-Cpl v2v1v0 = 000
UpdateFC-P v2v1v0 = 000
UpdateFC-NP v2v1v0 = 000
UpdateFC-Cpl v2v1v0 = 000
82574 GbE Controller—Interconnects
42
Table 24. DLLPs initiated by The 82574L
3.1.7.3 Transmit EDB Nullifying
In case of a retrain necessity, there is a need to guarantee that no abrupt termination
of the Tx packet happens. For this reason, early termination of the transmitted packet
is possible. This is done by appending the EDB to the packet.
3.1.8 PHY
3.1.8.1 Link Width
The 82574L supports a link width of x1 only.
3.1.8.2 Polarity Inversion
If polarity inversion is detected, the receiver must invert the received data.
During the training sequence, the receiver looks at Symbols 6-15 of TS1 and TS2 as the
indicator of lane polarity inversion (D+ and D- are swapped). If lane polarity inversion
occurs, the TS1 Symbols 6-15 received are D21.5 as opposed to the expected D10.2.
Similarly, if lane polarity inversion occurs, Symbols 6-15 of the TS2 ordered set are
D26.5 as opposed to the expected 5D5.2. This provides the clear indication of lane
polarity inversion.
3.1.8.3 L0s Exit Latency
The number of FTS sequences (N_FTS), sent during L1 exit, is loaded from the NVM
into an 8-bit read-only register.
Remarks1
1. UpdateFC-Cpl is not sent because of the infinite FC-Cpl allocation.
Remarks
ACK
NAK
PM_Enter_L1
PM_Enter_L23
PM_Active_State_Request_L1
InitFC1-P v2v1v0 = 000
InitFC1-NP v2v1v0 = 000
InitFC1-Cpl v2v1v0 = 000
InitFC2-P v2v1v0 = 000
InitFC2-NP v2v1v0 = 000
InitFC2-Cpl v2v1v0 = 000
UpdateFC-P v2v1v0 = 000
UpdateFC-NP v2v1v0 = 000
43
Interconnects—82574 GbE Controller
3.1.8.4 Reset
The PCIe PHY can initiate core reset to the 82574. The reset can be caused by three
sources:
• Upstream move to hot reset - Inband Mechanism (LTSSM).
• Recovery failure (LTSSM returns to detect).
• Upstream component move to disable.
3.1.8.5 Scrambler Disable
The Scrambler/de-scrambler functionality in the 82574 can be eliminated by two
mechanisms:
• Upstream according to the PCIe specification.
•NVM bit.
3.1.9 Performance Monitoring
The 82574L incorporates PCIe performance monitoring counters to provide common
capabilities to evaluate performance. The 82574L implements four 32-bit counters to
correlate between concurrent measurements of events as well as the sample delay and
interval timers. The four 32-bit counters can also operate in a two 64-bit mode to count
long intervals or payloads.
The list of events supported by the 82574 and the counters control bits are described in
the memory register map.
3.2 Ethernet Interface
The 82574L MAC provides a complete CSMA/CD function, supporting IEEE 802.3
(10 Mb/s), 802.3u (100 Mb/s), 802.3z, and 802.3ab (1000 Mb/s) implementations. The
82574L performs all of the functions required for transmission, reception, and collision
handling called out in the standards.
The GMII/MII mode used to communicate between the MAC and the PHY supports
10/100/1000 Mb/s operation, with both half- and full-duplex operation at 10/100 Mb/s,
and only full-duplex operation at 1000 Mb/s.
Note: The 82574L MAC is optimized for full-duplex operation in 1000 Mb/s mode. Half-duplex
1000 Mb/s operation is not supported.
The PHY features 10/100/1000-BaseT signaling and is capable of performing intelligent
power-management based on both the system power-state and LAN energy-detection
(detection of unplugged cables). Power management includes the ability to shutdown
to an extremely low (powered-down) state when not needed as well as ability to auto-
negotiate to a lower-speed 10/100 Mb/s operation when the system is in low power-
states.
3.2.1 MAC/PHY GMII/MII Interface
The 82574L MAC and PHY communicate through an internal GMII/MII interface that can
be configured for either 1000 Mb/s operation (GMII) or 10/100 Mb/s (MII) mode of
operation. For proper network operation, both the MAC and PHY must be properly
configured (either explicitly via software or via hardware auto-negotiation) to identical
speed and duplex settings. All MAC configuration is performed using device control
registers mapped into system memory or I/O space; an internal MDIO/MDC interface,
accessible via software, is used to configure the PHY operation.
82574 GbE Controller—Interconnects
44
The internal Gigabit Media Independent Interface (GMII) mode of operation is similar to
MII mode of operation. GMII mode uses the same MDIO/MDC management interface
and registers for PHY configuration as MII mode. These common elements of operation
enable the 82574 MAC and PHY to cooperatively determine a link partner's operational
capability and configure the hardware based on those capabilities.
3.2.1.1 MDIO/MDC
The 82574L implements an internal IEEE 802.3 MII Management Interface (also known
as the Management Data Input/Output or MDIO Interface) between the MAC and PHY.
This interface provides the MAC and software the ability to monitor and control the
state of the PHY. The internal MDIO interface defines a physical connection, a special
protocol that runs across the connection, and an internal set of addressable registers.
The internal interface consists of a data line (MDIO) and clock line (MDC), which are
accessible by software via the MAC register space.
Software can use MDIO accesses to read or write registers in either GMII or MII mode
by accessing the 82574's MDIC register (see section 10.2.2.7).
3.2.1.2 Other MAC/PHY Control and Status
In addition to the internal GMII/MII communication and MDIO interface between the
MAC and the PHY, the 82574 implements a handful of additional internal signals
between MAC and PHY, which provide richer control and features.
• PHY reset - The MAC provides an internal reset to the PHY. This signal combines the
PCI_RST_N input from the PCI bus and the PHY Reset bit of the Device Control
register (CTRL.PHY_RST).
• PHY link status indication - The PHY provides a direct internal indication of link
status (LINK) to the MAC to indicate whether it has sensed a valid link partner.
Unless the PHY has been configured via its MII management registers to assert this
indication unconditionally, this signal is a valid indication of whether a link is
present. The MAC relies on this internal indication to reflect the STATUS.LU status
as well as to initiate actions such as generating interrupts on link status changes,
re-initiating link speed sense, etc.
• PHY duplex indication - The PHY provides a direct internal indication to the MAC of
its resolved duplex mode (FDX). Normally, auto-negotiation by the PHY enables the
PHY to resolve full/duplex communications with the link partner (except when the
PHY is forced through MII register settings). The MAC normally uses this signal
after a link loss/restore to ensure that the MAC is configured consistently with the
re-linked PHY settings. This indication is effectively visible through the MAC register
bit STATUS.FD, each time MAC speed has not been forced.
• PHY speed indication(s) - The PHY provides direct internal indications (SPD_IND) to
the MAC of its negotiated speed (10/100/1000 Mb/s). The result of this indication is
effectively visible through the MAC register bits STATUS.SPEED each time MAC
speed has not been forced.
• MAC Dx power state indication - The MAC indicates its ACPI power state
(PWR_STATE) to the PHY to enable it to perform intelligent power-management
(provided that the PHY power-management is enabled in the MAC CTRL register).
3.2.2 Duplex Operation for Copper PHY/GMII/MII Operation
The 82574L supports half-duplex and full-duplex 10/100 Mb/s MII mode or 1000 Mb/s
GMII mode.
Configuring the duplex operation of the 82574 can either be forced or determined via
the auto-negotiation process. See section 3.2.3 for details on link configuration setup
and resolution.
45
Interconnects—82574 GbE Controller
3.2.2.1 Full Duplex
All aspects of the IEEE 802.3, 802.3u, 802.3z, and 802.3ab specifications are
supported in full duplex operation. Full duplex operation is enabled by several
mechanisms, depending on the speed configuration of the 82574 and the specific
capabilities of the link partner used in the application. During full duplex operation, the
82574 might transmit and receive packets simultaneously across the link interface.
In full-duplex GMII/MII mode, transmission and reception are delineated independently
by the GMII/MII control signals. Transmission starts at the assertion of TX_EN, which
indicates there is valid data on the TX_DATA bus driven from the MAC to the PHY.
Reception is signaled by the PHY by the assertion of the RX_DV signal, which indicates
valid receive data on the RX_DATA lines to the MAC.
3.2.2.2 Half Duplex
The 82574L MAC can operate in half duplex.
In half duplex operation, the MAC attempts to avoid contention with other traffic on the
link by monitoring the CRS signal provided by the PHY and deferring to passing traffic.
When the CRS signal is de-asserted or after a sufficient Inter-Packet Gap (IPG) has
elapsed after a transmission, frame transmission begins. The MAC signals the PHY with
TX_EN at the start of transmission.
If a collision occurs, the PHY detects the collision and asserts the COL signal to the
MAC. Transmitting the frame stops within four link clock times and the 82574 sends a
JAM sequence onto the link. After the end of a collided transmission, the 82574 backs
off and attempts to re-transmit per the standard CSMA/CD method.
Note: The re-transmissions are done from the data stored internally in the 82574 MAC
transmit packet buffer (no re-access to the data in host memory is performed).
After a successful transmission, the 82574 is ready to transmit any other frame(s)
queued in the MAC's transmit FIFO, after the minimum Inter-Frame Spacing (IFS) of
the link has elapsed.
During transmit, the PHY is expected to signal a carrier-sense (assert the CRS signal)
back to the MAC before one slot time has elapsed. The transmission completes
successfully even if the PHY fails to indicate CRS within the slot time window; if this
situation occurs, the PHY can either be configured incorrectly or be in a link down
situation. Such an event is counted in the Transmit Without CRS statistic register (see
section 10.2.7.11).
3.2.3 Auto-Negotiation & Link Setup Features
The method for configuring the link between two link partners is highly dependent on
the mode of operation.
Configuration of the link can be accomplished by several methods ranging from:
• software's forcing link settings
• software-controlled negotiation
• MAC-controlled auto-negotiation
• auto-negotiation initiated by a PHY.
The following sections describe processes of bringing the link up including configuration
of the 82574 and the transceiver, as well as the various methods of determining duplex
and speed configuration.
82574 GbE Controller—Interconnects
46
The PHY performs auto-negotiation per 802.3ab clause 40 and extensions to clause 28.
Link resolution is obtained by the MAC from the PHY after the link has been established.
The MAC accomplishes this via the MDIO interface, via specific signals from the PHY to
the MAC, or by MAC auto-detection functions.
3.2.3.1 Link Configuration
Link configuration is generally determined by PHY auto-negotiation. The software
device driver must intervene in cases where a successful link is not negotiated or a user
desires to manually configure the link. The following sections discuss the methods of
link configuration for copper PHY operation.
3.2.3.1.1 PHY Auto-Negotiation (Speed, Duplex, Flow-Control)
The PHY performs the auto-negotiation function. The details of this operation are
described in the IEEE P802.3ab draft standard and are not included here.
Auto-negotiation provides a method for two link partners to exchange information in a
systematic manner in order to establish a link configuration providing the highest
common level of functionality supported by both partners. Once configured, the link
partners exchange configuration information to resolve link settings such as:
• Speed: 10/100/1000 Mb/s
• Duplex: full or half
• Flow control operation
PHY specific information required for establishing the link is also exchanged.
Note: If flow control is enabled in the 82574, the settings for the desired flow control
behavior must be set by software in the PHY registers and auto-negotiation restarted.
After auto-negotiation completes, the software device driver must read the PHY
registers to determine the resolved flow control behavior of the link and reflect these in
the MAC register settings (CTRL.TFCE and CTRL.RFCE). If no software device driver is
loaded and auto-negotiation is enabled, then hardware sets these bits in accordance
with the auto-negotiation results.
Note: By default, the PHY advertises flow control support. Since the management path does
not support flow control, it should change this default. Therefore, when management is
active and there is no software device driver loaded, it should disable the flow control
support and restart auto-negotiation.
Note: Once PHY auto-negotiation completes, the PHY asserts a link indication (LINK) to the
MAC. Software must set the Set Link Up bit in the Device Control register (CTRL.SLU)
before the MAC recognizes the link indication from the PHY and can consider the link to
be up.
47
Interconnects—82574 GbE Controller
3.2.3.1.2 MAC Speed Resolution
For proper link operation, both the MAC and PHY must be configured for the same
speed of link operation. The speed of the link can be determined and set by several
methods with the 82574. These include:
• Software-forced configuration of the MAC speed setting based on PHY indications,
which can be determined as follows:
— Software reads of PHY registers directly to determine the PHY's auto-negotiated
speed
— Software reads the PHY's internal PHY-to-MAC speed indication (SPD_IND)
using the MAC STATUS.SPEED register
— Software signals the MAC to attempt to auto-detect the PHY speed from the
PHY-to-MAC RX_CLK, then programs the MAC speed accordingly
• The MAC automatically detecting and setting the link speed of the MAC based on
PHY indications by:
— Using the PHY's internal PHY-to-MAC speed indication (SPD_IND), setting the
MAC speed automatically
— Attempting to auto-detect the PHY speed from the PHY-to-MAC RX_CLK and
setting the MAC speed automatically
Aspects of these methods are discussed in the sections that follow.
3.2.3.1.2.1 Forcing MAC Speed
There might be circumstances when the software device driver must forcibly set the
link speed of the MAC. This can occur when the link is manually configured. To force the
MAC speed, the software device driver must set the CTRL.FRCSPD (force-speed) bit to
1b and then write the speed bits in the Device Control register (CTRL.SPEED) to the
desired speed setting. See section 10.2.2.1 for details.
Note: Forcing the MAC speed using CTRL.FRCSPD overrides all other mechanisms for
configuring the MAC speed and can yield non-functional links if the MAC and PHY are
not operating at the same speed/configuration.
When forcing the 82574 to a specific speed configuration, the software device driver
must also ensure the PHY is configured to a speed setting consistent with MAC speed
settings. This implies that software must access the PHY registers to either force the
PHY speed or to read the PHY status register bits that indicate link speed of the PHY.
Note: Forcing speed settings by CTRL.SPEED can also be accomplished by setting the
CTRL_EXT.SPD_BYPS bit. This bit bypasses the MAC's internal clock switching logic and
enables the software device driver complete control of when the speed setting takes
place. The CTRL.FRCSPD bit uses the MAC's internal clock switching logic, which does
delay the affect of the speed change.
3.2.3.1.2.2 Using PHY Direct Link-Speed Indication
The 82574L PHY provides a direct internal indication of its speed to the MAC
(SPD_IND). The most direct method for determining the PHY link speed and either
manually or automatically configuring the MAC speed is based on these direct speed
indications.
For MAC speed to be set/determined from these direct internal indications from the
PHY, the MAC must be configured such that CTRL.ASDE and CTRL.FRCSPD are both 0b
(both auto-speed detection and forced-speed override are disabled). As a result, the
MAC speed is reconfigured automatically each time the PHY indicates a new link-up
event to the MAC.
82574 GbE Controller—Interconnects
48
When MAC speed is neither forced nor auto-sensed by the MAC, the current MAC speed
setting and the speed indicated by the PHY is reflected in the Device Status register bits
STATUS.SPEED.
3.2.3.1.3 MAC Full/Half Duplex Resolution
The duplex configuration of the link is also resolved by the PHY during the auto-
negotiation process. The 82574L PHY provides an internal indication to the MAC of the
resolved duplex configuration using an internal full-duplex indication (FDX).
This internal duplex indication is normally sampled by the MAC each time the PHY
indicates the establishment of a good link (LINK indication). The PHY's indicated duplex
configuration is applied in the MAC and reflected in the MAC Device Status register
(STATUS.FD).
Software can override the duplex setting of the MAC via the CTRL.FD bit when the
CTRL.FRCDPLX (force duplex) bit is set. If CTRL.FRCDPLX is 0b, the CTRL.FD bit is
ignored and the PHY's internal duplex indication applied.
3.2.3.1.4 Using PHY Registers
The software device driver might be required under some circumstances to read from
or write to the MII management registers in the PHY. These accesses are performed via
the MDIC registers (see section 10.2.2.7). The MII registers enable the software device
driver to have direct control over the PHY's operation, which might include:
• Resetting the PHY
• Setting preferred link configuration for advertisement during the auto-negotiation
process
• Restarting the auto-negotiation process
• Reading auto-negotiation status from the PHY
• Forcing the PHY to a specific link configuration
The set of PHY management registers required for all PHY devices can be found in the
IEEE P802.3ab draft standard. The registers for the 82574 PHY are described in
section 10.2.
3.2.3.1.5 Comments Regarding Forcing Link
Forcing link requires the software device driver to configure both the MAC and PHY in a
consistent manner with respect to each other. After initialization, the software device
driver configures the desired modes in the MAC, then accesses the PHY registers to set
the PHY to the same configuration.
Before enabling the link, the speed and duplex settings of the MAC can be forced by
software using the CTRL.FRCSPD, CTRL.FRCDPX, CTRL.SPEED, and CTRL.FD bits. After
the PHY and MAC have both been configured, the software device driver should write a
1b to the CTRL.SLU bit.
3.2.4 Loss of Signal/Link Status Indication
PHY LOS/LINK signal provides an indication of physical link status to the MAC. This
signal from the PHY indicates whether the link is up or down; typically indicated after
successful auto-negotiation. Assuming that the MAC is configured with CTRL.SLU = 1b,
the MAC status bit STATUS.LU when read, generally reflects whether the PHY has link
(except under forced-link setup where even the PHY link indication might have been
forced).
49
Interconnects—82574 GbE Controller
When the link indication from the PHY is de-asserted, the MAC considers this to be a
transition to a link-down situation (such as, cable unplugged, loss of link partner, etc.).
If the LSC (Link Status Change) interrupt is enabled, the MAC generates an interrupt to
be serviced by the software device driver. See section 7.4 and section 10.2.4 for more
details.
3.2.5 10/100 Mb/s Specific Performance Enhancements
3.2.5.1 Adaptive IFS
The 82574L supports back-to-back transmit Inter-Frame-Spacing (IFS) of 960 ns in
100 Mb/s operation and 9.6 μs in 10 Mb/s operation. Although back-to-back
transmission is normally desirable, sometimes it can actually hurt performance in half-
duplex environments due to excessive collisions. Excessive collisions are likely to occur
in environments where one station is attempting to send large frames back-to-back,
while another station is attempting to send acknowledge (ACK) packets.
The 82574L contains an Adaptive IFS register (see section 10.2.6.3) that enables the
implementation of a driver-based adaptive IFS algorithm for collision reduction, which
is similar to Intel's other Ethernet products (such as PRO/100 adapters). Adaptive IFS
throttles back-to-back transmissions in the transmit MAC and delays their transfer to
the CSMA/CD transmit function and then can be used to delay the transmission of
back-to-back packets on the wire. Normally, this register should be set to zero.
However, if additional delay is desired between back-to-back transmits, then this
register can be set with a value greater than zero. This can be helpful in high-collision
half-duplex environments.
The AIFS field provides a similar function to the IGPT field in the TIPG register (see
section 10.2.6.3). However, this Adaptive IFS throttle register counts in units of GTX/
MTX_CLK clocks, which are 800 ns, 80 ns, 8 ns for 10/100/1000 Mb/s mode
respectively, and is 16 bits wide, thus providing a greater maximum delay value.
Using values lower than a certain minimum (determined by the ratio of GTX/MTX_CLK
clock to link speed), has no effect on back-to-back transmission. This is because the
82574 does not start transmission until the minimum IEEE IFS (9.6 μs at 10 Mb/s, 960
ns at 100 Mb/s, and 96 ns at 1000 Mb/s) has been met regardless of the value of
Adaptive IFS. For example, if the 82574 is configured for 100 Mb/s operation, the
minimum IEEE IFS at 100 Mb/s is 960 ns. Setting AIFS to a value of 10 (decimal) would
not effect back-to-back transmission time on the wire because the 800 ns delay
introduced (10 * 80 ns = 800 ns) is less than the minimum IEEE IFS delay of 960 ns.
However, setting this register with a value of 20 (decimal), which corresponds to
1600 ns for the above example, would delay back-to-back transmits because the
ensuing 1600 ns delay is greater than the minimum IFS time of 960 ns.
It is important to note that this register has no effect on transmissions that occur
immediately after receives or on transmissions that are not back-to-back (unlike the
IPGR1 and IPGR2 values in the TIPG register (see section 10.2.6.2). In addition,
Adaptive IFS also has no effect on re-transmission timing (re-transmissions occur after
collisions). Therefore, AIFS is only enabled in back-to-back transmission.
Note: The AIFS value is not additive to the TIPG.IPGT value; instead, the actual IPG equals
the larger of the two, AIFS and TIPG.IPGT.
82574 GbE Controller—Interconnects
50
3.2.6 Flow Control
Flow control as defined in 802.3x, as well as the specific operation of asymmetrical flow
control defined by 802.3z, are supported in the MAC. The following seven registers are
defined for the implementation of flow control:
• Flow Control Address Low (FCAL) - 6-byte flow control multicast address
• Flow Control Address High (FCAH) - 6-byte flow control multicast address
• Flow Control Type (FCT) - 16-bit field that indicates flow control type
• Flow Control Receive Thresh Hi (FCRTH) - 13-bit high-water mark indicating receive
buffer fullness
• Flow Control Receive Thresh Lo (FCRTL) - 13-bit low-water mark indicating receive
buffer emptiness
• Flow Control Transmit Timer Value (FCTTV) - 16-bit timer value to include in
transmitted pause frames
• Flow Control Refresh Threshold Value (FCRTV) - 16-bit pause refresh threshold
value
Flow control allows for local controlling of network congestion levels. Flow control is
implemented as a means of reducing the possibility of receive buffer overflows. Receive
buffer overflows result in the dropping of received packets. Flow control is
accomplished by notifying the transmitting station that the receiving station receive
buffer is nearly full.
Implementing asymmetric flow control allows for one link partner to send flow control
packets while being allowed to ignore their reception. For example, not required to
respond to pause frames.
3.2.6.1 MAC Control Frames and Reception of Flow Control Packets
Three comparisons are used to determine the validity of a flow control frame. All three
must be true for a positive result.
1. A match on the six-byte multicast address for MAC control frames or to the station
address of the device (Receive Address Register 0).
2. A match on the Type field.
3. A comparison of the MAC Control Opcode field.
The 802.3x standard defines the MAC control frame multicast address as 01-80-C2-00-
00-01. This address must be loaded into the Flow Control Address Low/High registers
(FCAL/FCAH).
The Flow Control Type (FCT) register contains a 16-bit field that is compared against
the flow control packet's Type field to determine if it is a valid flow control packet: XON
or XOFF. 802.3x reserves this as 0x8808. This value must be loaded into the Flow
Control Type register.
The final check for a valid pause frame is the MAC control opcode. At this time, only the
pause control frame opcode is defined. It has a value of 0x0001.
Frame-based flow control differentiates XOFF from XON based on the value of the
Pause Timer field. Non-zero values constitute XOFF frames while a value of zero
constitutes an XON frame. Values in the timer field are in units of slot time. A slot time
is hard wired to 64-byte times or 512 ns.
Note: An XON frame signals the cancellation of the pause from being initiated by an XOFF
frame (pause for zero slot times).
51
Interconnects—82574 GbE Controller
Figure 6. 802.3x MAC Control Frame Format
Where S is the start-of-packet delimiter and T is the first part of the end-of-packet
delimiters for 802.3z encapsulation.
The receiver is enabled to receive flow control frames if flow control is enabled via the
RFCE bit in the Device Control (CTRL) register.
Note: Flow control capability must be negotiated between link partners via the auto-
negotiation process. The auto-negotiation process might modify the value of these bits
based on the resolved capability between the local device and the link partner.
Once the receiver validates receiving an XOFF or pause frame, the 82574 performs the
following:
• Increments the appropriate statistics register(s).
• Sets the TXOFF bit in the Device Status (STATUS) register.
• Initializes the pause timer based on the packet's Pause Timer field.
• Disables packet transmission or schedules the disabling of transmissions after the
current packet completes.
Resuming transmission can occur under the following conditions:
• An expired pause timer
• Receiving an XON frame (a frame with its pause timer set to zero)
Either condition clears the TXOFF status bit in the Device Status register and
transmission can resume. Note that hardware records the number of received XON
frames.
(min_FrameSize -160)/8
Bytes
Preamble...
SFD
S
FCS
T
Up to 6 Bytes
1 Byte
1 Byte
Destination
Address
6 Bytes
Source
Address
6 Bytes
Type/Length2 Bytes
MAC Control
Opcode
2 Bytes
MAC Control
Parameters
1 Byte
4 Bytes
82574 GbE Controller—Interconnects
52
3.2.6.2 Discard Pause Frames and Pass MAC Control Frames
Two bits in the Receive Control register are implemented specifically for control over
receipt of pause and MAC control frames. These bits are Discard PAUSE Frames (DPF)
and Pass MAC Control Frames (PMCF). See section 10.2.6.2 for DPF and PMCF bit
definitions.
The DPF bit forces the discarding of any valid pause frame addressed to the 82574's
station address. If the packet is a valid pause frame and is addressed to the station
address (receive address [0]), the 82574 does not pass the packet to host memory if
the DPF bit is set to logic high. However, if a flow control packet is sent to the station
address and is a valid flow control frame, it is then be transferred when DPF is set to
0b. This bit has no affect on pause operation, only the DMA function.
The PMCF bit enables for the passing of any valid MAC control frames to the system,
which does not have a valid pause opcode. In other words, the frame must have the
correct MAC control frame multicast address (or the MAC station address) as well as
the correct Type field match with the FCT register, but does not have the defined pause
opcode of 0x0001. Frames of this type are transferred to host memory when PMCF is a
logic high.
3.2.6.3 Transmitting PAUSE Frames
Transmitting pause frames is enabled by software by writing a 1b to the TFCE bit in the
Device Control register.
Note: Similar to receiving flow control packets, XOFF packets can be transmitted only if this
configuration has been negotiated between the link partners via the auto-negotiation
process. In other words, setting this bit indicates the desired configuration. Resolving
the auto-negotiation process is described in section 3.2.3.
The content of the Flow Control Receive Threshold High register determines at what
point hardware transmits a pause frame. Hardware monitors the fullness of the receive
FIFO and compares it with the contents of FCRTH. When the threshold is reached,
hardware sends a pause frame with its pause time field equal to FCTTV.
At the time threshold is reached, the hardware starts counting an internal shadow
counter FCRTV (reflecting the pause time-out counter at the partner end) from zero.
When the counter reaches the value indicated in the FCRTV register, then, if the pause
condition is still valid (meaning that the buffer fullness is still above the low
watermark), an XOFF message is sent again and the shadow counter starts counting
again.
Once the receive buffer fullness reaches the low water mark, hardware sends an XON
message (a pause frame with a timer value of zero). Software enables this capability
with the XONE field of the FCRTL.
Hardware sends one more pause frame if it has previously sent one and the FIFO
overflows (so the threshold must not be set greater than the FIFO size). This is
intended to minimize the amount of packets dropped if the first pause frame does not
reach its target. Since the secure receive packets use the same data path, the behavior
is identical when secure packets are received.
Note: Transmitting flow control frames should only be enabled in full-duplex mode per the
IEEE 802.3 standard. Software should ensure that transmitting flow control packets is
disabled when the 82574 is operating in half-duplex mode.
Note: Regardless of the mechanism above, each time a receive packet is dropped due to lack
of space in the internal receive buffer, a pause frame is transmitted as well (if TFCE bit
in the Device Control register is enabled).
53
Interconnects—82574 GbE Controller
3.2.6.4 Software Initiated Pause Frame Transmission
The 82574L has the added capability to transmit an XOFF frame via software. This is
accomplished by software writing a 1b to the SWXOFF bit of the Transmit Control
register. Once this bit is set, hardware initiates transmitting a pause frame in a manner
similar to that automatically generated by hardware.
The SWXOFF bit is self-clearing after the pause frame has been transmitted.
The state of the CTRL.TFCE bit or the negotiated flow control configuration does not
affect software generated pause frame transmission.
Note: Software sends an XON frame by programming a zero in the Pause Timer field of the
FCTTV register.
Note: XOFF transmission is not supported in 802.3x for half-duplex links. Software should not
initiate an XOFF or XON transmission if the 82574 is configured for half-duplex
operation.
3.3 SPI Non-Volatile Memory Interface
3.3.1 General Overview
The 82574L requires non-volatile content for the 82574 configuration. The Non-Volatile
Memory (NVM) might contain the following main regions:
• LAN configuration space accessed by hardware - loaded by the 82574 after power
up, PCI reset de-assertion, D3->D0 transition, or a software commanded EEPROM
read (CTRL_EXT.EE_RST).
• LAN configuration space accessed by software - used by software only. The
meaning of these registers as listed here as a convention for the software only and
is ignored by the 82574.
3.3.2 Supported NVM Devices
Some Intel LAN controllers require both an EEPROM and Flash device for storing LAN
data. However, the 82574 reduces the Bill of Material (BOM) cost by consolidating the
EEPROM and Flash into a single non-volatile memory device. The NVM is connected to a
single Serial Peripheral Interface (SPI).
The 82574 is compatible with many sizes of 4-wire SPI NVM devices. The required NVM
size is dependent upon system requirements.
82574 GbE Controller—Interconnects
54
3.3.3 NVM Device Detection
The 82574L detects the device connected on the SPI interface in two phases.
1. It first detects the device type by the state of the NVMT strapping pin.
2. It then looks at the NVM content depending on a valid signature in word 0x12 in the
NVM.
In reference to the EEPROM, the 82574 detects the length of the address bytes by
sensing the signature at word 0x12. It then sets the NVADDS field in the EEC register.
The exact size of the NVM is fetched by the 82574 from word 0x0F and is stored in the
NVSize field in the EEC register. When operating with an EEPROM that has an invalid
signature, software can force the address length via the NVADDS field in the EEC
register. Controlling the address length enables software to access the EEPROM via the
parallel EERD and EEWR registers in all cases including invalid signature.
3.3.3.1 CRC Field
CRC calculation and management is done by software.
Table 25. NVM Configuration Size
Configuration Minimum NVM Size Memory Family
SMBus or NC-SI manageability1
1. If PXE and iSCSI boot firmware is required, they must be integrated into the BIOS.
32 Kb SPI EEPROM
No Manageability/No iSCSI boot11 Kb SPI EEPROM
PXE only 512 Kb SPI Flash
iSCSI boot only 2 Mb SPI Flash
Both iSCSI boot and PXE 4 Mb SPI Flash
Table 26. Compatible EEPROM Parts
Vendor 1 Kb 2 Kb 32 Kb
Atmel* AT25010N AT25020N AT25320N
STM* 95010W6 95020W6 95320W6
Catalyst* CAT25010S CAT25020S CAT25C320S
Table 27. Compatible Flash Parts
Vendor 512 Kb 1 Mb 2 Mb 4 Mb 8 Mb
Winbond* N/A W25X10BV W25X20BV W25X40BV N/A
Atmel AT25F512B N/A AT25DF021 AT25DF041A AT25DF081A
PMC* 25LV512A 25LV010A 25LV020 N/A N/A
SST* SST25VF512 SST25VF010A SST25VF020B SST25VF040B SST25VF080B
55
Interconnects—82574 GbE Controller
3.3.4 Device Operation with an External EEPROM
When the 82574 is connected to an external EEPROM, it provides similar functionality
to its predecessors with the following enhancements:
• Enables a complete parallel interface for read/write to the EEPROM.
• Enables software to specify explicitly the address length, thus eliminating the need
for bit banging access even on an empty EEPROM.
3.3.5 Device Operation with Flash
As previously stated, the 82574 merges the legacy EEPROM and Flash content in a
single Flash device. The 82574L copies the lower section in the Flash device to an
internal shadow RAM. The interface to the shadow RAM is the same as the interface for
an external EEPROM device. This mechanism provides a seamless backward compatible
interface for software to the legacy EEPROM space as if an external EEPROM device is
connected.
The 82574L supports Flash devices with a block erase size of 4 KB. Note that many
Flash vendors are using the term sector differently. This document uses the term Flash
sector for a logic section of 4 KB.
3.3.5.1 LAN Configuration Sectors
Flash devices require a block erase instruction in case a cell is modified from 0b to 1b.
As a result, in order to update a single byte (or block of data) it is required to erase it
first. The first addresses of the Flash contain the device configuration and must always
be valid. The 82574L maintains two sectors of 4 KB: S0 and S1 for the configuration
content. At least one of these two sectors is valid at any given time or else the 82574 is
set by the hardware default. section 3.3.6 provides more details on the shadow RAM
and the first two sectors.
3.3.6 Shadow RAM
The 82574L includes an internal 4 KB shadow RAM of the first 4 KB Flash sector(s).
When the 82574 is connected to a Flash device the legacy configuration parameters
might reside in any of the first two 4 KB sectors (S0 or S1) in the Flash. The 82574L
copies that data to an internal shadow memory. The shadow RAM emulates a seamless
EEPROM interface to the rest of the 82574 and host CPU. This way the legacy
configuration content is accessible to software and firmware on the same EEPROM
registers as on previous GbE controllers.
Figure 7 shows the shadow RAM mapping and interface relative to the Flash and the
EEPROM. The external EEPROM and the shadow RAM share the same interface. The
82574L might access the EEPROM or shadow RAM according to the setting of the
SELSHAD bit in the EEC register. By hardware default, the SELSHAD bit is set by the
NVMT strapping pin so that the EEPROM is selected in case of external EEPROM and the
shadow RAM is selected in the case of external Flash.
Note: Access to the shadow RAM uses the same interface as the external EEPROM with the
exception that bit banging is not supported for the shadow RAM.
82574 GbE Controller—Interconnects
56
Figure 7. NVM Shadow RAM
3.3.6.1 Flash Mode
The 82574L is initialized from the NVM. As part of the initialization sequence, the 82574
copies the 4 KB content of S0 or S1 from the Flash to the shadow RAM. Any access to
the EEPROM interface is directed to the shadow RAM. Following any write access to the
shadow RAM by software or firmware, the data should also be updated in the Flash. The
82574L maintains a watchdog timer defined by the FLASHT register to minimize Flash
updates. The timer is triggered by any write access to the shadow RAM. The 82574L
updates the Flash from the shadow RAM when the FLASHT timer expires or when
firmware or software request explicitly to update the Flash by setting the FLUPD bit in
the FLA register. The 82574L copies the content of the shadow RAM to the inactive
configuration sector and then makes it the active one. The Flash update sequence is
listed in the steps that follow:
1. Initiates block erase instruction(s) to the inactive sector (the inactive sector is
defined by the inverse value of the SEC1VAL bit in the EEC register).
2. Copy the shadow RAM to the inactive sector while the signature word is copied last.
3. Clear the signature word in the active sector to make it invalid.
4. Toggle the state of the SEC1VAL bit in the EEC register to indicate that the inactive
sector became the active one and visa versa.
Note: Software should be aware of the fact that actual programming to the Flash might
require a long latency following the write access to the shadow RAM. Software might
poll the FLUDONE bit in the FLMNGCTL register to complete the Flash programming,
when required.
3.3.6.2 EEPROM Mode
When the 82574 is attached to an external EEPROM, any access to the EEPROM
interface is directed to the external EEPROM.
Shadow RAM
A
dd
r
ess
00
Address
4K
Address
8K
EEPROM Interface
Sector 0
Sector 1
EEPROM
…
EEC.SELSHAD
LAN Flash
…
57
Interconnects—82574 GbE Controller
3.3.7 NVM Clients and Interfaces
There are several clients that might access the NVM or shadow RAM listed in the
following table. Listed are the various clients and their access type to the NVM:
software device driver, BIOS, firmware and hardware.
Table 28. Clients and Access Type to the NVM
3.3.7.1 Memory Mapped Host Interface via LAN Flash BAR
Software might read and write to the Flash via the LAN Flash BAR. The Flash BAR is
mapped to the physical Flash at offset 0x0. The 82574L supports read byte, word or
Dword and write byte through this interface. The host CPU waits (stalled) until the read
access to the Flash completes.
Note: One of the first two sectors of 4 KB in the Flash are also reflected in the shadow RAM.
During normal operation, when software requires access to these sectors it should
access the shadow RAM. Direct write accesses to the Flash in this space via the Flash
BAR might cause non-coherency between the Flash and the shadow RAM.
Note: Flash BAR access while FLA.FL_REQ is asserted (and granted) is forbidden.
3.3.7.2 CSR Mapped Host Interface
Software has bit banging and parallel accesses to the NVM or shadow RAM via the
registers in the CSR space. The 82574L supports the following cycles on the parallel
interface: posted write, posted read, block erase and device erase. Access to the
configuration space in the first two sectors is directed via the EEPROM registers
regardless of the external physical device. Access to the rest of the NVM space is done
according to the type of the physical device: Flash registers in reference to Flash and
EEPROM registers in reference to EEPROM. EEPROM CSR registers are as follows:
• EEC register for bit banging and device control
• EERD and EEWR registers for parallel read and write access
The Flash CSR registers are as follows:
• FLA register and EEC register for bit banging and device control
Client + Interface NVM port NVM instructions
Host CPU on EEC CSR EEPROM Legacy bit banging
Host CPU on EERD and
EEWR EEPROM Parallel word read and write to EEPROM or shadow RAM
(controlled by the EEC.SELSHAD bit)
MNG on EEMNG CSR EEPROM Parallel word read and write to EEPROM or shadow RAM
Host CPU on FLA CSR Flash Legacy bit banging and Flash erase instructions
Host CPU via BAR Flash Read byte word and Dword and byte programming1
1. Following a write instruction or erase instructions to the Flash, the 82574 initiates seamless write enable
before the write or erase instructions and polls the status at the end to check its completion.
Host CPU via FLSWxxx
CSR registers Flash Host write access to the Flash no support for burst (multiple
byte) writes
Direct HW accesses Both Read EEPROM/shadow RAM at device initialization
82574 GbE Controller—Interconnects
58
Note: When software accesses the EEPROM or Flash spaces via the bit banging interface, it
should follow these steps:
1. Write a 1b to the Request bit in the FLA or EEC registers.
2. Poll the Grant bit in the FLA or EEC registers until its ready.
3. Access the NVM using the direct interface to its signaling via the EEC or FLA
registers.
4. When access completes, software should clear the Request bit.
Note: Following a write or erase instruction, software should clear the Request bit only after it
checked that the cycles were completed by the NVM.
3.3.7.3 CSR Mapped Firmware Interface
Firmware might access the NVM or shadow RAM via the NVM MNG Control registers in
the CSR space with the following capabilities:
• Word read and write accesses to the EEPROM or shadow RAM via the EEMNGCTL
and EEMNGDATA registers.
• Read and write DMA and block erase to the Flash interface via the FLMNGCTL and
FLMNGDATA registers. Flash accesses are mapped to the physical NVM at offset
0x0. Note that nominal accesses to the first two 4 KB sectors should be addressed
to the shadow RAM via the EEPROM interface.
3.3.8 NVM Write and Erase Sequence
3.3.8.1 Software Flow to the Bit Banging Interface
When software accesses the EEPROM or Flash CSR registers to the bit banging interface
it should follow these steps:
1. Write a 1b to the Request bit in the FLA or EEC registers.
2. Poll the Grant bit in the FLA or EEC registers until its ready.
3. Access the NVM using the direct interface to its signaling via the EEC or FLA
registers.
4. When access is achieved, software should clear the Request bit. Note that following
a write or erase instruction, software should clear the Request bit only after it
checked that the cycles were completed by the NVM.
3.3.8.2 Software Byte Program Flow to the EEPROM Interface
Software initiates a write cycle to the NVM on the parallel EEPROM as follows:
1. Poll the Done bit in the EEWR register until its set.
2. Write the data word, its address, and the Start bit to the EEWR register.
As a response, hardware executes the following steps:
Case 1 - The 82574L is connected to a physical EEPROM device:
1. Initiate an autonomous write enable instruction.
2. Initiate the program instruction right after the enable instruction.
3. Poll the EEPROM status until programming completes.
4. Set the Done bit in the EEWR register.
59
Interconnects—82574 GbE Controller
Case 2 - The 82574L is connected to a physical Flash device:
1. The 82574L writes the data to the shadow RAM and sets the Done bit in the EEWR
register.
2. Update of the shadow RAM to the Flash device as described in section 3.3.6.
3.3.8.3 Flash Byte Program Flow
Software initiates a byte write cycle via the Flash BAR as follows:
1. Write access to the Flash must be first enabled in the FLEW field in the EEC register.
2. Poll the FLBUSY flag in the FLA register until cleared.
3. Write the data byte to the Flash through the Flash BAR.
4. Repeat the steps 2 and 3 if multiple bytes should be programmed.
5. Clear the write enable in the FLEW field in the EEC register to protect the Flash
device.
As a response, hardware executes the following steps for each write access:
1. Initiate autonomous write enable instruction.
2. Initiate the program instruction right after the enable instruction.
3. Poll the Flash status until programming completes.
4. Clear the FLBUSY bit in the FLA register.
Note: This section explains only the actual programming of a single byte or multiple bytes.
3.3.8.4 Flash Erase Flow
Device Erase Flow:
Erase instructions flow by software is almost identical to the program flow:
1. Erase access to the Flash must be first enabled in the FLEW field in the EEC
register.
2. Poll the FLBUSY flag in the FLA register until cleared.
3. Set the Flash Erase bit (FL_ER) in the FLA register.
4. Clear the Erase enable in the FLEW field in the EEC register to protect the Flash
device.
3.3.8.5 Flash Burst Program Flow
The 82574L provides a burst engine that can be useful for initial programming of the
entire Flash image according to the following flow:
1. Set the ADDR field with the byte resolution address in the FLSWCTL register.
2. Set the CMD field to 01b, which is the DMA write setting in the FLSWCTL register.
3. Write the first 32 bits of data to the FLSWGDATA register.
4. Set the RDCNT field to the byte count number in the FLSWCNT register.
5. Set the CMDV field in the FLSWCTL register to start a DMA write.
6. Hardware starts accessing the SPI bus and begins writing the first 32 bits from the
FLSWDATA register.
7. Once hardware writes the 32-bit data to the Flash, the DONE bit in the FLSWCTL
register is set indicating the next 32 bits are required.
82574 GbE Controller—Interconnects
60
8. Until new data is written to the FLSWDATA register, the Flash clock is paused.
9. Once data is written to the FLSWDATA by the software, the DONE bit in the
FLSWCTL register is cleared and is set after hardware writes it to the Flash.
10. After all bytes are written to the Flash, hardware completes the cycle on the SPI
bus and sets the WRDONE bit in the FLSWCTL register indicating that the entire
burst has completed.
3.3.8.6 Flash Programming Flow of S0 and S1
Other than initial programming of the Flash device, software and firmware should not
access the configuration sectors: S0 and S1. Any access to the configuration flow
should go to the Shadow RAM via the EEPROM interface registers.
3.4 System Management Bus (SMBus)
Note: The NC-SI and SMBus interfaces cannot be used together in the same implementation.
One or the other is selected by the NVM image and loaded into the Flash.
SMBus is a low speed (100 KHz) serial bus used to connect various components in a
system for manageability purposes. SMBus is used as an interface to pass traffic
between the Manageability Controller (MC) and the 82574. The interface can also be
used to enable the MC to configure the 82574’s filters and management related
capabilities. Any device on the bus can be a master or a slave.
The SMBus uses two primary signals: SMBCLK and SMBDAT, to communicate. the
82574's SMB_CLK and SMB_DATA pins correspond to these signals. Both of these
signals float high with board-level pull-ups.
The SMBus specification has defined various types of message protocols composed of
individual bytes. The message protocols supported by the 82574 are described in
section 8.0.
For more details about SMBus, see the SMBus specification and section 8.0.
3.5 NC-SI
The NC-SI interface in the 82574 is a connection to an external MC. It operates as a
single interface with an external MC, where all traffic between the 82574 and the MC
flows through the interface. See section 8.0 for more details.
Note: The NC-SI and SMBus interfaces cannot be used together in the same implementation.
One or the other is selected by the NVM image and loaded into the Flash.
Note: It is recommended that the MC turn off flow control packet reception on its MAC to
prevent the pause effect from a flow control packet that might arrive from the LAN.
61
Interconnects—82574 GbE Controller
Figure 8. NC-SI Interface
3.5.1 Interface Specification
The 82574L NC-SI interface meets the RMII Specification, Rev. 1.2 as a PHY-side
device.
The following NC-SI capabilities are not supported by the 82574:
• Collision Detection - The interface supports only full-duplex operation.
• MDIO - MDIO/MDC management traffic is not passed on NC-SI.
• Magic packets - Magic packets are not detected at the 82574 NC-SI receive end.
• Flow-control - The 82574L doesn't support flow control on this interface.
3.5.2 Electrical Characteristics
The 82574L complies with the electrical characteristics defined in the RMII
specification. However, the 82574 is not 5 V dc tolerance and requires that signals
conform to 3.3 V dc signaling.
The 82574L dynamically drives its NC-SI output signals (NC-SI_DV and NC-SI_RX) as
required by the sideband protocol:
• At power up, the 82574 floats the NC-SI outputs.
• The 82574L drives the NC-SI outputs as configured by the MC by the Select
Package and Deselect Package commands.
MAC - MEDIA ACCESS CONTROL
RECONCILIATION
PCS
PMA
PMD
NC-SI
MDI
GMII
MC 82574L
LLC - LOGICAL LINK CONTROL
MAC - MEDIA ACCESS CONTROL
RECONCILIATION
MEDIUM
MAC - MEDIA ACCESS CONTROL
RECONCILIATION
82574 GbE Controller—Initialization
62
4.0 Initialization
4.1 Introduction
This chapter discusses initialization steps. This includes:
• General hardware power-up state
• Basic device configuration
• Initialization of transmit and receive operation
• Link configuration and software reset capability
• Statistics initialization
4.2 Reset Operation
The 82574L reset sources are as follows:
• Internal Power On Reset- The 82574L has an internal mechanism for sensing the
power pins. Once power is up and stable, the 82574 implements an internal reset.
This reset acts as a master reset of the entire chip. It is level sensitive, and while it
is 0b holds all of the registers in reset. Internal Power On Reset is an indication that
device power supplies are all stable. Internal Power On Reset changes state during
system power up.
• PE_RST_N - Indicates that both the power and the PCIe clock sources are stable; a
value of 0b indicates reset active. This pin asserts an internal reset also after a
D3cold exit. Most units are reset on the rising edge of PE_RST_N. The only
exception is the PCIe unit, which is kept in reset while PE_RST_N is active.
• Device Disable/Dr Disable - The 82574L enters a device disable mode when the
DEV_OFF_N pin is asserted without shutdown (see Section 5.4.4.4). The 82574L
enters Dr disable mode when certain conditions are met in the Dr state (see
Section 5.4.4.3).
• In-band PCIe reset - The 82574L generates an internal reset in response to a
Physical Layer (PHY) message from PCIe or when the PCIe link goes down (entry to
polling or detect state). This reset is equivalent to PCI reset in previous (PCI) GbE
controllers.
• D3hotD0 transition - This is also known as ACPI reset. The 82574L generates an
internal reset on the transition from D3hot power state to D0 (caused after
configuration writes from D3 to D0 power state). Note that this reset is per function
and resets only the function that transitioned from D3hot to D0.
• Software Reset - Software can reset the 82574 by writing the Device Reset bit of
the Device Control (CTRL.RST) register. The 82574L re-reads the per-function NVM
fields after a software reset. Bits that are normally read from the NVM are reset to
their default hardware values. Note that this reset is per function and resets only
the function that received the software reset. PCI configuration space
(configuration and mapping) of the device is unaffected.
63
Initialization—82574 GbE Controller
• Force TCO - This reset is generated when manageability logic is enabled. It is only
generated if the reset on the Force TCO bit of the NVM's Management Control word
is 1b. In pass-through mode it is generated when receiving a Force TCO SMBus
command with bit 1 or bit 7 set.
• EEPROM Reset - Writing a 1b to the EEPROM Reset bit of the Extended Device
Control (CTRL_EXT.EE_RST) register causes the 82574 to re-read the per-function
configuration from the NVM, setting the appropriate bits in the registers loaded by
the NVM.
• PHY Reset - Software can write a 1b to the PHY Reset bit of the Device Control
(CTRL.PHY_RST) register to reset the internal PHY.
The resets affect the following registers and logic:
Table 29. 82574L Resets
Notes:
1. If D3cold is not supported, the wake-up context is reset (PME_Status and PME_En
bits).
2. Refers to bits in the Wake-Up Control (WUC) register that are not part of the wake-
up context (the PME_En and PME_Status bits).
3. The Wake-Up Status (WUS) registers include the following:
—WUS register.
—Wake-up packet length.
— Wake-up packet memory.
Reset Name
Reset
activation
Internal
Power
On
Reset
PE_
RST_
N
Device/Dr
Disable
In-band
PCIe
Reset
D3hot
D0 SW
Reset Force
TCO EE
Reset PHY
Reset Notes
PCIe Data Path √√ √ √
Load NVM √√ √ √ 6√√√
PCI Config
Registers RO √√ √ √
PCI Config
Registers RW √√ √ √ √
Data path √√ √ √ √√√ 5
Wake Up (PM)
Context √1√
Wake Up
Control
Register √√ 2
Wake Up
Status
Registers √√ 3
MNG Unit √√
Wake Up
Management
Registers √√ √ √ √√√ 4
PHY √√ √ √ √ √ √
Strapping Pins √√ √ √
82574 GbE Controller—Initialization
64
4. The Wake-Up Management (WUM) registers include the following:
— Wake-up filter control.
— IP address Valid.
— IPv4 address table
— IPv6 address table
— Flexible filter length table
— Flexible filter mask table
5. The following register fields do not follow the previously mentioned general rules:
— Packet Buffer Allocation (PBA) - reset on Internal Power On Reset only.
— Packet Buffer Size (PBS) - reset on Internal Power On Reset only.
— LED configuration registers.
—The Aux Power Detected bit in the PCIe Device Status register is reset on
Internal Power On Reset and PCIe Power Good only.
— FLA - reset on Internal Power On Reset only.
6. The NVM is loaded only when the LAN function exits D3hot state.
In situations where the device is reset using the software reset CTRL.RST, the TX data
lines will be forced to all zeros. This causes a substantial number of symbol errors to be
detected by the link partner.
4.3 Power Up
4.3.1 Power-Up Sequence
Figure 9 through Figure 15 shows the 82574’s power-up sequencing.
Figure 9 shows a high-level view of the power sequence, while Figure 10 through
Figure 15 provides a more detailed description of each state.
65
Initialization—82574 GbE Controller
Figure 9. 82574L Power Up - General Flow
A B
Flash EEPROM
Start
Power-On-Reset
Load EEPROM
Load Flash
C
Initialize manageability
and PHY
D
Read NVM after PERST#
de-assertion
E
Initialize PCIe and PHY
Bring up PCIe link
82574 GbE Controller—Initialization
66
Figure 10. 82574L Initialization - Power-On Reset
Stage
Comments
Duration (ms) Note
Legend
Power ramp up
(3.3 V dc, 1.9 V dc,
1.05 V dc)
Start
Xosc stabe
From power-up
<10
Internal power-on-
reset triggers
From power-up
<50
82574 samples NVMT
strapping
Determine NVM type
0
AB
Flash EEPROM
Start
67
Initialization—82574 GbE Controller
Figure 11. 82574L Initialization - Flash Load
Notes:
1. A 4 KB sector is read in a single burst, so the packet overhead is negligible. The
rate is 4 KB x 8 bits / 15.625 Mb/s = 2.1 ms.
2. The shadow RAM is read at the rate of one word every ~3 clocks of 62.5 MHz, or
~50 ns per word. The 64 words are read in 3.2 ms.
3. Clear write protection is required for an SST* Flash only. The instruction codes that
are required to initiate are hardwired in the design as defined by SST 25xxx Flash
family: code 0x50 for write status enable and code 0x01 for status write. The
82574L writes a data of 0x00 to the status word which clears all protection.
Software accesses to the Flash are not executed until this step completes.
Read signature at word
0x12
~0
Load sector 0 to Shadow
RAM
Set EEC.SHADV & clear
EEC.SEL1VAL
~2.1 1
Read signature at word
2K+0x12
~0
Load base area (0x00-
0x40) from Shadow
RAM
~0.0032 2
A
Good
signature
Bad
signature
C
Good
signature
Bad
signature
Load sector 1 to Shadow
RAM
Set EEC.SHADV & set
EEC.SEL1VAL
~2.1 1
82574 set to default
values
Set EEC.Auto_RD
0
Clear Write Protection
Set Flash write status
enable and write status
0.008 3
82574 GbE Controller—Initialization
68
Figure 12. 82574L Initialization - EEPROM Load
Each word is read separately using a 5-byte command (1 byte instruction, 2 byte
address, and 2 byte data). Total time at 2 Mb/s is 64 words x 5 bytes x 8 bits/2 Mb/s =
1.28 ms. The rate is 20 μs per word.
Detect Address length of
1B or 2B based on
signature
~0
Load base area (0x00-
0x40) from EEPROM
Set EEC.Auto_RD
~1.28 3
B
Good
signature
Bad
signature
C
82574 set to default
values
Set EEC.Auto_RD
0
69
Initialization—82574 GbE Controller
Figure 13. 82574L Initialization - PHY and Manageability
Each PCIe register write takes ~20 PCIe clocks (31.25 MHz) per table entry <=>
640 ns per Dword. Each PHY register write takes those 20 clocks + 64 MDC cycles on
the MDIO interface (2.5 MHz) => 26.24 ms per Dword. Therefore, the total is 640 ns x
4 + 26.24 ms x 16 = 422 ms.
Each PCIe register write takes ~20 PCIe clocks (31.25 MHz) per table entry <=>
640 ns per Dword. Therefore, the bottleneck is the EEPROM at 40 ms per Dword. Each
PHY register write takes those 20 clocks + 64 MDC cycles on the MDIO interface (2.5
MHz) => 26.24 ms per Dword. Therefore, the bottleneck is the EEPROM at 40 ms per
Dword. The 16+4 entries take 20 Dwords x 40 ms = 0.8 s.
Enable manageability
and/or wake up based
on NVM configuration
Based on MNG_Mode
bits in NVM word 0x0F
~0
Load Extended
Configuration from
EEPROM
Clear SW/HW NVM
semaphore
~0.8 5
C
Need to load
Extended
Configuration
D
82574 set to default
values
Clear SW/HW NVM
semaphore
0
Enable the PHY if
needed
PHY was inactive up to
now
11
No need to load
Extended
Configuration
Load Extended
Configuration from
Shadow RAM
Clear SW/HW NVM
semaphore
~0.42 4
Flash EEPROM
82574 GbE Controller—Initialization
70
Figure 14. 82574L Initialization - NVM Load After PE_RST_N
PERST# is de-asserted
by the platform
PHY is powered down
~0
D
NVMT strapping is
sampled
Determine NVM type
~0
Flash EEPROMNo NVM
Load base area (0x00-
0x40) from Shadow
RAM
Set EEC.Auto_RD
~0.0032 2
Load base area (0x00-
0x40) from EEPROM
Set EEC.Auto_RD
~1.28 3
82574 set to default
values
Set EEC.Auto_RD
0
E
Check valid Shadow and
signature
~0
Detect Address length of
1B or 2B based on
signature
~0
71
Initialization—82574 GbE Controller
Figure 15. 82574L Initialization - PHY and PCIe
Load Extended
Configuration from
EEPROM
Clear SW/HW NVM
semaphore
~0.8 5
E
Enable the PHY
PHY was in power-down
during NVM load
11
Load Extended
Configuration from
Shadow RAM
Clear SW/HW NVM
semaphore
~0.42 4
Flash EEPROM
Start PCIe link training
Must start < 20 µs after
PERST# de-assertion
PCIe link ready to
accept configuration
requests
Must start < 100 µs
after PERST#
82574 GbE Controller—Initialization
72
4.3.2 Timing Diagram
Figure 16. Power-Up Timing Diagram
Table 30. Notes to Power-Up Timing Diagram
D-State D0u
NVM Load
D0a
PHY State
PCIe Link up L0
Manageability /
Wake
4
5
7
Dr
8
9
10
3
Power
Power-On-Reset
(internal)
2
PCIe reference clock
PERST#
Xosc
1
6
txo
g
tee tee
11 12
tpgtrn
13
tpgrestpgcfg
tPWRGD
-CLK
tPVP
GL
tpp
g
Auto
Read
Ext.
Conf.
Auto
Read
Ext.
Conf.
Powered-down Active / Down
Note
1 Xosc is stable txog after power is stable
2Internal reset is released after all power supplies are good and tppg after Xosc
is stable.
3An NVM read starts on the rising edge of the internal reset or Internal Power
On Reset#.
4 After reading the NVM, PHY might exit power down mode.
5 APM wake up and/or manageability might be enabled based on NVM contents.
6The PCIe reference clock is valid tPWRGD-CLK before the de-assertion of
PE_RST_N (according to PCIe specification).
7PE_RST_N is de-asserted tPVPGL after power is stable (according to PCIe
specification).
8De-assertion of PE_RST_N causes the NVM to be re-read, asserts PHY power-
down, and disables Wake Up.
9 After reading the NVM, PHY exits power-down mode.
10 Link training starts after tpgtrn from PE_RST_N de-assertion.
11 A first PCIe configuration access might arrive after tpgcfg from PE_RST_N de-
assertion.
12 A first PCI configuration response can be sent after tpgres from PE_RST_N de-
assertion
13 Writing a 1b to the Memory Access Enable bit in the PCI Command register
transitions the device from D0u to D0 state.
73
Initialization—82574 GbE Controller
4.4 Global Reset (PE_RST_N, PCIe In-Band Reset)
4.4.1 Reset Sequence
Figure 17 and Figure 18 show the 82574's sequence following global reset (PE_RST_N
de-assertion or PCIe in-band reset) and until the device is ready to accept host
commands.
Figure 17. 82574L Global Reset - NVM Load
Reset (PE_RST_# de-
assertion or in-band)
PHY is powered down
~0
NVMT strapping is
sampled
Determine NVM type
~0
Flash EEPROMNo NVM
Load base area (0x00-
0x40) from Shadow
RAM
Set EEC.Auto_RD
~0.0032 2
Load base area (0x00-
0x40) from EEPROM
Set EEC.Auto_RD
~1.28 3
82574 set to default
values
Set EEC.Auto_RD
0
A
Check valid Shadow and
signature
~0
Detect Address length of
1B or 2B based on
signature
~0
82574 GbE Controller—Initialization
74
Figure 18. 82574L Global Reset - PHY and PCIe
4.4.2 Timing Diagram
The following timing diagram shows the 82574’s behavior through a PE_RST_N reset.
Load Extended
Configuration from
EEPROM
Clear SW/HW NVM
semaphore
~0.8 5
A
Enable the PHY
PHY was in power-down
during NVM load
11
Load Extended
Configuration from
Shadow RAM
Clear SW/HW NVM
semaphore
~0.42 4
Flash EEPROM
Start PCIe link training
Must start < 80 µs after
PERST# de-assertion
PCIe link ready to
accept configuration
requests
Must start < 100 µs
after PERST#
75
Initialization—82574 GbE Controller
Figure 19. Global Reset Timing Diagram
Table 31. Notes to Global Reset Timing Diagram
D-State D0u
NVM Load
D0a
PHY State
PCIe Link up L0
Wake
2
1
Dr
4
5
7
PCIe reference
clock
PERST#
tee
8 9
tpgtrn
10
tpgrestpgcfg
Auto
Read
Ext.
Conf.
Active Active / Down
tclkpg
L0
Any mode APM
D0a
3tPWRGD-CLK
6
Note
1The system must assert PE_RST_N before stopping the PCIe reference clock. It
must also wait tl2clk after link transition to L2/L3 before stopping the reference
clock.
2On assertion of PE_RST_N, the 82574 transitions to Dr state and the PCIe link
transition to electrical idle. The PHY state is defined by the wake and
manageability configuration.
3The system starts the PCIe reference clock tPWRGD-CLK before de-assertion
PE_RST_N.
4De-assertion of PE_RST_N causes the NVM to be re-read, asserts PHY power-
down, and disables wake up.
5After reading the NVM base area, PHY reset is de-asserted. APM wake might be
enabled.
6Link training starts after the NVM was fully read (including extended
configuration if needed).
7 Link training starts after tpgtrn from PE_RST_N de-assertion.
8A first PCIe configuration access might arrive after tpgcfg from PE_RST_N de-
assertion.
9A first PCI configuration response can be sent after tpgres from PE_RST_N de-
assertion.
10 Writing a 1b to the Memory Access Enable bit in the PCI Command register
transitions the device from D0u to D0 state.
82574 GbE Controller—Initialization
76
4.5 Timing Parameters
4.5.1 Timing Requirements
The 82574L requires the following start-up and power state transitions.
Table 32. Timing Requirements
4.5.2 MDIO and NVM Semaphore
The MDIO and NVM semaphore mechanism resolved possible conflicts between
software and hardware access to the MDIO and NVM (the latter applies only to software
accesses through the EERD register). The mechanism does not block software accesses
to MDIO or the NVM, therefore programmers can enable software to use or ignore this
process at will. For example, software might track the hardware state through other
means (such as, a software state machine) and avoid any MDIO and NVM accesses
when hardware is in configuration states. However, hardware must comply with the
protocol.
The EXTCNF_CTRL.MDIO/NVM SW Ownership bit, EXTCNF_CTRL.MDIO MNG Ownership
bit and the EXTCNF_CTRL.MDIO/NVM HW Ownership bit provide a mechanism for
software, manageability and hardware entities to arbitrate for accesses to MDIO and
NVM. Software arbitration for NVM accesses is only required when done through the
EERD register. A request for ownership is registered by writing a 1b into the respective
bit (software writes to the MDIO/NVM SW Ownership bit, manageability writes to the
MDIO MNG Ownership bit and hardware writes to the MDIO/NVM HW Ownership). The
requesting agent is granted access when the same bit is read as 1b (access is not
granted as long as the bit is 0b). The MDIO/NVM SW Ownership and the MDIO/NVM HW
Ownership bits are cleared on reset, while the MDIO MNG Ownership bit is reset only by
LAN_PWR_GOOD (or if the firmware clears it). The 82574 guarantees that at any given
time at most only one bit is 1b. Access is granted when a bit is actually written with 1b
and the other bits are 0b. Once the access completes, the controlling agent must write
a 0b to its ownership bit to enable accesses by the other agents.
The 82574L’s hardware sets the bit while loading the extended configuration area.
Parameter Description Min Max Notes
txog Xosc stable from power stable 10 ms
tPWRGD-
CLK PCIe clock valid to PCIe power good 100 μs - According to PCIe specification.
tPVPGL Power rails stable to PCIe PE_RST_N
inactive 100 ms - According to PCIe specification.
Tpgcfg External PE_RST_N signal to first
configuration cycle. 100 ms According to PCIe specification.
td0mem Device programmed from D3h to D0
state to next device access 10 ms According to PCI power
management specification.
tl2pg L2 link transition to PE_RST_N
assertion 0 ns According to PCIe specification.
tl2clk L2 link transition to removal of PCIe
reference clock 100 ns According to PCIe specification.
Tclkpg PE_RST_N assertion to removal of PCIe
reference clock 0 ns According to PCIe specification.
Tpgdl PE_RST_N assertion time 100 μs According to PCIe specification.
77
Initialization—82574 GbE Controller
4.6 Software Initialization Sequence
The following sequence of commands is typically issued to the device by the software
device driver in order to initialize the 82574 to normal operation. The major
initialization steps are:
1. Disable Interrupts - see Interrupts during initialization.
2. Issue Global Reset and perform General Configuration - see Global Reset and
General Configuration.
3. Setup the PHY and the link - see Link Setup Mechanisms and Control/Status Bit
Summary.
4. Initialize all statistical counters - see Initialization of Statistics.
5. Initialize Receive - see Receive Initialization.
6. Initialize Transmit - see Transmit Initialization.
7. Enable Interrupts - see Interrupts during initialization.
82574 GbE Controller—Initialization
78
4.6.1 Interrupts During Initialization
Most drivers disable interrupts during initialization to prevent re-entrancy. Interrupts
are disabled by writing to the IMC register. Note that the interrupts need to be disabled
also after issuing a global reset, so a typical driver initialization flow is:
1. Disable interrupts
2. Issue a global reset
3. Disable interrupts (again)
4. …
After the initialization completes, a typical driver enables the desired interrupts by
writing to the IMS register.
4.6.2 Global Reset and General Configuration
Device initialization typically starts with a global reset that puts the device into a known
state and enables the software device driver to continue the initialization sequence.
Several values in the Device Control (CTRL) register need to be set at power up or after
a device reset for normal operation.
• Full duplex should be set per interface negotiation (if done in software), or is set by
the hardware if the interface is auto-negotiating. This is reflected in the Device
Status register in the auto-negotiating case. A default value is loaded from the
NVM.
• Speed is determined via auto-negotiation by the PHY, or forced by software if the
link is forced. Status information for speed is also readable in STATUS.
• ILOS should normally be set to 0b.
If using XOFF flow control, program the FCAH, FCAL, and FCT registers. If not, they
should be written with 0x0.
GCR bit 22 should be set to 1b by software during initialization.
4.6.3 Link Setup Mechanisms and Control/Status Bit Summary
4.6.3.1 PHY Initialization
Refer to the PHY documentation for the initialization and link setup steps. The device
driver uses the MDIC register to initialize the PHY and setup the link.
4.6.3.2 MAC/PHY Link Setup
This section summarizes the various means of establishing proper MAC/PHY link
setups, differences in MAC CTRL register settings for each mechanism, and the relevant
MAC status bits. The methods are ordered in terms of preference (the first mechanism
being the most preferred).
• MAC settings automatically based on duplex and speed resolved by PHY.
(CTRL.FRCDPLX = 0b, CTRL.FRCSPD = 0b, CTRL.ASDE = 0b)
— CTRL.FD - Don't care; duplex setting is established from PHY's internal
indication to the MAC (FDX) after PHY has auto-negotiated a successful link-up.
— CTRL.SLU - Must be set to 1b by software to enable communications between
MAC and PHY.
— CTRL.RFCE - Must be set by software after reading flow control resolution from
PHY registers.
79
Initialization—82574 GbE Controller
— CTRL.TFCE - Must be set by software after reading flow control resolution from
PHY registers.
— CTRL.SPEED - Don't care; speed setting is established from PHY's internal
indication to the MAC (SPD_IND) after PHY has auto-negotiated a successful
link-up.
— STATUS.FD - Reflects the actual duplex setting (FDX) negotiated by the PHY
and indicated to the MAC.
— STATUS.LU - Reflects link indication (LINK) from the PHY qualified with
CTRL.SLU (set to 1b).
— STATUS.SPEED - Reflects actual speed setting negotiated by the PHY and
indicated to the MAC (SPD_IND).
• MAC duplex setting automatically based on resolution of PHY, software-
forced MAC/PHY speed. (CTRL.FRCDPLX = 0b, CTRL.FRCSPD = 1b,
CTRL.ASDE = don't care)
— CTRL.FD - Don't care; duplex setting is established from PHY's internal
indication to the MAC (FDX) after PHY has auto-negotiated a successful link-up.
— CTRL.SLU - Must be set to 1b by software to enable communications between
the MAC and PHY.
— CTRL.RFCE - Must be set by software after reading flow control resolution from
PHY registers.
— CTRL.TFCE - Must be set by software after reading flow control resolution from
the PHY registers.
— CTRL.SPEED - Set by software to desired link speed (must match speed setting
of PHY).
— STATUS.FD - Reflects the actual duplex setting (FDX) negotiated by the PHY
and indicated to MAC.
— STATUS.LU - Reflects link indication (LINK) from the PHY qualified with
CTRL.SLU (set to 1b).
— STATUS.SPEED - Reflects MAC forced speed setting written in CTRL.SPEED.
• MAC duplex and speed settings forced by software based on resolution of
PHY. (CTRL.FRCDPLX = 1b, CTRL.FRCSPD = 1b, CTRL.ASDE = don't care)
— CTRL.FD - Set by software based on reading PHY status register after the PHY
has auto-negotiated a successful link-up.
— CTRL.SLU. - Must be set to 1b by software to enable communications between
the MAC and PHY.
— CTRL.RFCE - Must be set by software after reading flow control resolution from
the PHY registers.
— CTRL.TFCE - Must be set by software after reading flow control resolution from
the PHY registers.
— CTRL.SPEED - Set by software based on reading PHY status register after the
PHY has auto-negotiated a successful link-up.
— STATUS.FD - Reflects the MAC forced duplex setting written to CTRL.FD.
— STATUS.LU - Reflects link indication (LINK) from the PHY qualified with
CTRL.SLU (set to 1b).
— STATUS.SPEED - Reflects MAC forced speed setting written in CTRL.SPEED.
82574 GbE Controller—Initialization
80
• MAC/PHY duplex and speed settings both forced by software (fully-forced
link setup). (CTRL.FRCDPLX = 1b, CTRL.FRCSPD = 1b, CTRL.SLU = 1b)
— CTRL.FD - Set by software to desired full-/half- duplex operation (must match
duplex setting of the PHY).
— CTRL.SLU - Must be set to 1b by software to enable communications between
the MAC and PHY. The PHY must also be forced/configured to indicate positive
link indication (LINK) to the MAC.
— CTRL.RFCE - Must be set by software to the desired flow-control operation
(must match flow-control settings of the PHY).
— CTRL.TFCE - Must be set by software to the desired flow-control operation
(must match flow-control settings of the PHY).
— CTRL.SPEED - Set by software to desired link speed (must match speed setting
of the PHY).
— STATUS.FD - Reflects the MAC duplex setting written by software to CTRL.FD.
— STATUS.LU - Reflects 1b (positive link indication LINK from PHY qualified with
CTRL.SLU).
Note: Since both CTRL.SLU and the PHY link indication LINK are forced, this bit set does not
guarantee that operation of the link has been truly established.
— STATUS.SPEED - Reflects MAC forced speed setting written in CTRL.SPEED.
4.6.4 Initialization of Statistics
Statistics registers are hardware-initialized to values as detailed in each particular
register's description. The initialization of these registers begins at transition to D0
active power state (when internal registers become accessible, as enabled by setting
the Memory Access Enable field of the PCIe Command register), and is guaranteed to
complete within 1 ms of this transition. Access to statistics registers prior to this
interval might return indeterminate values.
All of the statistical counters are cleared on read and a typical software device driver
reads them (thus making them zero) as a part of the initialization sequence.
4.6.5 Receive Initialization
Program the receive address register(s) per the station address. This can come from
the NVM or from any other means, for example, on some systems, this comes from the
system EEPROM not the NVM on a Network Interface Card (NIC).
Set up the Multicast Table Array (MTA) per software. This generally means zeroing all
entries initially and adding in entries as requested.
Program the interrupt mask register to pass any interrupt that the software device
driver cares about. Suggested bits include RXT, RXO, RXDMT and LSC. There is no
reason to enable the transmit interrupts.
Program RCTL with appropriate values. If initializing it at this stage, it is best to leave
the receive logic disabled (EN = 0b) until the receive descriptor ring has been
initialized. If VLANs are not used, software should clear the VFE bit. Then there is no
need to initialize the VFTA array. Select the receive descriptor type. Note that if using
the header split RX descriptors, tail and head registers should be incremented by two
per descriptor.
81
Initialization—82574 GbE Controller
4.6.5.1 Initialize the Receive Control Register
To properly receive packets requires simply that the receiver is enabled. This should be
done only after all other setup is accomplished. If software uses the Receive Descriptor
Minimum Threshold Interrupt, that value should be set.
The following should be done once per receive queue:
• Allocate a region of memory for the receive descriptor list.
• Receive buffers of appropriate size should be allocated and pointers to these
buffers should be stored in the descriptor ring.
• Program the descriptor base address with the address of the region.
• Set the length register to the size of the descriptor ring.
• If needed, program the head and tail registers. Note: the head and tail pointers are
initialized (by hardware) to zero after a power-on or a software-initiated device
reset.
• The tail pointer should be set to point one descriptor beyond the end.
4.6.6 Transmit Initialization
Program the TXDCTL register with the desired TX descriptor write-back policy.
Suggested values are:
• GRAN = 1b (descriptors)
•WTHRESH = 1b
• All other fields 0b.
Program the TCTL register. Suggested configuration:
• CT = 0x0F (16d collision)
• COLD: HDX = 511 (0x1FF); FDX = 63 (0x03F)
•PSP = 1b
•EN=1b
• All other fields 0b
The following should be done once per transmit queue:
• Allocate a region of memory for the transmit descriptor list.
• Program the descriptor base address with the address of the region.
• Set the length register to the size of the descriptor ring.
• If needed, program the head and tail registers.
Note: Note: the head and tail pointers are initialized (by hardware) to zero after a power-on
or a software-initiated device reset.
82574 GbE Controller—Initialization
82
Program the TIPG register with the following (decimal) values to get the minimum legal
IPG:
•IPGT = 8
•IPGR1 = 2
•IPGR2 = 10
Note: IPGR1 and IPGR2 are not needed in full-duplex, but it is easier to always program them
to the values listed.
Initialize the transmit descriptor registers (TDBAL, TDBAH, TDL, TDH, and TDT).
83
Initialization—82574 GbE Controller
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82574 GbE Controller—Power Management and Delivery
84
5.0 Power Management and Delivery
The 82574L supports the Advanced Configuration and Power Interface (ACPI 2.0)
specification as well as Advanced Power Management (APM). This section describes
how power management is implemented in the 82574.
Implementation requirements were obtained from the following documents:
• PCI Bus Power Management Interface Specification .................................Rev 1.1
• PCI Express Base Specification .............................................................Rev.1.1
• ACPI Specification ...............................................................................Rev 2.0
• PCI Express Card Electromechanical Specification....................................Rev 1.1
5.1 Assumptions
The following assumptions apply to the implementation of power management for the
82574.
• The software device driver sets up the filters prior to the system transition of the
82574 to a D3 state.
• Prior to transition from D0 to the D3 state, the operating system ensures that the
software device driver has been disabled. See Section 5.4.4.2.3 for the 82574
behavior on D3 entry.
• No wake up capability, except APM wake up if enabled in the NVM, is required after
the system puts the 82574 in D3 state and then returns the 82574 to D0.
•If the APMPME bit in the Wake Up Control (WUC) register is 1b, it is permissible to
assert PE_WAKE_N even when PME_En is 0b.
5.2 Power Consumption
Table 9 1 and Table 92 list power consumption in various modes (see Section 12.5). The
following sections describe the requirements in specific power states.
85
Power Management and Delivery—82574 GbE Controller
5.3 Power Delivery
82574L operates from the following power rails:
• A 3.3 V dc power rail for internal power regulation and for periphery. The 3.3 V dc
should be supplied by an external power source.
• A 1.9 V dc power rail.
• A 1.05 V dc power rail.
5.3.1 The 1.9 V dc Rail
The 1.9 V dc rail is used for core and I/O functions. It also feeds internal regulators to a
lower 1.05 V dc core voltage. The 1.9 V dc rail can be generated in one of two ways:
• An external power supply not dependent on support from the 82574. For example,
the platform designer might choose to route a platform-available 1.9 V dc supply to
the 82574.
• Internal voltage regulator solution, where the control logic for the power transistor
is embedded in the 82574, while the power transistor is placed externally. Control
is done using the CTRL18 pin.
5.3.2 The 1.05 V dc Rail
The 1.05 V dc rail is used for core functions and can be generated in one of the
following ways:
• An external power supply not dependent on support from the 82574.
• Internal voltage regulator solution, where the control logic for the power transistor
is embedded in the 82574, while the power transistor is placed externally. Control
is done using the CTRL10 pin.
• A complete internal voltage regulator solution. The internal voltage regulator can
be disabled by the DIS_REG10 pin.
5.4 Power Management
5.4.1 82574L Power States
The 82574L supports D0 and D3 power states defined in the PCI Power Management
and PCIe specifications. D0 is divided into two sub-states: D0u (D0 Un-initialized), and
D0a (D0 active). In addition, the 82574 supports a Dr state that is entered when
PE_RST_N is asserted (including the D3cold state).
Figure 20 shows the power states and transitions between them.
82574 GbE Controller—Power Management and Delivery
86
Figure 20. Power Management State Diagram
5.4.2 Auxiliary Power Usage
If ADVD3WUC=1b, the 82574 uses the AUX_PWR indication that auxiliary power is
available to the controller, and therefore advertises D3cold wake up support. The
amount of power required for the function (which includes the entire NIC) is advertised
in the Power Management Data register, which is loaded from the NVM.
If D3cold is supported, the PME_En and PME_Status bits of the Power Management
Control/Status Register (PMCSR), as well as their shadow bits in the Wake Up Control
(WUC) register is reset only by the power up reset (detection of power rising).
The only effect of setting AUX_PWR to 1b is advertising D3cold wake up support and
changing the reset function of PME_En and PME_Status. AUX_PWR is a strapping option
in the 82574.
The 82574L tracks the PME_En bit of the Power Management Control / Status Register
(PMCSR) and the Auxiliary (AUX) Power PM Enable bit of the PCIe Device Control
register to determine the power it might consume (and therefore its power state) in the
D3cold state (internal Dr state).
Dr D0u
D0aD3
PE_RST_N de-
assertion and
EEPROM read
done
PE_RST_N
assertion
PE_RST_N
assertion
PE_RST_N
assertion
Write 11b
to power
state
Write 00b
to power
state
Enable
master or
slave access
Internal Power
On Reset
assertion
Hot (in-band)
Reset
87
Power Management and Delivery—82574 GbE Controller
The AUX Power PM Enable bit in the PCIe Device Control register determines if the
82574 complies with the auxiliary power regime defined in the PCIe specification. If
set, the 82574 might consume higher power for any purpose (such as, even if PME_En
is not set).
If the AUX Power PM Enable bit of the PCIe Device Control register is cleared, higher
power consumption is determined by the PCI-PM legacy PME_En bit in the Power
Management Control / Status Register (PMCSR).
Note: In the current implementation, the AUX Power PM Enable bit is hardwired to 0b.
5.4.3 Power Limits by Certain Form Factors
Table 33 lists the power limitations introduced by different form factors.
Table 33. Power Limits by Form Factor
1. This auxiliary current limit only applies when the primary 3.3 V dc voltage source is
not available (such as, the NIC is in a low power D3 state.
2. The 82574L exceeds the allowed power consumption in GbE speed. It therefore
cannot run from aux power, restricting the 82574 speed in Dr state.
The 82574L therefore implements two NVM bits to disable GbE operation in certain
cases:
1. The Disable 1000 NVM bit disables 1000 Mb/s operation under all conditions.
2. The Disable 1000 in non-D0a CSR bit disables 1000 Mb/s operation in non-D0a
states. If Disable 1000 in non-D0a is set, and the 82574 is at GbE speed on entry
to a non-D0a state, then the device removes advertisement for 1000 Mb/s and
auto-negotiates. The Disable 1000 in non-D0a bit is loaded from the NVM.
Note: The 82574L restarts link auto-negotiation each time it transitions from a state where
GbE speed is enabled to a state where GbE speed is disabled, or vice versa. For
example, if Disable 1000 in non-D0a is set but Disable 1000 is clear, the 82574 restarts
link auto-negotiation on transition from D0 state to D3 or Dr states.
5.4.4 Power States
5.4.4.1 D0 Uninitialized State
The D0u state is a low-power state used after PE_RST_N is de-asserted following a
power up (cold or warm), on hot reset (in-band reset through a PCIe physical layer
message), or on D3 exit.
Form Factor
LOM PCIe NIC (x1 connector)
Main 3 A @ 3.3 V dc 3 A @ 3.3 V dc
Auxiliary (aux enabled) 375 mA @ 3.3 V dc 375 mA @ 3.3 V dc
Auxiliary (aux disabled) 20 mA @ 3.3 V dc
82574 GbE Controller—Power Management and Delivery
88
When entering the D0u state, the 82574 disables all wake ups and asserts a reset to
the PHY while the NVM is being read. If the APM Mode bit in the NVM's Initialization
Control Word 2 is set, then APM wake up is enabled.
5.4.4.1.1 Entry into D0u state
D0u is reached from either the Dr state (on assertion of Internal PwrGd) or the D3hot
state (by configuration software writing a value of 00b to the Power State field of the
PCI-PM registers).
Asserting Internal PwrGd means that the entire state of the device is cleared, other
than sticky bits. The state is loaded from the NVM, followed by establishment of the
PCIe link. Once this is done, configuration software can access the device.
On a transition from the D3 to D0u state, the 82574’s PCI configuration space is not
reset. Per the PCI Power Management Specification (revision 1.1, Section 5.4),
software “will need to perform a full re-initialization of the function including its PCI
Configuration Space.”
5.4.4.2 D0active State
Once memory space is enabled, all internal clocks are activated and the 82574 enters
an active state. It can transmit and receive packets if properly configured by the
software device driver. The PHY is enabled or re-enabled by the software device driver
to operate / auto-negotiate to full-line speed/power if not already operating at full
capability. Any APM Wakeup previously active remains active. The software device
driver can deactivate APM Wakeup by writing to the WUC register, or activate other
wake-up filters by writing to the Wake Up Filter Control (WUFC) register.
Note: Fields that are auto-loaded from the NVM, like WUC.APME, should be configured
through an NVM setting, because D3 to D0 power state transition causes NVM auto-
read to reload those bits from the NVM.
5.4.4.2.1 Entry to D0a State
D0a is entered from the D0u state by writing a 1b to the Memory Access Enable or the
I/O Access Enable bit in the PCI Command register. The DMA, MAC, and PHY are
enabled. Manageability is also enabled if configured from the NVM.
5.4.4.2.2 D3 State (=PCI-PM D3hot)
When the system writes a 11b to the Power State field in the PMCSR, the 82574
transitions to D3. Any wake-up filter settings that were enabled before entering this
reset state are maintained. Upon transition to D3 state, the 82574 clears the Memory
Access Enable and I/O Access Enable bits of the PCI Command register, which disables
memory access decode. In D3, the 82574 only responds to PCI configuration accesses
and does not generate master cycles.
A D3 state is followed by either a D0u state (in preparation for a D0a state) or by a
transition to Dr state (PCI-PM D3cold state). To transition back to D0u, the system
writes a 00b to the Power State field of the PMCSR. Transition to Dr state is through
PE_RST_N assertion.
89
Power Management and Delivery—82574 GbE Controller
5.4.4.2.3 Entry to D3 State
Transition to the D3 state is through a configuration write to the Power State field of the
PCI-PM registers.
Prior to transition from D0 to the D3 state, the software device driver disables
scheduling of further tasks to the 82574, as follows:
• It masks all interrupts
• It does not write to the Transmit Descriptor Tail (TDT) register
• It does not write to the Receive Descriptor Tail (RDT) register
• Operates the master disable algorithm as defined in Section 3.1.3.10.
If wake-up capability is needed, the software device driver should set up the
appropriate wake-up registers and the system should write a 1b to the PME_En bit in
the PMCSR or to the AUX Power PM Enable bit of the PCIe Device Control register prior
to the transition to D3.
As a response to being programmed into the D3 state, the 82574 brings its PCIe link
into the L1 link state. As part of the transition into L1 state, the 82574 suspends
scheduling of new Transaction Layer Protocols (TLPs) and waits for the completion of all
previous TLPs it has sent. The 82574L clears the Memory Access Enable and I/O Access
Enable bits of the PCI Command register, which disables memory access decode. Any
receive packets that have not been transferred into system memory are kept in the
device (and discarded later on D3 exit). Any transmit packets that were not sent, can
still be transmitted (assuming the Ethernet link is up).
To reduce power consumption, if any of ASF manageability, APM wake, and PCI-PM PME
is enabled, the PHY auto-negotiates to a lower link speed on D3 entry (see
Section 5.4.4.2.3).
82574 GbE Controller—Power Management and Delivery
90
5.4.4.3 Dr State
Transition to Dr state is initiated on three occasions:
• At system power up - Dr state begins with the assertion of the internal power
detection circuit (Internal Power On Reset) and ends with the assertion of the
Internal Pwrgd signal (indicating that the system de-asserted its PCIe PE_RST_N
signal).
• At transition from a D0a state - During operation, the system might assert PCIe
PE_RST_N at any time. In an ACPI system, a system transition to the G2/S5 state
causes a transition from D0a to Dr state.
• At transition from a D3 state - The system transitions the device into the Dr state
by asserting PCIe PE_RST_N.
The 82574L meets the restrictions on using auxiliary power, defined in the PCI-PM
specification:
1. If wake is enabled (either APM wake, ACPI wake, or manageability), then the
82574 might consume up to 375 mA @ 3.3 V dc.
2. If wake is disabled, then the 82574 might consume up to 20 mA @ 3.3 V dc.
The restrictions apply to all cases of Dr state (power up, D3 entry, Dr entry from D0).
Note: When the wake configuration is unknown (for example, during power up before an NVM
read), the 82574 must meet the 20 mA limit.
The system might maintain PE_RST_N asserted for an arbitrary time. The de-assertion
(rising edge) of PE_RST_N causes a transition to D0u state.
Any Wake-up filter settings that were enabled before entering this reset state are
maintained.
5.4.4.3.1 Entry to Dr State
Dr entry on platform power up begins by asserting the internal power detection circuit
(Internal Power On Reset). The NVM is read and determines device configuration. If the
APM Enable bit in the NVM's Initialization Control Word 2 is set, then APM wake up is
enabled. The PHY and MAC states are determined by the state of manageability and
APM wake. To reduce power consumption, if manageability or APM wake is enabled, the
PHY auto-negotiates to a lower link speed on Dr entry (see Section 5.4.4.3.1). The
PCIe link is not enabled in Dr state following system power up (since PERS# is
asserted).
Entry to Dr state from D0a state is by asserting the PE_RST_N signal. An ACPI
transition to the G2/S5 state is reflected in a device transition from D0a to Dr state.
The transition might be orderly (for example, the designer selected the shut down
option), in which case the software device driver might have a chance to intervene. Or,
it might be an emergency transition (such as, power button override), in which case,
the software device driver is not notified.
To reduce power consumption, if any of manageability, APM wake or PCI-PM PME is
enabled, the PHY auto-negotiates to a lower link speed on D0a to Dr transition (see
Section 5.4.4.3.1).
Transition from D3 state to Dr state is done by asserting the PE_RST_N signal. Prior to
that, the system initiates a transition of the PCIe link from the L1 state to either the L2
or L3 state. The link enters L2 state if PCI-PM PME is enabled.
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Power Management and Delivery—82574 GbE Controller
5.4.4.4 Device Disable
For a LOM design, it might be desirable for the system to provide BIOS-setup capability
for selectively enabling or disabling LOM devices. This might allow the designers more
control over system resource-management, avoid conflicts with add-in NIC solutions,
etc. The 82574L provides support for selectively enabling or disabling it.
• Device Disable - the device is in a global power down state.
Device disable is initiated by asserting the asynchronous DEV_OFF_N pin. The
DEV_OFF_N pin has an internal pull-up resistor, so that it can be left not connected to
enable device operation.
While in device disable mode, the PCIe link is in L3 state. The PHY is in power-down
mode. All internal clocks are gated. Output buffers are tri-stated.
Asserting or de-asserting PCIe PE_RST_N does not have any effect while the device is
in device disable mode (for example, the device stays in the respective mode as long as
DEV_OFF_N is asserted). However, the device might momentarily exit the device
disable mode from the time PCIe PE_RST_N is de-asserted again and until the NVM is
read.
Note: Note to system designers: The DEV_OFF_N pin should maintain its state during system
reset and system sleep states. It should also insure the proper default value on system
power up. For example, a system designer could use a GPIO pin that defaults to 1b
(enable) and is on system suspend power (for example, it maintains state in S0-S5
ACPI states).
5.4.4.5 Link-Disconnect
In any of D0u, D0a, D3, or Dr states, the 82574 enters a link-disconnect state if it
detects a link-disconnect condition on the Ethernet link. Note that the link-disconnect
state is invisible to software (other than the Link Energy Detect bit state). In particular,
while in D0 state, software might be able to access any of the device registers as in a
link-connect state.
During link disconnect mode, the CCM PLL might be shut down. See Section 5.4.4.5.
5.4.5 Timing of Power-State Transitions
The following sections give detailed timing for the state transitions. In the diagrams the
dotted connecting lines represent the 82574 requirements, while the solid connecting
lines represent the 82574 guarantees.
The timing diagrams are not to scale. The clocks edges are shown to indicate running
clocks only, they are not used to indicate the actual number of cycles for any operation.
5.4.5.1 Transition From D0a to D3 and Back Without PE_RST_N
Figure 21 shows the 82574’s reaction to a D3 transition.
82574 GbE Controller—Power Management and Delivery
92
Figure 21. D3hot Transition Timing Diagram
Table 34. Notes to D3hot Timing Diagram
5.4.5.2 Transition From D0a to D3 and Back with PE_RST_N
Figure 22 shows the 82574’s reaction to a D3 transition.
PCIe Reference
Clock
PCIe PwrGd
PHY Reset
PCIe Link
Reading EEPROM Auto
Read
DState D3 D0u D0
Wake Up Enabled
Memory Access Enable
L0
D3 write
APM / SMBusAny mode
D0 Write
D0a
2
L1 L0
PHY Power State full fullpower-managed power-
managed
tee
1
3
4
5
6
7
td0me
m
Ext.
Conf.
Note Description
1 Writing 11b to the Power State field of the PMCSR transitions the 82574 to D3.
2 The system keeps the 82574 in D3 state for an arbitrary amount of time.
3 To exit D3 state the system writes 00b to the Power State field of the PMCSR.
4 APM wake up or SMBus mode can be enabled based on what is read in the NVM.
5After reading the NVM, reset to the PHY is de-asserted. The PHY operates at reduced-speed if APM
wake up or SMBus is enabled, else powered-down.
6 The system can delay an arbitrary time before enabling memory access.
7Writing a 1b to the Memory Access Enable bit or to the I/O Access Enable bit in the PCI Command
register transitions the 82574 from D0u to D0 state and returns the PHY to full-power/speed
operation.
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Power Management and Delivery—82574 GbE Controller
Figure 22. D3cold Transition Timing Diagram
Table 35. Notes to D3cold Timing Diagram
PCIe Reference
Clock
PCIe PwrGd
DState
PHY Power State
D0u
Reading EEPROM Auto
Read
D0a
power-managed full
Reset to PHY
(active low)
PCIe Link
Wake Up Enabled
Dr
11
Any mode APM/SMBus
full
D3 write
D0a D3
15
L0 L1 L2/L3 L0
1
2
6
13 14
3
4a
4b
12
Internal PCIe clock
(2.5 GHz)
Internal PwrGd
(PLL) 9
7
8
10
tee
tppg-
clkint
tpgtrn tpgres
tpgcfg
tclkp
r
tpgdl
tl2clk
tclkp
gtPWRGD-CLK
tl2pg
5
L0
Ext.
Conf.
Note Description
1Writing 11b to the Power State field of the PMCSR transitions the 82574 to D3. PCIe link transitions
to L1 state.
2The system can delay an arbitrary amount of time between setting D3 mode and transition the link to
an L2 or L3 state.
3 Following link transition, PE_RST_N is asserted.
4The system must assert PE_RST_N before stopping the PCIe reference clock. It must also wait tl2clk
after link transition to L2/L3 before stopping the reference clock.
5 On assertion of PE_RST_N, the 82574 transitions to Dr state.
6 The system starts the PCIe reference clock tPWRGD-CLK before de-asserting PE_RST_N.
7 The Internal PCIe clock is valid and stable tppg-clkint from PE_RST_N de-assertion.
8 The PCIe Internal PWRGD signal is asserted tclkpr after the external PE_RST_N signal.
9Asserting Internal PCIe PWRGD causes the NVM to be re-read, asserts PHY reset, and disables wake
up.
10 APM wake-up mode can be enabled based on what is read from the NVM.
11 After reading the NVM, PHY reset is de-asserted.
12 Link training starts after tpgtrn from PE_RST_N de-assertion.
13 A first PCIe configuration access might arrive after tpgcfg from PE_RST_N de-assertion.
14 A first PCI configuration response can be sent after tpgres from PE_RST_N de-assertion
15 Writing a 1b to the Memory Access Enable bit in the PCI Command register transitions the device
from the D0u to D0 state.
82574 GbE Controller—Power Management and Delivery
94
5.5 Wake Up
The 82574L supports two types of wake-up mechanisms:
• Advanced Power Management (APM) wake up
• PCIe power management wake up
The PCIe power management wake up uses the PE_WAKE_N pin to wake the system
up. The advanced power management wake up can be configured to use the
PE_WAKE_N pin as well.
5.5.1 Advanced Power Management Wake Up
Advanced power management wake up, or APM wake up, was previously known as
wake on LAN. It is a feature that has existed in the 10/100 Mb/s NICs for several
generations. The basic premise is to receive a broadcast or unicast packet with an
explicit data pattern, and then to assert a signal to wake up the system. In the earlier
generations, this was accomplished by using special signal that ran across a cable to a
defined connector on the motherboard. The NIC would assert the signal for
approximately 50 ms to signal a wake up. The 82574L uses (if configured to) an in-
band PM_PME message for this.
At power up, the 82574 reads the APM Enable bits from the NVM Initialization Control
Word 2 into the APM Enable (APME) bits of the WUC. These bits control enabling of APM
wake up.
When APM wake up is enabled, the 82574 checks all incoming packets for Magic
Packets. See Section 5.5.3.1.4 for a definition of Magic Packets.
Once the 82574 receives a matching wake-up packet, it:
•If the Assert PME On APM Wakeup (APMPME) bit is set in the WUC:
— Sets the PME_Status bit in the PMCSR and issues a PM_PME message (in some
cases, this might require asserting the PE_WAKE_N signal first to resume
power and clock to the PCIe interface).
• Stores the first 128 bytes of the packet in the WUPM.
• Sets the relevant <wake up packet type> received bit in the WUS.
The 82574L maintains the first wake-up packet received in the WUPM until the software
device driver writes a 1b to the Magic Packet Received MAG bit in the WUS.
Note: The WUPM latches on the first wake-up packet. Subsequent wake-up packets are not
saved until the programmer writes 1b to the relevant bit in the WUS. The best course of
action is to write a 1b to ALL of the WUC's bits, for example, set WUC = 0xFFFFFFFF.
Note: Full power-on reset also clears the WUC.
APM wake up is supported in all power states and only disabled if a subsequent NVM
read results in the APM Wake Up bit being cleared or software explicitly writes a 0b to
the APM Wake Up (APM) bit of the WUC register.
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Power Management and Delivery—82574 GbE Controller
5.5.2 PCIe Power Management Wake Up
The 82574L supports PCIe power management based wake ups. It can generate
system wake-up events from three sources:
• Reception of a Magic Packet*.
• Reception of a network wake-up packet.
• Detection of a link change of state.
Activating PCIe power management wake up requires the following steps:
• The software device driver programs the WUFC to indicate the packets it needs to
use to indicate wake up and supplies the necessary data to the Ipv4/v6 Address
Table (IP4AT, IP6AT) and the Flexible Filter Mask Table (FFMT), Flexible Filter
Length Table (FFLT), and the Flexible Filter Value Table (FFVT). It can also set the
Link Status Change Wake Up Enable (LNKC) bit in the WUFC to cause a wake up
when the link changes state.
• The operating system (at configuration time) writes a 1b to the PME_EN bit of the
PMCSR (bit 8).
Normally, after enabling wake up, the operating system writes a 11b to the lower two
bits of the PMCSR to put the 82574 into a low-power mode.
Once wake up is enabled, the 82574 monitors incoming packets, first filtering them
according to its standard address filtering method, then filtering them with all of the
enabled wake-up filters. If a packet passes both the standard address filtering and at
least one of the enabled wake-up filters, the 82574:
• Sets the PME_Status bit in the PMCSR.
•If the PME_En bit in the PMCSR is set, asserts PE_WAKE_N.
• Stores the first 128 bytes of the packet in the WPM.
• Sets one or more of the Received bits in the WUS. (the 82574 set more than one
bit if a packet matches more than one filter.)
If enabled, a link state change wake up causes similar results, setting PME_Status,
asserting PE_WAKE_N and setting the Link Status Changed (LNKC) bit in the WUS
when the link goes up or down.
PE_WAKE_N remains asserted until the operating system either writes a b1 to the
PME_Status bit of the PMCSR or writes a 0b to the PME_EN bit.
After receiving a wake-up packet, the 82574 ignores any subsequent wake-up packets
until the software device driver clears all of the Received bits in the WUS. It also
ignores link change events until the software device driver clears the Link Status
Changed (LNKC) bit in the WUS.
5.5.3 Wake-Up Packets
The 82574L supports various wake-up packets using two types of filters:
• Pre-defined filters
• Flexible filters
Each of these filters are enabled if the corresponding bit in the WUFC is set to 1b.
