REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD5203
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 1998
4-Channel, 64-Position
Digital Potentiometer
FUNCTIONAL BLOCK DIAGRAM
SHDN
DAC 1 A1
W1
B1
AGND1
6
VDD
DGND
SDI
CLK
CS
AD5203
SDO SHDN
A2
W2
B2
AGND2
A3
W3
B3
AGND3
A4
W4
B4
AGND4
6
2
RS
6-BIT
LATCH
CK RS
6
6-BIT
LATCH
CK RS SHDN
DAC 2
SHDN
DAC 3
6
6
SHDN
DAC 4
6-BIT
LATCH
CK RS
6-BIT
LATCH
CK RS
DAC
SELECT
A1, A0
1
2
3
4
8-BIT
SERIAL
LATCH
D
CK QRS
FEATURES
64 Position
Replaces Four Potentiometers
10 k⍀, 100 k⍀
Power Shutdown—Less than 5 ␮A
3-Wire SPI-Compatible Serial Data Input
10 MHz Update Data Loading Rate
+2.7 V to +5.5 V Single Supply Operation
Midscale Preset
APPLICATIONS
Mechanical Potentiometer Replacement
Programmable Filters, Delays, Time Constants
Volume Control, Panning
Line Impedance Matching
Power Supply Adjustment
GENERAL DESCRIPTION
The AD5203 provides a quad channel, 64-position digitally-
controlled variable resistor (VR) device. These parts perform the
same electronic adjustment function as a potentiometer or vari-
able resistor. The AD5203 contains four independent variable
resistors in a 24-lead SOIC and the compact TSSOP-24 pack-
ages. Each part contains a fixed resistor with a wiper contact
that taps the fixed resistor value at a point determined by a digi-
tal code loaded into the controlling serial input register. The
resistance between the wiper and either endpoint of the fixed
resistor varies linearly with respect to the digital code transferred
into the VR latch. Each variable resistor offers a completely
programmable value of resistance, between the A terminal and
the wiper or the B terminal and the wiper. The fixed A-to-B
terminal resistance of 10 kΩ, or 100 kΩ has a ±1% channel-to-
channel matching tolerance with a nominal temperature coeffi-
cient of 700 ppm/°C.
Each VR has its own VR latch which holds its programmed
resistance value. These VR latches are updated from an internal
serial-to-parallel shift register that is loaded from a standard
3-wire serial-input digital interface. Eight data bits make up the
data word clocked into the serial input register. The data word is
decoded where the first two bits determine the address of the VR
latch to be loaded, the last 6-bits are data. A serial data output
pin at the opposite end of the serial register allows simple daisy-
chaining in multiple VR applications without additional external
decoding logic.
The reset RS pin forces the wiper to the midscale position by
loading 20
H
into the VR latch. The SHDN pin forces the resis-
tor to an end-to-end open circuit condition on terminal A and
shorts the wiper to terminal B, achieving a microwatt power
shutdown state. When shutdown is returned to logic-high the
previous latch settings put the wiper in the same resistance set-
ting prior to shutdown.
The AD5203 is available in a narrow body P-DIP-24, the
24-lead surface mount package, and the compact 1.1 mm thin
TSSOP-24 package. All parts are guaranteed to operate over the
extended industrial temperature range of –40°C to +85°C.
For pin compatible higher resolution applications, see the 256-
position AD8403 product.
–2– REV. 0
AD5203–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter Symbol Conditions Min Typ
1
Max Units
DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs
Resistor Differential NL
2
R-DNL R
WB
, V
A
= No Connect –0.25 ±0.1 +0.25 LSB
Resistor Nonlinearity Error
2
R-INL R
WB
, V
A
= No Connect –0.5 ±0.1 +0.5 LSB
Nominal Resistor Tolerance
3
∆R
AB
–30 +30 %
Resistance Temperature Coefficient ∆R
AB
/∆TV
AB
= V
DD
, Wiper = No Connect 700 ppm/°C
Wiper Resistance R
W
I
W
= 1 V/R
AB
45 100 Ω
Nominal Resistance Match ∆R/R
O
CH 1 to CH 2,
V
AB
= V
DD
, T
A
= +25°C 0.2 1 %
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications Apply to All VRs
Resolution N 6 Bits
Differential Nonlinearity Error
4
DNL –0.25 ±0.1 +0.25 LSB
Integral Nonlinearity Error
4
INL –0.75 ±0.1 +0.75 LSB
Voltage Divider Temperature Coefficient ∆V
W
/∆T Code = 20
H
20 ppm/°C
Full-Scale Error V
WFSE
Code = 3F
H
–0.75 –0.2 0 LSB
Zero-Scale Error V
WZSE
Code = 00
H
0 +0.1 +0.75 LSB
RESISTOR TERMINALS
Voltage Range
5
V
A,
V
B,
V
W
0V
DD
V
Capacitance
6
Ax, Bx C
A,
C
B
f = 1 MHz, Measured to GND, Code = 20
H
75 pF
Capacitance
6
Wx C
W
f = 1 MHz, Measured to GND, Code = 20
H
120 pF
Shutdown Supply Current
7
I
A_SD
V
A
= V
DD
, V
B
= 0 V, SHDN = 0 0.01 5 µA
Shutdown Wiper Resistance R
W_SD
V
A
= V
DD
, V
B
= 0 V, SHDN = 0, V
DD
= +5 V 45 100 Ω
DIGITAL INPUTS AND OUTPUTS
Input Logic High V
IH
V
DD
= +5 V 2.4 V
Input Logic Low V
IL
V
DD
= +5 V 0.8 V
Input Logic High V
IH
V
DD
= +3 V 2.1 V
Input Logic Low V
IL
V
DD
= +3 V 0.6 V
Output Logic High V
OH
R
L
= 2.2 kΩ to V
DD
V
DD
–0.1 V
Output Logic Low V
OL
I
OL
= 1.6 mA, V
DD
= +5 V 0.4 V
Input Current I
IL
V
IN
= 0 V or +5 V, V
DD
= +5 V ±1µA
Input Capacitance
6
C
IL
5pF
POWER SUPPLIES
Power Supply Range V
DD
Range 2.7 5.5 V
Supply Current (CMOS) I
DD
V
IH
= V
DD
or V
IL
= 0 V 0.01 5 µA
Supply Current (TTL)
8
I
DD
V
IH
= 2.4 V or V
IL
= 0.8 V, V
DD
= +5.5 V 0.9 4 mA
Power Dissipation (CMOS)
9
P
DISS
V
IH
= V
DD
or V
IL
= 0 V, V
DD
= +5.5 V 27.5 µW
Power Supply Sensitivity PSS ∆V
DD
= +5 V ± 10% 0.0002 0.001 %/%
PSS ∆V
DD
= +3 V ± 10% 0.006 0.03 %/%
DYNAMIC CHARACTERISTICS
6, 10
Bandwidth –3 dB BW_10K R
AB
= 10 kΩ600 kHz
BW_100K R
AB
= 100 kΩ71 kHz
Total Harmonic Distortion THD
W
V
A
=1 V rms + 2 V dc, V
B
= 2 V dc, f = 1 kHz 0.003 %
V
W
Settling Time t
S
_10K V
A
= V
DD
, V
B
= 0 V, ±1 LSB Error Band 2 µs
t
S
_100K V
A
= V
DD
, V
B
= 0 V, ±1 LSB Error Band 18 µs
Resistor Noise Voltage e
NWB
R
WB
= 5 kΩ, f = 1 kHz, RS = 0 9 nV/√Hz
R
WB
= 50 kΩ, f = 1 kHz, RS = 0 29 nV/√Hz
Crosstalk
11
C
T
V
A
= V
DD
, V
B
= 0 V –65 dB
INTERFACE TIMING CHARACTERISTICS Applies to All Parts
6, 12
Input Clock Pulsewidth t
CH
, t
CL
Clock Level High or Low 10 ns
Data Setup Time t
DS
5ns
Data Hold Time t
DH
5ns
CLK to SDO Propagation Delay
13
t
PD
R
L
= 2.2 kΩ, C
L
< 20 pF 1 25 ns
CS Setup Time t
CSS
10 ns
CS High Pulsewidth t
CSW
10 ns
Reset Pulsewidth t
RS
50 ns
CLK Fall to CS Rise Hold Time t
CSH
0ns
CS Rise to Clock Rise Setup t
CS1
10 ns
(VDD = +3 V ⴞ 10% or +5 V ⴞ 10%, VA = +VDD, VB = 0 V, –40ⴗC < TA < +85ⴗC unless
otherwise noted)
–3–REV. 0
AD5203
NOTES
1
Typicals represent average readings at +25°C and V
DD
= +5 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi-
tions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 27 test circuit. I
W
= V
DD
/R
for both V
DD
= +3 V or V
DD
= +5 V.
3
V
AB
= V
DD
, Wiper (V
W
) = No connect.
4
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
A
= V
DD
and V
B
= 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. See Figure 26 test circuit.
5
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
Measured at the AX terminals. All AX terminals are open-circuited in shutdown mode.
8
Worst case supply current consumed when all logic-input levels set at 2.4 V, standard characteristic of CMOS logic. See Figure 19 for a plot of I
DD
vs. logic voltage
inputs result in minimum power dissipation.
9
P
DISS
is calculated from (I
DD
× V
DD
). CMOS logic level inputs result in minimum power dissipation.
10
All dynamic characteristics use V
DD
= +5 V.
11
Measured at a V
W
pin where an adjacent V
W
pin is making a full-scale voltage change.
12
See timing diagrams for location of measured values. All input control voltages are specified with t
R
= t
F
= 1 ns (10% to 90% of V
DD
) and timed from a voltage level
of 1.6 V. Switching characteristics are measured using both V
DD
= +3 V or +5 V. Input logic should have a 1 V/ µs minimum slew rate.
13
Propagation delay depends on value of V
DD
, R
L
and C
L
. See Operation section.
ABSOLUTE MAXIMUM RATINGS*
(T
A
= +25°C, unless otherwise noted)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +8 V
V
A
, V
B
, V
W
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, V
DD
I
AB
, I
AW
, I
BW
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Digital Input and Output Voltage to GND . . . . . . . 0 V, +8 V
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Maximum Junction Temperature (T
J
MAX) . . . . . . . .+150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C
Package Power Dissipation . . . . . . . . . . . . . . (T
J
max–T
A
)/θ
JA
Thermal Resistance θ
JA
P-DIP (N-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W
SOIC (SOL-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
TSSOP-24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143°C/W
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Table I. Serial-Data Word Format
ADDR DATA
B7 B6 B5 B4 B3 B2 B1 B0
A1 A0 D5 D4 D3 D2 D1 D0
MSB LSB MSB LSB
2
7
2
6
2
5
2
0
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD5203 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
SDI
CLK
CS
VOUT
1
0
1
0
1
0
VDD
0V
D0D1D2D3D4D5A0A1
DAC REGISTER LOAD
Figure 1a. Timing Diagram
CLK
VOUT
1
0
1
0
1
0
VDD
0V
SDI
(DATA IN)
SDO
(DATA OUT)
CS 1
0
Ax OR Dx Ax OR Dx
A'x OR D'x
tDS tDH
tPD MAX
tPD MIN
tCH tCS1
tCL
tCSS tCSH
61 LSB
6 1 LSB ERROR BAND
tCSW
tS
A'x OR D'x
Figure 1b. Detail Timing Diagram
VOUT
VDD
0V
RS 1
0
61 LSB
61 LSB ERROR BAND
tS
tRS
Figure 1c. Reset Timing Diagram
AD5203
–4– REV. 0
PIN FUNCTION DESCRIPTIONS
Pin
No. Name Description
1 AGND2 Analog Ground #2*
2 B2 B Terminal RDAC #2
3 A2 A Terminal RDAC #2
4 W2 Wiper RDAC #2, addr = 01
2
5 AGND4 Analog Ground #4*
6 B4 B Terminal RDAC #4
7 A4 A Terminal RDAC #4
8 W4 Wiper RDAC #4, addr = 11
2
9 DGND Digital Ground*
10 SHDN Active Low Input. Terminal A open circuit.
Shutdown controls Variable Resistors #1
through #4.
11 CS Chip Select Input, Active Low. When CS
returns high data in the serial input register
is decoded based on the address bits and
loaded into the target DAC register.
12 SDI Serial Data Input
13 SDO Serial Data Output. Open drain transistor
requires pull-up resistor.
14 CLK Serial Clock Input, positive edge triggered.
15 RS Active low reset to midscale; sets RDAC
registers to 20
H
.
16 V
DD
Positive power supply, specified for opera-
tion at both +3 V and +5 V.
17 AGND3 Analog Ground #3*
18 W3 Wiper RDAC #3, addr =10
2
19 A3 A Terminal RDAC #3
20 B3 B Terminal RDAC #3
21 AGND1 Analog Ground #1*
22 W1 Wiper RDAC #1, addr = 00
2
23 A1 A Terminal RDAC #1
24 B1 B Terminal RDAC #1
*All AGNDs must be connected to DGND voltage potential.
ORDERING GUIDE
Model k⍀Temperature Range Package Descriptions Package Options
AD5203AN10 10 –40°C to +85°C 24-Lead Narrow Body Plastic DIP N-24
AD5203AR10 10 –40°C to +85°C 24-Lead Wide Body (SOIC) SOL-24
AD5203ARU10 10 –40°C to +85°C 24-Lead Thin Surface Mount Package (TSSOP) RU-24
AD5203AN100 100 –40°C to +85°C 24-Lead Narrow Body Plastic DIP N-24
AD5203AR100 100 –40°C to +85°C 24-Lead Wide Body (SOIC) SOL-24
AD5203ARU100 100 –40°C to +85°C 24-Lead Thin Surface Mount Package (TSSOP) RU-24
PIN CONFIGURATION
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
AD5203
SDI
CS
SHDN
DGND
W4
AGND2
B2
A2
W2
A4
B4
AGND4
SDO
CLK
RS
VDD
AGND3
B1
A1
W1
AGND1
W3
A3
B3
(Not to Scale)
AD5203
–5–REV. 0
Typical Performance Characteristics–
CODE – Decimal
RESISTANCE – kV
10
008 64
16 24 32 40 48 56
9
6
5
3
1
8
7
4
2
VDD = +3V, OR +5V
RAB = 10kV
RWB RWA
Figure 2. Wiper to End Terminal
␣ ␣ Resistance vs. Code
WIPER RESISTANCE – V
FREQUENCY
80
60
030 31 32 33 34 35 36 37 38 39
40
20
SS = 544 UNITS
VDD = +4.5V
TA = +258C
Figure 5.␣ Wiper-Contact-Resistance
Histogram
DIGITAL INPUT CODE – Decimal
DNL ERROR – LSB
0.25
–0.25 0864
16 24 32 40 48 56
0.2
0.05
0
–0.1
–0.2
0.15
0.1
–0.05
–0.15
VDD = +3.0V
TA = +258C, +858C, –408C
Figure 8. Potentiometer Divider
Differential Nonlinearity Error vs.
Code
05H
IWA CURRENT – mA
VWB VOLTAGE – V
5
001723456
4.5
2
1.5
1
0.5
3.5
2.5
4
3
RAB = 10kV
VDD = +5V
TA = +258C
3FH
20H10H
08H
02H
Figure 3. Resistance Linearity vs.
␣ ␣ Conduction Current
TEMPERATURE – 8C
NOMINAL RESISTANCE – kV
12
0
–75 –50 125
–25 0 25 50 75 100
10
8
6
4
2
AD5203-10K VERSION
RAB (END-TO-END)
RWB (WIPER-TO-END)
CODE = 20H
␣ ␣ Figure 6.␣ Nominal Resistance vs.
␣ ␣ Temperature
CODE – Decimal
POTENTIOMETER MODE TEMPCO – ppm/8C
50
008 6416 24 32 40 48 56
30
40
20
10
VDD = +3.0V
TA = –408C/+858C
VA = +2.0V
VB = 0V
Figure 9.␣
∆
V
WB
/
∆
T Potentiometer
Mode Tempco
DIGITAL INPUT CODE – Decimal
RINL ERROR – LSB
0.25
–0.2508 64
16 24 32 40 48 56
0.2
0.05
0
–0.1
–0.2
0.15
0.1
–0.05
–0.15
VDD = +3.0V
TA = –558C
TA = +858C
TA = +258C
Figure 4. Resistance Step Position
␣ ␣ Nonlinearity Error vs. Code
DIGITAL INPUT CODE – Decimal
INL NONLINEARITY ERROR – LSB
0.25
–0.2508 6416 24 32 40 48 56
0.2
0.05
0
–0.1
–0.2
0.15
0.1
–0.05
–0.15
–558C
+858C
+258C
VDD = +3.0V
␣␣␣ Figure 7. Potentiometer Divider
␣ ␣ Nonlinearity Error vs. Code
CODE – Decimal
RHEOSTAT MODE TEMPCO – ppm/8C
120
008 64
16 24 32 40 48 56
80
100
60
40
20
VDD = +3.0V
TA = –408C/+858C
VA = NO CONNECT
RWB MEASURED
Figure 10.
∆
R
WB
/
∆
T Rheostat Mode
Tempco
AD5203
–6– REV. 0
–Typical Performance Characteristics
RW
(20mV/DIV)
CS
(5V/DIV)
TIME 500ns/DIV
Figure 11. One Position Step Change
at Half-Scale (Code 1F
H
to 20
H
)
OUTPUT
CS
TIME 5
s/DIV
Figure 14. Large Signal Settling Time
0
–50
10 100 1M
1k 10k 100k
–10
–20
–30
–40
GAIN – dB
FREQUENCY – Hz
CODE = 3FH
20H
10H
08H
04H
02H
01H
VDD = +5V
TA = +258C
5dB/DIV
Figure 17. 100 k
Ω
Gain vs. Frequency
vs. Code
0
–50
10 100 1M
1k 10k 100k
–10
–20
–30
–40
10M
GAIN – dB
FREQUENCY – Hz
TA = +258C
SEE TEST CIRCUIT FIGURE 32
CODE = 3FH
20H
10H
08H
04H
02H
01H
Figure 12. Gain vs. Frequency for
R = 10 k
Ω
FREQUENCY – Hz
THD + NOISE – %
10
0.00110 100k100 1k 10k
1
0.1
FILTER = 22kHz
VDD = +5V
TA = +258C
RAB = 10kV
0.01
SEE TEST CIRCUIT FIGURE 31
SEE TEST CIRCUIT FIGURE 30
Figure 15.␣ Total Harmonic Distortion
Plus Noise vs. Frequency
0
–0.5
10 100 1M
1k 10k 100k
–0.1
–0.2
–0.3
–0.4
NORMALIZED GAIN FLATNESS – 0.1dB/DIV
FREQUENCY – Hz
–0.6
–0.7
–0.8
–0.9
–1.0
VDD = +5V
CODE = 3FH
TA = +258C
SEE TEST CIRCUIT FIGURE 32
RAB = 10kV
RAB = 100kV
Figure 18. Normalized Gain Flat-
ness vs. Frequency
HOURS OF OPERATION @ 1508C
DRWB RESISTANCE – %
0.75
–0.75 0 100 600
200 300 400 500
0.5
0.25
0
–0.25
–0.5
VDD = +5V
CODE = 3FH
SS = 77 UNITS
AVG –2 S
AVG +2 S
AVG
␣␣␣␣ Figure 13. Long-Term Drift
Accelerated by Burn-In
VOUT
(20mV/DIV)
TIME 100ns/DIV
Figure 16. Digital Feedthrough vs.
Time
10
1
0.1
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
INPUT LOGIC VOLTAGE – Volts
IDD SUPPLY CURRENT – mA
VDD = +5.0V
VDD = +3.0V
0.01
Figure 19. Supply Current vs. Logic
Input Voltage
AD5203
–7–REV. 0
80
0100k1k 10k
60
40
20
1M
FREQUENCY – Hz
PSRR – dB
VDD = +5V DC 61V p-p AC
TA = +258C
CODE = 80H
CL = 10pF
VA = 4V, VB = 0V
Figure 20. Power Supply Rejection
vs. Frequency
VDD – Volts
RON – V
100
80
001 6
23 45
60
40
20
TA = +258C
VDD = +2.7V
VDD = +5.5V
Figure 23. Incremental Wiper ON
Resistance vs. V
DD
0
–50
10 100 1M
1k 10k 100k
–10
–20
–30
–40
GAIN – dB
FREQUENCY – Hz
–5
–15
–25
–35
–45
VDD = +5V
VIN = 100mV rms
CODE = 20H
TA = +258C
f–3dB = 625kHz,
R = 10kV
f–3dB = 65kHz,
R = 100kV
Figure 21. –3␣ dB Frequency at
Half-Scale
IA SHUTDOWN CURRENT – nA
100
1
–55 –35
10
–15 5 25 45 65 85 105 125
TEMPERATURE – 8C
VDD = +5V
␣␣␣␣Figure 24. Shutdown Current vs.
␣ ␣ ␣ ␣ Temperature
FREQUENCY – Hz
1k 1M 10M10k 100k
IDD – SUPPLY CURRENT – mA
1200
1000
800
600
400
200
0
TA = +258C
AB
C
D
A – VDD = +5.5V
CODE = 15H
B – VDD = +3.3V
CODE = 15H
C – VDD = +5.5V
CODE = 3FH
D – VDD = +3.3V
CODE = 3FH
Figure 22. Supply Current vs. Clock
Frequency
TEMPERATURE – 8C
IDD – SUPPLY CURRENT – mA
1
0.1
0.001
–55 –35 125–15 5 25 45 65 85 105
0.01 VDD = +5.5V
VDD = +3.3V
LOGIC INPUT
VOLTAGE = 0, VDD
Figure 25. Supply Current vs.
Temperature
AD5203
–8– REV. 0
–Parametric Test Circuits
V+
DUT
VMS
A
B
W
V+ = VDD
1LSB = V+/64
Figure 26. Potentiometer Divider Nonlinearity Error Test
Circuit (INL, DNL)
NO CONNECT
IW
DUT
VMS
A
B
W
Figure 27. Resistor Position Nonlinearity Error (Rheostat
Operation; R-INL, R-DNL)
IMS
VWIW = 1V/RNOMINAL
V+
DUT
VMS
A
B
W
VW2 – [VW1 + IW (RAWII RBW)]
IW
V+ < VDD
WHERE VW1 = VMS WHEN IW = 0
AND VW2 = VMS WHEN IW = 1/R
RW = ––––––––––––––––––––––––––
␣ ␣ Figure 28.␣ Wiper Resistance Test Circuit
PSRR (dB) = 20 LOG ( ––––– )
PSS (%/%) = –––––––
DVMS
DVDD
DVMS%
DVDD%
V+ = VDD ± 10%
VDD
VA
~
V+
VMS
A
B
W
Figure 29. Power Supply Sensitivity Test Circuit (PSS,
PSRR)
~
AB
VIN
2.5V DC
OP279
+5V
VOUT
DUT
W
OFFSET
GND
Figure 30. Inverting Programmable Gain Test Circuit
~
AB
VIN
2.5V
OP279
+5V
VOUT
DUT
W
OFFSET
GND
␣ Figure 31. Noninverting Programmable Gain Test Circuit
+15V
–15V
A
B
VIN
2.5V
OP42 VOUT
DUT W
OFFSET
GND
~
␣ Figure 32. Gain vs. Frequency Test Circuit
ISW
0 TO VDD
RSW =0.1V
ISW
CODE = ØØH
0.1V
DUT
B
W
Figure 33. Incremental ON Resistance Test Circuit
AD5203
–9–REV. 0
OPERATION
The AD5203 provides a quad channel, 64-position digitally-
controlled variable resistor (VR) device. Changing the pro-
grammed VR settings is accomplished by clocking in an 8-bit
serial data word into the SDI (Serial Data Input) pin. The for-
mat of this data word is two address bits, MSB first, followed by
six data bits, MSB first. Table I provides the serial register data
word format. The AD5203 has the following address assign-
ments for the ADDR decode, which determines the location of
VR latch receiving the serial register data in Bits B5 through B0:
VR# = A1 × 2 + A0 + 1
VR outputs can be changed one at a time in random sequence.
The serial clock running at 10 MHz makes it possible to load all
four VRs in under 3.2 µs (8 × 4 × 100 ns) for the AD5203. The
exact timing requirements are shown in Figure 1.
The AD5203 resets to a midscale by asserting the RS pin, sim-
plifying initial conditions at power-up. Both parts have a power
shutdown SHDN pin that places the RDAC in a zero power
consumption state where terminals Ax are open-circuited and
the wiper Wx is connected to Bx, resulting in only leakage cur-
rents being consumed in the VR structure. In shutdown mode
the VR latch settings are maintained so that, returning to opera-
tional mode from power shutdown, the VR settings return to
their previous resistance values.
D5
D4
D3
D2
D1
D0
RDAC
LATCH
&
DECODER
Ax
Wx
Bx
RS = RAB/64
RS
RS
RS
RS
SHDN
Figure 34. Equivalent RDAC Circuit
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
The nominal resistance of the RDAC between Terminals A and
B are available with values of 10 kΩ, and 100 kΩ. The final
digits of the part number determine the nominal resistance
value, e.g., 10 kΩ = 10; 100 kΩ = 100. The nominal resistance
(R
AB
) of the VR has 64 contact points accessed by the wiper
terminal, plus the B terminal contact. The 6-bit data word in
the RDAC latch is decoded to select one of the 64 possible
settings. The wiper’s first connection starts at the B terminal for
data 00
H
. This B–terminal connection has a wiper contact resis-
tance of 45 Ω. The second connection (10 kΩ part) is the first
tap point located at 201 Ω [= R
BA
(nominal resistance)/64 + R
W
= 156 Ω + 45 Ω)] for data 01
H
. The third connection is the next
tap point representing 312 + 45 = 357 Ω for data 02
H
. Each
LSB data value increase moves the wiper up the resistor ladder
until the last tap point is reached at 9889 Ω. The wiper does not
directly connect to the B Terminal. See Figure 34 for a simpli-
fied diagram of the equivalent RDAC circuit.
The general transfer equation that determines the digitally pro-
grammed output resistance between Wx and Bx is:
R
WB
(Dx) = (Dx)/64 × R
BA
+ R
W
(1)
where Dx is the data contained in the 6-bit RDACx latch and
R
BA
is the nominal end-to-end resistance.
For example, when V
B
= 0 V and A–terminal is open circuit the
following output resistance values will be set for the following
RDAC latch codes (applies to the 10K potentiometer):
D (DEC) R
WB
(⍀) Output State
63 9889 Full-Scale
32 5045 Midscale (RS = 0 Condition)
1 201 1 LSB
0 45 Zero-Scale (Wiper Contact Resistance)
Note that in the zero-scale condition a finite wiper resistance of
45 Ω is present. Care should be taken to limit the current flow
between W and B in this state to a maximum value of 5 mA to
avoid degradation or possible destruction of the internal switch
contact.
Like the mechanical potentiometer the RDAC replaces, it is
totally symmetrical. The resistance between the wiper W and
terminal A also produces a digitally controlled resistance R
WA
.
When these terminals are used the B–terminal should be tied to
the wiper. Setting the resistance value for R
WA
starts at a maxi-
mum value of resistance and decreases as the data loaded in the
latch is increased in value. The general transfer equation for this
operation is:
R
WA
(Dx) = (64-Dx)/64 × R
BA
+ R
W
(2)
where Dx is the data contained in the 6-bit RDACx latch and
R
BA
is the nominal end-to-end resistance. For example, when
V
A
= 0 V and B–terminal is tied to the wiper W, the following
output resistance values will be set for the following RDAC
latch codes:
D (DEC) R
WA
(⍀) Output State
63 201 Full-Scale
32 5045 Midscale (RS = 0 Condition)
1 9889 1 LSB
0 10045 Zero-Scale
The typical distribution of R
BA
from channel to channel matches
within ±1%. However, device-to-device matching is process-lot-
dependent, having a ±30% variation. The change in R
BA
with
temperature has a 700 ppm/°C temperature coefficient.
AD5203
–10– REV. 0
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates an output voltage
proportional to the input voltage applied to a given terminal.
For example connecting A–terminal to +5 V and B–terminal to
ground produces an output voltage at the wiper which can be
any value starting at zero volts up to 1 LSB less than +5 V.
Each LSB of voltage is equal to the voltage applied across ter-
minal AB divided by the 64 position resolution of the potenti-
ometer divider. The general equation defining the output
voltage with respect to ground for any given input voltage ap-
plied to terminals AB is:
V
W
(Dx) = Dx/64 × V
AB
+ V
B
Operation of the digital potentiometer in the divider mode
results in more accurate operation over temperature. Here the
output voltage is dependent on the ratio of the internal resistors
not the absolute value, therefore the drift improves to 20 ppm/°C.
DIGITAL INTERFACING
The AD5203 contains a standard three-wire serial input control
interface. The three inputs are clock (CLK), CS and serial data
input (SDI). The positive-edge sensitive CLK input requires
clean transitions to avoid clocking incorrect data into the serial
input register. Standard logic families work well. If mechanical
switches are used for product evaluation they should be de-
bounced by a flip-flop or other suitable means. The Figure 35
block diagram shows more detail of the internal digital cir-
cuitry. When CS is taken active low the clock loads data into
the serial register on each positive clock edge, see Table III.
AGND
A1
W1
B1
VDD
AD5203
CS
CLK
6
D5
D0
EN
ADDR
DEC
A1
A0
SDI DI
SER
REG
D0
D5
SDO DO
DGND
A4
W4
B4
SHDN
RS
DAC
LAT
#1
R
R
D5
D0
DAC
LAT
#4
R
R
Figure 35. Block Diagram
The serial-data-output (SDO) pin contains an open drain
n-channel FET. This output requires a pull-up resistor in order
to transfer data to the next package’s SDI pin. The pull-up
resistor termination voltage may be larger than the V
DD
supply
of the AD5203 SDO output device, e.g., the AD5203 could
operate at V
DD
= 3.3 V and the pull-up for interface to the next
device could be set at +5 V. This allows for daisy chaining sev-
eral RDACs from a single processor serial data line. Clock pe-
riod needs to be increased when using a pull-up resistor to the
SDI pin of the following device in the series. Capacitive loading
at the daisy chain node SDO-SDI between devices must be
accounted for to successfully transfer data. When daisy chaining
is used, the CS should be kept low until all the bits of every
package are clocked into their respective serial registers insuring
that the address bits and data bits are in the proper decoding
location. This would require 16 bits of address and data comply-
ing to the word format provided in Table I if two AD5203 four-
channel RDACs are daisy chained. During shutdown, SHDN
the SDO output pin is forced to the off (logic high state) to
disable power dissipation in the pull-up resistor. See Figure 37
for equivalent SDO output circuit schematic.
Table II. Input Logic Control Truth Table
CLK CS RS SHDN Register Activity
L L H H No SR effect, enables SDO pin.
P L H H Shift one bit in from the SDI pin.
The eighth previously entered bit
is shifted out of the SDO pin.
X P H H Load SR data into RDAC latch
based on A1, A0 decode (Table III).
X H H H No Operation.
X X L H Sets all RDAC latches to midscale,
wiper centered and SDO latch
cleared.
X H P H Latches all RDAC latches to 20
H
.
X H H L Open circuits all Resistor A–termi-
nals, connects W to B, turns off
SDO output transistor.
NOTE: P = positive edge, X = don’t care, SR = shift register.
Table III. Address Decode Table
A1 A0 Latch Decoded
0 0 RDAC#1
0 1 RDAC#2
1 0 RDAC#3
1 1 RDAC#4
AD5203
–11–REV. 0
The data setup and data hold times in the specification table
determine the data valid time requirements. The last eight bits
of the data word entered into the serial register are held when
CS returns high. At the same time CS goes high it gates the
address decoder which enables one of four positive edge trig-
gered RDAC latches, see Figure 36 detail.
RDAC 1
RDAC 2
RDAC 4
AD5203
SDI
CLK
CS ADDR
DECODE
SERIAL
REGISTER
Figure 36. Equivalent Input Control Logic
The target RDAC latch is loaded with the last six bits of the
serial data word completing one RDAC update. Four separate
8-bit data words must be clocked in to change all four VR
settings.
SERIAL
REGISTER
SDI
CK RS
DQ
SHDN
CS
CLK
RS
SDO
Figure 37. Detail, SDO Output Schematic of the AD5203
All digital inputs are protected with a series input resistor and
parallel Zener ESD structure shown in Figure 38. Applies to
digital input pins CS, SDI, SDO, RS, SHDN, CLK.
1kVLOGIC
Figure 38. Equivalent ESD Protection Circuit
DYNAMIC CHARACTERISTICS
The total harmonic distortion plus noise (THD+N) measures
0.003% using an offset ground with a rail-to-rail OP279 invert-
ing op amp test circuit, see Figure 30. Figure 15 plots THD
versus frequency for both inverting and noninverting amplifier
topologies. Thermal noise is primarily Johnson noise, typically
9 nV/√Hz for the 10 kΩ version measured at 1 kHz. For the
100 kΩ device, thermal noise measures 29 nV/√Hz. Channel-to-
channel crosstalk measures less than –65 dB at f = 100 kHz. To
achieve this isolation, the extra ground pins (AGND) located
between the potentiometer terminals (A, B, W) must be con-
nected to circuit ground. The AGND and DGND pins should
be at the same voltage potential. Any unused potentiometers in
a package should be connected to ground. Power supply rejec-
tion is typically –50 dB at 10 kHz (care is needed to minimize
power supply ripple injection in high accuracy applications).
AD5203
–12– REV. 0
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
C3364–8–7/98
PRINTED IN U.S.A.
24-Lead Narrow Body Plastic DIP
(N-24)
24
112
13 0.280 (7.11)
0.240 (6.10)
PIN 1
1.275 (32.30)
1.125 (28.60)
0.150
(3.81)
MIN
0.200 (5.05)
0.125 (3.18) SEATING
PLANE
0.022 (0.558)
0.014 (0.356)
0.060 (1.52)
0.015 (0.38)
0.210
(5.33)
MAX
0.070 (1.77)
0.045 (1.15)
0.100 (2.54)
BSC
0.325 (8.25)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
0.195 (4.95)
0.115 (2.93)
24-Lead SOIC
(SOL-24)
24 13
12
1
0.6141 (15.60)
0.5985 (15.20)
0.4193 (10.65)
0.3937 (10.00)
0.2992 (7.60)
0.2914 (7.40)
PIN 1
SEATING
PLANE
0.0118 (0.30)
0.0040 (0.10) 0.0192 (0.49)
0.0138 (0.35)
0.1043 (2.65)
0.0926 (2.35)
0.0500
(1.27)
BSC 0.0125 (0.32)
0.0091 (0.23)
0.0500 (1.27)
0.0157 (0.40)
8°
0°
0.0291 (0.74)
0.0098 (0.25) x 45°
24-Lead Thin Surface Mount TSSOP
(RU-24)
24 13
12
1
0.311 (7.90)
0.303 (7.70)
0.256 (6.50)
0.246 (6.25)
0.177 (4.50)
0.169 (4.30)
PIN 1
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0.0118 (0.30)
0.0075 (0.19)
0.0256 (0.65)
BSC
0.0433
(1.10)
MAX
0.0079 (0.20)
0.0035 (0.090)
0.028 (0.70)
0.020 (0.50)
8°
0°